blob: c99e8b4bae14db1b18ffb45b308ce64a88760fbf [file] [log] [blame]
2022-12-05 17:26:01 - [INFO] - {{Project Git Info}} Repository: https://github.com/AllenDBoston/PMU_caravel_mpw7.git | Branch: main | Commit: a98d42ceb9735e29c75fba3db675698033cab1ac
2022-12-05 17:26:01 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: fpga_programming_management_unit
2022-12-05 17:26:01 - [INFO] - {{Project Type Info}} digital
2022-12-05 17:26:02 - [INFO] - {{Project GDS Info}} user_project_wrapper: 3372b133a5c761f8ca13bb9929c32f761e549d75
2022-12-05 17:26:02 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
2022-12-05 17:26:02 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
2022-12-05 17:26:02 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs'
2022-12-05 17:26:02 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-12-05 17:26:02 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2022-12-05 17:26:03 - [INFO] - An approved LICENSE (Apache-2.0) was found in fpga_programming_management_unit.
2022-12-05 17:26:03 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-12-05 17:26:04 - [INFO] - An approved LICENSE (Apache-2.0) was found in fpga_programming_management_unit.
2022-12-05 17:26:04 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-12-05 17:26:14 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 2759 non-compliant file(s) with the SPDX Standard.
2022-12-05 17:26:14 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['fpga_programming_management_unit/dependencies/pdks/volare/sky130/current', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/SOURCES', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/.config/nodeinfo.json', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/cdl/sky130_ef_io.cdl', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_100C_1v95_5v50.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50_nointpwr.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_100C_1v65_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_100C_1v95_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_100C_1v95_1v95.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_n40C_1v65_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_n40C_1v95_1v65.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ss_n40C_1v95_1v95.lib', 'fpga_programming_management_unit/dependencies/pdks/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ff_100C_1v40_5v50.lib']
2022-12-05 17:26:14 - [INFO] - For the full SPDX compliance report check: fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/spdx_compliance_report.log
2022-12-05 17:26:14 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
2022-12-05 17:26:14 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-12-05 17:26:14 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
2022-12-05 17:26:14 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-12-05 17:26:16 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-12-05 17:26:16 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
2022-12-05 17:26:16 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-12-05 17:26:16 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
2022-12-05 17:26:29 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2022-12-05 17:26:29 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2022-12-05 17:26:29 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2022-12-05 17:26:29 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (304 instances).
2022-12-05 17:26:29 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2022-12-05 17:26:29 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2022-12-05 17:26:29 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2022-12-05 17:26:29 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2022-12-05 17:26:29 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2022-12-05 17:26:30 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-12-05 17:26:30 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
2022-12-05 17:26:30 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'fpga_programming_management_unit/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
2022-12-05 17:26:32 - [INFO] - GPIO-DEFINES report path: fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/gpio_defines.report
2022-12-05 17:26:32 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
2022-12-05 17:26:32 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2022-12-05 17:29:00 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper.xor.gds
2022-12-05 17:29:00 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-12-05 17:29:00 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
2022-12-05 17:29:02 - [INFO] - 0 DRC violations
2022-12-05 17:29:02 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 17:29:02 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
2022-12-05 17:29:02 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-05 17:29:02 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_feol_check.xml -rd feol=true >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_feol_check.log
2022-12-05 17:35:48 - [INFO] - No DRC Violations found
2022-12-05 17:35:48 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 17:35:48 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
2022-12-05 17:35:48 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-05 17:35:48 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_beol_check.xml -rd beol=true >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_beol_check.log
2022-12-05 18:25:41 - [INFO] - No DRC Violations found
2022-12-05 18:25:41 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 18:25:41 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
2022-12-05 18:25:41 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-05 18:25:41 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_offgrid_check.log
2022-12-05 18:35:11 - [INFO] - No DRC Violations found
2022-12-05 18:35:11 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 18:35:11 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
2022-12-05 18:35:11 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-05 18:35:11 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_met_min_ca_density_check.xml >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_met_min_ca_density_check.log
2022-12-05 18:38:27 - [INFO] - No DRC Violations found
2022-12-05 18:38:27 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 18:38:27 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
2022-12-05 18:38:27 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-05 18:38:27 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
2022-12-05 18:40:02 - [INFO] - No DRC Violations found
2022-12-05 18:40:02 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 18:40:02 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
2022-12-05 18:40:02 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-05 18:40:02 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=fpga_programming_management_unit/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/outputs/user_project_wrapper_no_zero_areas.gds >& fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs/klayout_zeroarea_check.log
2022-12-05 18:40:24 - [INFO] - No DRC Violations found
2022-12-05 18:40:24 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 18:40:24 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'fpga_programming_management_unit/jobs/mpw_precheck/57850534-f8fc-4dbd-933d-9683190ed5e8/logs'
2022-12-05 18:40:24 - [INFO] - {{SUCCESS}} All Checks Passed !!!