Add verilog/dv/{dhrystone,jtag}
diff --git a/verilog/dv/dhrystone/Makefile b/verilog/dv/dhrystone/Makefile
new file mode 100644
index 0000000..0a7e211
--- /dev/null
+++ b/verilog/dv/dhrystone/Makefile
@@ -0,0 +1,55 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# RTL/GL/GL_SDF
+export SIM ?= RTL
+
+# Questa only
+SIMULATOR = Questa
+
+export TARGET_PATH = $(MARMOT_ROOT)
+export DESIGNS = $(TARGET_PATH)
+export CARAVEL_ROOT = $(TARGET_PATH)/caravel
+export MCW_ROOT = $(TARGET_PATH)/mgmt_core_wrapper
+export CORE_VERILOG_PATH = $(MCW_ROOT)/verilog
+#export PDK_ROOT = $(PDK_ROOT)
+#export PDK = $(PDK)
+export TOOLS = $(RISCV)
+export GCC_PREFIX = riscv64-unknown-linux-gnu
+
+TESTCASE_DIR = $(HOME)/Development/RISC-V/chipyard/vlsi/sim/testcase
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include ../make/sim.makefile
+
+setup:
+ echo "// $(TESTCASE_DIR)/dhrystone-2.1/gcc_dry2reg_flash.mem" > spi_flash.mem
+ cat $(TESTCASE_DIR)/dhrystone-2.1/gcc_dry2reg_flash.mem >> spi_flash.mem
+ cp $(TESTCASE_DIR)/dhrystone-2.1/gcc_dry2reg_flash.lis spi_flash.lis
+ cp $(TESTCASE_DIR)/dhrystone-2.1/Proc_6_pc_flash.v .
+
+wave:
+ vsim -gui vsim.wlf -do wave.do &
+
diff --git a/verilog/dv/dhrystone/Proc_6_pc_flash.v b/verilog/dv/dhrystone/Proc_6_pc_flash.v
new file mode 100644
index 0000000..7db9caa
--- /dev/null
+++ b/verilog/dv/dhrystone/Proc_6_pc_flash.v
@@ -0,0 +1 @@
+`define Proc_6 32'h2000023a
diff --git a/verilog/dv/dhrystone/dhrystone.c b/verilog/dv/dhrystone/dhrystone.c
new file mode 100644
index 0000000..0ca3628
--- /dev/null
+++ b/verilog/dv/dhrystone/dhrystone.c
@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+#define MARMOT_ICACHE_TAG_RAM_CLK_DELAY 2
+#define MARMOT_ICACHE_DATA_RAM0_CLK_DELAY 5
+#define MARMOT_ICACHE_DATA_RAM1_CLK_DELAY 4
+#define MARMOT_ICACHE_DATA_RAM2_CLK_DELAY 1
+#define MARMOT_ICACHE_DATA_RAM3_CLK_DELAY 3
+
+void main()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spi_enable = 1;
+ reg_wb_enable = 1;
+ //reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // All GPIO pins are configured to be bi-directional for Marmot use
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+
+#if 0
+ // For actual use
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+#else
+ // For simulation
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+#endif
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ //reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ //reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ //reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ //reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ //reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Initialize LA probes [127:0]
+ // Input:
+ // [31: 0] <- Marmot.gpio_out[31:0]
+ // Output:
+ // [31: 0] -> Marmot.gpio_in[31:0]
+ // [63:32] -> Marmot.ram_clk_delay_sel[31:0]
+ // [ 4: 0] -> u_clk_skew_adjust_0.sel[4:0] (I-$ Tag RAM)
+ // [ 9: 5] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM0)
+ // [14:10] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM1)
+ // [19:15] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM2)
+ // [24:20] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM3)
+
+ reg_la0_oenb = reg_la0_iena = 0xffffffff; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0xffffffff; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0xffffffff; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0xffffffff; // [127:96]
+ reg_la0_data = 0xffffffff;
+ reg_la1_data = 0xffffffff;
+ reg_la2_data = 0xffffffff;
+ reg_la3_data = 0xffffffff;
+ reg_la0_data = 0x00000000;
+ reg_la1_data = 0x00000000;
+ reg_la2_data = 0x00000000;
+ reg_la3_data = 0x00000000;
+
+ // Configure LA probes [31:0] as inputs to mgmt_soc
+ reg_la0_iena = 0x00000000; // [31:0] <- Marmot.gpio_out[31:0]
+
+ // Set clock delay for Marmot RAMs
+ reg_la1_data = (MARMOT_ICACHE_TAG_RAM_CLK_DELAY)
+ | (MARMOT_ICACHE_DATA_RAM0_CLK_DELAY << 5)
+ | (MARMOT_ICACHE_DATA_RAM1_CLK_DELAY << 10)
+ | (MARMOT_ICACHE_DATA_RAM2_CLK_DELAY << 15)
+ | (MARMOT_ICACHE_DATA_RAM3_CLK_DELAY << 20);
+
+ // Start Marmot
+ reg_mprj_slave = 0x00000001;
+
+ // Wait for Marmot to finish and check result
+ while (1) {
+ reg_la0_data ^= 0xffffffff;
+
+ if ((reg_la0_data_in & 0xc0000000) != 0x0) {
+ if ((reg_la0_data_in & 0xc0000000) == 0x80000000) {
+ reg_mprj_datal = 0x12340000; // Pass
+ } else {
+ reg_mprj_datal = 0xdead0000; // Fail
+ }
+ break;
+ }
+ }
+}
diff --git a/verilog/dv/dhrystone/dhrystone_tb.v b/verilog/dv/dhrystone/dhrystone_tb.v
new file mode 100644
index 0000000..17f486c
--- /dev/null
+++ b/verilog/dv/dhrystone/dhrystone_tb.v
@@ -0,0 +1,386 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 100 ps
+
+`define TB testbench
+`define CARAVEL `TB.uut
+`define USER_PROJECT_WRAPPER `CARAVEL.mprj
+`define MARMOT `USER_PROJECT_WRAPPER.Marmot
+`define CHIP `MARMOT.MarmotCaravelChip
+`define PLATFORM `CHIP.dut
+`define SYS `PLATFORM.sys
+`define TILE `SYS.tile_prci_domain.tile_reset_domain.tile
+`define CORE `TILE.core
+`define UART0 `SYS.uartClockDomainWrapper.uart_0
+`define UART1 `SYS.uartClockDomainWrapper_1.uart_1
+`define UART2 `SYS.uartClockDomainWrapper_2.uart_2
+`define UART3 `SYS.uartClockDomainWrapper_3.uart_3
+`define UART4 `SYS.uartClockDomainWrapper_4.uart_4
+`define TLSPIRAM `SYS.qspiClockDomainWrapper_1.qspi_ram_0
+
+module testbench;
+ `include "io_mapping.v"
+
+ localparam CLOCK_PERIOD = 40; // ns
+ localparam TCK_PERIOD = 100;
+ localparam MAX_CYCLE = 200000;
+ localparam MAX_EXCEPTION_PC_COUNT = 100;
+
+ reg clock;
+ wire clock_wire = clock;
+ reg RSTB;
+ reg tck;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ wire reset = `MARMOT.wb_rst_i;
+
+`ifdef SIM
+ wire [31:0] PC = `CORE.coreMonitorBundle_pc;
+`else
+ wire [31:0] PC = {
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[31] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[30] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[29] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[28] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[27] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[26] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[25] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[24] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[23] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[22] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[21] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[20] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[19] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[18] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[17] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[16] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[15] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[14] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[13] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[12] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[11] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[10] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[9] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[8] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[7] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[6] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[5] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[4] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[3] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[2] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[1] ,
+ 1'b0};
+`endif
+
+//-------------------------------------------------------------------------------
+// Timeformat
+ initial begin
+ $timeformat(-9, 0, " ns", 12);
+ end
+
+//-------------------------------------------------------------------------------
+// Pull-up
+`ifdef PULLUP_IO
+ genvar gen_i;
+ generate
+ for (gen_i = 0; gen_i < 38; gen_i = gen_i + 1) begin
+ pullup(mprj_io[gen_i]);
+ end
+ endgenerate
+`endif
+
+//-------------------------------------------------------------------------------
+// Clock
+ initial begin
+ clock = 0;
+ tck = 0;
+ end
+
+ always #(CLOCK_PERIOD/2) clock <= (clock === 1'b0);
+ always #(TCK_PERIOD/2) tck <= (tck === 1'b0);
+
+//-------------------------------------------------------------------------------
+// Waveform
+ initial begin
+ if ($test$plusargs("waveform")) begin
+ $dumpfile("wave.vcd");
+ $dumpvars(0, `TB);
+ end
+ end
+
+//-------------------------------------------------------------------------------
+// Initialize FFs for gate level sim.
+`ifdef GL
+ `include "init_ff.v"
+`endif
+
+//-------------------------------------------------------------------------------
+// SDF annotate
+`ifdef ENABLE_SDF
+ initial begin
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", `CARAVEL.soc.DFFRAM_0 );
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", `CARAVEL.soc.core);
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core_wrapper.sdf", `CARAVEL.soc);
+ $sdf_annotate("../../../sdf/user_project_wrapper.sdf.gz", `USER_PROJECT_WRAPPER);
+ $sdf_annotate("../../../sdf/Marmot.sdf.gz", `MARMOT);
+ end
+`endif
+
+//-------------------------------------------------------------------------------
+// Count cycle
+ reg [31:0] cycle;
+ initial begin
+ cycle = 0;
+ end
+
+ always @(posedge clock) begin
+ cycle = cycle + 1;
+ end
+
+//-------------------------------------------------------------------------------
+// Monitor PC
+ integer exception_pc_count;
+
+ always @ (posedge clock) begin
+ if ($test$plusargs("pc_monitor")) begin
+ if (cycle % 1000 == 0) begin
+ $fwrite(32'h80000002, "[%t] %10d pc=%08x\n", $time, cycle, PC);
+ end
+ end
+
+ // Finish on PC=x
+ //if (^PC === 1'bx) begin
+ // $display("[%t] PC=xxxxxxxx", $time);
+ // repeat (50) @(posedge clock);
+ // $finish;
+ //end
+
+ // Finish on exception
+ if (PC == 32'h00000000 || PC == 32'h00000002) begin
+ exception_pc_count <= exception_pc_count + 1;
+ if (exception_pc_count > MAX_EXCEPTION_PC_COUNT) begin
+ $display("[%t] Exception occurred.", $time);
+ $finish;
+ end
+ end
+ else begin
+ exception_pc_count <= 0;
+ end
+ end
+
+//-------------------------------------------------------------------------------
+// Timeout
+ reg [31:0] max_cycle;
+ initial begin
+ if (! $value$plusargs("max_cycle=%d", max_cycle)) begin
+ max_cycle = MAX_CYCLE;
+ end
+
+ wait (reset === 1'b0);
+ wait (cycle < 10);
+ wait (cycle >= max_cycle);
+ $display("\n*** Timeout ***");
+ $finish;
+ end
+
+//-------------------------------------------------------------------------------
+// Pass
+ initial begin
+ wait (mprj_io[31:28] == 4'h1);
+ $display("\n*** Test Pass ***");
+ $finish;
+ end
+
+//-------------------------------------------------------------------------------
+// Fail
+ initial begin
+ wait (mprj_io[31:28] == 4'hd);
+ $display("\n*** Test Fail ***");
+ $finish;
+ end
+
+//-------------------------------------------------------------------------------
+// Reset
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+//-------------------------------------------------------------------------------
+// Power-up sequence
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1; // Force CSB high.
+ assign mprj_io[0] = 0; // Disable debug mode
+
+//-------------------------------------------------------------------------------
+// JTAG
+ assign mprj_io[io_TCK] = tck;
+ //assign mprj_io[io_TMS] = 1; // same pin as CSB
+ assign mprj_io[io_TDI] = 0;
+
+//-------------------------------------------------------------------------------
+// Caravel
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock_wire),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+//-------------------------------------------------------------------------------
+// SPI Flash for Mgmt. SoC
+ spiflash #(
+ .FILENAME(`MGMT_SOC_PROG)
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(),
+ .io3()
+ );
+
+//-------------------------------------------------------------------------------
+// SPI Flash model for Marmot
+MX25U3235F #(.Init_File("spi_flash.mem")) spi_flash
+(
+ .SCLK (mprj_io[io_spi0_flash_sck]),
+ .CS (mprj_io[io_spi0_flash_csb]),
+ .SI (mprj_io[io_spi0_flash_io_0]),
+ .SO (mprj_io[io_spi0_flash_io_1]),
+ .WP (mprj_io[io_spi0_flash_io_2]),
+ .SIO3 (mprj_io[io_spi0_flash_io_3])
+);
+
+//-------------------------------------------------------------------------------
+// SPI RAM model (APM APS6404L-3SQN_SQPI_PSRAM)
+`ifdef SIMULATOR_QUESTA
+sqpi_model #(.VeriOutStr(1), .STOP_ON_ERROR(0)) spi_ram
+(
+ .SCK_i (mprj_io[io_spi2_sck]),
+ .nCE_i (mprj_io[io_spi2_csb]),
+ .SI_io (mprj_io[io_spi2_io_0]),
+ .SO_io (mprj_io[io_spi2_io_1]),
+ .nWP_io (mprj_io[io_spi2_io_2]),
+ .NC_io (mprj_io[io_spi2_io_3])
+);
+`else
+// SPI Flash model
+MX25U3235F spi_ram
+(
+ .SCLK (mprj_io[io_spi2_sck]),
+ .CS (mprj_io[io_spi2_csb]),
+ .SI (mprj_io[io_spi2_io_0]),
+ .SO (mprj_io[io_spi2_io_1]),
+ .WP (mprj_io[io_spi2_io_2]),
+ .SIO3 (mprj_io[io_spi2_io_3])
+);
+`endif
+
+//-------------------------------------------------------------------------------
+// UART model for Marmot
+`ifdef UART_HIGH_SPEED
+ `define CLKS_PER_BIT 16 // F_CLK / 16 baud
+`else
+ `define CLKS_PER_BIT ((1000/CLOCK_PERIOD)*1000000 / 115200) // 115200 baud
+ //`define CLKS_PER_BIT 104 // 12MHz / 115200 baud
+`endif
+
+uart_tb #(.CLKS_PER_BIT(`CLKS_PER_BIT)) uart0_tb
+(
+ .clk (clock_wire),
+ .rst (~RSTB),
+ .rxd (mprj_io[io_uart0_tx]),
+ .txd (mprj_io[io_uart0_rx])
+);
+
+//-------------------------------------------------------------------------------
+// Count cycles of each loop
+`include "Proc_6_pc_flash.v"
+
+reg [31:0] pc_prev;
+reg [31:0] loop_cycle;
+
+initial begin
+ pc_prev = 0;
+ loop_cycle = 0;
+end
+
+always @(posedge clock) begin
+ if (RSTB) begin
+ if ((PC != pc_prev) && (PC === `Proc_6)) begin
+ $fwrite(32'h80000002, "[%t] %10d pc=Proc_6(%08x), %d cycles\n", $time, cycle, PC, loop_cycle);
+ loop_cycle = 0;
+ end
+ pc_prev = PC;
+ loop_cycle = loop_cycle + 1;
+ end
+end
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/dhrystone/io_mapping.v b/verilog/dv/dhrystone/io_mapping.v
new file mode 100644
index 0000000..fcd74b5
--- /dev/null
+++ b/verilog/dv/dhrystone/io_mapping.v
@@ -0,0 +1,52 @@
+localparam io_TDO = 1;
+localparam io_TDI = 2;
+localparam io_TMS = 3;
+localparam io_TCK = 4;
+localparam io_uart0_rx = 5;
+localparam io_uart0_tx = 6;
+localparam io_spi1_csb_1 = 7;
+localparam io_spi0_flash_csb = 8;
+localparam io_spi0_flash_sck = 9;
+localparam io_spi0_flash_io_0 = 10;
+localparam io_spi0_flash_io_1 = 11;
+localparam io_spi0_flash_io_2 = 12;
+localparam io_spi0_flash_io_3 = 13;
+localparam io_spi1_csb_0 = 14;
+localparam io_spi1_sck = 15;
+localparam io_spi1_io_0 = 16;
+localparam io_spi1_io_1 = 17;
+localparam io_spi1_io_2 = 18;
+localparam io_spi1_io_3 = 19;
+localparam io_spi2_csb = 20;
+localparam io_spi2_sck = 21;
+localparam io_spi2_io_0 = 22;
+localparam io_spi2_io_1 = 23;
+localparam io_spi2_io_2 = 24;
+localparam io_spi2_io_3 = 25;
+localparam io_i2c0_sda = 26;
+localparam io_i2c0_scl = 27;
+localparam io_i2c1_sda = 28;
+localparam io_i2c1_scl = 29;
+localparam io_uart1_rx = 30;
+localparam io_uart1_tx = 31;
+localparam io_uart2_rx = 32;
+localparam io_uart2_tx = 33;
+localparam io_uart3_rx = 34;
+localparam io_uart3_tx = 35;
+localparam io_uart4_rx = 36;
+localparam io_uart4_tx = 37;
+
+// IOF1
+localparam io_pwm0_0 = 26;
+localparam io_pwm0_1 = 27;
+localparam io_pwm0_2 = 28;
+localparam io_pwm0_3 = 29;
+localparam io_pwm1_0 = 30;
+localparam io_pwm1_1 = 31;
+localparam io_pwm1_2 = 32;
+localparam io_pwm1_3 = 33;
+localparam io_pwm2_0 = 34;
+localparam io_pwm2_1 = 35;
+localparam io_pwm2_2 = 36;
+localparam io_pwm2_3 = 37;
+
diff --git a/verilog/dv/dhrystone/run_sim.csh b/verilog/dv/dhrystone/run_sim.csh
new file mode 100755
index 0000000..0361397
--- /dev/null
+++ b/verilog/dv/dhrystone/run_sim.csh
@@ -0,0 +1,27 @@
+#!/bin/csh -f
+
+# RTL/GL
+set sim = RTL
+#set sim = GL
+
+# Simulator (Questa is needed for AP Memory's encrypted QSPI-PSRAM model)
+set simulator = Questa
+
+# Compile option
+set mgmt_soc_prog = \\\"dhrystone.hex\\\"
+set compopt = "+define+MGMT_SOC_PROG=$mgmt_soc_prog"
+set compopt = "$compopt +define+PRINTF_COND=0" # 0 = stop instruction trace
+
+# Simulation option
+set simopt =
+#set simopt = "$simopt +waveform"
+set simopt = "$simopt +pc_monitor"
+#set simopt = "$simopt +max_cycle=200000"
+
+# Do
+set doopt = ""
+#set doopt = "log -r /testbench/* ;" # waveform
+
+make SIMULATOR=$simulator SIM=$sim USER_COMPOPT="$compopt" USER_SIMOPT="$simopt" DOOPT="$doopt" \
+ |& spike-dasm | egrep -v '\[0\] pc=' | tee sim_${sim}.log
+
diff --git a/verilog/dv/dhrystone/spi_flash.lis b/verilog/dv/dhrystone/spi_flash.lis
new file mode 100644
index 0000000..57adb4c
--- /dev/null
+++ b/verilog/dv/dhrystone/spi_flash.lis
@@ -0,0 +1,3040 @@
+
+gcc_dry2reg_flash.elf: file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+20000000 <_start>:
+20000000: 00000093 li ra,0
+20000004: 00000113 li sp,0
+20000008: 00000193 li gp,0
+2000000c: 00000213 li tp,0
+20000010: 00000293 li t0,0
+20000014: 00000313 li t1,0
+20000018: 00000393 li t2,0
+2000001c: 00000413 li s0,0
+20000020: 00000493 li s1,0
+20000024: 00000513 li a0,0
+20000028: 00000593 li a1,0
+2000002c: 00000613 li a2,0
+20000030: 00000693 li a3,0
+20000034: 00000713 li a4,0
+20000038: 00000793 li a5,0
+2000003c: 00000813 li a6,0
+20000040: 00000893 li a7,0
+20000044: 00000913 li s2,0
+20000048: 00000993 li s3,0
+2000004c: 00000a13 li s4,0
+20000050: 00000a93 li s5,0
+20000054: 00000b13 li s6,0
+20000058: 00000b93 li s7,0
+2000005c: 00000c13 li s8,0
+20000060: 00000c93 li s9,0
+20000064: 00000d13 li s10,0
+20000068: 00000d93 li s11,0
+2000006c: 00000e13 li t3,0
+20000070: 00000e93 li t4,0
+20000074: 00000f13 li t5,0
+20000078: 00000f93 li t6,0
+2000007c: 08002137 lui sp,0x8002
+20000080: ff010113 addi sp,sp,-16 # 8001ff0 <_stack>
+20000084: 2475 jal 20000330 <init>
+ ...
+
+200000c6 <Proc_2>:
+200000c6: 20003717 auipc a4,0x20003
+200000ca: f7b74703 lbu a4,-133(a4) # 40003041 <Ch_1_Glob>
+200000ce: 04100793 li a5,65
+200000d2: 00f70363 beq a4,a5,200000d8 <Proc_2+0x12>
+200000d6: 8082 ret
+200000d8: 411c lw a5,0(a0)
+200000da: 20003717 auipc a4,0x20003
+200000de: f6e72703 lw a4,-146(a4) # 40003048 <Int_Glob>
+200000e2: 07a5 addi a5,a5,9
+200000e4: 8f99 sub a5,a5,a4
+200000e6: c11c sw a5,0(a0)
+200000e8: 8082 ret
+
+200000ea <Proc_3>:
+200000ea: 20003797 auipc a5,0x20003
+200000ee: f6678793 addi a5,a5,-154 # 40003050 <Ptr_Glob>
+200000f2: 4390 lw a2,0(a5)
+200000f4: c601 beqz a2,200000fc <Proc_3+0x12>
+200000f6: 4218 lw a4,0(a2)
+200000f8: c118 sw a4,0(a0)
+200000fa: 4390 lw a2,0(a5)
+200000fc: 0631 addi a2,a2,12
+200000fe: 20003597 auipc a1,0x20003
+20000102: f4a5a583 lw a1,-182(a1) # 40003048 <Int_Glob>
+20000106: 4529 li a0,10
+20000108: a2bd j 20000276 <Proc_7>
+
+2000010a <Proc_1>:
+2000010a: 1141 addi sp,sp,-16
+2000010c: c04a sw s2,0(sp)
+2000010e: 20003917 auipc s2,0x20003
+20000112: f4290913 addi s2,s2,-190 # 40003050 <Ptr_Glob>
+20000116: 00092783 lw a5,0(s2)
+2000011a: c422 sw s0,8(sp)
+2000011c: 4100 lw s0,0(a0)
+2000011e: 4398 lw a4,0(a5)
+20000120: 0047ae83 lw t4,4(a5)
+20000124: 0087ae03 lw t3,8(a5)
+20000128: 0107a303 lw t1,16(a5)
+2000012c: 0147a883 lw a7,20(a5)
+20000130: 0187a803 lw a6,24(a5)
+20000134: 538c lw a1,32(a5)
+20000136: 53d0 lw a2,36(a5)
+20000138: 5794 lw a3,40(a5)
+2000013a: c226 sw s1,4(sp)
+2000013c: c606 sw ra,12(sp)
+2000013e: 84aa mv s1,a0
+20000140: 4fc8 lw a0,28(a5)
+20000142: 57dc lw a5,44(a5)
+20000144: c018 sw a4,0(s0)
+20000146: 4098 lw a4,0(s1)
+20000148: cc48 sw a0,28(s0)
+2000014a: d45c sw a5,44(s0)
+2000014c: 01d42223 sw t4,4(s0)
+20000150: 4795 li a5,5
+20000152: 01c42423 sw t3,8(s0)
+20000156: 00642823 sw t1,16(s0)
+2000015a: 01142a23 sw a7,20(s0)
+2000015e: 01042c23 sw a6,24(s0)
+20000162: d00c sw a1,32(s0)
+20000164: d050 sw a2,36(s0)
+20000166: d414 sw a3,40(s0)
+20000168: c4dc sw a5,12(s1)
+2000016a: c45c sw a5,12(s0)
+2000016c: c018 sw a4,0(s0)
+2000016e: 8522 mv a0,s0
+20000170: 3fad jal 200000ea <Proc_3>
+20000172: 405c lw a5,4(s0)
+20000174: cfb1 beqz a5,200001d0 <Proc_1+0xc6>
+20000176: 409c lw a5,0(s1)
+20000178: 40b2 lw ra,12(sp)
+2000017a: 4422 lw s0,8(sp)
+2000017c: 0007af83 lw t6,0(a5)
+20000180: 0047af03 lw t5,4(a5)
+20000184: 0087ae83 lw t4,8(a5)
+20000188: 00c7ae03 lw t3,12(a5)
+2000018c: 0107a303 lw t1,16(a5)
+20000190: 0147a883 lw a7,20(a5)
+20000194: 0187a803 lw a6,24(a5)
+20000198: 4fcc lw a1,28(a5)
+2000019a: 5390 lw a2,32(a5)
+2000019c: 53d4 lw a3,36(a5)
+2000019e: 5798 lw a4,40(a5)
+200001a0: 57dc lw a5,44(a5)
+200001a2: 01f4a023 sw t6,0(s1)
+200001a6: 01e4a223 sw t5,4(s1)
+200001aa: 01d4a423 sw t4,8(s1)
+200001ae: 01c4a623 sw t3,12(s1)
+200001b2: 0064a823 sw t1,16(s1)
+200001b6: 0114aa23 sw a7,20(s1)
+200001ba: 0104ac23 sw a6,24(s1)
+200001be: cccc sw a1,28(s1)
+200001c0: d090 sw a2,32(s1)
+200001c2: d0d4 sw a3,36(s1)
+200001c4: d498 sw a4,40(s1)
+200001c6: d4dc sw a5,44(s1)
+200001c8: 4902 lw s2,0(sp)
+200001ca: 4492 lw s1,4(sp)
+200001cc: 0141 addi sp,sp,16
+200001ce: 8082 ret
+200001d0: 4488 lw a0,8(s1)
+200001d2: 4799 li a5,6
+200001d4: 00840593 addi a1,s0,8
+200001d8: c45c sw a5,12(s0)
+200001da: 2085 jal 2000023a <Proc_6>
+200001dc: 00092783 lw a5,0(s2)
+200001e0: 4448 lw a0,12(s0)
+200001e2: 00c40613 addi a2,s0,12
+200001e6: 439c lw a5,0(a5)
+200001e8: 40b2 lw ra,12(sp)
+200001ea: 4492 lw s1,4(sp)
+200001ec: c01c sw a5,0(s0)
+200001ee: 4422 lw s0,8(sp)
+200001f0: 4902 lw s2,0(sp)
+200001f2: 45a9 li a1,10
+200001f4: 0141 addi sp,sp,16
+200001f6: a041 j 20000276 <Proc_7>
+
+200001f8 <Proc_4>:
+200001f8: 20003717 auipc a4,0x20003
+200001fc: e4c70713 addi a4,a4,-436 # 40003044 <Bool_Glob>
+20000200: 4314 lw a3,0(a4)
+20000202: 20003797 auipc a5,0x20003
+20000206: e3f7c783 lbu a5,-449(a5) # 40003041 <Ch_1_Glob>
+2000020a: fbf78793 addi a5,a5,-65
+2000020e: 0017b793 seqz a5,a5
+20000212: 8fd5 or a5,a5,a3
+20000214: c31c sw a5,0(a4)
+20000216: 04200793 li a5,66
+2000021a: 20003717 auipc a4,0x20003
+2000021e: e2f70323 sb a5,-474(a4) # 40003040 <Ch_2_Glob>
+20000222: 8082 ret
+
+20000224 <Proc_5>:
+20000224: 04100793 li a5,65
+20000228: 20003717 auipc a4,0x20003
+2000022c: e0f70ca3 sb a5,-487(a4) # 40003041 <Ch_1_Glob>
+20000230: 20003797 auipc a5,0x20003
+20000234: e007aa23 sw zero,-492(a5) # 40003044 <Bool_Glob>
+20000238: 8082 ret
+
+2000023a <Proc_6>:
+2000023a: 4709 li a4,2
+2000023c: 02e50a63 beq a0,a4,20000270 <Proc_6+0x36>
+20000240: 478d li a5,3
+20000242: c19c sw a5,0(a1)
+20000244: 4785 li a5,1
+20000246: 00f50963 beq a0,a5,20000258 <Proc_6+0x1e>
+2000024a: 00a7ff63 bgeu a5,a0,20000268 <Proc_6+0x2e>
+2000024e: 4791 li a5,4
+20000250: 00f51f63 bne a0,a5,2000026e <Proc_6+0x34>
+20000254: c198 sw a4,0(a1)
+20000256: 8082 ret
+20000258: 20003717 auipc a4,0x20003
+2000025c: df072703 lw a4,-528(a4) # 40003048 <Int_Glob>
+20000260: 06400793 li a5,100
+20000264: fee7d9e3 bge a5,a4,20000256 <Proc_6+0x1c>
+20000268: 0005a023 sw zero,0(a1)
+2000026c: 8082 ret
+2000026e: 8082 ret
+20000270: 4785 li a5,1
+20000272: c19c sw a5,0(a1)
+20000274: 8082 ret
+
+20000276 <Proc_7>:
+20000276: 0509 addi a0,a0,2
+20000278: 95aa add a1,a1,a0
+2000027a: c20c sw a1,0(a2)
+2000027c: 8082 ret
+
+2000027e <Proc_8>:
+2000027e: 00560713 addi a4,a2,5
+20000282: 0c800813 li a6,200
+20000286: 03070833 mul a6,a4,a6
+2000028a: 060a slli a2,a2,0x2
+2000028c: 00271793 slli a5,a4,0x2
+20000290: 953e add a0,a0,a5
+20000292: c114 sw a3,0(a0)
+20000294: dd38 sw a4,120(a0)
+20000296: c154 sw a3,4(a0)
+20000298: 00c807b3 add a5,a6,a2
+2000029c: 97ae add a5,a5,a1
+2000029e: 4b94 lw a3,16(a5)
+200002a0: cbd8 sw a4,20(a5)
+200002a2: cf98 sw a4,24(a5)
+200002a4: 00168713 addi a4,a3,1
+200002a8: cb98 sw a4,16(a5)
+200002aa: 4118 lw a4,0(a0)
+200002ac: 95c2 add a1,a1,a6
+200002ae: 95b2 add a1,a1,a2
+200002b0: 6785 lui a5,0x1
+200002b2: 95be add a1,a1,a5
+200002b4: 4795 li a5,5
+200002b6: fae5aa23 sw a4,-76(a1)
+200002ba: 20003717 auipc a4,0x20003
+200002be: d8f72723 sw a5,-626(a4) # 40003048 <Int_Glob>
+200002c2: 8082 ret
+
+200002c4 <Func_1>:
+200002c4: 0ff57513 andi a0,a0,255
+200002c8: 0ff5f593 andi a1,a1,255
+200002cc: 00b50463 beq a0,a1,200002d4 <Func_1+0x10>
+200002d0: 4501 li a0,0
+200002d2: 8082 ret
+200002d4: 20003797 auipc a5,0x20003
+200002d8: d6a786a3 sb a0,-659(a5) # 40003041 <Ch_1_Glob>
+200002dc: 4505 li a0,1
+200002de: 8082 ret
+
+200002e0 <Func_2>:
+200002e0: 1141 addi sp,sp,-16
+200002e2: c606 sw ra,12(sp)
+200002e4: 20003817 auipc a6,0x20003
+200002e8: d5d80813 addi a6,a6,-675 # 40003041 <Ch_1_Glob>
+200002ec: 00254783 lbu a5,2(a0)
+200002f0: 0035c703 lbu a4,3(a1)
+200002f4: 00084603 lbu a2,0(a6)
+200002f8: 4681 li a3,0
+200002fa: 02e78463 beq a5,a4,20000322 <Func_2+0x42>
+200002fe: c299 beqz a3,20000304 <Func_2+0x24>
+20000300: 00c80023 sb a2,0(a6)
+20000304: 2fd000ef jal ra,20000e00 <strcmp>
+20000308: 4781 li a5,0
+2000030a: 00a05863 blez a0,2000031a <Func_2+0x3a>
+2000030e: 47a9 li a5,10
+20000310: 20003717 auipc a4,0x20003
+20000314: d2f72c23 sw a5,-712(a4) # 40003048 <Int_Glob>
+20000318: 4785 li a5,1
+2000031a: 40b2 lw ra,12(sp)
+2000031c: 853e mv a0,a5
+2000031e: 0141 addi sp,sp,16
+20000320: 8082 ret
+20000322: 4685 li a3,1
+20000324: 863e mv a2,a5
+20000326: bfd1 j 200002fa <Func_2+0x1a>
+
+20000328 <Func_3>:
+20000328: 1579 addi a0,a0,-2
+2000032a: 00153513 seqz a0,a0
+2000032e: 8082 ret
+
+20000330 <init>:
+20000330: e8000517 auipc a0,0xe8000
+20000334: cd050513 addi a0,a0,-816 # 8000000 <spi_quad_mode>
+20000338: e8000617 auipc a2,0xe8000
+2000033c: d3c60613 addi a2,a2,-708 # 8000074 <itim_end>
+20000340: 1141 addi sp,sp,-16
+20000342: 8e09 sub a2,a2,a0
+20000344: 00001597 auipc a1,0x1
+20000348: 34258593 addi a1,a1,834 # 20001686 <itim_load_start>
+2000034c: c606 sw ra,12(sp)
+2000034e: 22d000ef jal ra,20000d7a <memcpy>
+20000352: 10014537 lui a0,0x10014
+20000356: e8000097 auipc ra,0xe8000
+2000035a: caa080e7 jalr -854(ra) # 8000000 <spi_quad_mode>
+2000035e: 10034537 lui a0,0x10034
+20000362: e8000097 auipc ra,0xe8000
+20000366: c9e080e7 jalr -866(ra) # 8000000 <spi_quad_mode>
+2000036a: 000977b7 lui a5,0x97
+2000036e: 10034737 lui a4,0x10034
+20000372: a0278793 addi a5,a5,-1534 # 96a02 <spi_quad_mode-0x7f695fe>
+20000376: 20000517 auipc a0,0x20000
+2000037a: c8a50513 addi a0,a0,-886 # 40000000 <rodata_start>
+2000037e: 20000617 auipc a2,0x20000
+20000382: 4c260613 addi a2,a2,1218 # 40000840 <rodata_end>
+20000386: d73c sw a5,104(a4)
+20000388: 8e09 sub a2,a2,a0
+2000038a: 00001597 auipc a1,0x1
+2000038e: 37058593 addi a1,a1,880 # 200016fa <rodata_load_start>
+20000392: 1e9000ef jal ra,20000d7a <memcpy>
+20000396: 20000517 auipc a0,0x20000
+2000039a: 4aa50513 addi a0,a0,1194 # 40000840 <rodata_end>
+2000039e: 20000617 auipc a2,0x20000
+200003a2: 4a660613 addi a2,a2,1190 # 40000844 <data_end>
+200003a6: 8e09 sub a2,a2,a0
+200003a8: 00002597 auipc a1,0x2
+200003ac: b9258593 addi a1,a1,-1134 # 20001f3a <data_load_start>
+200003b0: 1cb000ef jal ra,20000d7a <memcpy>
+200003b4: 20000517 auipc a0,0x20000
+200003b8: 49050513 addi a0,a0,1168 # 40000844 <data_end>
+200003bc: 20003617 auipc a2,0x20003
+200003c0: ca860613 addi a2,a2,-856 # 40003064 <_end>
+200003c4: 8e09 sub a2,a2,a0
+200003c6: 4581 li a1,0
+200003c8: 199000ef jal ra,20000d60 <memset>
+200003cc: 4585 li a1,1
+200003ce: 4501 li a0,0
+200003d0: 0f1000ef jal ra,20000cc0 <serial_init>
+200003d4: 4e7000ef jal ra,200010ba <main>
+200003d8: 100127b7 lui a5,0x10012
+200003dc: 5f98 lw a4,56(a5)
+200003de: c00006b7 lui a3,0xc0000
+200003e2: 070a slli a4,a4,0x2
+200003e4: 8309 srli a4,a4,0x2
+200003e6: df98 sw a4,56(a5)
+200003e8: 4798 lw a4,8(a5)
+200003ea: 8f55 or a4,a4,a3
+200003ec: c798 sw a4,8(a5)
+200003ee: 80000737 lui a4,0x80000
+200003f2: c7d8 sw a4,12(a5)
+200003f4: a001 j 200003f4 <init+0xc4>
+
+200003f6 <number>:
+200003f6: 711d addi sp,sp,-96
+200003f8: cea2 sw s0,92(sp)
+200003fa: cca6 sw s1,88(sp)
+200003fc: 0407f813 andi a6,a5,64
+20000400: 20000e17 auipc t3,0x20000
+20000404: 3fce0e13 addi t3,t3,1020 # 400007fc <uart_ctrl_addr+0x5f8>
+20000408: 00081663 bnez a6,20000414 <number+0x1e>
+2000040c: 20000e17 auipc t3,0x20000
+20000410: 3c8e0e13 addi t3,t3,968 # 400007d4 <uart_ctrl_addr+0x5d0>
+20000414: 0107f413 andi s0,a5,16
+20000418: 14040263 beqz s0,2000055c <number+0x166>
+2000041c: 9bf9 andi a5,a5,-2
+2000041e: 84a2 mv s1,s0
+20000420: 0027f813 andi a6,a5,2
+20000424: 02000f93 li t6,32
+20000428: 0207f393 andi t2,a5,32
+2000042c: 14080663 beqz a6,20000578 <number+0x182>
+20000430: 1405c663 bltz a1,2000057c <number+0x186>
+20000434: 0047f813 andi a6,a5,4
+20000438: 16081c63 bnez a6,200005b0 <number+0x1ba>
+2000043c: 8ba1 andi a5,a5,8
+2000043e: 4281 li t0,0
+20000440: c781 beqz a5,20000448 <number+0x52>
+20000442: 16fd addi a3,a3,-1
+20000444: 02000293 li t0,32
+20000448: 00038a63 beqz t2,2000045c <number+0x66>
+2000044c: 47c1 li a5,16
+2000044e: 16f60f63 beq a2,a5,200005cc <number+0x1d6>
+20000452: ff860793 addi a5,a2,-8
+20000456: 0017b793 seqz a5,a5
+2000045a: 8e9d sub a3,a3,a5
+2000045c: 12059763 bnez a1,2000058a <number+0x194>
+20000460: 03000793 li a5,48
+20000464: 00f10623 sb a5,12(sp)
+20000468: 4301 li t1,0
+2000046a: 03000813 li a6,48
+2000046e: 4885 li a7,1
+20000470: 007c addi a5,sp,12
+20000472: 8ec6 mv t4,a7
+20000474: 00e8d363 bge a7,a4,2000047a <number+0x84>
+20000478: 8eba mv t4,a4
+2000047a: 41d68e33 sub t3,a3,t4
+2000047e: fffe0593 addi a1,t3,-1
+20000482: ec91 bnez s1,2000049e <number+0xa8>
+20000484: 01c506b3 add a3,a0,t3
+20000488: 02000713 li a4,32
+2000048c: 15c05a63 blez t3,200005e0 <number+0x1ea>
+20000490: 0505 addi a0,a0,1
+20000492: fee50fa3 sb a4,-1(a0)
+20000496: fed51de3 bne a0,a3,20000490 <number+0x9a>
+2000049a: 55f9 li a1,-2
+2000049c: 5e7d li t3,-1
+2000049e: 00028563 beqz t0,200004a8 <number+0xb2>
+200004a2: 00550023 sb t0,0(a0)
+200004a6: 0505 addi a0,a0,1
+200004a8: 00038863 beqz t2,200004b8 <number+0xc2>
+200004ac: 4721 li a4,8
+200004ae: 12e60163 beq a2,a4,200005d0 <number+0x1da>
+200004b2: 4741 li a4,16
+200004b4: 10e60263 beq a2,a4,200005b8 <number+0x1c2>
+200004b8: e80d bnez s0,200004ea <number+0xf4>
+200004ba: 862a mv a2,a0
+200004bc: 4705 li a4,1
+200004be: 13c05663 blez t3,200005ea <number+0x1f4>
+200004c2: 0605 addi a2,a2,1
+200004c4: 40c706b3 sub a3,a4,a2
+200004c8: 96ae add a3,a3,a1
+200004ca: 96aa add a3,a3,a0
+200004cc: fff60fa3 sb t6,-1(a2)
+200004d0: fed049e3 bgtz a3,200004c2 <number+0xcc>
+200004d4: fff5c713 not a4,a1
+200004d8: 877d srai a4,a4,0x1f
+200004da: 8f6d and a4,a4,a1
+200004dc: 15fd addi a1,a1,-1
+200004de: 40e58e33 sub t3,a1,a4
+200004e2: 0705 addi a4,a4,1
+200004e4: 953a add a0,a0,a4
+200004e6: fffe0593 addi a1,t3,-1
+200004ea: 411e8733 sub a4,t4,a7
+200004ee: 972a add a4,a4,a0
+200004f0: 03000693 li a3,48
+200004f4: 0fd8d463 bge a7,t4,200005dc <number+0x1e6>
+200004f8: 0505 addi a0,a0,1
+200004fa: fed50fa3 sb a3,-1(a0)
+200004fe: fea71de3 bne a4,a0,200004f8 <number+0x102>
+20000502: 00678633 add a2,a5,t1
+20000506: 86ba mv a3,a4
+20000508: 4505 li a0,1
+2000050a: a019 j 20000510 <number+0x11a>
+2000050c: 00064803 lbu a6,0(a2)
+20000510: 0685 addi a3,a3,1
+20000512: 40d507b3 sub a5,a0,a3
+20000516: 979a add a5,a5,t1
+20000518: 97ba add a5,a5,a4
+2000051a: ff068fa3 sb a6,-1(a3) # bfffffff <_end+0x7fffcf9b>
+2000051e: 167d addi a2,a2,-1
+20000520: fef046e3 bgtz a5,2000050c <number+0x116>
+20000524: 00130513 addi a0,t1,1
+20000528: 953a add a0,a0,a4
+2000052a: 03c05563 blez t3,20000554 <number+0x15e>
+2000052e: 872a mv a4,a0
+20000530: 02000613 li a2,32
+20000534: 4685 li a3,1
+20000536: 0705 addi a4,a4,1
+20000538: 40e687b3 sub a5,a3,a4
+2000053c: 97ae add a5,a5,a1
+2000053e: 97aa add a5,a5,a0
+20000540: fec70fa3 sb a2,-1(a4) # 7fffffff <_end+0x3fffcf9b>
+20000544: fef049e3 bgtz a5,20000536 <number+0x140>
+20000548: fff5c793 not a5,a1
+2000054c: 87fd srai a5,a5,0x1f
+2000054e: 8dfd and a1,a1,a5
+20000550: 0585 addi a1,a1,1
+20000552: 952e add a0,a0,a1
+20000554: 4476 lw s0,92(sp)
+20000556: 44e6 lw s1,88(sp)
+20000558: 6125 addi sp,sp,96
+2000055a: 8082 ret
+2000055c: 0017f813 andi a6,a5,1
+20000560: 0117f493 andi s1,a5,17
+20000564: 03000f93 li t6,48
+20000568: ea080ce3 beqz a6,20000420 <number+0x2a>
+2000056c: 0027f813 andi a6,a5,2
+20000570: 0207f393 andi t2,a5,32
+20000574: ea081ee3 bnez a6,20000430 <number+0x3a>
+20000578: 4281 li t0,0
+2000057a: b5f9 j 20000448 <number+0x52>
+2000057c: 40b005b3 neg a1,a1
+20000580: 16fd addi a3,a3,-1
+20000582: 02d00293 li t0,45
+20000586: ec0393e3 bnez t2,2000044c <number+0x56>
+2000058a: 4881 li a7,0
+2000058c: 007c addi a5,sp,12
+2000058e: 02c5f833 remu a6,a1,a2
+20000592: 8346 mv t1,a7
+20000594: 0885 addi a7,a7,1
+20000596: 01178f33 add t5,a5,a7
+2000059a: 8eae mv t4,a1
+2000059c: 9872 add a6,a6,t3
+2000059e: 00084803 lbu a6,0(a6)
+200005a2: 02c5d5b3 divu a1,a1,a2
+200005a6: ff0f0fa3 sb a6,-1(t5)
+200005aa: fecef2e3 bgeu t4,a2,2000058e <number+0x198>
+200005ae: b5d1 j 20000472 <number+0x7c>
+200005b0: 16fd addi a3,a3,-1
+200005b2: 02b00293 li t0,43
+200005b6: bd49 j 20000448 <number+0x52>
+200005b8: 03000713 li a4,48
+200005bc: 00e50023 sb a4,0(a0)
+200005c0: 07800713 li a4,120
+200005c4: 00e500a3 sb a4,1(a0)
+200005c8: 0509 addi a0,a0,2
+200005ca: b5fd j 200004b8 <number+0xc2>
+200005cc: 16f9 addi a3,a3,-2
+200005ce: b579 j 2000045c <number+0x66>
+200005d0: 03000713 li a4,48
+200005d4: 00e50023 sb a4,0(a0)
+200005d8: 0505 addi a0,a0,1
+200005da: bdf9 j 200004b8 <number+0xc2>
+200005dc: 872a mv a4,a0
+200005de: b715 j 20000502 <number+0x10c>
+200005e0: ffee0713 addi a4,t3,-2
+200005e4: 8e2e mv t3,a1
+200005e6: 85ba mv a1,a4
+200005e8: bd5d j 2000049e <number+0xa8>
+200005ea: 8e2e mv t3,a1
+200005ec: 15fd addi a1,a1,-1
+200005ee: bdf5 j 200004ea <number+0xf4>
+
+200005f0 <uart_send_char>:
+200005f0: 85aa mv a1,a0
+200005f2: 4501 li a0,0
+200005f4: af19 j 20000d0a <serial_send_byte>
+
+200005f6 <ee_printf>:
+200005f6: 7149 addi sp,sp,-368
+200005f8: 13612823 sw s6,304(sp)
+200005fc: 14112623 sw ra,332(sp)
+20000600: 14812423 sw s0,328(sp)
+20000604: 14912223 sw s1,324(sp)
+20000608: 15212023 sw s2,320(sp)
+2000060c: 13312e23 sw s3,316(sp)
+20000610: 13412c23 sw s4,312(sp)
+20000614: 13512a23 sw s5,308(sp)
+20000618: 13712623 sw s7,300(sp)
+2000061c: 13812423 sw s8,296(sp)
+20000620: 13912223 sw s9,292(sp)
+20000624: 13a12023 sw s10,288(sp)
+20000628: 14b12a23 sw a1,340(sp)
+2000062c: 14c12c23 sw a2,344(sp)
+20000630: 14d12e23 sw a3,348(sp)
+20000634: 16e12023 sw a4,352(sp)
+20000638: 16f12223 sw a5,356(sp)
+2000063c: 17012423 sw a6,360(sp)
+20000640: 17112623 sw a7,364(sp)
+20000644: 00054783 lbu a5,0(a0)
+20000648: 15410b13 addi s6,sp,340
+2000064c: c25a sw s6,4(sp)
+2000064e: 5c078963 beqz a5,20000c20 <ee_printf+0x62a>
+20000652: 02010993 addi s3,sp,32
+20000656: 832a mv t1,a0
+20000658: 20000a97 auipc s5,0x20000
+2000065c: 9a8a8a93 addi s5,s5,-1624 # 40000000 <rodata_start>
+20000660: 854e mv a0,s3
+20000662: 02e00b93 li s7,46
+20000666: 20000a17 auipc s4,0x20000
+2000066a: 9dea0a13 addi s4,s4,-1570 # 40000044 <rodata_start+0x44>
+2000066e: 20000497 auipc s1,0x20000
+20000672: 16648493 addi s1,s1,358 # 400007d4 <uart_ctrl_addr+0x5d0>
+20000676: 20000417 auipc s0,0x20000
+2000067a: aae40413 addi s0,s0,-1362 # 40000124 <rodata_start+0x124>
+2000067e: 02500713 li a4,37
+20000682: 06e78463 beq a5,a4,200006ea <ee_printf+0xf4>
+20000686: 00f50023 sb a5,0(a0)
+2000068a: 00134783 lbu a5,1(t1)
+2000068e: 0505 addi a0,a0,1
+20000690: 0305 addi t1,t1,1
+20000692: f7f5 bnez a5,2000067e <ee_printf+0x88>
+20000694: 00050023 sb zero,0(a0)
+20000698: 02014583 lbu a1,32(sp)
+2000069c: 12058463 beqz a1,200007c4 <ee_printf+0x1ce>
+200006a0: 4405 li s0,1
+200006a2: 41340433 sub s0,s0,s3
+200006a6: 4501 li a0,0
+200006a8: 258d jal 20000d0a <serial_send_byte>
+200006aa: 0019c583 lbu a1,1(s3)
+200006ae: 00898533 add a0,s3,s0
+200006b2: 0985 addi s3,s3,1
+200006b4: f9ed bnez a1,200006a6 <ee_printf+0xb0>
+200006b6: 14c12083 lw ra,332(sp)
+200006ba: 14812403 lw s0,328(sp)
+200006be: 14412483 lw s1,324(sp)
+200006c2: 14012903 lw s2,320(sp)
+200006c6: 13c12983 lw s3,316(sp)
+200006ca: 13812a03 lw s4,312(sp)
+200006ce: 13412a83 lw s5,308(sp)
+200006d2: 13012b03 lw s6,304(sp)
+200006d6: 12c12b83 lw s7,300(sp)
+200006da: 12812c03 lw s8,296(sp)
+200006de: 12412c83 lw s9,292(sp)
+200006e2: 12012d03 lw s10,288(sp)
+200006e6: 6175 addi sp,sp,368
+200006e8: 8082 ret
+200006ea: 4781 li a5,0
+200006ec: 46c1 li a3,16
+200006ee: 00134583 lbu a1,1(t1)
+200006f2: 00130913 addi s2,t1,1
+200006f6: fe058713 addi a4,a1,-32
+200006fa: 0ff77713 andi a4,a4,255
+200006fe: 00e6e763 bltu a3,a4,2000070c <ee_printf+0x116>
+20000702: 070a slli a4,a4,0x2
+20000704: 9756 add a4,a4,s5
+20000706: 4318 lw a4,0(a4)
+20000708: 9756 add a4,a4,s5
+2000070a: 8702 jr a4
+2000070c: fd058713 addi a4,a1,-48
+20000710: 0ff77713 andi a4,a4,255
+20000714: 46a5 li a3,9
+20000716: 0ce6fb63 bgeu a3,a4,200007ec <ee_printf+0x1f6>
+2000071a: 02a00713 li a4,42
+2000071e: 56fd li a3,-1
+20000720: 0ee58963 beq a1,a4,20000812 <ee_printf+0x21c>
+20000724: 577d li a4,-1
+20000726: 0b758163 beq a1,s7,200007c8 <ee_printf+0x1d2>
+2000072a: 0df5f613 andi a2,a1,223
+2000072e: 04c00813 li a6,76
+20000732: 05060363 beq a2,a6,20000778 <ee_printf+0x182>
+20000736: fbf58613 addi a2,a1,-65
+2000073a: 0ff67613 andi a2,a2,255
+2000073e: 03700813 li a6,55
+20000742: 04c86e63 bltu a6,a2,2000079e <ee_printf+0x1a8>
+20000746: 060a slli a2,a2,0x2
+20000748: 9652 add a2,a2,s4
+2000074a: 4210 lw a2,0(a2)
+2000074c: 9652 add a2,a2,s4
+2000074e: 8602 jr a2
+20000750: 0017e793 ori a5,a5,1
+20000754: 834a mv t1,s2
+20000756: bf61 j 200006ee <ee_printf+0xf8>
+20000758: 0107e793 ori a5,a5,16
+2000075c: 834a mv t1,s2
+2000075e: bf41 j 200006ee <ee_printf+0xf8>
+20000760: 0047e793 ori a5,a5,4
+20000764: 834a mv t1,s2
+20000766: b761 j 200006ee <ee_printf+0xf8>
+20000768: 0207e793 ori a5,a5,32
+2000076c: 834a mv t1,s2
+2000076e: b741 j 200006ee <ee_printf+0xf8>
+20000770: 0087e793 ori a5,a5,8
+20000774: 834a mv t1,s2
+20000776: bfa5 j 200006ee <ee_printf+0xf8>
+20000778: 00194803 lbu a6,1(s2)
+2000077c: 03700313 li t1,55
+20000780: 00190893 addi a7,s2,1
+20000784: fbf80613 addi a2,a6,-65
+20000788: 0ff67613 andi a2,a2,255
+2000078c: 00c36763 bltu t1,a2,2000079a <ee_printf+0x1a4>
+20000790: 060a slli a2,a2,0x2
+20000792: 9622 add a2,a2,s0
+20000794: 4210 lw a2,0(a2)
+20000796: 9622 add a2,a2,s0
+20000798: 8602 jr a2
+2000079a: 85c2 mv a1,a6
+2000079c: 8946 mv s2,a7
+2000079e: 02500713 li a4,37
+200007a2: 00150793 addi a5,a0,1
+200007a6: 42e58963 beq a1,a4,20000bd8 <ee_printf+0x5e2>
+200007aa: 00e50023 sb a4,0(a0)
+200007ae: 00094703 lbu a4,0(s2)
+200007b2: 4c071a63 bnez a4,20000c86 <ee_printf+0x690>
+200007b6: 853e mv a0,a5
+200007b8: 00050023 sb zero,0(a0)
+200007bc: 02014583 lbu a1,32(sp)
+200007c0: ee0590e3 bnez a1,200006a0 <ee_printf+0xaa>
+200007c4: 4501 li a0,0
+200007c6: bdc5 j 200006b6 <ee_printf+0xc0>
+200007c8: 00194583 lbu a1,1(s2)
+200007cc: 4625 li a2,9
+200007ce: 00190813 addi a6,s2,1
+200007d2: fd058713 addi a4,a1,-48
+200007d6: 0ff77713 andi a4,a4,255
+200007da: 3ae67763 bgeu a2,a4,20000b88 <ee_printf+0x592>
+200007de: 02a00713 li a4,42
+200007e2: 3ce58b63 beq a1,a4,20000bb8 <ee_printf+0x5c2>
+200007e6: 8942 mv s2,a6
+200007e8: 4701 li a4,0
+200007ea: b781 j 2000072a <ee_printf+0x134>
+200007ec: 4681 li a3,0
+200007ee: 4625 li a2,9
+200007f0: 00269713 slli a4,a3,0x2
+200007f4: 96ba add a3,a3,a4
+200007f6: 0905 addi s2,s2,1
+200007f8: 0686 slli a3,a3,0x1
+200007fa: 96ae add a3,a3,a1
+200007fc: 00094583 lbu a1,0(s2)
+20000800: fd068693 addi a3,a3,-48
+20000804: fd058713 addi a4,a1,-48
+20000808: 0ff77713 andi a4,a4,255
+2000080c: fee672e3 bgeu a2,a4,200007f0 <ee_printf+0x1fa>
+20000810: bf11 j 20000724 <ee_printf+0x12e>
+20000812: 000b2683 lw a3,0(s6)
+20000816: 00234583 lbu a1,2(t1)
+2000081a: 00230913 addi s2,t1,2
+2000081e: 0b11 addi s6,s6,4
+20000820: f006d2e3 bgez a3,20000724 <ee_printf+0x12e>
+20000824: 40d006b3 neg a3,a3
+20000828: 0107e793 ori a5,a5,16
+2000082c: bde5 j 20000724 <ee_printf+0x12e>
+2000082e: 004b0813 addi a6,s6,4
+20000832: 4641 li a2,16
+20000834: 000b2583 lw a1,0(s6)
+20000838: 8b42 mv s6,a6
+2000083a: 3e75 jal 200003f6 <number>
+2000083c: 00194783 lbu a5,1(s2)
+20000840: 00190313 addi t1,s2,1
+20000844: e2079de3 bnez a5,2000067e <ee_printf+0x88>
+20000848: b5b1 j 20000694 <ee_printf+0x9e>
+2000084a: 004b0813 addi a6,s6,4
+2000084e: 4629 li a2,10
+20000850: b7d5 j 20000834 <ee_printf+0x23e>
+20000852: 8946 mv s2,a7
+20000854: 000b2603 lw a2,0(s6)
+20000858: 0b11 addi s6,s6,4
+2000085a: 3a060163 beqz a2,20000bfc <ee_printf+0x606>
+2000085e: 00064583 lbu a1,0(a2)
+20000862: 3e058b63 beqz a1,20000c58 <ee_printf+0x662>
+20000866: 3e070963 beqz a4,20000c58 <ee_printf+0x662>
+2000086a: 85b2 mv a1,a2
+2000086c: a029 j 20000876 <ee_printf+0x280>
+2000086e: 40e58833 sub a6,a1,a4
+20000872: 00c80763 beq a6,a2,20000880 <ee_printf+0x28a>
+20000876: 0015c803 lbu a6,1(a1)
+2000087a: 0585 addi a1,a1,1
+2000087c: fe0819e3 bnez a6,2000086e <ee_printf+0x278>
+20000880: 8bc1 andi a5,a5,16
+20000882: 8d91 sub a1,a1,a2
+20000884: 3a078263 beqz a5,20000c28 <ee_printf+0x632>
+20000888: 40b05b63 blez a1,20000c9e <ee_printf+0x6a8>
+2000088c: 00b60833 add a6,a2,a1
+20000890: 87aa mv a5,a0
+20000892: 00064703 lbu a4,0(a2)
+20000896: 0605 addi a2,a2,1
+20000898: 0785 addi a5,a5,1
+2000089a: fee78fa3 sb a4,-1(a5) # 10011fff <_stack+0x801000f>
+2000089e: ff061ae3 bne a2,a6,20000892 <ee_printf+0x29c>
+200008a2: 00b50733 add a4,a0,a1
+200008a6: 40b68533 sub a0,a3,a1
+200008aa: 00190313 addi t1,s2,1
+200008ae: 953a add a0,a0,a4
+200008b0: 02000793 li a5,32
+200008b4: 3cd5d163 bge a1,a3,20000c76 <ee_printf+0x680>
+200008b8: 0705 addi a4,a4,1
+200008ba: fef70fa3 sb a5,-1(a4)
+200008be: fea71de3 bne a4,a0,200008b8 <ee_printf+0x2c2>
+200008c2: 00194783 lbu a5,1(s2)
+200008c6: da079ce3 bnez a5,2000067e <ee_printf+0x88>
+200008ca: b3e9 j 20000694 <ee_printf+0x9e>
+200008cc: 8946 mv s2,a7
+200008ce: 567d li a2,-1
+200008d0: 32c68263 beq a3,a2,20000bf4 <ee_printf+0x5fe>
+200008d4: 000b2583 lw a1,0(s6)
+200008d8: 4641 li a2,16
+200008da: 0b11 addi s6,s6,4
+200008dc: 3e29 jal 200003f6 <number>
+200008de: 00194783 lbu a5,1(s2)
+200008e2: 00190313 addi t1,s2,1
+200008e6: d8079ce3 bnez a5,2000067e <ee_printf+0x88>
+200008ea: b36d j 20000694 <ee_printf+0x9e>
+200008ec: 004b0813 addi a6,s6,4
+200008f0: 4621 li a2,8
+200008f2: b789 j 20000834 <ee_printf+0x23e>
+200008f4: 0027e793 ori a5,a5,2
+200008f8: 004b0813 addi a6,s6,4
+200008fc: 4629 li a2,10
+200008fe: bf1d j 20000834 <ee_printf+0x23e>
+20000900: 8946 mv s2,a7
+20000902: 8bc1 andi a5,a5,16
+20000904: 16fd addi a3,a3,-1
+20000906: 30078063 beqz a5,20000c06 <ee_printf+0x610>
+2000090a: 000b2603 lw a2,0(s6)
+2000090e: 00150713 addi a4,a0,1
+20000912: 00168793 addi a5,a3,1
+20000916: 00c50023 sb a2,0(a0)
+2000091a: 0b11 addi s6,s6,4
+2000091c: 953e add a0,a0,a5
+2000091e: 00190313 addi t1,s2,1
+20000922: 87ba mv a5,a4
+20000924: 02000613 li a2,32
+20000928: 34d05763 blez a3,20000c76 <ee_printf+0x680>
+2000092c: 0785 addi a5,a5,1
+2000092e: fec78fa3 sb a2,-1(a5)
+20000932: fea79de3 bne a5,a0,2000092c <ee_printf+0x336>
+20000936: 00194783 lbu a5,1(s2)
+2000093a: 00d70533 add a0,a4,a3
+2000093e: d40790e3 bnez a5,2000067e <ee_printf+0x88>
+20000942: bb89 j 20000694 <ee_printf+0x9e>
+20000944: 0407e793 ori a5,a5,64
+20000948: 004b0813 addi a6,s6,4
+2000094c: 4641 li a2,16
+2000094e: b5dd j 20000834 <ee_printf+0x23e>
+20000950: 000b2703 lw a4,0(s6)
+20000954: 0407e793 ori a5,a5,64
+20000958: 0b11 addi s6,s6,4
+2000095a: 00074583 lbu a1,0(a4)
+2000095e: 4801 li a6,0
+20000960: 00470893 addi a7,a4,4
+20000964: 06300e93 li t4,99
+20000968: 4fa5 li t6,9
+2000096a: 4329 li t1,10
+2000096c: 06400f13 li t5,100
+20000970: 03000e13 li t3,48
+20000974: 00180613 addi a2,a6,1
+20000978: e19d bnez a1,2000099e <ee_printf+0x3a8>
+2000097a: 120c addi a1,sp,288
+2000097c: 982e add a6,a6,a1
+2000097e: efc80423 sb t3,-280(a6)
+20000982: 0705 addi a4,a4,1
+20000984: 07170663 beq a4,a7,200009f0 <ee_printf+0x3fa>
+20000988: 120c addi a1,sp,288
+2000098a: 95b2 add a1,a1,a2
+2000098c: ef758423 sb s7,-280(a1)
+20000990: 00074583 lbu a1,0(a4)
+20000994: 00160813 addi a6,a2,1
+20000998: 00180613 addi a2,a6,1
+2000099c: ddf9 beqz a1,2000097a <ee_printf+0x384>
+2000099e: 1cbed063 bge t4,a1,20000b5e <ee_printf+0x568>
+200009a2: 03e5ec33 rem s8,a1,t5
+200009a6: 12010293 addi t0,sp,288
+200009aa: 01028d33 add s10,t0,a6
+200009ae: 00c28cb3 add s9,t0,a2
+200009b2: 00280393 addi t2,a6,2
+200009b6: 00380613 addi a2,a6,3
+200009ba: 03e5c5b3 div a1,a1,t5
+200009be: 026c4833 div a6,s8,t1
+200009c2: 00b482b3 add t0,s1,a1
+200009c6: 0002c583 lbu a1,0(t0)
+200009ca: eebd0423 sb a1,-280(s10)
+200009ce: 026c65b3 rem a1,s8,t1
+200009d2: 9826 add a6,a6,s1
+200009d4: 00084803 lbu a6,0(a6)
+200009d8: ef0c8423 sb a6,-280(s9)
+200009dc: 95a6 add a1,a1,s1
+200009de: 0005c803 lbu a6,0(a1)
+200009e2: 120c addi a1,sp,288
+200009e4: 959e add a1,a1,t2
+200009e6: ef058423 sb a6,-280(a1)
+200009ea: 0705 addi a4,a4,1
+200009ec: f9171ee3 bne a4,a7,20000988 <ee_printf+0x392>
+200009f0: 8bc1 andi a5,a5,16
+200009f2: fff68813 addi a6,a3,-1
+200009f6: e395 bnez a5,20000a1a <ee_printf+0x424>
+200009f8: 40c687b3 sub a5,a3,a2
+200009fc: 97aa add a5,a5,a0
+200009fe: 02000713 li a4,32
+20000a02: 28d65463 bge a2,a3,20000c8a <ee_printf+0x694>
+20000a06: 0505 addi a0,a0,1
+20000a08: fee50fa3 sb a4,-1(a0)
+20000a0c: fea79de3 bne a5,a0,20000a06 <ee_printf+0x410>
+20000a10: 40d606b3 sub a3,a2,a3
+20000a14: 96c2 add a3,a3,a6
+20000a16: fff68813 addi a6,a3,-1
+20000a1a: 003c addi a5,sp,8
+20000a1c: 00c505b3 add a1,a0,a2
+20000a20: 0007c703 lbu a4,0(a5)
+20000a24: 0505 addi a0,a0,1
+20000a26: 0785 addi a5,a5,1
+20000a28: fee50fa3 sb a4,-1(a0)
+20000a2c: feb51ae3 bne a0,a1,20000a20 <ee_printf+0x42a>
+20000a30: e0d656e3 bge a2,a3,2000083c <ee_printf+0x246>
+20000a34: 872e mv a4,a1
+20000a36: 02000513 li a0,32
+20000a3a: 4685 li a3,1
+20000a3c: 0705 addi a4,a4,1
+20000a3e: 40e687b3 sub a5,a3,a4
+20000a42: 97c2 add a5,a5,a6
+20000a44: 97ae add a5,a5,a1
+20000a46: fea70fa3 sb a0,-1(a4)
+20000a4a: fef649e3 blt a2,a5,20000a3c <ee_printf+0x446>
+20000a4e: 4505 li a0,1
+20000a50: 16c85f63 bge a6,a2,20000bce <ee_printf+0x5d8>
+20000a54: 952e add a0,a0,a1
+20000a56: b3dd j 2000083c <ee_printf+0x246>
+20000a58: 0027e793 ori a5,a5,2
+20000a5c: 4629 li a2,10
+20000a5e: 06c00313 li t1,108
+20000a62: 004b0813 addi a6,s6,4
+20000a66: 20659e63 bne a1,t1,20000c82 <ee_printf+0x68c>
+20000a6a: 000b2583 lw a1,0(s6)
+20000a6e: 8946 mv s2,a7
+20000a70: 8b42 mv s6,a6
+20000a72: b3e1 j 2000083a <ee_printf+0x244>
+20000a74: 4621 li a2,8
+20000a76: b7e5 j 20000a5e <ee_printf+0x468>
+20000a78: 0407e793 ori a5,a5,64
+20000a7c: 4641 li a2,16
+20000a7e: b7c5 j 20000a5e <ee_printf+0x468>
+20000a80: 0407e793 ori a5,a5,64
+20000a84: 06c00613 li a2,108
+20000a88: 000b2703 lw a4,0(s6)
+20000a8c: 0b11 addi s6,s6,4
+20000a8e: 1ac59f63 bne a1,a2,20000c4c <ee_printf+0x656>
+20000a92: 0407f613 andi a2,a5,64
+20000a96: 88a6 mv a7,s1
+20000a98: c609 beqz a2,20000aa2 <ee_printf+0x4ac>
+20000a9a: 20000897 auipc a7,0x20000
+20000a9e: d6288893 addi a7,a7,-670 # 400007fc <uart_ctrl_addr+0x5f8>
+20000aa2: 00810313 addi t1,sp,8
+20000aa6: 01a10e13 addi t3,sp,26
+20000aaa: 859a mv a1,t1
+20000aac: 03a00e93 li t4,58
+20000ab0: a019 j 20000ab6 <ee_printf+0x4c0>
+20000ab2: ffd58fa3 sb t4,-1(a1)
+20000ab6: 00074603 lbu a2,0(a4)
+20000aba: 058d addi a1,a1,3
+20000abc: 0705 addi a4,a4,1
+20000abe: 00465813 srli a6,a2,0x4
+20000ac2: 8a3d andi a2,a2,15
+20000ac4: 9846 add a6,a6,a7
+20000ac6: 9646 add a2,a2,a7
+20000ac8: 00084803 lbu a6,0(a6)
+20000acc: 00064603 lbu a2,0(a2)
+20000ad0: ff058ea3 sb a6,-3(a1)
+20000ad4: fec58f23 sb a2,-2(a1)
+20000ad8: fdc59de3 bne a1,t3,20000ab2 <ee_printf+0x4bc>
+20000adc: 8bc1 andi a5,a5,16
+20000ade: fff68613 addi a2,a3,-1
+20000ae2: e39d bnez a5,20000b08 <ee_printf+0x512>
+20000ae4: fef68593 addi a1,a3,-17
+20000ae8: 4845 li a6,17
+20000aea: 00b50733 add a4,a0,a1
+20000aee: 02000793 li a5,32
+20000af2: 1ad85163 bge a6,a3,20000c94 <ee_printf+0x69e>
+20000af6: 0505 addi a0,a0,1
+20000af8: fef50fa3 sb a5,-1(a0)
+20000afc: fee51de3 bne a0,a4,20000af6 <ee_printf+0x500>
+20000b00: 40b606b3 sub a3,a2,a1
+20000b04: fff68613 addi a2,a3,-1
+20000b08: 87aa mv a5,a0
+20000b0a: 01130593 addi a1,t1,17
+20000b0e: 00034703 lbu a4,0(t1)
+20000b12: 0305 addi t1,t1,1
+20000b14: 0785 addi a5,a5,1
+20000b16: fee78fa3 sb a4,-1(a5)
+20000b1a: feb31ae3 bne t1,a1,20000b0e <ee_printf+0x518>
+20000b1e: 47c5 li a5,17
+20000b20: 0545 addi a0,a0,17
+20000b22: 02d7d763 bge a5,a3,20000b50 <ee_printf+0x55a>
+20000b26: 872a mv a4,a0
+20000b28: 02000813 li a6,32
+20000b2c: 4585 li a1,1
+20000b2e: 46c5 li a3,17
+20000b30: 0705 addi a4,a4,1
+20000b32: 40e587b3 sub a5,a1,a4
+20000b36: 97b2 add a5,a5,a2
+20000b38: 97aa add a5,a5,a0
+20000b3a: ff070fa3 sb a6,-1(a4)
+20000b3e: fef6c9e3 blt a3,a5,20000b30 <ee_printf+0x53a>
+20000b42: 4741 li a4,16
+20000b44: 4785 li a5,1
+20000b46: 00c75463 bge a4,a2,20000b4e <ee_printf+0x558>
+20000b4a: ff060793 addi a5,a2,-16
+20000b4e: 953e add a0,a0,a5
+20000b50: 00294783 lbu a5,2(s2)
+20000b54: 00290313 addi t1,s2,2
+20000b58: b20793e3 bnez a5,2000067e <ee_printf+0x88>
+20000b5c: be25 j 20000694 <ee_printf+0x9e>
+20000b5e: 83c2 mv t2,a6
+20000b60: e6bfdee3 bge t6,a1,200009dc <ee_printf+0x3e6>
+20000b64: 0265c2b3 div t0,a1,t1
+20000b68: 12010393 addi t2,sp,288
+20000b6c: 01038c33 add s8,t2,a6
+20000b70: 83b2 mv t2,a2
+20000b72: 00280613 addi a2,a6,2
+20000b76: 00548833 add a6,s1,t0
+20000b7a: 00084803 lbu a6,0(a6)
+20000b7e: 0265e5b3 rem a1,a1,t1
+20000b82: ef0c0423 sb a6,-280(s8)
+20000b86: bd99 j 200009dc <ee_printf+0x3e6>
+20000b88: 4701 li a4,0
+20000b8a: 48a5 li a7,9
+20000b8c: 00271613 slli a2,a4,0x2
+20000b90: 9732 add a4,a4,a2
+20000b92: 0805 addi a6,a6,1
+20000b94: 0706 slli a4,a4,0x1
+20000b96: 972e add a4,a4,a1
+20000b98: 00084583 lbu a1,0(a6)
+20000b9c: fd070713 addi a4,a4,-48
+20000ba0: fd058613 addi a2,a1,-48
+20000ba4: 0ff67613 andi a2,a2,255
+20000ba8: fec8f2e3 bgeu a7,a2,20000b8c <ee_printf+0x596>
+20000bac: 8942 mv s2,a6
+20000bae: beb5 j 2000072a <ee_printf+0x134>
+20000bb0: 000b2703 lw a4,0(s6)
+20000bb4: 0b11 addi s6,s6,4
+20000bb6: b355 j 2000095a <ee_printf+0x364>
+20000bb8: 000b2703 lw a4,0(s6)
+20000bbc: 00294583 lbu a1,2(s2)
+20000bc0: 0b11 addi s6,s6,4
+20000bc2: fff74613 not a2,a4
+20000bc6: 867d srai a2,a2,0x1f
+20000bc8: 8f71 and a4,a4,a2
+20000bca: 0909 addi s2,s2,2
+20000bcc: beb9 j 2000072a <ee_printf+0x134>
+20000bce: 8e91 sub a3,a3,a2
+20000bd0: 01068533 add a0,a3,a6
+20000bd4: 952e add a0,a0,a1
+20000bd6: b19d j 2000083c <ee_printf+0x246>
+20000bd8: 00094703 lbu a4,0(s2)
+20000bdc: 86be mv a3,a5
+20000bde: 87aa mv a5,a0
+20000be0: 8536 mv a0,a3
+20000be2: 00e78023 sb a4,0(a5)
+20000be6: 00194783 lbu a5,1(s2)
+20000bea: 00190313 addi t1,s2,1
+20000bee: a80798e3 bnez a5,2000067e <ee_printf+0x88>
+20000bf2: b44d j 20000694 <ee_printf+0x9e>
+20000bf4: 0017e793 ori a5,a5,1
+20000bf8: 46a1 li a3,8
+20000bfa: b9e9 j 200008d4 <ee_printf+0x2de>
+20000bfc: 20000617 auipc a2,0x20000
+20000c00: c2860613 addi a2,a2,-984 # 40000824 <uart_ctrl_addr+0x620>
+20000c04: b18d j 20000866 <ee_printf+0x270>
+20000c06: 00d50733 add a4,a0,a3
+20000c0a: 02000793 li a5,32
+20000c0e: 04d05b63 blez a3,20000c64 <ee_printf+0x66e>
+20000c12: 0505 addi a0,a0,1
+20000c14: fef50fa3 sb a5,-1(a0)
+20000c18: fee51de3 bne a0,a4,20000c12 <ee_printf+0x61c>
+20000c1c: 56fd li a3,-1
+20000c1e: b1f5 j 2000090a <ee_printf+0x314>
+20000c20: 02010993 addi s3,sp,32
+20000c24: 854e mv a0,s3
+20000c26: b4bd j 20000694 <ee_printf+0x9e>
+20000c28: fff68813 addi a6,a3,-1
+20000c2c: 08d5d263 bge a1,a3,20000cb0 <ee_printf+0x6ba>
+20000c30: 40b687b3 sub a5,a3,a1
+20000c34: 97aa add a5,a5,a0
+20000c36: 02000713 li a4,32
+20000c3a: 0505 addi a0,a0,1
+20000c3c: fee50fa3 sb a4,-1(a0)
+20000c40: fef51de3 bne a0,a5,20000c3a <ee_printf+0x644>
+20000c44: 40d586b3 sub a3,a1,a3
+20000c48: 96c2 add a3,a3,a6
+20000c4a: b93d j 20000888 <ee_printf+0x292>
+20000c4c: 8946 mv s2,a7
+20000c4e: b331 j 2000095a <ee_printf+0x364>
+20000c50: 4641 li a2,16
+20000c52: b531 j 20000a5e <ee_printf+0x468>
+20000c54: 4629 li a2,10
+20000c56: b521 j 20000a5e <ee_printf+0x468>
+20000c58: 0107f593 andi a1,a5,16
+20000c5c: c1b9 beqz a1,20000ca2 <ee_printf+0x6ac>
+20000c5e: 872a mv a4,a0
+20000c60: 4581 li a1,0
+20000c62: b191 j 200008a6 <ee_printf+0x2b0>
+20000c64: 000b2783 lw a5,0(s6)
+20000c68: 00150713 addi a4,a0,1
+20000c6c: 0b11 addi s6,s6,4
+20000c6e: 00f50023 sb a5,0(a0)
+20000c72: 00190313 addi t1,s2,1
+20000c76: 00194783 lbu a5,1(s2)
+20000c7a: 853a mv a0,a4
+20000c7c: a00791e3 bnez a5,2000067e <ee_printf+0x88>
+20000c80: bc11 j 20000694 <ee_printf+0x9e>
+20000c82: 8946 mv s2,a7
+20000c84: be45 j 20000834 <ee_printf+0x23e>
+20000c86: 0509 addi a0,a0,2
+20000c88: bfa9 j 20000be2 <ee_printf+0x5ec>
+20000c8a: ffe68793 addi a5,a3,-2
+20000c8e: 86c2 mv a3,a6
+20000c90: 883e mv a6,a5
+20000c92: b361 j 20000a1a <ee_printf+0x424>
+20000c94: ffe68793 addi a5,a3,-2
+20000c98: 86b2 mv a3,a2
+20000c9a: 863e mv a2,a5
+20000c9c: b5b5 j 20000b08 <ee_printf+0x512>
+20000c9e: 872a mv a4,a0
+20000ca0: b119 j 200008a6 <ee_printf+0x2b0>
+20000ca2: fff68813 addi a6,a3,-1
+20000ca6: f8d045e3 bgtz a3,20000c30 <ee_printf+0x63a>
+20000caa: 86c2 mv a3,a6
+20000cac: 872a mv a4,a0
+20000cae: bee5 j 200008a6 <ee_printf+0x2b0>
+20000cb0: 86c2 mv a3,a6
+20000cb2: bed9 j 20000888 <ee_printf+0x292>
+
+20000cb4 <mytimes>:
+20000cb4: 87aa mv a5,a0
+20000cb6: b0002773 csrr a4,mcycle
+20000cba: 4501 li a0,0
+20000cbc: c398 sw a4,0(a5)
+20000cbe: 8082 ret
+
+20000cc0 <serial_init>:
+20000cc0: 00251793 slli a5,a0,0x2
+20000cc4: 1ffff517 auipc a0,0x1ffff
+20000cc8: 54050513 addi a0,a0,1344 # 40000204 <uart_ctrl_addr>
+20000ccc: 953e add a0,a0,a5
+20000cce: 4118 lw a4,0(a0)
+20000cd0: 4785 li a5,1
+20000cd2: c71c sw a5,8(a4)
+20000cd4: c75c sw a5,12(a4)
+20000cd6: 00f58a63 beq a1,a5,20000cea <serial_init+0x2a>
+20000cda: 36300793 li a5,867
+20000cde: cf1c sw a5,24(a4)
+20000ce0: 435c lw a5,4(a4)
+20000ce2: fe07dfe3 bgez a5,20000ce0 <serial_init+0x20>
+20000ce6: 4501 li a0,0
+20000ce8: 8082 ret
+20000cea: 47bd li a5,15
+20000cec: cf1c sw a5,24(a4)
+20000cee: bfcd j 20000ce0 <serial_init+0x20>
+
+20000cf0 <serial_is_send_enable>:
+20000cf0: 00251793 slli a5,a0,0x2
+20000cf4: 1ffff517 auipc a0,0x1ffff
+20000cf8: 51050513 addi a0,a0,1296 # 40000204 <uart_ctrl_addr>
+20000cfc: 953e add a0,a0,a5
+20000cfe: 411c lw a5,0(a0)
+20000d00: 4388 lw a0,0(a5)
+20000d02: fff54513 not a0,a0
+20000d06: 817d srli a0,a0,0x1f
+20000d08: 8082 ret
+
+20000d0a <serial_send_byte>:
+20000d0a: 00251793 slli a5,a0,0x2
+20000d0e: 1ffff517 auipc a0,0x1ffff
+20000d12: 4f650513 addi a0,a0,1270 # 40000204 <uart_ctrl_addr>
+20000d16: 953e add a0,a0,a5
+20000d18: 4118 lw a4,0(a0)
+20000d1a: 431c lw a5,0(a4)
+20000d1c: fe07cfe3 bltz a5,20000d1a <serial_send_byte+0x10>
+20000d20: c30c sw a1,0(a4)
+20000d22: 4501 li a0,0
+20000d24: 8082 ret
+
+20000d26 <serial_is_recv_enable>:
+20000d26: 00251793 slli a5,a0,0x2
+20000d2a: 1ffff517 auipc a0,0x1ffff
+20000d2e: 4da50513 addi a0,a0,1242 # 40000204 <uart_ctrl_addr>
+20000d32: 953e add a0,a0,a5
+20000d34: 411c lw a5,0(a0)
+20000d36: 43dc lw a5,4(a5)
+20000d38: fff7c513 not a0,a5
+20000d3c: 00f58023 sb a5,0(a1)
+20000d40: 817d srli a0,a0,0x1f
+20000d42: 8082 ret
+
+20000d44 <serial_recv_byte>:
+20000d44: 00251793 slli a5,a0,0x2
+20000d48: 1ffff517 auipc a0,0x1ffff
+20000d4c: 4bc50513 addi a0,a0,1212 # 40000204 <uart_ctrl_addr>
+20000d50: 953e add a0,a0,a5
+20000d52: 411c lw a5,0(a0)
+20000d54: 43c8 lw a0,4(a5)
+20000d56: fe054fe3 bltz a0,20000d54 <serial_recv_byte+0x10>
+20000d5a: 0ff57513 andi a0,a0,255
+20000d5e: 8082 ret
+
+20000d60 <memset>:
+20000d60: 0ff5f593 andi a1,a1,255
+20000d64: 00c50733 add a4,a0,a2
+20000d68: 87aa mv a5,a0
+20000d6a: 00c05763 blez a2,20000d78 <memset+0x18>
+20000d6e: 0785 addi a5,a5,1
+20000d70: feb78fa3 sb a1,-1(a5)
+20000d74: fef71de3 bne a4,a5,20000d6e <memset+0xe>
+20000d78: 8082 ret
+
+20000d7a <memcpy>:
+20000d7a: 00c05c63 blez a2,20000d92 <memcpy+0x18>
+20000d7e: 962a add a2,a2,a0
+20000d80: 87aa mv a5,a0
+20000d82: 0005c703 lbu a4,0(a1)
+20000d86: 0785 addi a5,a5,1
+20000d88: 0585 addi a1,a1,1
+20000d8a: fee78fa3 sb a4,-1(a5)
+20000d8e: fef61ae3 bne a2,a5,20000d82 <memcpy+0x8>
+20000d92: 8082 ret
+
+20000d94 <memcmp>:
+20000d94: 02c05563 blez a2,20000dbe <memcmp+0x2a>
+20000d98: 962e add a2,a2,a1
+20000d9a: a019 j 20000da0 <memcmp+0xc>
+20000d9c: 02b60163 beq a2,a1,20000dbe <memcmp+0x2a>
+20000da0: 00054783 lbu a5,0(a0)
+20000da4: 0005c703 lbu a4,0(a1)
+20000da8: 0505 addi a0,a0,1
+20000daa: 0585 addi a1,a1,1
+20000dac: fee788e3 beq a5,a4,20000d9c <memcmp+0x8>
+20000db0: 00f73533 sltu a0,a4,a5
+20000db4: 40a00533 neg a0,a0
+20000db8: 8909 andi a0,a0,2
+20000dba: 157d addi a0,a0,-1
+20000dbc: 8082 ret
+20000dbe: 4501 li a0,0
+20000dc0: 8082 ret
+
+20000dc2 <strlen>:
+20000dc2: 00054783 lbu a5,0(a0)
+20000dc6: 872a mv a4,a0
+20000dc8: 4501 li a0,0
+20000dca: cb81 beqz a5,20000dda <strlen+0x18>
+20000dcc: 0505 addi a0,a0,1
+20000dce: 00a707b3 add a5,a4,a0
+20000dd2: 0007c783 lbu a5,0(a5)
+20000dd6: fbfd bnez a5,20000dcc <strlen+0xa>
+20000dd8: 8082 ret
+20000dda: 8082 ret
+
+20000ddc <strcpy>:
+20000ddc: 0005c783 lbu a5,0(a1)
+20000de0: 00f50023 sb a5,0(a0)
+20000de4: 0005c783 lbu a5,0(a1)
+20000de8: cb99 beqz a5,20000dfe <strcpy+0x22>
+20000dea: 87aa mv a5,a0
+20000dec: 0015c703 lbu a4,1(a1)
+20000df0: 0585 addi a1,a1,1
+20000df2: 0785 addi a5,a5,1
+20000df4: 00e78023 sb a4,0(a5)
+20000df8: 0005c703 lbu a4,0(a1)
+20000dfc: fb65 bnez a4,20000dec <strcpy+0x10>
+20000dfe: 8082 ret
+
+20000e00 <strcmp>:
+20000e00: a019 j 20000e06 <strcmp+0x6>
+20000e02: 00e79d63 bne a5,a4,20000e1c <strcmp+0x1c>
+20000e06: 00054783 lbu a5,0(a0)
+20000e0a: 0005c703 lbu a4,0(a1)
+20000e0e: 0505 addi a0,a0,1
+20000e10: 0585 addi a1,a1,1
+20000e12: 00e7e6b3 or a3,a5,a4
+20000e16: f6f5 bnez a3,20000e02 <strcmp+0x2>
+20000e18: 4501 li a0,0
+20000e1a: 8082 ret
+20000e1c: 00f73533 sltu a0,a4,a5
+20000e20: 40a00533 neg a0,a0
+20000e24: 8909 andi a0,a0,2
+20000e26: 157d addi a0,a0,-1
+20000e28: 8082 ret
+
+20000e2a <strncmp>:
+20000e2a: 87aa mv a5,a0
+20000e2c: 00c50833 add a6,a0,a2
+20000e30: 0007c703 lbu a4,0(a5)
+20000e34: 40f806b3 sub a3,a6,a5
+20000e38: eb19 bnez a4,20000e4e <strncmp+0x24>
+20000e3a: 0005c703 lbu a4,0(a1)
+20000e3e: c70d beqz a4,20000e68 <strncmp+0x3e>
+20000e40: 9532 add a0,a0,a2
+20000e42: 8d1d sub a0,a0,a5
+20000e44: 00a02533 sgtz a0,a0
+20000e48: 40a00533 neg a0,a0
+20000e4c: 8082 ret
+20000e4e: 00d05d63 blez a3,20000e68 <strncmp+0x3e>
+20000e52: 0005c683 lbu a3,0(a1)
+20000e56: 0785 addi a5,a5,1
+20000e58: 0585 addi a1,a1,1
+20000e5a: fce68be3 beq a3,a4,20000e30 <strncmp+0x6>
+20000e5e: 4505 li a0,1
+20000e60: fee6e6e3 bltu a3,a4,20000e4c <strncmp+0x22>
+20000e64: 557d li a0,-1
+20000e66: 8082 ret
+20000e68: 4501 li a0,0
+20000e6a: 8082 ret
+
+20000e6c <putc>:
+20000e6c: 1141 addi sp,sp,-16
+20000e6e: c422 sw s0,8(sp)
+20000e70: c606 sw ra,12(sp)
+20000e72: 47a9 li a5,10
+20000e74: 842a mv s0,a0
+20000e76: 00f50863 beq a0,a5,20000e86 <putc+0x1a>
+20000e7a: 85a2 mv a1,s0
+20000e7c: 4422 lw s0,8(sp)
+20000e7e: 40b2 lw ra,12(sp)
+20000e80: 4501 li a0,0
+20000e82: 0141 addi sp,sp,16
+20000e84: b559 j 20000d0a <serial_send_byte>
+20000e86: 45b5 li a1,13
+20000e88: 4501 li a0,0
+20000e8a: 3541 jal 20000d0a <serial_send_byte>
+20000e8c: 85a2 mv a1,s0
+20000e8e: 4422 lw s0,8(sp)
+20000e90: 40b2 lw ra,12(sp)
+20000e92: 4501 li a0,0
+20000e94: 0141 addi sp,sp,16
+20000e96: bd95 j 20000d0a <serial_send_byte>
+
+20000e98 <getc>:
+20000e98: 1141 addi sp,sp,-16
+20000e9a: 4501 li a0,0
+20000e9c: c422 sw s0,8(sp)
+20000e9e: c606 sw ra,12(sp)
+20000ea0: 3555 jal 20000d44 <serial_recv_byte>
+20000ea2: 47b5 li a5,13
+20000ea4: 4429 li s0,10
+20000ea6: 00f50363 beq a0,a5,20000eac <getc+0x14>
+20000eaa: 842a mv s0,a0
+20000eac: 8522 mv a0,s0
+20000eae: 3f7d jal 20000e6c <putc>
+20000eb0: 40b2 lw ra,12(sp)
+20000eb2: 8522 mv a0,s0
+20000eb4: 4422 lw s0,8(sp)
+20000eb6: 0141 addi sp,sp,16
+20000eb8: 8082 ret
+
+20000eba <puts>:
+20000eba: 1141 addi sp,sp,-16
+20000ebc: c422 sw s0,8(sp)
+20000ebe: c606 sw ra,12(sp)
+20000ec0: 842a mv s0,a0
+20000ec2: 00054503 lbu a0,0(a0)
+20000ec6: c511 beqz a0,20000ed2 <puts+0x18>
+20000ec8: 0405 addi s0,s0,1
+20000eca: 374d jal 20000e6c <putc>
+20000ecc: 00044503 lbu a0,0(s0)
+20000ed0: fd65 bnez a0,20000ec8 <puts+0xe>
+20000ed2: 40b2 lw ra,12(sp)
+20000ed4: 4422 lw s0,8(sp)
+20000ed6: 4501 li a0,0
+20000ed8: 0141 addi sp,sp,16
+20000eda: 8082 ret
+
+20000edc <gets>:
+20000edc: 1141 addi sp,sp,-16
+20000ede: c422 sw s0,8(sp)
+20000ee0: c226 sw s1,4(sp)
+20000ee2: c04a sw s2,0(sp)
+20000ee4: c606 sw ra,12(sp)
+20000ee6: 4929 li s2,10
+20000ee8: 842a mv s0,a0
+20000eea: 4481 li s1,0
+20000eec: 3775 jal 20000e98 <getc>
+20000eee: 01250c63 beq a0,s2,20000f06 <gets+0x2a>
+20000ef2: 00a40023 sb a0,0(s0)
+20000ef6: 00148793 addi a5,s1,1
+20000efa: 0405 addi s0,s0,1
+20000efc: c519 beqz a0,20000f0a <gets+0x2e>
+20000efe: 84be mv s1,a5
+20000f00: 3f61 jal 20000e98 <getc>
+20000f02: ff2518e3 bne a0,s2,20000ef2 <gets+0x16>
+20000f06: 00040023 sb zero,0(s0)
+20000f0a: 40b2 lw ra,12(sp)
+20000f0c: 4422 lw s0,8(sp)
+20000f0e: 4902 lw s2,0(sp)
+20000f10: 8526 mv a0,s1
+20000f12: 4492 lw s1,4(sp)
+20000f14: 0141 addi sp,sp,16
+20000f16: 8082 ret
+
+20000f18 <putxval>:
+20000f18: 1101 addi sp,sp,-32
+20000f1a: ce06 sw ra,28(sp)
+20000f1c: cc22 sw s0,24(sp)
+20000f1e: 00010623 sb zero,12(sp)
+20000f22: ed05 bnez a0,20000f5a <putxval+0x42>
+20000f24: e191 bnez a1,20000f28 <putxval+0x10>
+20000f26: 4585 li a1,1
+20000f28: 00b10793 addi a5,sp,11
+20000f2c: 03000713 li a4,48
+20000f30: c591 beqz a1,20000f3c <putxval+0x24>
+20000f32: 00e78023 sb a4,0(a5)
+20000f36: 15fd addi a1,a1,-1
+20000f38: 17fd addi a5,a5,-1
+20000f3a: fde5 bnez a1,20000f32 <putxval+0x1a>
+20000f3c: 0017c503 lbu a0,1(a5)
+20000f40: 00178413 addi s0,a5,1
+20000f44: c511 beqz a0,20000f50 <putxval+0x38>
+20000f46: 0405 addi s0,s0,1
+20000f48: 3715 jal 20000e6c <putc>
+20000f4a: 00044503 lbu a0,0(s0)
+20000f4e: fd65 bnez a0,20000f46 <putxval+0x2e>
+20000f50: 40f2 lw ra,28(sp)
+20000f52: 4462 lw s0,24(sp)
+20000f54: 4501 li a0,0
+20000f56: 6105 addi sp,sp,32
+20000f58: 8082 ret
+20000f5a: 872a mv a4,a0
+20000f5c: 00f77793 andi a5,a4,15
+20000f60: 20000817 auipc a6,0x20000
+20000f64: 8cc80813 addi a6,a6,-1844 # 4000082c <uart_ctrl_addr+0x628>
+20000f68: 97c2 add a5,a5,a6
+20000f6a: 0007c503 lbu a0,0(a5)
+20000f6e: 00b10413 addi s0,sp,11
+20000f72: fff40793 addi a5,s0,-1
+20000f76: 00a780a3 sb a0,1(a5)
+20000f7a: 8311 srli a4,a4,0x4
+20000f7c: cd99 beqz a1,20000f9a <putxval+0x82>
+20000f7e: 15fd addi a1,a1,-1
+20000f80: d755 beqz a4,20000f2c <putxval+0x14>
+20000f82: 843e mv s0,a5
+20000f84: 00f77793 andi a5,a4,15
+20000f88: 97c2 add a5,a5,a6
+20000f8a: 0007c503 lbu a0,0(a5)
+20000f8e: 8311 srli a4,a4,0x4
+20000f90: fff40793 addi a5,s0,-1
+20000f94: 00a780a3 sb a0,1(a5)
+20000f98: f1fd bnez a1,20000f7e <putxval+0x66>
+20000f9a: 00f77693 andi a3,a4,15
+20000f9e: 96c2 add a3,a3,a6
+20000fa0: fff78613 addi a2,a5,-1
+20000fa4: d345 beqz a4,20000f44 <putxval+0x2c>
+20000fa6: 0006c503 lbu a0,0(a3)
+20000faa: 8311 srli a4,a4,0x4
+20000fac: 843e mv s0,a5
+20000fae: 00a78023 sb a0,0(a5)
+20000fb2: 00f77693 andi a3,a4,15
+20000fb6: 87b2 mv a5,a2
+20000fb8: 96c2 add a3,a3,a6
+20000fba: fff78613 addi a2,a5,-1
+20000fbe: d359 beqz a4,20000f44 <putxval+0x2c>
+20000fc0: b7dd j 20000fa6 <putxval+0x8e>
+
+20000fc2 <malloc_init>:
+20000fc2: 1141 addi sp,sp,-16
+20000fc4: 4501 li a0,0
+20000fc6: c606 sw ra,12(sp)
+20000fc8: 20f9 jal 20001096 <sbrk>
+20000fca: 40b2 lw ra,12(sp)
+20000fcc: 20002797 auipc a5,0x20002
+20000fd0: 08a7a423 sw a0,136(a5) # 40003054 <last_valid_address>
+20000fd4: 20002797 auipc a5,0x20002
+20000fd8: 08a7a223 sw a0,132(a5) # 40003058 <managed_memory_start>
+20000fdc: 4785 li a5,1
+20000fde: 20002717 auipc a4,0x20002
+20000fe2: 06f72f23 sw a5,126(a4) # 4000305c <has_initialized>
+20000fe6: 0141 addi sp,sp,16
+20000fe8: 8082 ret
+
+20000fea <free>:
+20000fea: 4785 li a5,1
+20000fec: fef52c23 sw a5,-8(a0)
+20000ff0: 8082 ret
+
+20000ff2 <malloc>:
+20000ff2: 1141 addi sp,sp,-16
+20000ff4: c04a sw s2,0(sp)
+20000ff6: 20002917 auipc s2,0x20002
+20000ffa: 06690913 addi s2,s2,102 # 4000305c <has_initialized>
+20000ffe: 00092783 lw a5,0(s2)
+20001002: c422 sw s0,8(sp)
+20001004: c606 sw ra,12(sp)
+20001006: c226 sw s1,4(sp)
+20001008: 00850413 addi s0,a0,8
+2000100c: c7a1 beqz a5,20001054 <malloc+0x62>
+2000100e: 20002497 auipc s1,0x20002
+20001012: 04648493 addi s1,s1,70 # 40003054 <last_valid_address>
+20001016: 4094 lw a3,0(s1)
+20001018: 20002517 auipc a0,0x20002
+2000101c: 04052503 lw a0,64(a0) # 40003058 <managed_memory_start>
+20001020: 04d50863 beq a0,a3,20001070 <malloc+0x7e>
+20001024: 4118 lw a4,0(a0)
+20001026: 415c lw a5,4(a0)
+20001028: c319 beqz a4,2000102e <malloc+0x3c>
+2000102a: 0487dd63 bge a5,s0,20001084 <malloc+0x92>
+2000102e: 953e add a0,a0,a5
+20001030: fed51ae3 bne a0,a3,20001024 <malloc+0x32>
+20001034: 8522 mv a0,s0
+20001036: 2085 jal 20001096 <sbrk>
+20001038: 4088 lw a0,0(s1)
+2000103a: 008507b3 add a5,a0,s0
+2000103e: c09c sw a5,0(s1)
+20001040: 00052023 sw zero,0(a0)
+20001044: c140 sw s0,4(a0)
+20001046: 40b2 lw ra,12(sp)
+20001048: 4422 lw s0,8(sp)
+2000104a: 4492 lw s1,4(sp)
+2000104c: 4902 lw s2,0(sp)
+2000104e: 0521 addi a0,a0,8
+20001050: 0141 addi sp,sp,16
+20001052: 8082 ret
+20001054: 4501 li a0,0
+20001056: 2081 jal 20001096 <sbrk>
+20001058: 20002797 auipc a5,0x20002
+2000105c: 00a7a023 sw a0,0(a5) # 40003058 <managed_memory_start>
+20001060: 20002497 auipc s1,0x20002
+20001064: ff448493 addi s1,s1,-12 # 40003054 <last_valid_address>
+20001068: 4785 li a5,1
+2000106a: c088 sw a0,0(s1)
+2000106c: 00f92023 sw a5,0(s2)
+20001070: 8522 mv a0,s0
+20001072: 2015 jal 20001096 <sbrk>
+20001074: 4088 lw a0,0(s1)
+20001076: 008507b3 add a5,a0,s0
+2000107a: c09c sw a5,0(s1)
+2000107c: 00052023 sw zero,0(a0)
+20001080: c140 sw s0,4(a0)
+20001082: b7d1 j 20001046 <malloc+0x54>
+20001084: 40b2 lw ra,12(sp)
+20001086: 4422 lw s0,8(sp)
+20001088: 00052023 sw zero,0(a0)
+2000108c: 4492 lw s1,4(sp)
+2000108e: 4902 lw s2,0(sp)
+20001090: 0521 addi a0,a0,8
+20001092: 0141 addi sp,sp,16
+20001094: 8082 ret
+
+20001096 <sbrk>:
+20001096: 20002717 auipc a4,0x20002
+2000109a: fca70713 addi a4,a4,-54 # 40003060 <heap_ptr>
+2000109e: 431c lw a5,0(a4)
+200010a0: c789 beqz a5,200010aa <sbrk+0x14>
+200010a2: 953e add a0,a0,a5
+200010a4: c308 sw a0,0(a4)
+200010a6: 853e mv a0,a5
+200010a8: 8082 ret
+200010aa: 20002797 auipc a5,0x20002
+200010ae: fba78793 addi a5,a5,-70 # 40003064 <_end>
+200010b2: 953e add a0,a0,a5
+200010b4: c308 sw a0,0(a4)
+200010b6: 853e mv a0,a5
+200010b8: 8082 ret
+
+Disassembly of section .text.startup:
+
+200010ba <main>:
+200010ba: 7135 addi sp,sp,-160
+200010bc: 03000513 li a0,48
+200010c0: cf06 sw ra,156(sp)
+200010c2: cd22 sw s0,152(sp)
+200010c4: dae6 sw s9,116(sp)
+200010c6: cb26 sw s1,148(sp)
+200010c8: c94a sw s2,144(sp)
+200010ca: c74e sw s3,140(sp)
+200010cc: c552 sw s4,136(sp)
+200010ce: c356 sw s5,132(sp)
+200010d0: c15a sw s6,128(sp)
+200010d2: dede sw s7,124(sp)
+200010d4: dce2 sw s8,120(sp)
+200010d6: d8ea sw s10,112(sp)
+200010d8: d6ee sw s11,108(sp)
+200010da: 3f21 jal 20000ff2 <malloc>
+200010dc: 87aa mv a5,a0
+200010de: 20002417 auipc s0,0x20002
+200010e2: f6e40413 addi s0,s0,-146 # 4000304c <Next_Ptr_Glob>
+200010e6: 03000513 li a0,48
+200010ea: c01c sw a5,0(s0)
+200010ec: 3719 jal 20000ff2 <malloc>
+200010ee: 401c lw a5,0(s0)
+200010f0: 20002c97 auipc s9,0x20002
+200010f4: f60c8c93 addi s9,s9,-160 # 40003050 <Ptr_Glob>
+200010f8: 00aca023 sw a0,0(s9)
+200010fc: c11c sw a5,0(a0)
+200010fe: 4789 li a5,2
+20001100: c51c sw a5,8(a0)
+20001102: 02800793 li a5,40
+20001106: c55c sw a5,12(a0)
+20001108: 1ffff597 auipc a1,0x1ffff
+2000110c: 11458593 addi a1,a1,276 # 4000021c <uart_ctrl_addr+0x18>
+20001110: 00052223 sw zero,4(a0)
+20001114: 0541 addi a0,a0,16
+20001116: 31d9 jal 20000ddc <strcpy>
+20001118: 1ffff597 auipc a1,0x1ffff
+2000111c: 12458593 addi a1,a1,292 # 4000023c <uart_ctrl_addr+0x38>
+20001120: 1008 addi a0,sp,32
+20001122: 396d jal 20000ddc <strcpy>
+20001124: 47a9 li a5,10
+20001126: 1ffff717 auipc a4,0x1ffff
+2000112a: 7f670713 addi a4,a4,2038 # 4000091c <Arr_2_Glob>
+2000112e: 1ffff517 auipc a0,0x1ffff
+20001132: 3b250513 addi a0,a0,946 # 400004e0 <uart_ctrl_addr+0x2dc>
+20001136: 64f72e23 sw a5,1628(a4)
+2000113a: cbcff0ef jal ra,200005f6 <ee_printf>
+2000113e: 1ffff517 auipc a0,0x1ffff
+20001142: 11e50513 addi a0,a0,286 # 4000025c <uart_ctrl_addr+0x58>
+20001146: cb0ff0ef jal ra,200005f6 <ee_printf>
+2000114a: 1ffff517 auipc a0,0x1ffff
+2000114e: 39650513 addi a0,a0,918 # 400004e0 <uart_ctrl_addr+0x2dc>
+20001152: ca4ff0ef jal ra,200005f6 <ee_printf>
+20001156: 1ffff797 auipc a5,0x1ffff
+2000115a: 6ea7a783 lw a5,1770(a5) # 40000840 <rodata_end>
+2000115e: 50078763 beqz a5,2000166c <main+0x5b2>
+20001162: 1ffff517 auipc a0,0x1ffff
+20001166: 12a50513 addi a0,a0,298 # 4000028c <uart_ctrl_addr+0x88>
+2000116a: c8cff0ef jal ra,200005f6 <ee_printf>
+2000116e: 1ffff517 auipc a0,0x1ffff
+20001172: 37250513 addi a0,a0,882 # 400004e0 <uart_ctrl_addr+0x2dc>
+20001176: c80ff0ef jal ra,200005f6 <ee_printf>
+2000117a: 1ffff517 auipc a0,0x1ffff
+2000117e: 16e50513 addi a0,a0,366 # 400002e8 <uart_ctrl_addr+0xe4>
+20001182: c74ff0ef jal ra,200005f6 <ee_printf>
+20001186: 1ffff517 auipc a0,0x1ffff
+2000118a: 35a50513 addi a0,a0,858 # 400004e0 <uart_ctrl_addr+0x2dc>
+2000118e: c68ff0ef jal ra,200005f6 <ee_printf>
+20001192: 45a9 li a1,10
+20001194: 1ffff517 auipc a0,0x1ffff
+20001198: 18c50513 addi a0,a0,396 # 40000320 <uart_ctrl_addr+0x11c>
+2000119c: c5aff0ef jal ra,200005f6 <ee_printf>
+200011a0: 1ffff517 auipc a0,0x1ffff
+200011a4: 6a450513 addi a0,a0,1700 # 40000844 <data_end>
+200011a8: 3631 jal 20000cb4 <mytimes>
+200011aa: 1ffff797 auipc a5,0x1ffff
+200011ae: 69a78793 addi a5,a5,1690 # 40000844 <data_end>
+200011b2: 439c lw a5,0(a5)
+200011b4: 20002717 auipc a4,0x20002
+200011b8: e8870713 addi a4,a4,-376 # 4000303c <Begin_Time>
+200011bc: 4485 li s1,1
+200011be: c31c sw a5,0(a4)
+200011c0: 20002997 auipc s3,0x20002
+200011c4: e8198993 addi s3,s3,-383 # 40003041 <Ch_1_Glob>
+200011c8: 20002a17 auipc s4,0x20002
+200011cc: e7ca0a13 addi s4,s4,-388 # 40003044 <Bool_Glob>
+200011d0: 20002417 auipc s0,0x20002
+200011d4: e7040413 addi s0,s0,-400 # 40003040 <Ch_2_Glob>
+200011d8: 20002a97 auipc s5,0x20002
+200011dc: e70a8a93 addi s5,s5,-400 # 40003048 <Int_Glob>
+200011e0: 04100b93 li s7,65
+200011e4: 4b05 li s6,1
+200011e6: 1ffffd17 auipc s10,0x1ffff
+200011ea: 16ad0d13 addi s10,s10,362 # 40000350 <uart_ctrl_addr+0x14c>
+200011ee: 1ffffc17 auipc s8,0x1ffff
+200011f2: 182c0c13 addi s8,s8,386 # 40000370 <uart_ctrl_addr+0x16c>
+200011f6: 04200793 li a5,66
+200011fa: 85ea mv a1,s10
+200011fc: 0088 addi a0,sp,64
+200011fe: 00f40023 sb a5,0(s0)
+20001202: 01798023 sb s7,0(s3)
+20001206: 016a2023 sw s6,0(s4)
+2000120a: 3ec9 jal 20000ddc <strcpy>
+2000120c: 008c addi a1,sp,64
+2000120e: 1008 addi a0,sp,32
+20001210: ce5a sw s6,28(sp)
+20001212: 8ceff0ef jal ra,200002e0 <Func_2>
+20001216: 00153793 seqz a5,a0
+2000121a: 0830 addi a2,sp,24
+2000121c: 458d li a1,3
+2000121e: 00fa2023 sw a5,0(s4)
+20001222: 4509 li a0,2
+20001224: 479d li a5,7
+20001226: cc3e sw a5,24(sp)
+20001228: 84eff0ef jal ra,20000276 <Proc_7>
+2000122c: 46e2 lw a3,24(sp)
+2000122e: 460d li a2,3
+20001230: 1ffff597 auipc a1,0x1ffff
+20001234: 6ec58593 addi a1,a1,1772 # 4000091c <Arr_2_Glob>
+20001238: 1ffff517 auipc a0,0x1ffff
+2000123c: 61c50513 addi a0,a0,1564 # 40000854 <Arr_1_Glob>
+20001240: 83eff0ef jal ra,2000027e <Proc_8>
+20001244: 000ca503 lw a0,0(s9)
+20001248: ec3fe0ef jal ra,2000010a <Proc_1>
+2000124c: 00044703 lbu a4,0(s0)
+20001250: 04000793 li a5,64
+20001254: 40e7fa63 bgeu a5,a4,20001668 <main+0x5ae>
+20001258: 04100d93 li s11,65
+2000125c: 490d li s2,3
+2000125e: a809 j 20001270 <main+0x1b6>
+20001260: 00044703 lbu a4,0(s0)
+20001264: 001d8793 addi a5,s11,1
+20001268: 0ff7fd93 andi s11,a5,255
+2000126c: 03b76c63 bltu a4,s11,200012a4 <main+0x1ea>
+20001270: 04300593 li a1,67
+20001274: 856e mv a0,s11
+20001276: 84eff0ef jal ra,200002c4 <Func_1>
+2000127a: 4772 lw a4,28(sp)
+2000127c: fee512e3 bne a0,a4,20001260 <main+0x1a6>
+20001280: 086c addi a1,sp,28
+20001282: 4501 li a0,0
+20001284: fb7fe0ef jal ra,2000023a <Proc_6>
+20001288: 85e2 mv a1,s8
+2000128a: 0088 addi a0,sp,64
+2000128c: 3e81 jal 20000ddc <strcpy>
+2000128e: 00044703 lbu a4,0(s0)
+20001292: 001d8793 addi a5,s11,1
+20001296: 009aa023 sw s1,0(s5)
+2000129a: 0ff7fd93 andi s11,a5,255
+2000129e: 8926 mv s2,s1
+200012a0: fdb778e3 bgeu a4,s11,20001270 <main+0x1b6>
+200012a4: 00191793 slli a5,s2,0x1
+200012a8: 993e add s2,s2,a5
+200012aa: 4662 lw a2,24(sp)
+200012ac: 0009c703 lbu a4,0(s3)
+200012b0: 02c946b3 div a3,s2,a2
+200012b4: 87b6 mv a5,a3
+200012b6: 01771863 bne a4,s7,200012c6 <main+0x20c>
+200012ba: 000aa783 lw a5,0(s5)
+200012be: 00968713 addi a4,a3,9
+200012c2: 40f707b3 sub a5,a4,a5
+200012c6: 0485 addi s1,s1,1
+200012c8: 472d li a4,11
+200012ca: f2e496e3 bne s1,a4,200011f6 <main+0x13c>
+200012ce: 1ffff517 auipc a0,0x1ffff
+200012d2: 57650513 addi a0,a0,1398 # 40000844 <data_end>
+200012d6: c436 sw a3,8(sp)
+200012d8: c232 sw a2,4(sp)
+200012da: c63e sw a5,12(sp)
+200012dc: 1ffffb97 auipc s7,0x1ffff
+200012e0: 568b8b93 addi s7,s7,1384 # 40000844 <data_end>
+200012e4: 3ac1 jal 20000cb4 <mytimes>
+200012e6: 000ba703 lw a4,0(s7)
+200012ea: 20002b17 auipc s6,0x20002
+200012ee: d4eb0b13 addi s6,s6,-690 # 40003038 <End_Time>
+200012f2: 1ffff517 auipc a0,0x1ffff
+200012f6: 09e50513 addi a0,a0,158 # 40000390 <uart_ctrl_addr+0x18c>
+200012fa: 00eb2023 sw a4,0(s6)
+200012fe: af8ff0ef jal ra,200005f6 <ee_printf>
+20001302: 1ffff517 auipc a0,0x1ffff
+20001306: 1de50513 addi a0,a0,478 # 400004e0 <uart_ctrl_addr+0x2dc>
+2000130a: aecff0ef jal ra,200005f6 <ee_printf>
+2000130e: 1ffff517 auipc a0,0x1ffff
+20001312: 09250513 addi a0,a0,146 # 400003a0 <uart_ctrl_addr+0x19c>
+20001316: ae0ff0ef jal ra,200005f6 <ee_printf>
+2000131a: 1ffff517 auipc a0,0x1ffff
+2000131e: 1c650513 addi a0,a0,454 # 400004e0 <uart_ctrl_addr+0x2dc>
+20001322: ad4ff0ef jal ra,200005f6 <ee_printf>
+20001326: 000aa583 lw a1,0(s5)
+2000132a: 1ffff517 auipc a0,0x1ffff
+2000132e: 0ae50513 addi a0,a0,174 # 400003d8 <uart_ctrl_addr+0x1d4>
+20001332: 20002497 auipc s1,0x20002
+20001336: d0248493 addi s1,s1,-766 # 40003034 <User_Time>
+2000133a: abcff0ef jal ra,200005f6 <ee_printf>
+2000133e: 4595 li a1,5
+20001340: 1ffff517 auipc a0,0x1ffff
+20001344: 0b450513 addi a0,a0,180 # 400003f4 <uart_ctrl_addr+0x1f0>
+20001348: aaeff0ef jal ra,200005f6 <ee_printf>
+2000134c: 000a2583 lw a1,0(s4)
+20001350: 1ffff517 auipc a0,0x1ffff
+20001354: 0c050513 addi a0,a0,192 # 40000410 <uart_ctrl_addr+0x20c>
+20001358: a9eff0ef jal ra,200005f6 <ee_printf>
+2000135c: 4585 li a1,1
+2000135e: 1ffff517 auipc a0,0x1ffff
+20001362: 09650513 addi a0,a0,150 # 400003f4 <uart_ctrl_addr+0x1f0>
+20001366: a90ff0ef jal ra,200005f6 <ee_printf>
+2000136a: 0009c583 lbu a1,0(s3)
+2000136e: 1ffff517 auipc a0,0x1ffff
+20001372: 0be50513 addi a0,a0,190 # 4000042c <uart_ctrl_addr+0x228>
+20001376: a80ff0ef jal ra,200005f6 <ee_printf>
+2000137a: 04100593 li a1,65
+2000137e: 1ffff517 auipc a0,0x1ffff
+20001382: 0ca50513 addi a0,a0,202 # 40000448 <uart_ctrl_addr+0x244>
+20001386: a70ff0ef jal ra,200005f6 <ee_printf>
+2000138a: 00044583 lbu a1,0(s0)
+2000138e: 1ffff517 auipc a0,0x1ffff
+20001392: 0d650513 addi a0,a0,214 # 40000464 <uart_ctrl_addr+0x260>
+20001396: 20002417 auipc s0,0x20002
+2000139a: cb640413 addi s0,s0,-842 # 4000304c <Next_Ptr_Glob>
+2000139e: a58ff0ef jal ra,200005f6 <ee_printf>
+200013a2: 04200593 li a1,66
+200013a6: 1ffff517 auipc a0,0x1ffff
+200013aa: 0a250513 addi a0,a0,162 # 40000448 <uart_ctrl_addr+0x244>
+200013ae: a48ff0ef jal ra,200005f6 <ee_printf>
+200013b2: 030ba583 lw a1,48(s7)
+200013b6: 1ffff517 auipc a0,0x1ffff
+200013ba: 0ca50513 addi a0,a0,202 # 40000480 <uart_ctrl_addr+0x27c>
+200013be: a38ff0ef jal ra,200005f6 <ee_printf>
+200013c2: 459d li a1,7
+200013c4: 1ffff517 auipc a0,0x1ffff
+200013c8: 03050513 addi a0,a0,48 # 400003f4 <uart_ctrl_addr+0x1f0>
+200013cc: a2aff0ef jal ra,200005f6 <ee_printf>
+200013d0: 1ffff797 auipc a5,0x1ffff
+200013d4: 54c78793 addi a5,a5,1356 # 4000091c <Arr_2_Glob>
+200013d8: 65c7a583 lw a1,1628(a5)
+200013dc: 1ffff517 auipc a0,0x1ffff
+200013e0: 0c050513 addi a0,a0,192 # 4000049c <uart_ctrl_addr+0x298>
+200013e4: a12ff0ef jal ra,200005f6 <ee_printf>
+200013e8: 1ffff517 auipc a0,0x1ffff
+200013ec: 0d050513 addi a0,a0,208 # 400004b8 <uart_ctrl_addr+0x2b4>
+200013f0: a06ff0ef jal ra,200005f6 <ee_printf>
+200013f4: 1ffff517 auipc a0,0x1ffff
+200013f8: 0f050513 addi a0,a0,240 # 400004e4 <uart_ctrl_addr+0x2e0>
+200013fc: 9faff0ef jal ra,200005f6 <ee_printf>
+20001400: 000ca703 lw a4,0(s9)
+20001404: 1ffff517 auipc a0,0x1ffff
+20001408: 0ec50513 addi a0,a0,236 # 400004f0 <uart_ctrl_addr+0x2ec>
+2000140c: 430c lw a1,0(a4)
+2000140e: 9e8ff0ef jal ra,200005f6 <ee_printf>
+20001412: 1ffff517 auipc a0,0x1ffff
+20001416: 0fa50513 addi a0,a0,250 # 4000050c <uart_ctrl_addr+0x308>
+2000141a: 9dcff0ef jal ra,200005f6 <ee_printf>
+2000141e: 000ca703 lw a4,0(s9)
+20001422: 1ffff517 auipc a0,0x1ffff
+20001426: 11e50513 addi a0,a0,286 # 40000540 <uart_ctrl_addr+0x33c>
+2000142a: 434c lw a1,4(a4)
+2000142c: 9caff0ef jal ra,200005f6 <ee_printf>
+20001430: 4581 li a1,0
+20001432: 1ffff517 auipc a0,0x1ffff
+20001436: fc250513 addi a0,a0,-62 # 400003f4 <uart_ctrl_addr+0x1f0>
+2000143a: 9bcff0ef jal ra,200005f6 <ee_printf>
+2000143e: 000ca703 lw a4,0(s9)
+20001442: 1ffff517 auipc a0,0x1ffff
+20001446: 11a50513 addi a0,a0,282 # 4000055c <uart_ctrl_addr+0x358>
+2000144a: 470c lw a1,8(a4)
+2000144c: 9aaff0ef jal ra,200005f6 <ee_printf>
+20001450: 4589 li a1,2
+20001452: 1ffff517 auipc a0,0x1ffff
+20001456: fa250513 addi a0,a0,-94 # 400003f4 <uart_ctrl_addr+0x1f0>
+2000145a: 99cff0ef jal ra,200005f6 <ee_printf>
+2000145e: 000ca703 lw a4,0(s9)
+20001462: 1ffff517 auipc a0,0x1ffff
+20001466: 11650513 addi a0,a0,278 # 40000578 <uart_ctrl_addr+0x374>
+2000146a: 474c lw a1,12(a4)
+2000146c: 98aff0ef jal ra,200005f6 <ee_printf>
+20001470: 45c5 li a1,17
+20001472: 1ffff517 auipc a0,0x1ffff
+20001476: f8250513 addi a0,a0,-126 # 400003f4 <uart_ctrl_addr+0x1f0>
+2000147a: 97cff0ef jal ra,200005f6 <ee_printf>
+2000147e: 000ca583 lw a1,0(s9)
+20001482: 1ffff517 auipc a0,0x1ffff
+20001486: 11250513 addi a0,a0,274 # 40000594 <uart_ctrl_addr+0x390>
+2000148a: 05c1 addi a1,a1,16
+2000148c: 96aff0ef jal ra,200005f6 <ee_printf>
+20001490: 1ffff517 auipc a0,0x1ffff
+20001494: 12050513 addi a0,a0,288 # 400005b0 <uart_ctrl_addr+0x3ac>
+20001498: 95eff0ef jal ra,200005f6 <ee_printf>
+2000149c: 1ffff517 auipc a0,0x1ffff
+200014a0: 14c50513 addi a0,a0,332 # 400005e8 <uart_ctrl_addr+0x3e4>
+200014a4: 952ff0ef jal ra,200005f6 <ee_printf>
+200014a8: 4018 lw a4,0(s0)
+200014aa: 1ffff517 auipc a0,0x1ffff
+200014ae: 04650513 addi a0,a0,70 # 400004f0 <uart_ctrl_addr+0x2ec>
+200014b2: 430c lw a1,0(a4)
+200014b4: 942ff0ef jal ra,200005f6 <ee_printf>
+200014b8: 1ffff517 auipc a0,0x1ffff
+200014bc: 14450513 addi a0,a0,324 # 400005fc <uart_ctrl_addr+0x3f8>
+200014c0: 936ff0ef jal ra,200005f6 <ee_printf>
+200014c4: 4018 lw a4,0(s0)
+200014c6: 1ffff517 auipc a0,0x1ffff
+200014ca: 07a50513 addi a0,a0,122 # 40000540 <uart_ctrl_addr+0x33c>
+200014ce: 434c lw a1,4(a4)
+200014d0: 926ff0ef jal ra,200005f6 <ee_printf>
+200014d4: 4581 li a1,0
+200014d6: 1ffff517 auipc a0,0x1ffff
+200014da: f1e50513 addi a0,a0,-226 # 400003f4 <uart_ctrl_addr+0x1f0>
+200014de: 918ff0ef jal ra,200005f6 <ee_printf>
+200014e2: 4018 lw a4,0(s0)
+200014e4: 1ffff517 auipc a0,0x1ffff
+200014e8: 07850513 addi a0,a0,120 # 4000055c <uart_ctrl_addr+0x358>
+200014ec: 470c lw a1,8(a4)
+200014ee: 908ff0ef jal ra,200005f6 <ee_printf>
+200014f2: 4585 li a1,1
+200014f4: 1ffff517 auipc a0,0x1ffff
+200014f8: f0050513 addi a0,a0,-256 # 400003f4 <uart_ctrl_addr+0x1f0>
+200014fc: 8faff0ef jal ra,200005f6 <ee_printf>
+20001500: 4018 lw a4,0(s0)
+20001502: 1ffff517 auipc a0,0x1ffff
+20001506: 07650513 addi a0,a0,118 # 40000578 <uart_ctrl_addr+0x374>
+2000150a: 474c lw a1,12(a4)
+2000150c: 8eaff0ef jal ra,200005f6 <ee_printf>
+20001510: 45c9 li a1,18
+20001512: 1ffff517 auipc a0,0x1ffff
+20001516: ee250513 addi a0,a0,-286 # 400003f4 <uart_ctrl_addr+0x1f0>
+2000151a: 8dcff0ef jal ra,200005f6 <ee_printf>
+2000151e: 400c lw a1,0(s0)
+20001520: 1ffff517 auipc a0,0x1ffff
+20001524: 07450513 addi a0,a0,116 # 40000594 <uart_ctrl_addr+0x390>
+20001528: 20002417 auipc s0,0x20002
+2000152c: b1440413 addi s0,s0,-1260 # 4000303c <Begin_Time>
+20001530: 05c1 addi a1,a1,16
+20001532: 8c4ff0ef jal ra,200005f6 <ee_printf>
+20001536: 1ffff517 auipc a0,0x1ffff
+2000153a: 07a50513 addi a0,a0,122 # 400005b0 <uart_ctrl_addr+0x3ac>
+2000153e: 8b8ff0ef jal ra,200005f6 <ee_printf>
+20001542: 47b2 lw a5,12(sp)
+20001544: 1ffff517 auipc a0,0x1ffff
+20001548: 0f850513 addi a0,a0,248 # 4000063c <uart_ctrl_addr+0x438>
+2000154c: 85be mv a1,a5
+2000154e: 8a8ff0ef jal ra,200005f6 <ee_printf>
+20001552: 4595 li a1,5
+20001554: 1ffff517 auipc a0,0x1ffff
+20001558: ea050513 addi a0,a0,-352 # 400003f4 <uart_ctrl_addr+0x1f0>
+2000155c: 89aff0ef jal ra,200005f6 <ee_printf>
+20001560: 4612 lw a2,4(sp)
+20001562: 46a2 lw a3,8(sp)
+20001564: 1ffff517 auipc a0,0x1ffff
+20001568: 0f450513 addi a0,a0,244 # 40000658 <uart_ctrl_addr+0x454>
+2000156c: 40c90933 sub s2,s2,a2
+20001570: 00391793 slli a5,s2,0x3
+20001574: 41278933 sub s2,a5,s2
+20001578: 40d905b3 sub a1,s2,a3
+2000157c: 87aff0ef jal ra,200005f6 <ee_printf>
+20001580: 45b5 li a1,13
+20001582: 1ffff517 auipc a0,0x1ffff
+20001586: e7250513 addi a0,a0,-398 # 400003f4 <uart_ctrl_addr+0x1f0>
+2000158a: 86cff0ef jal ra,200005f6 <ee_printf>
+2000158e: 45e2 lw a1,24(sp)
+20001590: 1ffff517 auipc a0,0x1ffff
+20001594: 0e450513 addi a0,a0,228 # 40000674 <uart_ctrl_addr+0x470>
+20001598: 85eff0ef jal ra,200005f6 <ee_printf>
+2000159c: 459d li a1,7
+2000159e: 1ffff517 auipc a0,0x1ffff
+200015a2: e5650513 addi a0,a0,-426 # 400003f4 <uart_ctrl_addr+0x1f0>
+200015a6: 850ff0ef jal ra,200005f6 <ee_printf>
+200015aa: 45f2 lw a1,28(sp)
+200015ac: 1ffff517 auipc a0,0x1ffff
+200015b0: 0e450513 addi a0,a0,228 # 40000690 <uart_ctrl_addr+0x48c>
+200015b4: 842ff0ef jal ra,200005f6 <ee_printf>
+200015b8: 4585 li a1,1
+200015ba: 1ffff517 auipc a0,0x1ffff
+200015be: e3a50513 addi a0,a0,-454 # 400003f4 <uart_ctrl_addr+0x1f0>
+200015c2: 834ff0ef jal ra,200005f6 <ee_printf>
+200015c6: 100c addi a1,sp,32
+200015c8: 1ffff517 auipc a0,0x1ffff
+200015cc: 0e450513 addi a0,a0,228 # 400006ac <uart_ctrl_addr+0x4a8>
+200015d0: 826ff0ef jal ra,200005f6 <ee_printf>
+200015d4: 1ffff517 auipc a0,0x1ffff
+200015d8: 0f450513 addi a0,a0,244 # 400006c8 <uart_ctrl_addr+0x4c4>
+200015dc: 81aff0ef jal ra,200005f6 <ee_printf>
+200015e0: 008c addi a1,sp,64
+200015e2: 1ffff517 auipc a0,0x1ffff
+200015e6: 11e50513 addi a0,a0,286 # 40000700 <uart_ctrl_addr+0x4fc>
+200015ea: 80cff0ef jal ra,200005f6 <ee_printf>
+200015ee: 1ffff517 auipc a0,0x1ffff
+200015f2: 12e50513 addi a0,a0,302 # 4000071c <uart_ctrl_addr+0x518>
+200015f6: 800ff0ef jal ra,200005f6 <ee_printf>
+200015fa: 1ffff517 auipc a0,0x1ffff
+200015fe: ee650513 addi a0,a0,-282 # 400004e0 <uart_ctrl_addr+0x2dc>
+20001602: ff5fe0ef jal ra,200005f6 <ee_printf>
+20001606: 4018 lw a4,0(s0)
+20001608: 000b2783 lw a5,0(s6)
+2000160c: 1ffff517 auipc a0,0x1ffff
+20001610: 14850513 addi a0,a0,328 # 40000754 <uart_ctrl_addr+0x550>
+20001614: 8f99 sub a5,a5,a4
+20001616: c09c sw a5,0(s1)
+20001618: fdffe0ef jal ra,200005f6 <ee_printf>
+2000161c: 1ffff517 auipc a0,0x1ffff
+20001620: 17050513 addi a0,a0,368 # 4000078c <uart_ctrl_addr+0x588>
+20001624: fd3fe0ef jal ra,200005f6 <ee_printf>
+20001628: 4094 lw a3,0(s1)
+2000162a: 000b2603 lw a2,0(s6)
+2000162e: 400c lw a1,0(s0)
+20001630: 1ffff517 auipc a0,0x1ffff
+20001634: 17c50513 addi a0,a0,380 # 400007ac <uart_ctrl_addr+0x5a8>
+20001638: fbffe0ef jal ra,200005f6 <ee_printf>
+2000163c: 1ffff517 auipc a0,0x1ffff
+20001640: ea450513 addi a0,a0,-348 # 400004e0 <uart_ctrl_addr+0x2dc>
+20001644: fb3fe0ef jal ra,200005f6 <ee_printf>
+20001648: 40fa lw ra,156(sp)
+2000164a: 446a lw s0,152(sp)
+2000164c: 44da lw s1,148(sp)
+2000164e: 494a lw s2,144(sp)
+20001650: 49ba lw s3,140(sp)
+20001652: 4a2a lw s4,136(sp)
+20001654: 4a9a lw s5,132(sp)
+20001656: 4b0a lw s6,128(sp)
+20001658: 5bf6 lw s7,124(sp)
+2000165a: 5c66 lw s8,120(sp)
+2000165c: 5cd6 lw s9,116(sp)
+2000165e: 5d46 lw s10,112(sp)
+20001660: 5db6 lw s11,108(sp)
+20001662: 4501 li a0,0
+20001664: 610d addi sp,sp,160
+20001666: 8082 ret
+20001668: 4925 li s2,9
+2000166a: b181 j 200012aa <main+0x1f0>
+2000166c: 1ffff517 auipc a0,0x1ffff
+20001670: c4c50513 addi a0,a0,-948 # 400002b8 <uart_ctrl_addr+0xb4>
+20001674: f83fe0ef jal ra,200005f6 <ee_printf>
+20001678: 1ffff517 auipc a0,0x1ffff
+2000167c: e6850513 addi a0,a0,-408 # 400004e0 <uart_ctrl_addr+0x2dc>
+20001680: f77fe0ef jal ra,200005f6 <ee_printf>
+20001684: bcdd j 2000117a <main+0xc0>
+
+Disassembly of section .text_itim:
+
+08000000 <spi_quad_mode>:
+ 8000000: 1141 addi sp,sp,-16
+ 8000002: 0ff0000f fence
+ 8000006: 0000100f fence.i
+ 800000a: 4114 lw a3,0(a0)
+ 800000c: 4705 li a4,1
+ 800000e: 4785 li a5,1
+ 8000010: 00e68663 beq a3,a4,800001c <spi_quad_mode+0x1c>
+ 8000014: c11c sw a5,0(a0)
+ 8000016: 4118 lw a4,0(a0)
+ 8000018: fef71ee3 bne a4,a5,8000014 <spi_quad_mode+0x14>
+ 800001c: 5138 lw a4,96(a0)
+ 800001e: 06050793 addi a5,a0,96
+ 8000022: c709 beqz a4,800002c <spi_quad_mode+0x2c>
+ 8000024: 0007a023 sw zero,0(a5)
+ 8000028: 4398 lw a4,0(a5)
+ 800002a: ff6d bnez a4,8000024 <spi_quad_mode+0x24>
+ 800002c: 04850693 addi a3,a0,72
+ 8000030: 4298 lw a4,0(a3)
+ 8000032: fe074fe3 bltz a4,8000030 <spi_quad_mode+0x30>
+ 8000036: 03500713 li a4,53
+ 800003a: c538 sw a4,72(a0)
+ 800003c: 000b3737 lui a4,0xb3
+ 8000040: a4770713 addi a4,a4,-1465 # b2a47 <spi_quad_mode-0x7f4d5b9>
+ 8000044: c63a sw a4,12(sp)
+ 8000046: 5174 lw a3,100(a0)
+ 8000048: 4632 lw a2,12(sp)
+ 800004a: 06450713 addi a4,a0,100
+ 800004e: 00d60863 beq a2,a3,800005e <spi_quad_mode+0x5e>
+ 8000052: 46b2 lw a3,12(sp)
+ 8000054: c314 sw a3,0(a4)
+ 8000056: 4310 lw a2,0(a4)
+ 8000058: 46b2 lw a3,12(sp)
+ 800005a: fed61ce3 bne a2,a3,8000052 <spi_quad_mode+0x52>
+ 800005e: 5130 lw a2,96(a0)
+ 8000060: 4685 li a3,1
+ 8000062: 4705 li a4,1
+ 8000064: 00d60663 beq a2,a3,8000070 <spi_quad_mode+0x70>
+ 8000068: c398 sw a4,0(a5)
+ 800006a: 4394 lw a3,0(a5)
+ 800006c: fee69ee3 bne a3,a4,8000068 <spi_quad_mode+0x68>
+ 8000070: 0141 addi sp,sp,16
+ 8000072: 8082 ret
+
+Disassembly of section .rodata:
+
+40000000 <rodata_start>:
+40000000: 0770 addi a2,sp,908
+40000002: e000 fsw fs0,0(s0)
+40000004: 070c addi a1,sp,896
+40000006: e000 fsw fs0,0(s0)
+40000008: 070c addi a1,sp,896
+4000000a: e000 fsw fs0,0(s0)
+4000000c: 0768 addi a0,sp,908
+4000000e: e000 fsw fs0,0(s0)
+40000010: 070c addi a1,sp,896
+40000012: e000 fsw fs0,0(s0)
+40000014: 070c addi a1,sp,896
+40000016: e000 fsw fs0,0(s0)
+40000018: 070c addi a1,sp,896
+4000001a: e000 fsw fs0,0(s0)
+4000001c: 070c addi a1,sp,896
+4000001e: e000 fsw fs0,0(s0)
+40000020: 070c addi a1,sp,896
+40000022: e000 fsw fs0,0(s0)
+40000024: 070c addi a1,sp,896
+40000026: e000 fsw fs0,0(s0)
+40000028: 070c addi a1,sp,896
+4000002a: e000 fsw fs0,0(s0)
+4000002c: 0760 addi s0,sp,908
+4000002e: e000 fsw fs0,0(s0)
+40000030: 070c addi a1,sp,896
+40000032: e000 fsw fs0,0(s0)
+40000034: 0758 addi a4,sp,900
+40000036: e000 fsw fs0,0(s0)
+40000038: 070c addi a1,sp,896
+4000003a: e000 fsw fs0,0(s0)
+4000003c: 070c addi a1,sp,896
+4000003e: e000 fsw fs0,0(s0)
+40000040: 0750 addi a2,sp,900
+40000042: e000 fsw fs0,0(s0)
+40000044: 090c addi a1,sp,144
+40000046: e000 fsw fs0,0(s0)
+40000048: 075a slli a4,a4,0x16
+4000004a: e000 fsw fs0,0(s0)
+4000004c: 075a slli a4,a4,0x16
+4000004e: e000 fsw fs0,0(s0)
+40000050: 075a slli a4,a4,0x16
+40000052: e000 fsw fs0,0(s0)
+40000054: 075a slli a4,a4,0x16
+40000056: e000 fsw fs0,0(s0)
+40000058: 075a slli a4,a4,0x16
+4000005a: e000 fsw fs0,0(s0)
+4000005c: 075a slli a4,a4,0x16
+4000005e: e000 fsw fs0,0(s0)
+40000060: 075a slli a4,a4,0x16
+40000062: e000 fsw fs0,0(s0)
+40000064: 075a slli a4,a4,0x16
+40000066: e000 fsw fs0,0(s0)
+40000068: 075a slli a4,a4,0x16
+4000006a: e000 fsw fs0,0(s0)
+4000006c: 075a slli a4,a4,0x16
+4000006e: e000 fsw fs0,0(s0)
+40000070: 075a slli a4,a4,0x16
+40000072: e000 fsw fs0,0(s0)
+40000074: 075a slli a4,a4,0x16
+40000076: e000 fsw fs0,0(s0)
+40000078: 075a slli a4,a4,0x16
+4000007a: e000 fsw fs0,0(s0)
+4000007c: 075a slli a4,a4,0x16
+4000007e: e000 fsw fs0,0(s0)
+40000080: 075a slli a4,a4,0x16
+40000082: e000 fsw fs0,0(s0)
+40000084: 075a slli a4,a4,0x16
+40000086: e000 fsw fs0,0(s0)
+40000088: 075a slli a4,a4,0x16
+4000008a: e000 fsw fs0,0(s0)
+4000008c: 075a slli a4,a4,0x16
+4000008e: e000 fsw fs0,0(s0)
+40000090: 075a slli a4,a4,0x16
+40000092: e000 fsw fs0,0(s0)
+40000094: 075a slli a4,a4,0x16
+40000096: e000 fsw fs0,0(s0)
+40000098: 075a slli a4,a4,0x16
+4000009a: e000 fsw fs0,0(s0)
+4000009c: 075a slli a4,a4,0x16
+4000009e: e000 fsw fs0,0(s0)
+400000a0: 0900 addi s0,sp,144
+400000a2: e000 fsw fs0,0(s0)
+400000a4: 075a slli a4,a4,0x16
+400000a6: e000 fsw fs0,0(s0)
+400000a8: 075a slli a4,a4,0x16
+400000aa: e000 fsw fs0,0(s0)
+400000ac: 075a slli a4,a4,0x16
+400000ae: e000 fsw fs0,0(s0)
+400000b0: 075a slli a4,a4,0x16
+400000b2: e000 fsw fs0,0(s0)
+400000b4: 075a slli a4,a4,0x16
+400000b6: e000 fsw fs0,0(s0)
+400000b8: 075a slli a4,a4,0x16
+400000ba: e000 fsw fs0,0(s0)
+400000bc: 075a slli a4,a4,0x16
+400000be: e000 fsw fs0,0(s0)
+400000c0: 075a slli a4,a4,0x16
+400000c2: e000 fsw fs0,0(s0)
+400000c4: 0b6c addi a1,sp,412
+400000c6: e000 fsw fs0,0(s0)
+400000c8: 075a slli a4,a4,0x16
+400000ca: e000 fsw fs0,0(s0)
+400000cc: 08be slli a7,a7,0xf
+400000ce: e000 fsw fs0,0(s0)
+400000d0: 08b0 addi a2,sp,88
+400000d2: e000 fsw fs0,0(s0)
+400000d4: 075a slli a4,a4,0x16
+400000d6: e000 fsw fs0,0(s0)
+400000d8: 075a slli a4,a4,0x16
+400000da: e000 fsw fs0,0(s0)
+400000dc: 075a slli a4,a4,0x16
+400000de: e000 fsw fs0,0(s0)
+400000e0: 075a slli a4,a4,0x16
+400000e2: e000 fsw fs0,0(s0)
+400000e4: 08b0 addi a2,sp,88
+400000e6: e000 fsw fs0,0(s0)
+400000e8: 075a slli a4,a4,0x16
+400000ea: e000 fsw fs0,0(s0)
+400000ec: 075a slli a4,a4,0x16
+400000ee: e000 fsw fs0,0(s0)
+400000f0: 075a slli a4,a4,0x16
+400000f2: e000 fsw fs0,0(s0)
+400000f4: 075a slli a4,a4,0x16
+400000f6: e000 fsw fs0,0(s0)
+400000f8: 075a slli a4,a4,0x16
+400000fa: e000 fsw fs0,0(s0)
+400000fc: 08a8 addi a0,sp,88
+400000fe: e000 fsw fs0,0(s0)
+40000100: 088a slli a7,a7,0x2
+40000102: e000 fsw fs0,0(s0)
+40000104: 075a slli a4,a4,0x16
+40000106: e000 fsw fs0,0(s0)
+40000108: 075a slli a4,a4,0x16
+4000010a: e000 fsw fs0,0(s0)
+4000010c: 0810 addi a2,sp,16
+4000010e: e000 fsw fs0,0(s0)
+40000110: 075a slli a4,a4,0x16
+40000112: e000 fsw fs0,0(s0)
+40000114: 0806 slli a6,a6,0x1
+40000116: e000 fsw fs0,0(s0)
+40000118: 075a slli a4,a4,0x16
+4000011a: e000 fsw fs0,0(s0)
+4000011c: 075a slli a4,a4,0x16
+4000011e: e000 fsw fs0,0(s0)
+40000120: 07ea slli a5,a5,0x1a
+40000122: e000 fsw fs0,0(s0)
+40000124: 095c addi a5,sp,148
+40000126: e000 fsw fs0,0(s0)
+40000128: 0676 slli a2,a2,0x1d
+4000012a: e000 fsw fs0,0(s0)
+4000012c: 0676 slli a2,a2,0x1d
+4000012e: e000 fsw fs0,0(s0)
+40000130: 0676 slli a2,a2,0x1d
+40000132: e000 fsw fs0,0(s0)
+40000134: 0676 slli a2,a2,0x1d
+40000136: e000 fsw fs0,0(s0)
+40000138: 0676 slli a2,a2,0x1d
+4000013a: e000 fsw fs0,0(s0)
+4000013c: 0676 slli a2,a2,0x1d
+4000013e: e000 fsw fs0,0(s0)
+40000140: 0676 slli a2,a2,0x1d
+40000142: e000 fsw fs0,0(s0)
+40000144: 0676 slli a2,a2,0x1d
+40000146: e000 fsw fs0,0(s0)
+40000148: 0676 slli a2,a2,0x1d
+4000014a: e000 fsw fs0,0(s0)
+4000014c: 0676 slli a2,a2,0x1d
+4000014e: e000 fsw fs0,0(s0)
+40000150: 0676 slli a2,a2,0x1d
+40000152: e000 fsw fs0,0(s0)
+40000154: 0676 slli a2,a2,0x1d
+40000156: e000 fsw fs0,0(s0)
+40000158: 0676 slli a2,a2,0x1d
+4000015a: e000 fsw fs0,0(s0)
+4000015c: 0676 slli a2,a2,0x1d
+4000015e: e000 fsw fs0,0(s0)
+40000160: 0676 slli a2,a2,0x1d
+40000162: e000 fsw fs0,0(s0)
+40000164: 0676 slli a2,a2,0x1d
+40000166: e000 fsw fs0,0(s0)
+40000168: 0676 slli a2,a2,0x1d
+4000016a: e000 fsw fs0,0(s0)
+4000016c: 0676 slli a2,a2,0x1d
+4000016e: e000 fsw fs0,0(s0)
+40000170: 0676 slli a2,a2,0x1d
+40000172: e000 fsw fs0,0(s0)
+40000174: 0676 slli a2,a2,0x1d
+40000176: e000 fsw fs0,0(s0)
+40000178: 0676 slli a2,a2,0x1d
+4000017a: e000 fsw fs0,0(s0)
+4000017c: 0676 slli a2,a2,0x1d
+4000017e: e000 fsw fs0,0(s0)
+40000180: 0954 addi a3,sp,148
+40000182: e000 fsw fs0,0(s0)
+40000184: 0676 slli a2,a2,0x1d
+40000186: e000 fsw fs0,0(s0)
+40000188: 0676 slli a2,a2,0x1d
+4000018a: e000 fsw fs0,0(s0)
+4000018c: 0676 slli a2,a2,0x1d
+4000018e: e000 fsw fs0,0(s0)
+40000190: 0676 slli a2,a2,0x1d
+40000192: e000 fsw fs0,0(s0)
+40000194: 0676 slli a2,a2,0x1d
+40000196: e000 fsw fs0,0(s0)
+40000198: 0676 slli a2,a2,0x1d
+4000019a: e000 fsw fs0,0(s0)
+4000019c: 0676 slli a2,a2,0x1d
+4000019e: e000 fsw fs0,0(s0)
+400001a0: 0676 slli a2,a2,0x1d
+400001a2: e000 fsw fs0,0(s0)
+400001a4: 0960 addi s0,sp,156
+400001a6: e000 fsw fs0,0(s0)
+400001a8: 0676 slli a2,a2,0x1d
+400001aa: e000 fsw fs0,0(s0)
+400001ac: 07dc addi a5,sp,964
+400001ae: e000 fsw fs0,0(s0)
+400001b0: 0934 addi a3,sp,152
+400001b2: e000 fsw fs0,0(s0)
+400001b4: 0676 slli a2,a2,0x1d
+400001b6: e000 fsw fs0,0(s0)
+400001b8: 0676 slli a2,a2,0x1d
+400001ba: e000 fsw fs0,0(s0)
+400001bc: 0676 slli a2,a2,0x1d
+400001be: e000 fsw fs0,0(s0)
+400001c0: 0676 slli a2,a2,0x1d
+400001c2: e000 fsw fs0,0(s0)
+400001c4: 0934 addi a3,sp,152
+400001c6: e000 fsw fs0,0(s0)
+400001c8: 0676 slli a2,a2,0x1d
+400001ca: e000 fsw fs0,0(s0)
+400001cc: 0676 slli a2,a2,0x1d
+400001ce: e000 fsw fs0,0(s0)
+400001d0: 0676 slli a2,a2,0x1d
+400001d2: e000 fsw fs0,0(s0)
+400001d4: 0676 slli a2,a2,0x1d
+400001d6: e000 fsw fs0,0(s0)
+400001d8: 0676 slli a2,a2,0x1d
+400001da: e000 fsw fs0,0(s0)
+400001dc: 0950 addi a2,sp,148
+400001de: e000 fsw fs0,0(s0)
+400001e0: 07a8 addi a0,sp,968
+400001e2: e000 fsw fs0,0(s0)
+400001e4: 0676 slli a2,a2,0x1d
+400001e6: e000 fsw fs0,0(s0)
+400001e8: 0676 slli a2,a2,0x1d
+400001ea: e000 fsw fs0,0(s0)
+400001ec: 072e slli a4,a4,0xb
+400001ee: e000 fsw fs0,0(s0)
+400001f0: 0676 slli a2,a2,0x1d
+400001f2: e000 fsw fs0,0(s0)
+400001f4: 0b30 addi a2,sp,408
+400001f6: e000 fsw fs0,0(s0)
+400001f8: 0676 slli a2,a2,0x1d
+400001fa: e000 fsw fs0,0(s0)
+400001fc: 0676 slli a2,a2,0x1d
+400001fe: e000 fsw fs0,0(s0)
+40000200: 0b2c addi a1,sp,408
+40000202: e000 fsw fs0,0(s0)
+
+40000204 <uart_ctrl_addr>:
+40000204: 3000 fld fs0,32(s0)
+40000206: 1001 c.nop -32
+40000208: 3000 fld fs0,32(s0)
+4000020a: 1002 c.slli zero,0x20
+4000020c: 3000 fld fs0,32(s0)
+4000020e: 30001003 lh zero,768(zero) # 300 <spi_quad_mode-0x7fffd00>
+40000212: 1004 addi s1,sp,32
+40000214: 3000 fld fs0,32(s0)
+40000216: 1005 c.nop -31
+40000218: 3000 fld fs0,32(s0)
+4000021a: 1006 c.slli zero,0x21
+4000021c: 4844 lw s1,20(s0)
+4000021e: 5952 lw s2,52(sp)
+40000220: 4e4f5453 0x4e4f5453
+40000224: 2045 jal 400002c4 <uart_ctrl_addr+0xc0>
+40000226: 5250 lw a2,36(a2)
+40000228: 4152474f fnmadd.s fa4,ft4,fs5,fs0,rmm
+4000022c: 2c4d jal 400004de <uart_ctrl_addr+0x2da>
+4000022e: 5320 lw s0,96(a4)
+40000230: 20454d4f fnmadd.s fs10,fa0,ft4,ft4,rmm
+40000234: 49525453 0x49525453
+40000238: 474e lw a4,208(sp)
+4000023a: 0000 unimp
+4000023c: 4844 lw s1,20(s0)
+4000023e: 5952 lw s2,52(sp)
+40000240: 4e4f5453 0x4e4f5453
+40000244: 2045 jal 400002e4 <uart_ctrl_addr+0xe0>
+40000246: 5250 lw a2,36(a2)
+40000248: 4152474f fnmadd.s fa4,ft4,fs5,fs0,rmm
+4000024c: 2c4d jal 400004fe <uart_ctrl_addr+0x2fa>
+4000024e: 3120 fld fs0,96(a0)
+40000250: 20545327 0x20545327
+40000254: 49525453 0x49525453
+40000258: 474e lw a4,208(sp)
+4000025a: 0000 unimp
+4000025c: 6844 flw fs1,20(s0)
+4000025e: 7972 flw fs2,60(sp)
+40000260: 6e6f7473 csrrci s0,0x6e6,30
+40000264: 2065 jal 4000030c <uart_ctrl_addr+0x108>
+40000266: 6542 flw fa0,16(sp)
+40000268: 636e flw ft6,216(sp)
+4000026a: 6d68 flw fa0,92(a0)
+4000026c: 7261 lui tp,0xffff8
+4000026e: 56202c6b 0x56202c6b
+40000272: 7265 lui tp,0xffff9
+40000274: 6e6f6973 csrrsi s2,0x6e6,30
+40000278: 3220 fld fs0,96(a2)
+4000027a: 312e fld ft2,232(sp)
+4000027c: 2820 fld fs0,80(s0)
+4000027e: 614c flw fa1,4(a0)
+40000280: 676e flw fa4,216(sp)
+40000282: 6175 addi sp,sp,368
+40000284: 203a6567 0x203a6567
+40000288: 000a2943 fmadd.s fs2,fs4,ft0,ft0,rdn
+4000028c: 7250 flw fa2,36(a2)
+4000028e: 6172676f jal a4,400270a4 <_end+0x24040>
+40000292: 206d jal 4000033c <uart_ctrl_addr+0x138>
+40000294: 706d6f63 bltu s10,t1,400009b2 <Arr_2_Glob+0x96>
+40000298: 6c69 lui s8,0x1a
+4000029a: 6465 lui s0,0x19
+4000029c: 7720 flw fs0,104(a4)
+4000029e: 7469 lui s0,0xffffa
+400002a0: 2068 fld fa0,192(s0)
+400002a2: 67657227 0x67657227
+400002a6: 7369 lui t1,0xffffa
+400002a8: 6574 flw fa3,76(a0)
+400002aa: 2772 fld fa4,280(sp)
+400002ac: 6120 flw fs0,64(a0)
+400002ae: 7474 flw fa3,108(s0)
+400002b0: 6972 flw fs2,28(sp)
+400002b2: 7562 flw fa0,56(sp)
+400002b4: 6574 flw fa3,76(a0)
+400002b6: 000a c.slli zero,0x2
+400002b8: 7250 flw fa2,36(a2)
+400002ba: 6172676f jal a4,400270d0 <_end+0x2406c>
+400002be: 206d jal 40000368 <uart_ctrl_addr+0x164>
+400002c0: 706d6f63 bltu s10,t1,400009de <Arr_2_Glob+0xc2>
+400002c4: 6c69 lui s8,0x1a
+400002c6: 6465 lui s0,0x19
+400002c8: 7720 flw fs0,104(a4)
+400002ca: 7469 lui s0,0xffffa
+400002cc: 6f68 flw fa0,92(a4)
+400002ce: 7475 lui s0,0xffffd
+400002d0: 2720 fld fs0,72(a4)
+400002d2: 6572 flw fa0,28(sp)
+400002d4: 74736967 0x74736967
+400002d8: 7265 lui tp,0xffff9
+400002da: 74612027 fsw ft6,1856(sp)
+400002de: 7274 flw fa3,100(a2)
+400002e0: 6269 lui tp,0x1a
+400002e2: 7475 lui s0,0xffffd
+400002e4: 0a65 addi s4,s4,25
+400002e6: 0000 unimp
+400002e8: 6c50 flw fa2,28(s0)
+400002ea: 6165 addi sp,sp,112
+400002ec: 67206573 csrrsi a0,0x672,0
+400002f0: 7669 lui a2,0xffffa
+400002f2: 2065 jal 4000039a <uart_ctrl_addr+0x196>
+400002f4: 6874 flw fa3,84(s0)
+400002f6: 2065 jal 4000039e <uart_ctrl_addr+0x19a>
+400002f8: 756e flw fa0,248(sp)
+400002fa: 626d lui tp,0x1b
+400002fc: 7265 lui tp,0xffff9
+400002fe: 6f20 flw fs0,88(a4)
+40000300: 2066 fld ft0,88(sp)
+40000302: 7572 flw fa0,60(sp)
+40000304: 736e flw ft6,248(sp)
+40000306: 7420 flw fs0,104(s0)
+40000308: 7268 flw fa0,100(a2)
+4000030a: 6867756f jal a0,40077990 <_end+0x7492c>
+4000030e: 7420 flw fs0,104(s0)
+40000310: 6568 flw fa0,76(a0)
+40000312: 6220 flw fs0,64(a2)
+40000314: 6e65 lui t3,0x19
+40000316: 616d6863 bltu s10,s6,40000926 <Arr_2_Glob+0xa>
+4000031a: 6b72 flw fs6,28(sp)
+4000031c: 203a fld ft0,392(sp)
+4000031e: 0000 unimp
+40000320: 7845 lui a6,0xffff1
+40000322: 6365 lui t1,0x19
+40000324: 7475 lui s0,0xffffd
+40000326: 6f69 lui t5,0x1a
+40000328: 206e fld ft0,216(sp)
+4000032a: 72617473 csrrci s0,0x726,2
+4000032e: 7374 flw fa3,100(a4)
+40000330: 202c fld fa1,64(s0)
+40000332: 6425 lui s0,0x9
+40000334: 7220 flw fs0,96(a2)
+40000336: 6e75 lui t3,0x1d
+40000338: 68742073 csrs 0x687,s0
+4000033c: 6f72 flw ft10,28(sp)
+4000033e: 6775 lui a4,0x1d
+40000340: 2068 fld fa0,192(s0)
+40000342: 6844 flw fs1,20(s0)
+40000344: 7972 flw fs2,60(sp)
+40000346: 6e6f7473 csrrci s0,0x6e6,30
+4000034a: 0a65 addi s4,s4,25
+4000034c: 0000 unimp
+4000034e: 0000 unimp
+40000350: 4844 lw s1,20(s0)
+40000352: 5952 lw s2,52(sp)
+40000354: 4e4f5453 0x4e4f5453
+40000358: 2045 jal 400003f8 <uart_ctrl_addr+0x1f4>
+4000035a: 5250 lw a2,36(a2)
+4000035c: 4152474f fnmadd.s fa4,ft4,fs5,fs0,rmm
+40000360: 2c4d jal 40000612 <uart_ctrl_addr+0x40e>
+40000362: 3220 fld fs0,96(a2)
+40000364: 20444e27 fsq ft4,540(s0) # 921c <spi_quad_mode-0x7ff6de4>
+40000368: 49525453 0x49525453
+4000036c: 474e lw a4,208(sp)
+4000036e: 0000 unimp
+40000370: 4844 lw s1,20(s0)
+40000372: 5952 lw s2,52(sp)
+40000374: 4e4f5453 0x4e4f5453
+40000378: 2045 jal 40000418 <uart_ctrl_addr+0x214>
+4000037a: 5250 lw a2,36(a2)
+4000037c: 4152474f fnmadd.s fa4,ft4,fs5,fs0,rmm
+40000380: 2c4d jal 40000632 <uart_ctrl_addr+0x42e>
+40000382: 3320 fld fs0,96(a4)
+40000384: 20445227 0x20445227
+40000388: 49525453 0x49525453
+4000038c: 474e lw a4,208(sp)
+4000038e: 0000 unimp
+40000390: 7845 lui a6,0xffff1
+40000392: 6365 lui t1,0x19
+40000394: 7475 lui s0,0xffffd
+40000396: 6f69 lui t5,0x1a
+40000398: 206e fld ft0,216(sp)
+4000039a: 6e65 lui t3,0x19
+4000039c: 7364 flw fs1,100(a4)
+4000039e: 000a c.slli zero,0x2
+400003a0: 6946 flw fs2,80(sp)
+400003a2: 616e flw ft2,216(sp)
+400003a4: 206c fld fa1,192(s0)
+400003a6: 6176 flw ft2,92(sp)
+400003a8: 756c flw fa1,108(a0)
+400003aa: 7365 lui t1,0xffff9
+400003ac: 6f20 flw fs0,88(a4)
+400003ae: 2066 fld ft0,88(sp)
+400003b0: 6874 flw fa3,84(s0)
+400003b2: 2065 jal 4000045a <uart_ctrl_addr+0x256>
+400003b4: 6176 flw ft2,92(sp)
+400003b6: 6972 flw fs2,28(sp)
+400003b8: 6261 lui tp,0x18
+400003ba: 656c flw fa1,76(a0)
+400003bc: 73752073 csrs 0x737,a0
+400003c0: 6465 lui s0,0x19
+400003c2: 6920 flw fs0,80(a0)
+400003c4: 206e fld ft0,216(sp)
+400003c6: 6874 flw fa3,84(s0)
+400003c8: 2065 jal 40000470 <uart_ctrl_addr+0x26c>
+400003ca: 6562 flw fa0,24(sp)
+400003cc: 636e flw ft6,216(sp)
+400003ce: 6d68 flw fa0,92(a0)
+400003d0: 7261 lui tp,0xffff8
+400003d2: 000a3a6b 0xa3a6b
+400003d6: 0000 unimp
+400003d8: 6e49 lui t3,0x12
+400003da: 5f74 lw a3,124(a4)
+400003dc: 626f6c47 fmsub.d fs8,ft10,ft6,fa2,unknown
+400003e0: 203a fld ft0,392(sp)
+400003e2: 2020 fld fs0,64(s0)
+400003e4: 2020 fld fs0,64(s0)
+400003e6: 2020 fld fs0,64(s0)
+400003e8: 2020 fld fs0,64(s0)
+400003ea: 2020 fld fs0,64(s0)
+400003ec: 2520 fld fs0,72(a0)
+400003ee: 0a64 addi s1,sp,284
+400003f0: 0000 unimp
+400003f2: 0000 unimp
+400003f4: 2020 fld fs0,64(s0)
+400003f6: 2020 fld fs0,64(s0)
+400003f8: 2020 fld fs0,64(s0)
+400003fa: 2020 fld fs0,64(s0)
+400003fc: 756f6873 csrrsi a6,0x756,30
+40000400: 646c flw fa1,76(s0)
+40000402: 6220 flw fs0,64(a2)
+40000404: 3a65 jal 3ffffdbc <data_load_start+0x1fffde82>
+40000406: 2020 fld fs0,64(s0)
+40000408: 2520 fld fs0,72(a0)
+4000040a: 0a64 addi s1,sp,284
+4000040c: 0000 unimp
+4000040e: 0000 unimp
+40000410: 6f42 flw ft10,16(sp)
+40000412: 475f6c6f jal s8,400f7086 <_end+0xf4022>
+40000416: 6f6c flw fa1,92(a4)
+40000418: 3a62 fld fs4,56(sp)
+4000041a: 2020 fld fs0,64(s0)
+4000041c: 2020 fld fs0,64(s0)
+4000041e: 2020 fld fs0,64(s0)
+40000420: 2020 fld fs0,64(s0)
+40000422: 2020 fld fs0,64(s0)
+40000424: 2520 fld fs0,72(a0)
+40000426: 0a64 addi s1,sp,284
+40000428: 0000 unimp
+4000042a: 0000 unimp
+4000042c: 315f6843 fmadd.s fa6,ft10,fs5,ft6,unknown
+40000430: 475f 6f6c 3a62 0x3a626f6c475f
+40000436: 2020 fld fs0,64(s0)
+40000438: 2020 fld fs0,64(s0)
+4000043a: 2020 fld fs0,64(s0)
+4000043c: 2020 fld fs0,64(s0)
+4000043e: 2020 fld fs0,64(s0)
+40000440: 2520 fld fs0,72(a0)
+40000442: 00000a63 beqz zero,40000456 <uart_ctrl_addr+0x252>
+40000446: 0000 unimp
+40000448: 2020 fld fs0,64(s0)
+4000044a: 2020 fld fs0,64(s0)
+4000044c: 2020 fld fs0,64(s0)
+4000044e: 2020 fld fs0,64(s0)
+40000450: 756f6873 csrrsi a6,0x756,30
+40000454: 646c flw fa1,76(s0)
+40000456: 6220 flw fs0,64(a2)
+40000458: 3a65 jal 3ffffe10 <data_load_start+0x1fffded6>
+4000045a: 2020 fld fs0,64(s0)
+4000045c: 2520 fld fs0,72(a0)
+4000045e: 00000a63 beqz zero,40000472 <uart_ctrl_addr+0x26e>
+40000462: 0000 unimp
+40000464: 325f6843 fmadd.d fa6,ft10,ft5,ft6,unknown
+40000468: 475f 6f6c 3a62 0x3a626f6c475f
+4000046e: 2020 fld fs0,64(s0)
+40000470: 2020 fld fs0,64(s0)
+40000472: 2020 fld fs0,64(s0)
+40000474: 2020 fld fs0,64(s0)
+40000476: 2020 fld fs0,64(s0)
+40000478: 2520 fld fs0,72(a0)
+4000047a: 00000a63 beqz zero,4000048e <uart_ctrl_addr+0x28a>
+4000047e: 0000 unimp
+40000480: 7241 lui tp,0xffff0
+40000482: 5f72 lw t5,60(sp)
+40000484: 5f31 li t5,-20
+40000486: 626f6c47 fmsub.d fs8,ft10,ft6,fa2,unknown
+4000048a: 3a5d385b 0x3a5d385b
+4000048e: 2020 fld fs0,64(s0)
+40000490: 2020 fld fs0,64(s0)
+40000492: 2020 fld fs0,64(s0)
+40000494: 2520 fld fs0,72(a0)
+40000496: 0a64 addi s1,sp,284
+40000498: 0000 unimp
+4000049a: 0000 unimp
+4000049c: 7241 lui tp,0xffff0
+4000049e: 5f72 lw t5,60(sp)
+400004a0: 5f32 lw t5,44(sp)
+400004a2: 626f6c47 fmsub.d fs8,ft10,ft6,fa2,unknown
+400004a6: 5b5d385b 0x5b5d385b
+400004aa: 203a5d37 lui s10,0x203a5
+400004ae: 2020 fld fs0,64(s0)
+400004b0: 2520 fld fs0,72(a0)
+400004b2: 0a64 addi s1,sp,284
+400004b4: 0000 unimp
+400004b6: 0000 unimp
+400004b8: 2020 fld fs0,64(s0)
+400004ba: 2020 fld fs0,64(s0)
+400004bc: 2020 fld fs0,64(s0)
+400004be: 2020 fld fs0,64(s0)
+400004c0: 756f6873 csrrsi a6,0x756,30
+400004c4: 646c flw fa1,76(s0)
+400004c6: 6220 flw fs0,64(a2)
+400004c8: 3a65 jal 3ffffe80 <data_load_start+0x1fffdf46>
+400004ca: 2020 fld fs0,64(s0)
+400004cc: 4e20 lw s0,88(a2)
+400004ce: 6d75 lui s10,0x1d
+400004d0: 6562 flw fa0,24(sp)
+400004d2: 5f72 lw t5,60(sp)
+400004d4: 525f664f fnmadd.d fa2,ft10,ft5,fa0,unknown
+400004d8: 6e75 lui t3,0x1d
+400004da: 202b2073 csrs hedeleg,s6
+400004de: 3031 jal 3ffffcea <data_load_start+0x1fffddb0>
+400004e0: 000a c.slli zero,0x2
+400004e2: 0000 unimp
+400004e4: 7450 flw fa2,44(s0)
+400004e6: 5f72 lw t5,60(sp)
+400004e8: 626f6c47 fmsub.d fs8,ft10,ft6,fa2,unknown
+400004ec: 3e2d jal 40000026 <rodata_start+0x26>
+400004ee: 000a c.slli zero,0x2
+400004f0: 2020 fld fs0,64(s0)
+400004f2: 7450 flw fa2,44(s0)
+400004f4: 5f72 lw t5,60(sp)
+400004f6: 706d6f43 fmadd.s ft10,fs10,ft6,fa4,unknown
+400004fa: 203a fld ft0,392(sp)
+400004fc: 2020 fld fs0,64(s0)
+400004fe: 2020 fld fs0,64(s0)
+40000500: 2020 fld fs0,64(s0)
+40000502: 2020 fld fs0,64(s0)
+40000504: 2520 fld fs0,72(a0)
+40000506: 0a64 addi s1,sp,284
+40000508: 0000 unimp
+4000050a: 0000 unimp
+4000050c: 2020 fld fs0,64(s0)
+4000050e: 2020 fld fs0,64(s0)
+40000510: 2020 fld fs0,64(s0)
+40000512: 2020 fld fs0,64(s0)
+40000514: 756f6873 csrrsi a6,0x756,30
+40000518: 646c flw fa1,76(s0)
+4000051a: 6220 flw fs0,64(a2)
+4000051c: 3a65 jal 3ffffed4 <data_load_start+0x1fffdf9a>
+4000051e: 2020 fld fs0,64(s0)
+40000520: 2820 fld fs0,80(s0)
+40000522: 6d69 lui s10,0x1a
+40000524: 6c70 flw fa2,92(s0)
+40000526: 6d65 lui s10,0x19
+40000528: 6e65 lui t3,0x19
+4000052a: 6174 flw fa3,68(a0)
+4000052c: 6974 flw fa3,84(a0)
+4000052e: 642d6e6f jal t3,400d6b70 <_end+0xd3b0c>
+40000532: 7065 c.lui zero,0xffff9
+40000534: 6e65 lui t3,0x19
+40000536: 6564 flw fs1,76(a0)
+40000538: 746e flw fs0,248(sp)
+4000053a: 0a29 addi s4,s4,10
+4000053c: 0000 unimp
+4000053e: 0000 unimp
+40000540: 2020 fld fs0,64(s0)
+40000542: 6944 flw fs1,20(a0)
+40000544: 3a726373 csrrsi t1,0x3a7,4
+40000548: 2020 fld fs0,64(s0)
+4000054a: 2020 fld fs0,64(s0)
+4000054c: 2020 fld fs0,64(s0)
+4000054e: 2020 fld fs0,64(s0)
+40000550: 2020 fld fs0,64(s0)
+40000552: 2020 fld fs0,64(s0)
+40000554: 2520 fld fs0,72(a0)
+40000556: 0a64 addi s1,sp,284
+40000558: 0000 unimp
+4000055a: 0000 unimp
+4000055c: 2020 fld fs0,64(s0)
+4000055e: 6e45 lui t3,0x11
+40000560: 6d75 lui s10,0x1d
+40000562: 435f 6d6f 3a70 0x3a706d6f435f
+40000568: 2020 fld fs0,64(s0)
+4000056a: 2020 fld fs0,64(s0)
+4000056c: 2020 fld fs0,64(s0)
+4000056e: 2020 fld fs0,64(s0)
+40000570: 2520 fld fs0,72(a0)
+40000572: 0a64 addi s1,sp,284
+40000574: 0000 unimp
+40000576: 0000 unimp
+40000578: 2020 fld fs0,64(s0)
+4000057a: 6e49 lui t3,0x12
+4000057c: 5f74 lw a3,124(a4)
+4000057e: 706d6f43 fmadd.s ft10,fs10,ft6,fa4,unknown
+40000582: 203a fld ft0,392(sp)
+40000584: 2020 fld fs0,64(s0)
+40000586: 2020 fld fs0,64(s0)
+40000588: 2020 fld fs0,64(s0)
+4000058a: 2020 fld fs0,64(s0)
+4000058c: 2520 fld fs0,72(a0)
+4000058e: 0a64 addi s1,sp,284
+40000590: 0000 unimp
+40000592: 0000 unimp
+40000594: 2020 fld fs0,64(s0)
+40000596: 5f727453 0x5f727453
+4000059a: 706d6f43 fmadd.s ft10,fs10,ft6,fa4,unknown
+4000059e: 203a fld ft0,392(sp)
+400005a0: 2020 fld fs0,64(s0)
+400005a2: 2020 fld fs0,64(s0)
+400005a4: 2020 fld fs0,64(s0)
+400005a6: 2020 fld fs0,64(s0)
+400005a8: 2520 fld fs0,72(a0)
+400005aa: 00000a73 0xa73
+400005ae: 0000 unimp
+400005b0: 2020 fld fs0,64(s0)
+400005b2: 2020 fld fs0,64(s0)
+400005b4: 2020 fld fs0,64(s0)
+400005b6: 2020 fld fs0,64(s0)
+400005b8: 756f6873 csrrsi a6,0x756,30
+400005bc: 646c flw fa1,76(s0)
+400005be: 6220 flw fs0,64(a2)
+400005c0: 3a65 jal 3fffff78 <data_load_start+0x1fffe03e>
+400005c2: 2020 fld fs0,64(s0)
+400005c4: 4420 lw s0,72(s0)
+400005c6: 5248 lw a0,36(a2)
+400005c8: 5359 li t1,-10
+400005ca: 4f54 lw a3,28(a4)
+400005cc: 454e lw a0,208(sp)
+400005ce: 5020 lw s0,96(s0)
+400005d0: 4f52 lw t5,20(sp)
+400005d2: 4d415247 0x4d415247
+400005d6: 202c fld fa1,64(s0)
+400005d8: 454d4f53 0x454d4f53
+400005dc: 5320 lw s0,96(a4)
+400005de: 5254 lw a3,36(a2)
+400005e0: 4e49 li t3,18
+400005e2: 00000a47 fmsub.s fs4,ft0,ft0,ft0,rne
+400005e6: 0000 unimp
+400005e8: 654e flw fa0,208(sp)
+400005ea: 7478 flw fa4,108(s0)
+400005ec: 505f 7274 475f 0x475f7274505f
+400005f2: 6f6c flw fa1,92(a4)
+400005f4: 2d62 fld fs10,24(sp)
+400005f6: 0a3e slli s4,s4,0xf
+400005f8: 0000 unimp
+400005fa: 0000 unimp
+400005fc: 2020 fld fs0,64(s0)
+400005fe: 2020 fld fs0,64(s0)
+40000600: 2020 fld fs0,64(s0)
+40000602: 2020 fld fs0,64(s0)
+40000604: 756f6873 csrrsi a6,0x756,30
+40000608: 646c flw fa1,76(s0)
+4000060a: 6220 flw fs0,64(a2)
+4000060c: 3a65 jal 3fffffc4 <data_load_start+0x1fffe08a>
+4000060e: 2020 fld fs0,64(s0)
+40000610: 2820 fld fs0,80(s0)
+40000612: 6d69 lui s10,0x1a
+40000614: 6c70 flw fa2,92(s0)
+40000616: 6d65 lui s10,0x19
+40000618: 6e65 lui t3,0x19
+4000061a: 6174 flw fa3,68(a0)
+4000061c: 6974 flw fa3,84(a0)
+4000061e: 642d6e6f jal t3,400d6c60 <_end+0xd3bfc>
+40000622: 7065 c.lui zero,0xffff9
+40000624: 6e65 lui t3,0x19
+40000626: 6564 flw fs1,76(a0)
+40000628: 746e flw fs0,248(sp)
+4000062a: 2c29 jal 40000844 <data_end>
+4000062c: 7320 flw fs0,96(a4)
+4000062e: 6d61 lui s10,0x18
+40000630: 2065 jal 400006d8 <uart_ctrl_addr+0x4d4>
+40000632: 7361 lui t1,0xffff8
+40000634: 6120 flw fs0,64(a0)
+40000636: 6f62 flw ft10,24(sp)
+40000638: 6576 flw fa0,92(sp)
+4000063a: 000a c.slli zero,0x2
+4000063c: 6e49 lui t3,0x12
+4000063e: 5f74 lw a3,124(a4)
+40000640: 5f31 li t5,-20
+40000642: 6f4c flw fa1,28(a4)
+40000644: 20203a63 0x20203a63
+40000648: 2020 fld fs0,64(s0)
+4000064a: 2020 fld fs0,64(s0)
+4000064c: 2020 fld fs0,64(s0)
+4000064e: 2020 fld fs0,64(s0)
+40000650: 2520 fld fs0,72(a0)
+40000652: 0a64 addi s1,sp,284
+40000654: 0000 unimp
+40000656: 0000 unimp
+40000658: 6e49 lui t3,0x12
+4000065a: 5f74 lw a3,124(a4)
+4000065c: 5f32 lw t5,44(sp)
+4000065e: 6f4c flw fa1,28(a4)
+40000660: 20203a63 0x20203a63
+40000664: 2020 fld fs0,64(s0)
+40000666: 2020 fld fs0,64(s0)
+40000668: 2020 fld fs0,64(s0)
+4000066a: 2020 fld fs0,64(s0)
+4000066c: 2520 fld fs0,72(a0)
+4000066e: 0a64 addi s1,sp,284
+40000670: 0000 unimp
+40000672: 0000 unimp
+40000674: 6e49 lui t3,0x12
+40000676: 5f74 lw a3,124(a4)
+40000678: 6f4c5f33 0x6f4c5f33
+4000067c: 20203a63 0x20203a63
+40000680: 2020 fld fs0,64(s0)
+40000682: 2020 fld fs0,64(s0)
+40000684: 2020 fld fs0,64(s0)
+40000686: 2020 fld fs0,64(s0)
+40000688: 2520 fld fs0,72(a0)
+4000068a: 0a64 addi s1,sp,284
+4000068c: 0000 unimp
+4000068e: 0000 unimp
+40000690: 6e45 lui t3,0x11
+40000692: 6d75 lui s10,0x1d
+40000694: 4c5f 636f 203a 0x203a636f4c5f
+4000069a: 2020 fld fs0,64(s0)
+4000069c: 2020 fld fs0,64(s0)
+4000069e: 2020 fld fs0,64(s0)
+400006a0: 2020 fld fs0,64(s0)
+400006a2: 2020 fld fs0,64(s0)
+400006a4: 2520 fld fs0,72(a0)
+400006a6: 0a64 addi s1,sp,284
+400006a8: 0000 unimp
+400006aa: 0000 unimp
+400006ac: 5f727453 0x5f727453
+400006b0: 5f31 li t5,-20
+400006b2: 6f4c flw fa1,28(a4)
+400006b4: 20203a63 0x20203a63
+400006b8: 2020 fld fs0,64(s0)
+400006ba: 2020 fld fs0,64(s0)
+400006bc: 2020 fld fs0,64(s0)
+400006be: 2020 fld fs0,64(s0)
+400006c0: 2520 fld fs0,72(a0)
+400006c2: 00000a73 0xa73
+400006c6: 0000 unimp
+400006c8: 2020 fld fs0,64(s0)
+400006ca: 2020 fld fs0,64(s0)
+400006cc: 2020 fld fs0,64(s0)
+400006ce: 2020 fld fs0,64(s0)
+400006d0: 756f6873 csrrsi a6,0x756,30
+400006d4: 646c flw fa1,76(s0)
+400006d6: 6220 flw fs0,64(a2)
+400006d8: 3a65 jal 40000090 <rodata_start+0x90>
+400006da: 2020 fld fs0,64(s0)
+400006dc: 4420 lw s0,72(s0)
+400006de: 5248 lw a0,36(a2)
+400006e0: 5359 li t1,-10
+400006e2: 4f54 lw a3,28(a4)
+400006e4: 454e lw a0,208(sp)
+400006e6: 5020 lw s0,96(s0)
+400006e8: 4f52 lw t5,20(sp)
+400006ea: 4d415247 0x4d415247
+400006ee: 202c fld fa1,64(s0)
+400006f0: 2731 jal 40000dfc <Arr_2_Glob+0x4e0>
+400006f2: 53205453 0x53205453
+400006f6: 5254 lw a3,36(a2)
+400006f8: 4e49 li t3,18
+400006fa: 00000a47 fmsub.s fs4,ft0,ft0,ft0,rne
+400006fe: 0000 unimp
+40000700: 5f727453 0x5f727453
+40000704: 5f32 lw t5,44(sp)
+40000706: 6f4c flw fa1,28(a4)
+40000708: 20203a63 0x20203a63
+4000070c: 2020 fld fs0,64(s0)
+4000070e: 2020 fld fs0,64(s0)
+40000710: 2020 fld fs0,64(s0)
+40000712: 2020 fld fs0,64(s0)
+40000714: 2520 fld fs0,72(a0)
+40000716: 00000a73 0xa73
+4000071a: 0000 unimp
+4000071c: 2020 fld fs0,64(s0)
+4000071e: 2020 fld fs0,64(s0)
+40000720: 2020 fld fs0,64(s0)
+40000722: 2020 fld fs0,64(s0)
+40000724: 756f6873 csrrsi a6,0x756,30
+40000728: 646c flw fa1,76(s0)
+4000072a: 6220 flw fs0,64(a2)
+4000072c: 3a65 jal 400000e4 <rodata_start+0xe4>
+4000072e: 2020 fld fs0,64(s0)
+40000730: 4420 lw s0,72(s0)
+40000732: 5248 lw a0,36(a2)
+40000734: 5359 li t1,-10
+40000736: 4f54 lw a3,28(a4)
+40000738: 454e lw a0,208(sp)
+4000073a: 5020 lw s0,96(s0)
+4000073c: 4f52 lw t5,20(sp)
+4000073e: 4d415247 0x4d415247
+40000742: 202c fld fa1,64(s0)
+40000744: 2732 fld fa4,264(sp)
+40000746: 444e lw s0,208(sp)
+40000748: 5320 lw s0,96(a4)
+4000074a: 5254 lw a3,36(a2)
+4000074c: 4e49 li t3,18
+4000074e: 00000a47 fmsub.s fs4,ft0,ft0,ft0,rne
+40000752: 0000 unimp
+40000754: 654d lui a0,0x13
+40000756: 7361 lui t1,0xffff8
+40000758: 7275 lui tp,0xffffd
+4000075a: 6465 lui s0,0x19
+4000075c: 7420 flw fs0,104(s0)
+4000075e: 6d69 lui s10,0x1a
+40000760: 2065 jal 40000808 <uart_ctrl_addr+0x604>
+40000762: 6f74 flw fa3,92(a4)
+40000764: 6d73206f j 4003363a <_end+0x305d6>
+40000768: 6c61 lui s8,0x18
+4000076a: 206c fld fa1,192(s0)
+4000076c: 6f74 flw fa3,92(a4)
+4000076e: 6f20 flw fs0,88(a4)
+40000770: 7462 flw fs0,56(sp)
+40000772: 6961 lui s2,0x18
+40000774: 206e fld ft0,216(sp)
+40000776: 656d lui a0,0x1b
+40000778: 6e61 lui t3,0x18
+4000077a: 6e69 lui t3,0x1a
+4000077c: 6c756667 0x6c756667
+40000780: 7220 flw fs0,96(a2)
+40000782: 7365 lui t1,0xffff9
+40000784: 6c75 lui s8,0x1d
+40000786: 7374 flw fa3,100(a4)
+40000788: 000a c.slli zero,0x2
+4000078a: 0000 unimp
+4000078c: 6c50 flw fa2,28(s0)
+4000078e: 6165 addi sp,sp,112
+40000790: 69206573 csrrsi a0,0x692,0
+40000794: 636e flw ft6,216(sp)
+40000796: 6572 flw fa0,28(sp)
+40000798: 7361 lui t1,0xffff8
+4000079a: 2065 jal 40000842 <rodata_end+0x2>
+4000079c: 756e flw fa0,248(sp)
+4000079e: 626d lui tp,0x1b
+400007a0: 7265 lui tp,0xffff9
+400007a2: 6f20 flw fs0,88(a4)
+400007a4: 2066 fld ft0,88(sp)
+400007a6: 7572 flw fa0,60(sp)
+400007a8: 736e flw ft6,248(sp)
+400007aa: 000a c.slli zero,0x2
+400007ac: 6542 flw fa0,16(sp)
+400007ae: 5f6e6967 0x5f6e6967
+400007b2: 6974 flw fa3,84(a0)
+400007b4: 656d lui a0,0x1b
+400007b6: 253d jal 40000de4 <Arr_2_Glob+0x4c8>
+400007b8: 2064 fld fs1,192(s0)
+400007ba: 6e45 lui t3,0x11
+400007bc: 5f64 lw s1,124(a4)
+400007be: 6954 flw fa3,20(a0)
+400007c0: 656d lui a0,0x1b
+400007c2: 253d jal 40000df0 <Arr_2_Glob+0x4d4>
+400007c4: 2064 fld fs1,192(s0)
+400007c6: 7355 lui t1,0xffff5
+400007c8: 7265 lui tp,0xffff9
+400007ca: 545f 6d69 3d65 0x3d656d69545f
+400007d0: 6425 lui s0,0x9
+400007d2: 000a c.slli zero,0x2
+400007d4: 3130 fld fa2,96(a0)
+400007d6: 3332 fld ft6,296(sp)
+400007d8: 3534 fld fa3,104(a0)
+400007da: 3736 fld fa4,360(sp)
+400007dc: 3938 fld fa4,112(a0)
+400007de: 6261 lui tp,0x18
+400007e0: 66656463 bltu a0,t1,40000e48 <Arr_2_Glob+0x52c>
+400007e4: 6a696867 0x6a696867
+400007e8: 6e6d6c6b 0x6e6d6c6b
+400007ec: 7271706f j 40018712 <_end+0x156ae>
+400007f0: 76757473 csrrci s0,0x767,10
+400007f4: 7a797877 0x7a797877
+400007f8: 0000 unimp
+400007fa: 0000 unimp
+400007fc: 3130 fld fa2,96(a0)
+400007fe: 3332 fld ft6,296(sp)
+40000800: 3534 fld fa3,104(a0)
+40000802: 3736 fld fa4,360(sp)
+40000804: 3938 fld fa4,112(a0)
+40000806: 4241 li tp,16
+40000808: 46454443 fmadd.q fs0,fa0,ft4,fs0,rmm
+4000080c: 4a494847 fmsub.d fa6,fs2,ft4,fs1,rmm
+40000810: 4e4d4c4b fnmsub.q fs8,fs10,ft4,fs1,rmm
+40000814: 5251504f fnmadd.d ft0,ft2,ft5,fa0,unknown
+40000818: 56555453 0x56555453
+4000081c: 5a595857 0x5a595857
+40000820: 0000 unimp
+40000822: 0000 unimp
+40000824: 4e3c lw a5,88(a2)
+40000826: 4c55 li s8,21
+40000828: 3e4c fld fa1,184(a2)
+4000082a: 0000 unimp
+4000082c: 3130 fld fa2,96(a0)
+4000082e: 3332 fld ft6,296(sp)
+40000830: 3534 fld fa3,104(a0)
+40000832: 3736 fld fa4,360(sp)
+40000834: 3938 fld fa4,112(a0)
+40000836: 6261 lui tp,0x18
+40000838: 66656463 bltu a0,t1,40000ea0 <Arr_2_Glob+0x584>
+4000083c: 0000 unimp
+ ...
+
+Disassembly of section .data:
+
+40000840 <Reg>:
+40000840: 0001 nop
+ ...
+
+Disassembly of section .bss:
+
+40000844 <time_info>:
+ ...
+
+40000854 <Arr_1_Glob>:
+ ...
+
+4000091c <Arr_2_Glob>:
+ ...
+
+4000302c <Dhrystones_Per_Second>:
+4000302c: 0000 unimp
+ ...
+
+40003030 <Microseconds>:
+40003030: 0000 unimp
+ ...
+
+40003034 <User_Time>:
+40003034: 0000 unimp
+ ...
+
+40003038 <End_Time>:
+40003038: 0000 unimp
+ ...
+
+4000303c <Begin_Time>:
+4000303c: 0000 unimp
+ ...
+
+40003040 <Ch_2_Glob>:
+ ...
+
+40003041 <Ch_1_Glob>:
+40003041: 0000 unimp
+ ...
+
+40003044 <Bool_Glob>:
+40003044: 0000 unimp
+ ...
+
+40003048 <Int_Glob>:
+40003048: 0000 unimp
+ ...
+
+4000304c <Next_Ptr_Glob>:
+4000304c: 0000 unimp
+ ...
+
+40003050 <Ptr_Glob>:
+40003050: 0000 unimp
+ ...
+
+40003054 <last_valid_address>:
+40003054: 0000 unimp
+ ...
+
+40003058 <managed_memory_start>:
+40003058: 0000 unimp
+ ...
+
+4000305c <has_initialized>:
+4000305c: 0000 unimp
+ ...
+
+40003060 <heap_ptr>:
+40003060: 0000 unimp
+ ...
+
+Disassembly of section .comment:
+
+00000000 <_stack-0x8001ff0>:
+ 0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
+ 4: 2820 fld fs0,80(s0)
+ 6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm
+ a: 3920 fld fs0,112(a0)
+ c: 322e fld ft4,232(sp)
+ e: 302e fld ft0,232(sp)
+ ...
+
+Disassembly of section .riscv.attributes:
+
+00000000 <.riscv.attributes>:
+ 0: 2a41 jal 190 <spi_quad_mode-0x7fffe70>
+ 2: 0000 unimp
+ 4: 7200 flw fs0,32(a2)
+ 6: 7369 lui t1,0xffffa
+ 8: 01007663 bgeu zero,a6,14 <spi_quad_mode-0x7ffffec>
+ c: 0020 addi s0,sp,8
+ e: 0000 unimp
+ 10: 1004 addi s1,sp,32
+ 12: 7205 lui tp,0xfffe1
+ 14: 3376 fld ft6,376(sp)
+ 16: 6932 flw fs2,12(sp)
+ 18: 7032 flw ft0,44(sp)
+ 1a: 5f30 lw a2,120(a4)
+ 1c: 326d jal fffff9c6 <_end+0xbfffc962>
+ 1e: 3070 fld fa2,224(s0)
+ 20: 615f 7032 5f30 0x5f307032615f
+ 26: 30703263 0x30703263
+ ...
diff --git a/verilog/dv/dhrystone/spi_flash.mem b/verilog/dv/dhrystone/spi_flash.mem
new file mode 100644
index 0000000..139f0dc
--- /dev/null
+++ b/verilog/dv/dhrystone/spi_flash.mem
@@ -0,0 +1,8502 @@
+// /home/shc/Development/RISC-V/chipyard/vlsi/sim/testcase/dhrystone-2.1/gcc_dry2reg_flash.mem
+// gcc_dry2reg_flash.srec
+@00000000
+93
+00
+00
+00
+13
+01
+00
+00
+93
+01
+00
+00
+13
+02
+00
+00
+@00000010
+93
+02
+00
+00
+13
+03
+00
+00
+93
+03
+00
+00
+13
+04
+00
+00
+@00000020
+93
+04
+00
+00
+13
+05
+00
+00
+93
+05
+00
+00
+13
+06
+00
+00
+@00000030
+93
+06
+00
+00
+13
+07
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+93
+07
+00
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+13
+08
+00
+00
+@00000040
+93
+08
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+09
+00
+00
+93
+09
+00
+00
+13
+0A
+00
+00
+@00000050
+93
+0A
+00
+00
+13
+0B
+00
+00
+93
+0B
+00
+00
+13
+0C
+00
+00
+@00000060
+93
+0C
+00
+00
+13
+0D
+00
+00
+93
+0D
+00
+00
+13
+0E
+00
+00
+@00000070
+93
+0E
+00
+00
+13
+0F
+00
+00
+93
+0F
+00
+00
+37
+21
+00
+08
+@00000080
+13
+01
+01
+FF
+75
+24
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
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diff --git a/verilog/dv/dhrystone/wave.do b/verilog/dv/dhrystone/wave.do
new file mode 100644
index 0000000..8dcc64d
--- /dev/null
+++ b/verilog/dv/dhrystone/wave.do
@@ -0,0 +1,90 @@
+onerror {resume}
+quietly virtual function -install /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core -env /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core { ( ~(ctrl_killd ) )} dbgTemp1_ex_reg_valid_56
+quietly virtual function -install /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ibuf/exp -env /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ibuf/exp { (_io_out_T_2[4:0] == 5'b11111)} dbgTemp143_1026
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -expand -group CPU -radix decimal /testbench/cycle
+add wave -noupdate -expand -group CPU -expand -group coreMonitor /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc
+add wave -noupdate -expand -group CPU -expand -group coreMonitor /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst
+add wave -noupdate -expand -group CPU -expand -group coreMonitor /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_valid
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_valid
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_ready
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_bits_cmd
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_bits_addr
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_bits_size
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_valid
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_data
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_data_word_bypass
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_has_data
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_tag
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_s1_data_data
+add wave -noupdate -expand -group CPU -expand -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_s1_kill
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_valid
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_ready
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_opcode
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_size
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_param
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_address
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_corrupt
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_mask
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_data
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_source
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_valid
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_ready
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_opcode
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_size
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_source
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_data
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_valid
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_ready
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_opcode
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_param
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_address
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_corrupt
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_data
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_mask
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_size
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_source
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_valid
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_ready
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_opcode
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_data
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_size
+add wave -noupdate -expand -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_source
+add wave -noupdate -expand -group SPI-PSRAM /testbench/spi_ram/SCK_i
+add wave -noupdate -expand -group SPI-PSRAM /testbench/spi_ram/nCE_i
+add wave -noupdate -expand -group SPI-PSRAM /testbench/spi_ram/NC_io
+add wave -noupdate -expand -group SPI-PSRAM /testbench/spi_ram/nWP_io
+add wave -noupdate -expand -group SPI-PSRAM /testbench/spi_ram/SI_io
+add wave -noupdate -expand -group SPI-PSRAM /testbench/spi_ram/SO_io
+add wave -noupdate /testbench/uut/mprj/Marmot/io_oeb
+add wave -noupdate -expand -group SPI-Flash /testbench/spi_flash/SCLK
+add wave -noupdate -expand -group SPI-Flash /testbench/spi_flash/CS
+add wave -noupdate -expand -group SPI-Flash /testbench/spi_flash/SI
+add wave -noupdate -expand -group SPI-Flash /testbench/spi_flash/SO
+add wave -noupdate -expand -group SPI-Flash /testbench/spi_flash/WP
+add wave -noupdate -expand -group SPI-Flash /testbench/spi_flash/SIO3
+add wave -noupdate /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ctrl_killd
+add wave -noupdate /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/id_raddr1
+add wave -noupdate /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ex_waddr
+add wave -noupdate /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ibuf/exp/io_out_rs1
+add wave -noupdate /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ibuf/exp_io_in
+add wave -noupdate /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ibuf/icData
+add wave -noupdate /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/ibuf/icData_data
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1714380000 ps} 0} {{Cursor 2} {21100900000 ps} 0} {Trace {21511428110 ps} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 312
+configure wave -valuecolwidth 142
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {21099208519 ps} {21102591481 ps}
diff --git a/verilog/dv/jtag/Makefile b/verilog/dv/jtag/Makefile
new file mode 100644
index 0000000..2291ae2
--- /dev/null
+++ b/verilog/dv/jtag/Makefile
@@ -0,0 +1,54 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# RTL/GL/GL_SDF
+export SIM ?= RTL
+
+# Questa only
+SIMULATOR = Questa
+
+export TARGET_PATH = $(MARMOT_ROOT)
+export DESIGNS = $(TARGET_PATH)
+export CARAVEL_ROOT = $(TARGET_PATH)/caravel
+export MCW_ROOT = $(TARGET_PATH)/mgmt_core_wrapper
+export CORE_VERILOG_PATH = $(MCW_ROOT)/verilog
+#export PDK_ROOT = $(PDK_ROOT)
+#export PDK = $(PDK)
+export TOOLS = $(RISCV)
+export GCC_PREFIX = riscv64-unknown-linux-gnu
+
+TESTCASE_DIR = $(HOME)/Development/RISC-V/chipyard/vlsi/sim/testcase
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include ../make/sim.makefile
+
+setup:
+ echo "// $(TESTCASE_DIR)/jtag/spi_flash.mem" > spi_flash.mem
+ cat $(TESTCASE_DIR)/jtag/spi_flash.mem >> spi_flash.mem
+ cp $(TESTCASE_DIR)/jtag/spi_flash.lis spi_flash.lis
+
+wave:
+ vsim -gui vsim.wlf -do wave.do &
+
diff --git a/verilog/dv/jtag/io_mapping.v b/verilog/dv/jtag/io_mapping.v
new file mode 120000
index 0000000..35e5eff
--- /dev/null
+++ b/verilog/dv/jtag/io_mapping.v
@@ -0,0 +1 @@
+../dhrystone/io_mapping.v
\ No newline at end of file
diff --git a/verilog/dv/jtag/jtag.c b/verilog/dv/jtag/jtag.c
new file mode 100644
index 0000000..a27f576
--- /dev/null
+++ b/verilog/dv/jtag/jtag.c
@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+#define MARMOT_ICACHE_TAG_RAM_CLK_DELAY 2
+#define MARMOT_ICACHE_DATA_RAM0_CLK_DELAY 5
+#define MARMOT_ICACHE_DATA_RAM1_CLK_DELAY 4
+#define MARMOT_ICACHE_DATA_RAM2_CLK_DELAY 1
+#define MARMOT_ICACHE_DATA_RAM3_CLK_DELAY 3
+
+void main()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spi_enable = 1;
+ reg_wb_enable = 1;
+ //reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // All GPIO pins are configured to be bi-directional for Marmot use
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+
+#if 0
+ // For actual use
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+#else
+ // For simulation
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+#endif
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // TCK
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // TMS
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // TDI
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // TDO
+ //reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Initialize LA probes [127:0]
+ // Input:
+ // [31: 0] <- Marmot.gpio_out[31:0]
+ // Output:
+ // [31: 0] -> Marmot.gpio_in[31:0]
+ // [63:32] -> Marmot.ram_clk_delay_sel[31:0]
+ // [ 4: 0] -> u_clk_skew_adjust_0.sel[4:0] (I-$ Tag RAM)
+ // [ 9: 5] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM0)
+ // [14:10] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM1)
+ // [19:15] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM2)
+ // [24:20] -> u_clk_skew_adjust_1.sel[4:0] (I-$ Data RAM3)
+
+ reg_la0_oenb = reg_la0_iena = 0xffffffff; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0xffffffff; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0xffffffff; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0xffffffff; // [127:96]
+ reg_la0_data = 0xffffffff;
+ reg_la1_data = 0xffffffff;
+ reg_la2_data = 0xffffffff;
+ reg_la3_data = 0xffffffff;
+ reg_la0_data = 0x00000000;
+ reg_la1_data = 0x00000000;
+ reg_la2_data = 0x00000000;
+ reg_la3_data = 0x00000000;
+
+ // Configure LA probes [31:0] as inputs to mgmt_soc
+ reg_la0_iena = 0x00000000; // [31:0] <- Marmot.gpio_out[31:0]
+
+ // Set clock delay for Marmot RAMs
+ reg_la1_data = (MARMOT_ICACHE_TAG_RAM_CLK_DELAY)
+ | (MARMOT_ICACHE_DATA_RAM0_CLK_DELAY << 5)
+ | (MARMOT_ICACHE_DATA_RAM1_CLK_DELAY << 10)
+ | (MARMOT_ICACHE_DATA_RAM2_CLK_DELAY << 15)
+ | (MARMOT_ICACHE_DATA_RAM3_CLK_DELAY << 20);
+
+ // Start Marmot
+ reg_mprj_slave = 0x00000001;
+
+ // Wait for Marmot to finish and check result
+ while (1) {
+ reg_la0_data ^= 0xffffffff;
+
+ if ((reg_la0_data_in & 0xc0000000) != 0x0) {
+ if ((reg_la0_data_in & 0xc0000000) == 0x80000000) {
+ reg_mprj_datal = 0x12340000; // Pass
+ } else {
+ reg_mprj_datal = 0xdead0000; // Fail
+ }
+ break;
+ }
+ }
+}
diff --git a/verilog/dv/jtag/jtag_tb.v b/verilog/dv/jtag/jtag_tb.v
new file mode 100644
index 0000000..ac91414
--- /dev/null
+++ b/verilog/dv/jtag/jtag_tb.v
@@ -0,0 +1,375 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 100 ps
+
+`define TB testbench
+`define CARAVEL `TB.uut
+`define USER_PROJECT_WRAPPER `CARAVEL.mprj
+`define MARMOT `USER_PROJECT_WRAPPER.Marmot
+`define CHIP `MARMOT.MarmotCaravelChip
+`define PLATFORM `CHIP.dut
+`define SYS `PLATFORM.sys
+`define TILE `SYS.tile_prci_domain.tile_reset_domain.tile
+`define CORE `TILE.core
+`define UART0 `SYS.uartClockDomainWrapper.uart_0
+`define UART1 `SYS.uartClockDomainWrapper_1.uart_1
+`define UART2 `SYS.uartClockDomainWrapper_2.uart_2
+`define UART3 `SYS.uartClockDomainWrapper_3.uart_3
+`define UART4 `SYS.uartClockDomainWrapper_4.uart_4
+`define TLSPIRAM `SYS.qspiClockDomainWrapper_1.qspi_ram_0
+
+module testbench;
+ `include "io_mapping.v"
+
+ localparam CLOCK_PERIOD = 40; // ns
+ localparam TCK_PERIOD = 100;
+ localparam IR_LEN = 5;
+ localparam MAX_CYCLE = 200000;
+ localparam MAX_EXCEPTION_PC_COUNT = 100;
+
+ reg clock;
+ wire clock_wire = clock;
+ reg RSTB;
+ reg tck;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ wire reset = `MARMOT.wb_rst_i;
+
+`ifdef SIM
+ wire [31:0] PC = `CORE.coreMonitorBundle_pc;
+`else
+ wire [31:0] PC = {
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[31] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[30] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[29] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[28] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[27] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[26] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[25] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[24] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[23] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[22] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[21] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[20] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[19] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[18] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[17] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[16] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[15] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[14] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[13] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[12] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[11] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[10] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[9] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[8] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[7] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[6] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[5] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[4] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[3] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[2] ,
+ `MARMOT.\MarmotCaravelChip_dut_sys_tile_prci_domain_tile_reset_domain_tile_core_coreMonitorBundle_pc[1] ,
+ 1'b0};
+`endif
+
+//-------------------------------------------------------------------------------
+// Timeformat
+ initial begin
+ $timeformat(-9, 0, " ns", 12);
+ end
+
+//-------------------------------------------------------------------------------
+// Pull-up
+`ifdef PULLUP_IO
+ genvar gen_i;
+ generate
+ for (gen_i = 0; gen_i < 38; gen_i = gen_i + 1) begin
+ pullup(mprj_io[gen_i]);
+ end
+ endgenerate
+`endif
+
+//-------------------------------------------------------------------------------
+// Clock
+ initial begin
+ clock = 0;
+ tck = 0;
+ end
+
+ always #(CLOCK_PERIOD/2) clock <= (clock === 1'b0);
+ always #(TCK_PERIOD/2) tck <= (tck === 1'b0);
+
+//-------------------------------------------------------------------------------
+// Waveform
+ initial begin
+ if ($test$plusargs("waveform")) begin
+ $dumpfile("wave.vcd");
+ $dumpvars(0, `TB);
+ end
+ end
+
+//-------------------------------------------------------------------------------
+// Initialize FFs for gate level sim.
+`ifdef GL
+ `include "init_ff.v"
+`endif
+
+//-------------------------------------------------------------------------------
+// SDF annotate
+`ifdef ENABLE_SDF
+ initial begin
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", `CARAVEL.soc.DFFRAM_0 );
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", `CARAVEL.soc.core);
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core_wrapper.sdf", `CARAVEL.soc);
+ $sdf_annotate("../../../sdf/user_project_wrapper.sdf.gz", `USER_PROJECT_WRAPPER);
+ $sdf_annotate("../../../sdf/Marmot.sdf.gz", `MARMOT);
+ end
+`endif
+
+//-------------------------------------------------------------------------------
+// Count cycle
+ reg [31:0] cycle;
+ initial begin
+ cycle = 0;
+ end
+
+ always @(posedge clock) begin
+ cycle = cycle + 1;
+ end
+
+//-------------------------------------------------------------------------------
+// Monitor PC
+ integer exception_pc_count;
+
+ always @ (posedge clock) begin
+ if ($test$plusargs("pc_monitor")) begin
+ if (cycle % 1000 == 0) begin
+ $fwrite(32'h80000002, "[%t] %10d pc=%08x\n", $time, cycle, PC);
+ end
+ end
+
+ // Finish on PC=x
+ //if (^PC === 1'bx) begin
+ // $display("[%t] PC=xxxxxxxx", $time);
+ // repeat (50) @(posedge clock);
+ // $finish;
+ //end
+
+ // Finish on exception
+ if (PC == 32'h00000000 || PC == 32'h00000002) begin
+ exception_pc_count <= exception_pc_count + 1;
+ if (exception_pc_count > MAX_EXCEPTION_PC_COUNT) begin
+ $display("[%t] Exception occurred.", $time);
+ $finish;
+ end
+ end
+ else begin
+ exception_pc_count <= 0;
+ end
+ end
+
+//-------------------------------------------------------------------------------
+// Timeout
+ reg [31:0] max_cycle;
+ initial begin
+ if (! $value$plusargs("max_cycle=%d", max_cycle)) begin
+ max_cycle = MAX_CYCLE;
+ end
+
+ wait (reset === 1'b0);
+ wait (cycle < 10);
+ wait (cycle >= max_cycle);
+ $display("\n*** Timeout ***");
+ $finish;
+ end
+
+//-------------------------------------------------------------------------------
+// Pass
+ initial begin
+ wait (mprj_io[31:28] == 4'h1);
+ $display("\n*** Test Pass ***");
+ $finish;
+ end
+
+//-------------------------------------------------------------------------------
+// Fail
+ initial begin
+ wait (mprj_io[31:28] == 4'hd);
+ $display("\n*** Test Fail ***");
+ $finish;
+ end
+
+//-------------------------------------------------------------------------------
+// Reset
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+//-------------------------------------------------------------------------------
+// Power-up sequence
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[0] = 0; // Disable debug mode
+
+//-------------------------------------------------------------------------------
+// Caravel
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock_wire),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+//-------------------------------------------------------------------------------
+// SPI Flash for Mgmt. SoC
+ spiflash #(
+ .FILENAME(`MGMT_SOC_PROG)
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(),
+ .io3()
+ );
+
+//-------------------------------------------------------------------------------
+// SPI Flash model for Marmot
+MX25U3235F #(.Init_File("spi_flash.mem")) spi_flash
+(
+ .SCLK (mprj_io[io_spi0_flash_sck]),
+ .CS (mprj_io[io_spi0_flash_csb]),
+ .SI (mprj_io[io_spi0_flash_io_0]),
+ .SO (mprj_io[io_spi0_flash_io_1]),
+ .WP (mprj_io[io_spi0_flash_io_2]),
+ .SIO3 (mprj_io[io_spi0_flash_io_3])
+);
+
+//-------------------------------------------------------------------------------
+// SPI RAM model (APM APS6404L-3SQN_SQPI_PSRAM)
+`ifdef SIMULATOR_QUESTA
+sqpi_model #(.VeriOutStr(1), .STOP_ON_ERROR(0)) spi_ram
+(
+ .SCK_i (mprj_io[io_spi2_sck]),
+ .nCE_i (mprj_io[io_spi2_csb]),
+ .SI_io (mprj_io[io_spi2_io_0]),
+ .SO_io (mprj_io[io_spi2_io_1]),
+ .nWP_io (mprj_io[io_spi2_io_2]),
+ .NC_io (mprj_io[io_spi2_io_3])
+);
+`else
+// SPI Flash model
+MX25U3235F spi_ram
+(
+ .SCLK (mprj_io[io_spi2_sck]),
+ .CS (mprj_io[io_spi2_csb]),
+ .SI (mprj_io[io_spi2_io_0]),
+ .SO (mprj_io[io_spi2_io_1]),
+ .WP (mprj_io[io_spi2_io_2]),
+ .SIO3 (mprj_io[io_spi2_io_3])
+);
+`endif
+
+//-------------------------------------------------------------------------------
+// UART model for Marmot
+`ifdef UART_HIGH_SPEED
+ `define CLKS_PER_BIT 16 // F_CLK / 16 baud
+`else
+ `define CLKS_PER_BIT ((1000/CLOCK_PERIOD)*1000000 / 115200) // 115200 baud
+ //`define CLKS_PER_BIT 104 // 12MHz / 115200 baud
+`endif
+
+uart_tb #(.CLKS_PER_BIT(`CLKS_PER_BIT)) uart0_tb
+(
+ .clk (clock_wire),
+ .rst (~RSTB),
+ .rxd (mprj_io[io_uart0_tx]),
+ .txd (mprj_io[io_uart0_rx])
+);
+
+//-------------------------------------------------------------------------------
+// JTAG driver
+ jtag_driver #(.TCK_PERIOD(TCK_PERIOD), .IR_LEN(IR_LEN))
+ jtag_driver (
+ .tck(mprj_io[io_TCK]),
+ .tms(mprj_io[io_TMS]),
+ .tdi(mprj_io[io_TDI]),
+ .tdo(mprj_io[io_TDO])
+ );
+
+`ifdef SIMULATOR_QUESTA
+ pullup(mprj_io[io_TDO]); // doesn't work well with Icarus
+`endif
+
+//-------------------------------------------------------------------------------
+// Stimulus
+`include "stm.v"
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/jtag/run_sim.csh b/verilog/dv/jtag/run_sim.csh
new file mode 100755
index 0000000..2bd2cbf
--- /dev/null
+++ b/verilog/dv/jtag/run_sim.csh
@@ -0,0 +1,34 @@
+#!/bin/csh -f
+
+# RTL/GL
+set sim = RTL
+#set sim = GL
+
+# Simulator
+set simulator = Icarus
+#set simulator = Questa
+
+# Compile option
+set mgmt_soc_prog = \\\"jtag.hex\\\"
+
+if ($simulator == Icarus) then
+ set compopt = "-DMGMT_SOC_PROG=$mgmt_soc_prog"
+ set compopt = "$compopt -DPRINTF_COND=0" # 0 = stop instruction trace
+else
+ set compopt = "+define+MGMT_SOC_PROG=$mgmt_soc_prog"
+ set compopt = "$compopt +define+PRINTF_COND=0" # 0 = stop instruction trace
+endif
+
+# Simulation option
+set simopt =
+#set simopt = "$simopt +waveform"
+#set simopt = "$simopt +pc_monitor"
+#set simopt = "$simopt +max_cycle=200000"
+
+# For Questa
+set doopt = ""
+#set doopt = "log -r /testbench/* ;" # waveform
+
+make SIMULATOR=$simulator SIM=$sim USER_COMPOPT="$compopt" USER_SIMOPT="$simopt" DOOPT="$doopt" \
+ |& spike-dasm | egrep -v '\[0\] pc=' | tee sim_${sim}.log
+
diff --git a/verilog/dv/jtag/spi_flash.lis b/verilog/dv/jtag/spi_flash.lis
new file mode 100644
index 0000000..0a54585
--- /dev/null
+++ b/verilog/dv/jtag/spi_flash.lis
@@ -0,0 +1,1218 @@
+
+spi_flash.elf: file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+20000000 <_prog_start>:
+20000000: 00000093 li ra,0
+20000004: 00000113 li sp,0
+20000008: 00000193 li gp,0
+2000000c: 00000213 li tp,0
+20000010: 00000293 li t0,0
+20000014: 00000313 li t1,0
+20000018: 00000393 li t2,0
+2000001c: 00000413 li s0,0
+20000020: 00000493 li s1,0
+20000024: 00000513 li a0,0
+20000028: 00000593 li a1,0
+2000002c: 00000613 li a2,0
+20000030: 00000693 li a3,0
+20000034: 00000713 li a4,0
+20000038: 00000793 li a5,0
+2000003c: 00000813 li a6,0
+20000040: 00000893 li a7,0
+20000044: 00000913 li s2,0
+20000048: 00000993 li s3,0
+2000004c: 00000a13 li s4,0
+20000050: 00000a93 li s5,0
+20000054: 00000b13 li s6,0
+20000058: 00000b93 li s7,0
+2000005c: 00000c13 li s8,0
+20000060: 00000c93 li s9,0
+20000064: 00000d13 li s10,0
+20000068: 00000d93 li s11,0
+2000006c: 00000e13 li t3,0
+20000070: 00000e93 li t4,0
+20000074: 00000f13 li t5,0
+20000078: 00000f93 li t6,0
+2000007c: 00800913 li s2,8
+20000080: 30491073 csrw mie,s2
+20000084: 00000493 li s1,0
+20000088: f1402973 csrr s2,mhartid
+2000008c: 03249663 bne s1,s2,200000b8 <_prog_start+0xb8>
+20000090: 08002137 lui sp,0x8002
+20000094: ff010113 addi sp,sp,-16 # 8001ff0 <_stack>
+20000098: 421000ef jal ra,20000cb8 <main>
+2000009c: 020004b7 lui s1,0x2000
+200000a0: 00100913 li s2,1
+200000a4: 0124a023 sw s2,0(s1) # 2000000 <spi_quad_mode-0x6000000>
+200000a8: 00448493 addi s1,s1,4
+200000ac: 02000937 lui s2,0x2000
+200000b0: 08090913 addi s2,s2,128 # 2000080 <spi_quad_mode-0x5ffff80>
+200000b4: ff24c6e3 blt s1,s2,200000a0 <_prog_start+0xa0>
+200000b8: 10500073 wfi
+200000bc: 34402973 csrr s2,mip
+200000c0: 00897913 andi s2,s2,8
+200000c4: fe090ae3 beqz s2,200000b8 <_prog_start+0xb8>
+200000c8: 020004b7 lui s1,0x2000
+200000cc: f1402973 csrr s2,mhartid
+200000d0: 00291913 slli s2,s2,0x2
+200000d4: 00990933 add s2,s2,s1
+200000d8: 00092023 sw zero,0(s2)
+200000dc: 0004a903 lw s2,0(s1) # 2000000 <spi_quad_mode-0x6000000>
+200000e0: fe091ee3 bnez s2,200000dc <_prog_start+0xdc>
+200000e4: 00448493 addi s1,s1,4
+200000e8: 02000937 lui s2,0x2000
+200000ec: 08090913 addi s2,s2,128 # 2000080 <spi_quad_mode-0x5ffff80>
+200000f0: ff24c6e3 blt s1,s2,200000dc <_prog_start+0xdc>
+
+200000f4 <loop>:
+200000f4: 0000006f j 200000f4 <loop>
+
+200000f8 <memset>:
+200000f8: 0ff5f593 andi a1,a1,255
+200000fc: 00c50733 add a4,a0,a2
+20000100: 87aa mv a5,a0
+20000102: 00c05763 blez a2,20000110 <memset+0x18>
+20000106: 0785 addi a5,a5,1
+20000108: feb78fa3 sb a1,-1(a5)
+2000010c: fef71de3 bne a4,a5,20000106 <memset+0xe>
+20000110: 8082 ret
+
+20000112 <memcpy>:
+20000112: 00c05c63 blez a2,2000012a <memcpy+0x18>
+20000116: 962a add a2,a2,a0
+20000118: 87aa mv a5,a0
+2000011a: 0005c703 lbu a4,0(a1)
+2000011e: 0785 addi a5,a5,1
+20000120: 0585 addi a1,a1,1
+20000122: fee78fa3 sb a4,-1(a5)
+20000126: fef61ae3 bne a2,a5,2000011a <memcpy+0x8>
+2000012a: 8082 ret
+
+2000012c <memcmp>:
+2000012c: 02c05563 blez a2,20000156 <memcmp+0x2a>
+20000130: 962e add a2,a2,a1
+20000132: a019 j 20000138 <memcmp+0xc>
+20000134: 02b60163 beq a2,a1,20000156 <memcmp+0x2a>
+20000138: 00054783 lbu a5,0(a0)
+2000013c: 0005c703 lbu a4,0(a1)
+20000140: 0505 addi a0,a0,1
+20000142: 0585 addi a1,a1,1
+20000144: fee788e3 beq a5,a4,20000134 <memcmp+0x8>
+20000148: 00f73533 sltu a0,a4,a5
+2000014c: 40a00533 neg a0,a0
+20000150: 8909 andi a0,a0,2
+20000152: 157d addi a0,a0,-1
+20000154: 8082 ret
+20000156: 4501 li a0,0
+20000158: 8082 ret
+
+2000015a <strlen>:
+2000015a: 00054783 lbu a5,0(a0)
+2000015e: 872a mv a4,a0
+20000160: 4501 li a0,0
+20000162: cb81 beqz a5,20000172 <strlen+0x18>
+20000164: 0505 addi a0,a0,1
+20000166: 00a707b3 add a5,a4,a0
+2000016a: 0007c783 lbu a5,0(a5)
+2000016e: fbfd bnez a5,20000164 <strlen+0xa>
+20000170: 8082 ret
+20000172: 8082 ret
+
+20000174 <strcpy>:
+20000174: 0005c783 lbu a5,0(a1)
+20000178: 00f50023 sb a5,0(a0)
+2000017c: 0005c783 lbu a5,0(a1)
+20000180: cb99 beqz a5,20000196 <strcpy+0x22>
+20000182: 87aa mv a5,a0
+20000184: 0015c703 lbu a4,1(a1)
+20000188: 0585 addi a1,a1,1
+2000018a: 0785 addi a5,a5,1
+2000018c: 00e78023 sb a4,0(a5)
+20000190: 0005c703 lbu a4,0(a1)
+20000194: fb65 bnez a4,20000184 <strcpy+0x10>
+20000196: 8082 ret
+
+20000198 <strcmp>:
+20000198: a019 j 2000019e <strcmp+0x6>
+2000019a: 00e79d63 bne a5,a4,200001b4 <strcmp+0x1c>
+2000019e: 00054783 lbu a5,0(a0)
+200001a2: 0005c703 lbu a4,0(a1)
+200001a6: 0505 addi a0,a0,1
+200001a8: 0585 addi a1,a1,1
+200001aa: 00e7e6b3 or a3,a5,a4
+200001ae: f6f5 bnez a3,2000019a <strcmp+0x2>
+200001b0: 4501 li a0,0
+200001b2: 8082 ret
+200001b4: 00f73533 sltu a0,a4,a5
+200001b8: 40a00533 neg a0,a0
+200001bc: 8909 andi a0,a0,2
+200001be: 157d addi a0,a0,-1
+200001c0: 8082 ret
+
+200001c2 <strncmp>:
+200001c2: 87aa mv a5,a0
+200001c4: 00c50833 add a6,a0,a2
+200001c8: 0007c703 lbu a4,0(a5)
+200001cc: 40f806b3 sub a3,a6,a5
+200001d0: eb19 bnez a4,200001e6 <strncmp+0x24>
+200001d2: 0005c703 lbu a4,0(a1)
+200001d6: c70d beqz a4,20000200 <strncmp+0x3e>
+200001d8: 9532 add a0,a0,a2
+200001da: 8d1d sub a0,a0,a5
+200001dc: 00a02533 sgtz a0,a0
+200001e0: 40a00533 neg a0,a0
+200001e4: 8082 ret
+200001e6: 00d05d63 blez a3,20000200 <strncmp+0x3e>
+200001ea: 0005c683 lbu a3,0(a1)
+200001ee: 0785 addi a5,a5,1
+200001f0: 0585 addi a1,a1,1
+200001f2: fce68be3 beq a3,a4,200001c8 <strncmp+0x6>
+200001f6: 4505 li a0,1
+200001f8: fee6e6e3 bltu a3,a4,200001e4 <strncmp+0x22>
+200001fc: 557d li a0,-1
+200001fe: 8082 ret
+20000200: 4501 li a0,0
+20000202: 8082 ret
+
+20000204 <putc>:
+20000204: 1141 addi sp,sp,-16
+20000206: c422 sw s0,8(sp)
+20000208: c606 sw ra,12(sp)
+2000020a: 47a9 li a5,10
+2000020c: 842a mv s0,a0
+2000020e: 00f50863 beq a0,a5,2000021e <putc+0x1a>
+20000212: 85a2 mv a1,s0
+20000214: 4422 lw s0,8(sp)
+20000216: 40b2 lw ra,12(sp)
+20000218: 4501 li a0,0
+2000021a: 0141 addi sp,sp,16
+2000021c: a261 j 200003a4 <serial_send_byte>
+2000021e: 45b5 li a1,13
+20000220: 4501 li a0,0
+20000222: 2249 jal 200003a4 <serial_send_byte>
+20000224: 85a2 mv a1,s0
+20000226: 4422 lw s0,8(sp)
+20000228: 40b2 lw ra,12(sp)
+2000022a: 4501 li a0,0
+2000022c: 0141 addi sp,sp,16
+2000022e: aa9d j 200003a4 <serial_send_byte>
+
+20000230 <getc>:
+20000230: 1141 addi sp,sp,-16
+20000232: 4501 li a0,0
+20000234: c422 sw s0,8(sp)
+20000236: c606 sw ra,12(sp)
+20000238: 225d jal 200003de <serial_recv_byte>
+2000023a: 47b5 li a5,13
+2000023c: 4429 li s0,10
+2000023e: 00f50363 beq a0,a5,20000244 <getc+0x14>
+20000242: 842a mv s0,a0
+20000244: 8522 mv a0,s0
+20000246: 3f7d jal 20000204 <putc>
+20000248: 40b2 lw ra,12(sp)
+2000024a: 8522 mv a0,s0
+2000024c: 4422 lw s0,8(sp)
+2000024e: 0141 addi sp,sp,16
+20000250: 8082 ret
+
+20000252 <puts>:
+20000252: 1141 addi sp,sp,-16
+20000254: c422 sw s0,8(sp)
+20000256: c606 sw ra,12(sp)
+20000258: 842a mv s0,a0
+2000025a: 00054503 lbu a0,0(a0)
+2000025e: c511 beqz a0,2000026a <puts+0x18>
+20000260: 0405 addi s0,s0,1
+20000262: 374d jal 20000204 <putc>
+20000264: 00044503 lbu a0,0(s0)
+20000268: fd65 bnez a0,20000260 <puts+0xe>
+2000026a: 40b2 lw ra,12(sp)
+2000026c: 4422 lw s0,8(sp)
+2000026e: 4501 li a0,0
+20000270: 0141 addi sp,sp,16
+20000272: 8082 ret
+
+20000274 <gets>:
+20000274: 1141 addi sp,sp,-16
+20000276: c422 sw s0,8(sp)
+20000278: c226 sw s1,4(sp)
+2000027a: c04a sw s2,0(sp)
+2000027c: c606 sw ra,12(sp)
+2000027e: 4929 li s2,10
+20000280: 842a mv s0,a0
+20000282: 4481 li s1,0
+20000284: 3775 jal 20000230 <getc>
+20000286: 01250c63 beq a0,s2,2000029e <gets+0x2a>
+2000028a: 00a40023 sb a0,0(s0)
+2000028e: 00148793 addi a5,s1,1
+20000292: 0405 addi s0,s0,1
+20000294: c519 beqz a0,200002a2 <gets+0x2e>
+20000296: 84be mv s1,a5
+20000298: 3f61 jal 20000230 <getc>
+2000029a: ff2518e3 bne a0,s2,2000028a <gets+0x16>
+2000029e: 00040023 sb zero,0(s0)
+200002a2: 40b2 lw ra,12(sp)
+200002a4: 4422 lw s0,8(sp)
+200002a6: 4902 lw s2,0(sp)
+200002a8: 8526 mv a0,s1
+200002aa: 4492 lw s1,4(sp)
+200002ac: 0141 addi sp,sp,16
+200002ae: 8082 ret
+
+200002b0 <putxval>:
+200002b0: 1101 addi sp,sp,-32
+200002b2: ce06 sw ra,28(sp)
+200002b4: cc22 sw s0,24(sp)
+200002b6: 00010623 sb zero,12(sp)
+200002ba: ed05 bnez a0,200002f2 <putxval+0x42>
+200002bc: e191 bnez a1,200002c0 <putxval+0x10>
+200002be: 4585 li a1,1
+200002c0: 00b10793 addi a5,sp,11
+200002c4: 03000713 li a4,48
+200002c8: c591 beqz a1,200002d4 <putxval+0x24>
+200002ca: 00e78023 sb a4,0(a5)
+200002ce: 15fd addi a1,a1,-1
+200002d0: 17fd addi a5,a5,-1
+200002d2: fde5 bnez a1,200002ca <putxval+0x1a>
+200002d4: 0017c503 lbu a0,1(a5)
+200002d8: 00178413 addi s0,a5,1
+200002dc: c511 beqz a0,200002e8 <putxval+0x38>
+200002de: 0405 addi s0,s0,1
+200002e0: 3715 jal 20000204 <putc>
+200002e2: 00044503 lbu a0,0(s0)
+200002e6: fd65 bnez a0,200002de <putxval+0x2e>
+200002e8: 40f2 lw ra,28(sp)
+200002ea: 4462 lw s0,24(sp)
+200002ec: 4501 li a0,0
+200002ee: 6105 addi sp,sp,32
+200002f0: 8082 ret
+200002f2: 872a mv a4,a0
+200002f4: 00f77793 andi a5,a4,15
+200002f8: 00001817 auipc a6,0x1
+200002fc: cfc80813 addi a6,a6,-772 # 20000ff4 <uart_ctrl_addr+0x22c>
+20000300: 97c2 add a5,a5,a6
+20000302: 0007c503 lbu a0,0(a5)
+20000306: 00b10413 addi s0,sp,11
+2000030a: fff40793 addi a5,s0,-1
+2000030e: 00a780a3 sb a0,1(a5)
+20000312: 8311 srli a4,a4,0x4
+20000314: cd99 beqz a1,20000332 <putxval+0x82>
+20000316: 15fd addi a1,a1,-1
+20000318: d755 beqz a4,200002c4 <putxval+0x14>
+2000031a: 843e mv s0,a5
+2000031c: 00f77793 andi a5,a4,15
+20000320: 97c2 add a5,a5,a6
+20000322: 0007c503 lbu a0,0(a5)
+20000326: 8311 srli a4,a4,0x4
+20000328: fff40793 addi a5,s0,-1
+2000032c: 00a780a3 sb a0,1(a5)
+20000330: f1fd bnez a1,20000316 <putxval+0x66>
+20000332: 00f77693 andi a3,a4,15
+20000336: 96c2 add a3,a3,a6
+20000338: fff78613 addi a2,a5,-1
+2000033c: d345 beqz a4,200002dc <putxval+0x2c>
+2000033e: 0006c503 lbu a0,0(a3)
+20000342: 8311 srli a4,a4,0x4
+20000344: 843e mv s0,a5
+20000346: 00a78023 sb a0,0(a5)
+2000034a: 00f77693 andi a3,a4,15
+2000034e: 87b2 mv a5,a2
+20000350: 96c2 add a3,a3,a6
+20000352: fff78613 addi a2,a5,-1
+20000356: d359 beqz a4,200002dc <putxval+0x2c>
+20000358: b7dd j 2000033e <putxval+0x8e>
+
+2000035a <serial_init>:
+2000035a: 00251793 slli a5,a0,0x2
+2000035e: 00001517 auipc a0,0x1
+20000362: a6a50513 addi a0,a0,-1430 # 20000dc8 <uart_ctrl_addr>
+20000366: 953e add a0,a0,a5
+20000368: 4118 lw a4,0(a0)
+2000036a: 4785 li a5,1
+2000036c: c71c sw a5,8(a4)
+2000036e: c75c sw a5,12(a4)
+20000370: 00f58a63 beq a1,a5,20000384 <serial_init+0x2a>
+20000374: 36300793 li a5,867
+20000378: cf1c sw a5,24(a4)
+2000037a: 435c lw a5,4(a4)
+2000037c: fe07dfe3 bgez a5,2000037a <serial_init+0x20>
+20000380: 4501 li a0,0
+20000382: 8082 ret
+20000384: 47bd li a5,15
+20000386: cf1c sw a5,24(a4)
+20000388: bfcd j 2000037a <serial_init+0x20>
+
+2000038a <serial_is_send_enable>:
+2000038a: 00251793 slli a5,a0,0x2
+2000038e: 00001517 auipc a0,0x1
+20000392: a3a50513 addi a0,a0,-1478 # 20000dc8 <uart_ctrl_addr>
+20000396: 953e add a0,a0,a5
+20000398: 411c lw a5,0(a0)
+2000039a: 4388 lw a0,0(a5)
+2000039c: fff54513 not a0,a0
+200003a0: 817d srli a0,a0,0x1f
+200003a2: 8082 ret
+
+200003a4 <serial_send_byte>:
+200003a4: 00251793 slli a5,a0,0x2
+200003a8: 00001517 auipc a0,0x1
+200003ac: a2050513 addi a0,a0,-1504 # 20000dc8 <uart_ctrl_addr>
+200003b0: 953e add a0,a0,a5
+200003b2: 4118 lw a4,0(a0)
+200003b4: 431c lw a5,0(a4)
+200003b6: fe07cfe3 bltz a5,200003b4 <serial_send_byte+0x10>
+200003ba: c30c sw a1,0(a4)
+200003bc: 4501 li a0,0
+200003be: 8082 ret
+
+200003c0 <serial_is_recv_enable>:
+200003c0: 00251793 slli a5,a0,0x2
+200003c4: 00001517 auipc a0,0x1
+200003c8: a0450513 addi a0,a0,-1532 # 20000dc8 <uart_ctrl_addr>
+200003cc: 953e add a0,a0,a5
+200003ce: 411c lw a5,0(a0)
+200003d0: 43dc lw a5,4(a5)
+200003d2: fff7c513 not a0,a5
+200003d6: 00f58023 sb a5,0(a1)
+200003da: 817d srli a0,a0,0x1f
+200003dc: 8082 ret
+
+200003de <serial_recv_byte>:
+200003de: 00251793 slli a5,a0,0x2
+200003e2: 00001517 auipc a0,0x1
+200003e6: 9e650513 addi a0,a0,-1562 # 20000dc8 <uart_ctrl_addr>
+200003ea: 953e add a0,a0,a5
+200003ec: 411c lw a5,0(a0)
+200003ee: 43c8 lw a0,4(a5)
+200003f0: fe054fe3 bltz a0,200003ee <serial_recv_byte+0x10>
+200003f4: 0ff57513 andi a0,a0,255
+200003f8: 8082 ret
+
+200003fa <number>:
+200003fa: 711d addi sp,sp,-96
+200003fc: cea2 sw s0,92(sp)
+200003fe: cca6 sw s1,88(sp)
+20000400: 0407f813 andi a6,a5,64
+20000404: 00001e17 auipc t3,0x1
+20000408: c2ce0e13 addi t3,t3,-980 # 20001030 <uart_ctrl_addr+0x268>
+2000040c: 00081663 bnez a6,20000418 <number+0x1e>
+20000410: 00001e17 auipc t3,0x1
+20000414: bf8e0e13 addi t3,t3,-1032 # 20001008 <uart_ctrl_addr+0x240>
+20000418: 0107f413 andi s0,a5,16
+2000041c: 14040263 beqz s0,20000560 <number+0x166>
+20000420: 9bf9 andi a5,a5,-2
+20000422: 84a2 mv s1,s0
+20000424: 0027f813 andi a6,a5,2
+20000428: 02000f93 li t6,32
+2000042c: 0207f393 andi t2,a5,32
+20000430: 14080663 beqz a6,2000057c <number+0x182>
+20000434: 1405c663 bltz a1,20000580 <number+0x186>
+20000438: 0047f813 andi a6,a5,4
+2000043c: 16081c63 bnez a6,200005b4 <number+0x1ba>
+20000440: 8ba1 andi a5,a5,8
+20000442: 4281 li t0,0
+20000444: c781 beqz a5,2000044c <number+0x52>
+20000446: 16fd addi a3,a3,-1
+20000448: 02000293 li t0,32
+2000044c: 00038a63 beqz t2,20000460 <number+0x66>
+20000450: 47c1 li a5,16
+20000452: 16f60f63 beq a2,a5,200005d0 <number+0x1d6>
+20000456: ff860793 addi a5,a2,-8
+2000045a: 0017b793 seqz a5,a5
+2000045e: 8e9d sub a3,a3,a5
+20000460: 12059763 bnez a1,2000058e <number+0x194>
+20000464: 03000793 li a5,48
+20000468: 00f10623 sb a5,12(sp)
+2000046c: 4301 li t1,0
+2000046e: 03000813 li a6,48
+20000472: 4885 li a7,1
+20000474: 007c addi a5,sp,12
+20000476: 8ec6 mv t4,a7
+20000478: 00e8d363 bge a7,a4,2000047e <number+0x84>
+2000047c: 8eba mv t4,a4
+2000047e: 41d68e33 sub t3,a3,t4
+20000482: fffe0593 addi a1,t3,-1
+20000486: ec91 bnez s1,200004a2 <number+0xa8>
+20000488: 01c506b3 add a3,a0,t3
+2000048c: 02000713 li a4,32
+20000490: 15c05a63 blez t3,200005e4 <number+0x1ea>
+20000494: 0505 addi a0,a0,1
+20000496: fee50fa3 sb a4,-1(a0)
+2000049a: fed51de3 bne a0,a3,20000494 <number+0x9a>
+2000049e: 55f9 li a1,-2
+200004a0: 5e7d li t3,-1
+200004a2: 00028563 beqz t0,200004ac <number+0xb2>
+200004a6: 00550023 sb t0,0(a0)
+200004aa: 0505 addi a0,a0,1
+200004ac: 00038863 beqz t2,200004bc <number+0xc2>
+200004b0: 4721 li a4,8
+200004b2: 12e60163 beq a2,a4,200005d4 <number+0x1da>
+200004b6: 4741 li a4,16
+200004b8: 10e60263 beq a2,a4,200005bc <number+0x1c2>
+200004bc: e80d bnez s0,200004ee <number+0xf4>
+200004be: 862a mv a2,a0
+200004c0: 4705 li a4,1
+200004c2: 13c05663 blez t3,200005ee <number+0x1f4>
+200004c6: 0605 addi a2,a2,1
+200004c8: 40c706b3 sub a3,a4,a2
+200004cc: 96ae add a3,a3,a1
+200004ce: 96aa add a3,a3,a0
+200004d0: fff60fa3 sb t6,-1(a2)
+200004d4: fed049e3 bgtz a3,200004c6 <number+0xcc>
+200004d8: fff5c713 not a4,a1
+200004dc: 877d srai a4,a4,0x1f
+200004de: 8f6d and a4,a4,a1
+200004e0: 15fd addi a1,a1,-1
+200004e2: 40e58e33 sub t3,a1,a4
+200004e6: 0705 addi a4,a4,1
+200004e8: 953a add a0,a0,a4
+200004ea: fffe0593 addi a1,t3,-1
+200004ee: 411e8733 sub a4,t4,a7
+200004f2: 972a add a4,a4,a0
+200004f4: 03000693 li a3,48
+200004f8: 0fd8d463 bge a7,t4,200005e0 <number+0x1e6>
+200004fc: 0505 addi a0,a0,1
+200004fe: fed50fa3 sb a3,-1(a0)
+20000502: fea71de3 bne a4,a0,200004fc <number+0x102>
+20000506: 00678633 add a2,a5,t1
+2000050a: 86ba mv a3,a4
+2000050c: 4505 li a0,1
+2000050e: a019 j 20000514 <number+0x11a>
+20000510: 00064803 lbu a6,0(a2)
+20000514: 0685 addi a3,a3,1
+20000516: 40d507b3 sub a5,a0,a3
+2000051a: 979a add a5,a5,t1
+2000051c: 97ba add a5,a5,a4
+2000051e: ff068fa3 sb a6,-1(a3)
+20000522: 167d addi a2,a2,-1
+20000524: fef046e3 bgtz a5,20000510 <number+0x116>
+20000528: 00130513 addi a0,t1,1
+2000052c: 953a add a0,a0,a4
+2000052e: 03c05563 blez t3,20000558 <number+0x15e>
+20000532: 872a mv a4,a0
+20000534: 02000613 li a2,32
+20000538: 4685 li a3,1
+2000053a: 0705 addi a4,a4,1
+2000053c: 40e687b3 sub a5,a3,a4
+20000540: 97ae add a5,a5,a1
+20000542: 97aa add a5,a5,a0
+20000544: fec70fa3 sb a2,-1(a4)
+20000548: fef049e3 bgtz a5,2000053a <number+0x140>
+2000054c: fff5c793 not a5,a1
+20000550: 87fd srai a5,a5,0x1f
+20000552: 8dfd and a1,a1,a5
+20000554: 0585 addi a1,a1,1
+20000556: 952e add a0,a0,a1
+20000558: 4476 lw s0,92(sp)
+2000055a: 44e6 lw s1,88(sp)
+2000055c: 6125 addi sp,sp,96
+2000055e: 8082 ret
+20000560: 0017f813 andi a6,a5,1
+20000564: 0117f493 andi s1,a5,17
+20000568: 03000f93 li t6,48
+2000056c: ea080ce3 beqz a6,20000424 <number+0x2a>
+20000570: 0027f813 andi a6,a5,2
+20000574: 0207f393 andi t2,a5,32
+20000578: ea081ee3 bnez a6,20000434 <number+0x3a>
+2000057c: 4281 li t0,0
+2000057e: b5f9 j 2000044c <number+0x52>
+20000580: 40b005b3 neg a1,a1
+20000584: 16fd addi a3,a3,-1
+20000586: 02d00293 li t0,45
+2000058a: ec0393e3 bnez t2,20000450 <number+0x56>
+2000058e: 4881 li a7,0
+20000590: 007c addi a5,sp,12
+20000592: 02c5f833 remu a6,a1,a2
+20000596: 8346 mv t1,a7
+20000598: 0885 addi a7,a7,1
+2000059a: 01178f33 add t5,a5,a7
+2000059e: 8eae mv t4,a1
+200005a0: 9872 add a6,a6,t3
+200005a2: 00084803 lbu a6,0(a6)
+200005a6: 02c5d5b3 divu a1,a1,a2
+200005aa: ff0f0fa3 sb a6,-1(t5)
+200005ae: fecef2e3 bgeu t4,a2,20000592 <number+0x198>
+200005b2: b5d1 j 20000476 <number+0x7c>
+200005b4: 16fd addi a3,a3,-1
+200005b6: 02b00293 li t0,43
+200005ba: bd49 j 2000044c <number+0x52>
+200005bc: 03000713 li a4,48
+200005c0: 00e50023 sb a4,0(a0)
+200005c4: 07800713 li a4,120
+200005c8: 00e500a3 sb a4,1(a0)
+200005cc: 0509 addi a0,a0,2
+200005ce: b5fd j 200004bc <number+0xc2>
+200005d0: 16f9 addi a3,a3,-2
+200005d2: b579 j 20000460 <number+0x66>
+200005d4: 03000713 li a4,48
+200005d8: 00e50023 sb a4,0(a0)
+200005dc: 0505 addi a0,a0,1
+200005de: bdf9 j 200004bc <number+0xc2>
+200005e0: 872a mv a4,a0
+200005e2: b715 j 20000506 <number+0x10c>
+200005e4: ffee0713 addi a4,t3,-2
+200005e8: 8e2e mv t3,a1
+200005ea: 85ba mv a1,a4
+200005ec: bd5d j 200004a2 <number+0xa8>
+200005ee: 8e2e mv t3,a1
+200005f0: 15fd addi a1,a1,-1
+200005f2: bdf5 j 200004ee <number+0xf4>
+
+200005f4 <uart_send_char>:
+200005f4: 85aa mv a1,a0
+200005f6: 4501 li a0,0
+200005f8: b375 j 200003a4 <serial_send_byte>
+
+200005fa <ee_printf>:
+200005fa: 7149 addi sp,sp,-368
+200005fc: 13612823 sw s6,304(sp)
+20000600: 14112623 sw ra,332(sp)
+20000604: 14812423 sw s0,328(sp)
+20000608: 14912223 sw s1,324(sp)
+2000060c: 15212023 sw s2,320(sp)
+20000610: 13312e23 sw s3,316(sp)
+20000614: 13412c23 sw s4,312(sp)
+20000618: 13512a23 sw s5,308(sp)
+2000061c: 13712623 sw s7,300(sp)
+20000620: 13812423 sw s8,296(sp)
+20000624: 13912223 sw s9,292(sp)
+20000628: 13a12023 sw s10,288(sp)
+2000062c: 14b12a23 sw a1,340(sp)
+20000630: 14c12c23 sw a2,344(sp)
+20000634: 14d12e23 sw a3,348(sp)
+20000638: 16e12023 sw a4,352(sp)
+2000063c: 16f12223 sw a5,356(sp)
+20000640: 17012423 sw a6,360(sp)
+20000644: 17112623 sw a7,364(sp)
+20000648: 00054783 lbu a5,0(a0)
+2000064c: 15410b13 addi s6,sp,340
+20000650: c25a sw s6,4(sp)
+20000652: 5c078963 beqz a5,20000c24 <ee_printf+0x62a>
+20000656: 02010993 addi s3,sp,32
+2000065a: 832a mv t1,a0
+2000065c: 00000a97 auipc s5,0x0
+20000660: 784a8a93 addi s5,s5,1924 # 20000de0 <uart_ctrl_addr+0x18>
+20000664: 854e mv a0,s3
+20000666: 02e00b93 li s7,46
+2000066a: 00000a17 auipc s4,0x0
+2000066e: 7baa0a13 addi s4,s4,1978 # 20000e24 <uart_ctrl_addr+0x5c>
+20000672: 00001497 auipc s1,0x1
+20000676: 99648493 addi s1,s1,-1642 # 20001008 <uart_ctrl_addr+0x240>
+2000067a: 00001417 auipc s0,0x1
+2000067e: 88a40413 addi s0,s0,-1910 # 20000f04 <uart_ctrl_addr+0x13c>
+20000682: 02500713 li a4,37
+20000686: 06e78463 beq a5,a4,200006ee <ee_printf+0xf4>
+2000068a: 00f50023 sb a5,0(a0)
+2000068e: 00134783 lbu a5,1(t1)
+20000692: 0505 addi a0,a0,1
+20000694: 0305 addi t1,t1,1
+20000696: f7f5 bnez a5,20000682 <ee_printf+0x88>
+20000698: 00050023 sb zero,0(a0)
+2000069c: 02014583 lbu a1,32(sp)
+200006a0: 12058463 beqz a1,200007c8 <ee_printf+0x1ce>
+200006a4: 4405 li s0,1
+200006a6: 41340433 sub s0,s0,s3
+200006aa: 4501 li a0,0
+200006ac: 39e5 jal 200003a4 <serial_send_byte>
+200006ae: 0019c583 lbu a1,1(s3)
+200006b2: 00898533 add a0,s3,s0
+200006b6: 0985 addi s3,s3,1
+200006b8: f9ed bnez a1,200006aa <ee_printf+0xb0>
+200006ba: 14c12083 lw ra,332(sp)
+200006be: 14812403 lw s0,328(sp)
+200006c2: 14412483 lw s1,324(sp)
+200006c6: 14012903 lw s2,320(sp)
+200006ca: 13c12983 lw s3,316(sp)
+200006ce: 13812a03 lw s4,312(sp)
+200006d2: 13412a83 lw s5,308(sp)
+200006d6: 13012b03 lw s6,304(sp)
+200006da: 12c12b83 lw s7,300(sp)
+200006de: 12812c03 lw s8,296(sp)
+200006e2: 12412c83 lw s9,292(sp)
+200006e6: 12012d03 lw s10,288(sp)
+200006ea: 6175 addi sp,sp,368
+200006ec: 8082 ret
+200006ee: 4781 li a5,0
+200006f0: 46c1 li a3,16
+200006f2: 00134583 lbu a1,1(t1)
+200006f6: 00130913 addi s2,t1,1
+200006fa: fe058713 addi a4,a1,-32
+200006fe: 0ff77713 andi a4,a4,255
+20000702: 00e6e763 bltu a3,a4,20000710 <ee_printf+0x116>
+20000706: 070a slli a4,a4,0x2
+20000708: 9756 add a4,a4,s5
+2000070a: 4318 lw a4,0(a4)
+2000070c: 9756 add a4,a4,s5
+2000070e: 8702 jr a4
+20000710: fd058713 addi a4,a1,-48
+20000714: 0ff77713 andi a4,a4,255
+20000718: 46a5 li a3,9
+2000071a: 0ce6fb63 bgeu a3,a4,200007f0 <ee_printf+0x1f6>
+2000071e: 02a00713 li a4,42
+20000722: 56fd li a3,-1
+20000724: 0ee58963 beq a1,a4,20000816 <ee_printf+0x21c>
+20000728: 577d li a4,-1
+2000072a: 0b758163 beq a1,s7,200007cc <ee_printf+0x1d2>
+2000072e: 0df5f613 andi a2,a1,223
+20000732: 04c00813 li a6,76
+20000736: 05060363 beq a2,a6,2000077c <ee_printf+0x182>
+2000073a: fbf58613 addi a2,a1,-65
+2000073e: 0ff67613 andi a2,a2,255
+20000742: 03700813 li a6,55
+20000746: 04c86e63 bltu a6,a2,200007a2 <ee_printf+0x1a8>
+2000074a: 060a slli a2,a2,0x2
+2000074c: 9652 add a2,a2,s4
+2000074e: 4210 lw a2,0(a2)
+20000750: 9652 add a2,a2,s4
+20000752: 8602 jr a2
+20000754: 0017e793 ori a5,a5,1
+20000758: 834a mv t1,s2
+2000075a: bf61 j 200006f2 <ee_printf+0xf8>
+2000075c: 0107e793 ori a5,a5,16
+20000760: 834a mv t1,s2
+20000762: bf41 j 200006f2 <ee_printf+0xf8>
+20000764: 0047e793 ori a5,a5,4
+20000768: 834a mv t1,s2
+2000076a: b761 j 200006f2 <ee_printf+0xf8>
+2000076c: 0207e793 ori a5,a5,32
+20000770: 834a mv t1,s2
+20000772: b741 j 200006f2 <ee_printf+0xf8>
+20000774: 0087e793 ori a5,a5,8
+20000778: 834a mv t1,s2
+2000077a: bfa5 j 200006f2 <ee_printf+0xf8>
+2000077c: 00194803 lbu a6,1(s2)
+20000780: 03700313 li t1,55
+20000784: 00190893 addi a7,s2,1
+20000788: fbf80613 addi a2,a6,-65
+2000078c: 0ff67613 andi a2,a2,255
+20000790: 00c36763 bltu t1,a2,2000079e <ee_printf+0x1a4>
+20000794: 060a slli a2,a2,0x2
+20000796: 9622 add a2,a2,s0
+20000798: 4210 lw a2,0(a2)
+2000079a: 9622 add a2,a2,s0
+2000079c: 8602 jr a2
+2000079e: 85c2 mv a1,a6
+200007a0: 8946 mv s2,a7
+200007a2: 02500713 li a4,37
+200007a6: 00150793 addi a5,a0,1
+200007aa: 42e58963 beq a1,a4,20000bdc <ee_printf+0x5e2>
+200007ae: 00e50023 sb a4,0(a0)
+200007b2: 00094703 lbu a4,0(s2)
+200007b6: 4c071a63 bnez a4,20000c8a <ee_printf+0x690>
+200007ba: 853e mv a0,a5
+200007bc: 00050023 sb zero,0(a0)
+200007c0: 02014583 lbu a1,32(sp)
+200007c4: ee0590e3 bnez a1,200006a4 <ee_printf+0xaa>
+200007c8: 4501 li a0,0
+200007ca: bdc5 j 200006ba <ee_printf+0xc0>
+200007cc: 00194583 lbu a1,1(s2)
+200007d0: 4625 li a2,9
+200007d2: 00190813 addi a6,s2,1
+200007d6: fd058713 addi a4,a1,-48
+200007da: 0ff77713 andi a4,a4,255
+200007de: 3ae67763 bgeu a2,a4,20000b8c <ee_printf+0x592>
+200007e2: 02a00713 li a4,42
+200007e6: 3ce58b63 beq a1,a4,20000bbc <ee_printf+0x5c2>
+200007ea: 8942 mv s2,a6
+200007ec: 4701 li a4,0
+200007ee: b781 j 2000072e <ee_printf+0x134>
+200007f0: 4681 li a3,0
+200007f2: 4625 li a2,9
+200007f4: 00269713 slli a4,a3,0x2
+200007f8: 96ba add a3,a3,a4
+200007fa: 0905 addi s2,s2,1
+200007fc: 0686 slli a3,a3,0x1
+200007fe: 96ae add a3,a3,a1
+20000800: 00094583 lbu a1,0(s2)
+20000804: fd068693 addi a3,a3,-48
+20000808: fd058713 addi a4,a1,-48
+2000080c: 0ff77713 andi a4,a4,255
+20000810: fee672e3 bgeu a2,a4,200007f4 <ee_printf+0x1fa>
+20000814: bf11 j 20000728 <ee_printf+0x12e>
+20000816: 000b2683 lw a3,0(s6)
+2000081a: 00234583 lbu a1,2(t1)
+2000081e: 00230913 addi s2,t1,2
+20000822: 0b11 addi s6,s6,4
+20000824: f006d2e3 bgez a3,20000728 <ee_printf+0x12e>
+20000828: 40d006b3 neg a3,a3
+2000082c: 0107e793 ori a5,a5,16
+20000830: bde5 j 20000728 <ee_printf+0x12e>
+20000832: 004b0813 addi a6,s6,4
+20000836: 4641 li a2,16
+20000838: 000b2583 lw a1,0(s6)
+2000083c: 8b42 mv s6,a6
+2000083e: 3e75 jal 200003fa <number>
+20000840: 00194783 lbu a5,1(s2)
+20000844: 00190313 addi t1,s2,1
+20000848: e2079de3 bnez a5,20000682 <ee_printf+0x88>
+2000084c: b5b1 j 20000698 <ee_printf+0x9e>
+2000084e: 004b0813 addi a6,s6,4
+20000852: 4629 li a2,10
+20000854: b7d5 j 20000838 <ee_printf+0x23e>
+20000856: 8946 mv s2,a7
+20000858: 000b2603 lw a2,0(s6)
+2000085c: 0b11 addi s6,s6,4
+2000085e: 3a060163 beqz a2,20000c00 <ee_printf+0x606>
+20000862: 00064583 lbu a1,0(a2)
+20000866: 3e058b63 beqz a1,20000c5c <ee_printf+0x662>
+2000086a: 3e070963 beqz a4,20000c5c <ee_printf+0x662>
+2000086e: 85b2 mv a1,a2
+20000870: a029 j 2000087a <ee_printf+0x280>
+20000872: 40e58833 sub a6,a1,a4
+20000876: 00c80763 beq a6,a2,20000884 <ee_printf+0x28a>
+2000087a: 0015c803 lbu a6,1(a1)
+2000087e: 0585 addi a1,a1,1
+20000880: fe0819e3 bnez a6,20000872 <ee_printf+0x278>
+20000884: 8bc1 andi a5,a5,16
+20000886: 8d91 sub a1,a1,a2
+20000888: 3a078263 beqz a5,20000c2c <ee_printf+0x632>
+2000088c: 40b05b63 blez a1,20000ca2 <ee_printf+0x6a8>
+20000890: 00b60833 add a6,a2,a1
+20000894: 87aa mv a5,a0
+20000896: 00064703 lbu a4,0(a2)
+2000089a: 0605 addi a2,a2,1
+2000089c: 0785 addi a5,a5,1
+2000089e: fee78fa3 sb a4,-1(a5)
+200008a2: ff061ae3 bne a2,a6,20000896 <ee_printf+0x29c>
+200008a6: 00b50733 add a4,a0,a1
+200008aa: 40b68533 sub a0,a3,a1
+200008ae: 00190313 addi t1,s2,1
+200008b2: 953a add a0,a0,a4
+200008b4: 02000793 li a5,32
+200008b8: 3cd5d163 bge a1,a3,20000c7a <ee_printf+0x680>
+200008bc: 0705 addi a4,a4,1
+200008be: fef70fa3 sb a5,-1(a4)
+200008c2: fea71de3 bne a4,a0,200008bc <ee_printf+0x2c2>
+200008c6: 00194783 lbu a5,1(s2)
+200008ca: da079ce3 bnez a5,20000682 <ee_printf+0x88>
+200008ce: b3e9 j 20000698 <ee_printf+0x9e>
+200008d0: 8946 mv s2,a7
+200008d2: 567d li a2,-1
+200008d4: 32c68263 beq a3,a2,20000bf8 <ee_printf+0x5fe>
+200008d8: 000b2583 lw a1,0(s6)
+200008dc: 4641 li a2,16
+200008de: 0b11 addi s6,s6,4
+200008e0: 3e29 jal 200003fa <number>
+200008e2: 00194783 lbu a5,1(s2)
+200008e6: 00190313 addi t1,s2,1
+200008ea: d8079ce3 bnez a5,20000682 <ee_printf+0x88>
+200008ee: b36d j 20000698 <ee_printf+0x9e>
+200008f0: 004b0813 addi a6,s6,4
+200008f4: 4621 li a2,8
+200008f6: b789 j 20000838 <ee_printf+0x23e>
+200008f8: 0027e793 ori a5,a5,2
+200008fc: 004b0813 addi a6,s6,4
+20000900: 4629 li a2,10
+20000902: bf1d j 20000838 <ee_printf+0x23e>
+20000904: 8946 mv s2,a7
+20000906: 8bc1 andi a5,a5,16
+20000908: 16fd addi a3,a3,-1
+2000090a: 30078063 beqz a5,20000c0a <ee_printf+0x610>
+2000090e: 000b2603 lw a2,0(s6)
+20000912: 00150713 addi a4,a0,1
+20000916: 00168793 addi a5,a3,1
+2000091a: 00c50023 sb a2,0(a0)
+2000091e: 0b11 addi s6,s6,4
+20000920: 953e add a0,a0,a5
+20000922: 00190313 addi t1,s2,1
+20000926: 87ba mv a5,a4
+20000928: 02000613 li a2,32
+2000092c: 34d05763 blez a3,20000c7a <ee_printf+0x680>
+20000930: 0785 addi a5,a5,1
+20000932: fec78fa3 sb a2,-1(a5)
+20000936: fea79de3 bne a5,a0,20000930 <ee_printf+0x336>
+2000093a: 00194783 lbu a5,1(s2)
+2000093e: 00d70533 add a0,a4,a3
+20000942: d40790e3 bnez a5,20000682 <ee_printf+0x88>
+20000946: bb89 j 20000698 <ee_printf+0x9e>
+20000948: 0407e793 ori a5,a5,64
+2000094c: 004b0813 addi a6,s6,4
+20000950: 4641 li a2,16
+20000952: b5dd j 20000838 <ee_printf+0x23e>
+20000954: 000b2703 lw a4,0(s6)
+20000958: 0407e793 ori a5,a5,64
+2000095c: 0b11 addi s6,s6,4
+2000095e: 00074583 lbu a1,0(a4)
+20000962: 4801 li a6,0
+20000964: 00470893 addi a7,a4,4
+20000968: 06300e93 li t4,99
+2000096c: 4fa5 li t6,9
+2000096e: 4329 li t1,10
+20000970: 06400f13 li t5,100
+20000974: 03000e13 li t3,48
+20000978: 00180613 addi a2,a6,1
+2000097c: e19d bnez a1,200009a2 <ee_printf+0x3a8>
+2000097e: 120c addi a1,sp,288
+20000980: 982e add a6,a6,a1
+20000982: efc80423 sb t3,-280(a6)
+20000986: 0705 addi a4,a4,1
+20000988: 07170663 beq a4,a7,200009f4 <ee_printf+0x3fa>
+2000098c: 120c addi a1,sp,288
+2000098e: 95b2 add a1,a1,a2
+20000990: ef758423 sb s7,-280(a1)
+20000994: 00074583 lbu a1,0(a4)
+20000998: 00160813 addi a6,a2,1
+2000099c: 00180613 addi a2,a6,1
+200009a0: ddf9 beqz a1,2000097e <ee_printf+0x384>
+200009a2: 1cbed063 bge t4,a1,20000b62 <ee_printf+0x568>
+200009a6: 03e5ec33 rem s8,a1,t5
+200009aa: 12010293 addi t0,sp,288
+200009ae: 01028d33 add s10,t0,a6
+200009b2: 00c28cb3 add s9,t0,a2
+200009b6: 00280393 addi t2,a6,2
+200009ba: 00380613 addi a2,a6,3
+200009be: 03e5c5b3 div a1,a1,t5
+200009c2: 026c4833 div a6,s8,t1
+200009c6: 00b482b3 add t0,s1,a1
+200009ca: 0002c583 lbu a1,0(t0)
+200009ce: eebd0423 sb a1,-280(s10)
+200009d2: 026c65b3 rem a1,s8,t1
+200009d6: 9826 add a6,a6,s1
+200009d8: 00084803 lbu a6,0(a6)
+200009dc: ef0c8423 sb a6,-280(s9)
+200009e0: 95a6 add a1,a1,s1
+200009e2: 0005c803 lbu a6,0(a1)
+200009e6: 120c addi a1,sp,288
+200009e8: 959e add a1,a1,t2
+200009ea: ef058423 sb a6,-280(a1)
+200009ee: 0705 addi a4,a4,1
+200009f0: f9171ee3 bne a4,a7,2000098c <ee_printf+0x392>
+200009f4: 8bc1 andi a5,a5,16
+200009f6: fff68813 addi a6,a3,-1
+200009fa: e395 bnez a5,20000a1e <ee_printf+0x424>
+200009fc: 40c687b3 sub a5,a3,a2
+20000a00: 97aa add a5,a5,a0
+20000a02: 02000713 li a4,32
+20000a06: 28d65463 bge a2,a3,20000c8e <ee_printf+0x694>
+20000a0a: 0505 addi a0,a0,1
+20000a0c: fee50fa3 sb a4,-1(a0)
+20000a10: fea79de3 bne a5,a0,20000a0a <ee_printf+0x410>
+20000a14: 40d606b3 sub a3,a2,a3
+20000a18: 96c2 add a3,a3,a6
+20000a1a: fff68813 addi a6,a3,-1
+20000a1e: 003c addi a5,sp,8
+20000a20: 00c505b3 add a1,a0,a2
+20000a24: 0007c703 lbu a4,0(a5)
+20000a28: 0505 addi a0,a0,1
+20000a2a: 0785 addi a5,a5,1
+20000a2c: fee50fa3 sb a4,-1(a0)
+20000a30: feb51ae3 bne a0,a1,20000a24 <ee_printf+0x42a>
+20000a34: e0d656e3 bge a2,a3,20000840 <ee_printf+0x246>
+20000a38: 872e mv a4,a1
+20000a3a: 02000513 li a0,32
+20000a3e: 4685 li a3,1
+20000a40: 0705 addi a4,a4,1
+20000a42: 40e687b3 sub a5,a3,a4
+20000a46: 97c2 add a5,a5,a6
+20000a48: 97ae add a5,a5,a1
+20000a4a: fea70fa3 sb a0,-1(a4)
+20000a4e: fef649e3 blt a2,a5,20000a40 <ee_printf+0x446>
+20000a52: 4505 li a0,1
+20000a54: 16c85f63 bge a6,a2,20000bd2 <ee_printf+0x5d8>
+20000a58: 952e add a0,a0,a1
+20000a5a: b3dd j 20000840 <ee_printf+0x246>
+20000a5c: 0027e793 ori a5,a5,2
+20000a60: 4629 li a2,10
+20000a62: 06c00313 li t1,108
+20000a66: 004b0813 addi a6,s6,4
+20000a6a: 20659e63 bne a1,t1,20000c86 <ee_printf+0x68c>
+20000a6e: 000b2583 lw a1,0(s6)
+20000a72: 8946 mv s2,a7
+20000a74: 8b42 mv s6,a6
+20000a76: b3e1 j 2000083e <ee_printf+0x244>
+20000a78: 4621 li a2,8
+20000a7a: b7e5 j 20000a62 <ee_printf+0x468>
+20000a7c: 0407e793 ori a5,a5,64
+20000a80: 4641 li a2,16
+20000a82: b7c5 j 20000a62 <ee_printf+0x468>
+20000a84: 0407e793 ori a5,a5,64
+20000a88: 06c00613 li a2,108
+20000a8c: 000b2703 lw a4,0(s6)
+20000a90: 0b11 addi s6,s6,4
+20000a92: 1ac59f63 bne a1,a2,20000c50 <ee_printf+0x656>
+20000a96: 0407f613 andi a2,a5,64
+20000a9a: 88a6 mv a7,s1
+20000a9c: c609 beqz a2,20000aa6 <ee_printf+0x4ac>
+20000a9e: 00000897 auipc a7,0x0
+20000aa2: 59288893 addi a7,a7,1426 # 20001030 <uart_ctrl_addr+0x268>
+20000aa6: 00810313 addi t1,sp,8
+20000aaa: 01a10e13 addi t3,sp,26
+20000aae: 859a mv a1,t1
+20000ab0: 03a00e93 li t4,58
+20000ab4: a019 j 20000aba <ee_printf+0x4c0>
+20000ab6: ffd58fa3 sb t4,-1(a1)
+20000aba: 00074603 lbu a2,0(a4)
+20000abe: 058d addi a1,a1,3
+20000ac0: 0705 addi a4,a4,1
+20000ac2: 00465813 srli a6,a2,0x4
+20000ac6: 8a3d andi a2,a2,15
+20000ac8: 9846 add a6,a6,a7
+20000aca: 9646 add a2,a2,a7
+20000acc: 00084803 lbu a6,0(a6)
+20000ad0: 00064603 lbu a2,0(a2)
+20000ad4: ff058ea3 sb a6,-3(a1)
+20000ad8: fec58f23 sb a2,-2(a1)
+20000adc: fdc59de3 bne a1,t3,20000ab6 <ee_printf+0x4bc>
+20000ae0: 8bc1 andi a5,a5,16
+20000ae2: fff68613 addi a2,a3,-1
+20000ae6: e39d bnez a5,20000b0c <ee_printf+0x512>
+20000ae8: fef68593 addi a1,a3,-17
+20000aec: 4845 li a6,17
+20000aee: 00b50733 add a4,a0,a1
+20000af2: 02000793 li a5,32
+20000af6: 1ad85163 bge a6,a3,20000c98 <ee_printf+0x69e>
+20000afa: 0505 addi a0,a0,1
+20000afc: fef50fa3 sb a5,-1(a0)
+20000b00: fee51de3 bne a0,a4,20000afa <ee_printf+0x500>
+20000b04: 40b606b3 sub a3,a2,a1
+20000b08: fff68613 addi a2,a3,-1
+20000b0c: 87aa mv a5,a0
+20000b0e: 01130593 addi a1,t1,17
+20000b12: 00034703 lbu a4,0(t1)
+20000b16: 0305 addi t1,t1,1
+20000b18: 0785 addi a5,a5,1
+20000b1a: fee78fa3 sb a4,-1(a5)
+20000b1e: feb31ae3 bne t1,a1,20000b12 <ee_printf+0x518>
+20000b22: 47c5 li a5,17
+20000b24: 0545 addi a0,a0,17
+20000b26: 02d7d763 bge a5,a3,20000b54 <ee_printf+0x55a>
+20000b2a: 872a mv a4,a0
+20000b2c: 02000813 li a6,32
+20000b30: 4585 li a1,1
+20000b32: 46c5 li a3,17
+20000b34: 0705 addi a4,a4,1
+20000b36: 40e587b3 sub a5,a1,a4
+20000b3a: 97b2 add a5,a5,a2
+20000b3c: 97aa add a5,a5,a0
+20000b3e: ff070fa3 sb a6,-1(a4)
+20000b42: fef6c9e3 blt a3,a5,20000b34 <ee_printf+0x53a>
+20000b46: 4741 li a4,16
+20000b48: 4785 li a5,1
+20000b4a: 00c75463 bge a4,a2,20000b52 <ee_printf+0x558>
+20000b4e: ff060793 addi a5,a2,-16
+20000b52: 953e add a0,a0,a5
+20000b54: 00294783 lbu a5,2(s2)
+20000b58: 00290313 addi t1,s2,2
+20000b5c: b20793e3 bnez a5,20000682 <ee_printf+0x88>
+20000b60: be25 j 20000698 <ee_printf+0x9e>
+20000b62: 83c2 mv t2,a6
+20000b64: e6bfdee3 bge t6,a1,200009e0 <ee_printf+0x3e6>
+20000b68: 0265c2b3 div t0,a1,t1
+20000b6c: 12010393 addi t2,sp,288
+20000b70: 01038c33 add s8,t2,a6
+20000b74: 83b2 mv t2,a2
+20000b76: 00280613 addi a2,a6,2
+20000b7a: 00548833 add a6,s1,t0
+20000b7e: 00084803 lbu a6,0(a6)
+20000b82: 0265e5b3 rem a1,a1,t1
+20000b86: ef0c0423 sb a6,-280(s8)
+20000b8a: bd99 j 200009e0 <ee_printf+0x3e6>
+20000b8c: 4701 li a4,0
+20000b8e: 48a5 li a7,9
+20000b90: 00271613 slli a2,a4,0x2
+20000b94: 9732 add a4,a4,a2
+20000b96: 0805 addi a6,a6,1
+20000b98: 0706 slli a4,a4,0x1
+20000b9a: 972e add a4,a4,a1
+20000b9c: 00084583 lbu a1,0(a6)
+20000ba0: fd070713 addi a4,a4,-48
+20000ba4: fd058613 addi a2,a1,-48
+20000ba8: 0ff67613 andi a2,a2,255
+20000bac: fec8f2e3 bgeu a7,a2,20000b90 <ee_printf+0x596>
+20000bb0: 8942 mv s2,a6
+20000bb2: beb5 j 2000072e <ee_printf+0x134>
+20000bb4: 000b2703 lw a4,0(s6)
+20000bb8: 0b11 addi s6,s6,4
+20000bba: b355 j 2000095e <ee_printf+0x364>
+20000bbc: 000b2703 lw a4,0(s6)
+20000bc0: 00294583 lbu a1,2(s2)
+20000bc4: 0b11 addi s6,s6,4
+20000bc6: fff74613 not a2,a4
+20000bca: 867d srai a2,a2,0x1f
+20000bcc: 8f71 and a4,a4,a2
+20000bce: 0909 addi s2,s2,2
+20000bd0: beb9 j 2000072e <ee_printf+0x134>
+20000bd2: 8e91 sub a3,a3,a2
+20000bd4: 01068533 add a0,a3,a6
+20000bd8: 952e add a0,a0,a1
+20000bda: b19d j 20000840 <ee_printf+0x246>
+20000bdc: 00094703 lbu a4,0(s2)
+20000be0: 86be mv a3,a5
+20000be2: 87aa mv a5,a0
+20000be4: 8536 mv a0,a3
+20000be6: 00e78023 sb a4,0(a5)
+20000bea: 00194783 lbu a5,1(s2)
+20000bee: 00190313 addi t1,s2,1
+20000bf2: a80798e3 bnez a5,20000682 <ee_printf+0x88>
+20000bf6: b44d j 20000698 <ee_printf+0x9e>
+20000bf8: 0017e793 ori a5,a5,1
+20000bfc: 46a1 li a3,8
+20000bfe: b9e9 j 200008d8 <ee_printf+0x2de>
+20000c00: 00000617 auipc a2,0x0
+20000c04: 45860613 addi a2,a2,1112 # 20001058 <uart_ctrl_addr+0x290>
+20000c08: b18d j 2000086a <ee_printf+0x270>
+20000c0a: 00d50733 add a4,a0,a3
+20000c0e: 02000793 li a5,32
+20000c12: 04d05b63 blez a3,20000c68 <ee_printf+0x66e>
+20000c16: 0505 addi a0,a0,1
+20000c18: fef50fa3 sb a5,-1(a0)
+20000c1c: fee51de3 bne a0,a4,20000c16 <ee_printf+0x61c>
+20000c20: 56fd li a3,-1
+20000c22: b1f5 j 2000090e <ee_printf+0x314>
+20000c24: 02010993 addi s3,sp,32
+20000c28: 854e mv a0,s3
+20000c2a: b4bd j 20000698 <ee_printf+0x9e>
+20000c2c: fff68813 addi a6,a3,-1
+20000c30: 08d5d263 bge a1,a3,20000cb4 <ee_printf+0x6ba>
+20000c34: 40b687b3 sub a5,a3,a1
+20000c38: 97aa add a5,a5,a0
+20000c3a: 02000713 li a4,32
+20000c3e: 0505 addi a0,a0,1
+20000c40: fee50fa3 sb a4,-1(a0)
+20000c44: fef51de3 bne a0,a5,20000c3e <ee_printf+0x644>
+20000c48: 40d586b3 sub a3,a1,a3
+20000c4c: 96c2 add a3,a3,a6
+20000c4e: b93d j 2000088c <ee_printf+0x292>
+20000c50: 8946 mv s2,a7
+20000c52: b331 j 2000095e <ee_printf+0x364>
+20000c54: 4641 li a2,16
+20000c56: b531 j 20000a62 <ee_printf+0x468>
+20000c58: 4629 li a2,10
+20000c5a: b521 j 20000a62 <ee_printf+0x468>
+20000c5c: 0107f593 andi a1,a5,16
+20000c60: c1b9 beqz a1,20000ca6 <ee_printf+0x6ac>
+20000c62: 872a mv a4,a0
+20000c64: 4581 li a1,0
+20000c66: b191 j 200008aa <ee_printf+0x2b0>
+20000c68: 000b2783 lw a5,0(s6)
+20000c6c: 00150713 addi a4,a0,1
+20000c70: 0b11 addi s6,s6,4
+20000c72: 00f50023 sb a5,0(a0)
+20000c76: 00190313 addi t1,s2,1
+20000c7a: 00194783 lbu a5,1(s2)
+20000c7e: 853a mv a0,a4
+20000c80: a00791e3 bnez a5,20000682 <ee_printf+0x88>
+20000c84: bc11 j 20000698 <ee_printf+0x9e>
+20000c86: 8946 mv s2,a7
+20000c88: be45 j 20000838 <ee_printf+0x23e>
+20000c8a: 0509 addi a0,a0,2
+20000c8c: bfa9 j 20000be6 <ee_printf+0x5ec>
+20000c8e: ffe68793 addi a5,a3,-2
+20000c92: 86c2 mv a3,a6
+20000c94: 883e mv a6,a5
+20000c96: b361 j 20000a1e <ee_printf+0x424>
+20000c98: ffe68793 addi a5,a3,-2
+20000c9c: 86b2 mv a3,a2
+20000c9e: 863e mv a2,a5
+20000ca0: b5b5 j 20000b0c <ee_printf+0x512>
+20000ca2: 872a mv a4,a0
+20000ca4: b119 j 200008aa <ee_printf+0x2b0>
+20000ca6: fff68813 addi a6,a3,-1
+20000caa: f8d045e3 bgtz a3,20000c34 <ee_printf+0x63a>
+20000cae: 86c2 mv a3,a6
+20000cb0: 872a mv a4,a0
+20000cb2: bee5 j 200008aa <ee_printf+0x2b0>
+20000cb4: 86c2 mv a3,a6
+20000cb6: bed9 j 2000088c <ee_printf+0x292>
+
+Disassembly of section .text.startup:
+
+20000cb8 <main>:
+20000cb8: e7fff517 auipc a0,0xe7fff
+20000cbc: 34850513 addi a0,a0,840 # 8000000 <spi_quad_mode>
+20000cc0: e7fff617 auipc a2,0xe7fff
+20000cc4: 3b460613 addi a2,a2,948 # 8000074 <itim_end>
+20000cc8: 1141 addi sp,sp,-16
+20000cca: 8e09 sub a2,a2,a0
+20000ccc: 00000597 auipc a1,0x0
+20000cd0: 08858593 addi a1,a1,136 # 20000d54 <itim_load_start>
+20000cd4: c606 sw ra,12(sp)
+20000cd6: c3cff0ef jal ra,20000112 <memcpy>
+20000cda: 1ffff517 auipc a0,0x1ffff
+20000cde: 32650513 addi a0,a0,806 # 40000000 <_end>
+20000ce2: 1ffff617 auipc a2,0x1ffff
+20000ce6: 31e60613 addi a2,a2,798 # 40000000 <_end>
+20000cea: 8e09 sub a2,a2,a0
+20000cec: 00000597 auipc a1,0x0
+20000cf0: 37458593 addi a1,a1,884 # 20001060 <erodata>
+20000cf4: c1eff0ef jal ra,20000112 <memcpy>
+20000cf8: 1ffff517 auipc a0,0x1ffff
+20000cfc: 30850513 addi a0,a0,776 # 40000000 <_end>
+20000d00: 1ffff617 auipc a2,0x1ffff
+20000d04: 30060613 addi a2,a2,768 # 40000000 <_end>
+20000d08: 8e09 sub a2,a2,a0
+20000d0a: 4581 li a1,0
+20000d0c: becff0ef jal ra,200000f8 <memset>
+20000d10: 10014537 lui a0,0x10014
+20000d14: e7fff097 auipc ra,0xe7fff
+20000d18: 2ec080e7 jalr 748(ra) # 8000000 <spi_quad_mode>
+20000d1c: 4585 li a1,1
+20000d1e: 4501 li a0,0
+20000d20: e3aff0ef jal ra,2000035a <serial_init>
+20000d24: 00000517 auipc a0,0x0
+20000d28: 2c050513 addi a0,a0,704 # 20000fe4 <uart_ctrl_addr+0x21c>
+20000d2c: d26ff0ef jal ra,20000252 <puts>
+20000d30: 100127b7 lui a5,0x10012
+20000d34: 5f98 lw a4,56(a5)
+20000d36: c00006b7 lui a3,0xc0000
+20000d3a: 40b2 lw ra,12(sp)
+20000d3c: 070a slli a4,a4,0x2
+20000d3e: 8309 srli a4,a4,0x2
+20000d40: df98 sw a4,56(a5)
+20000d42: 4798 lw a4,8(a5)
+20000d44: 4501 li a0,0
+20000d46: 8f55 or a4,a4,a3
+20000d48: c798 sw a4,8(a5)
+20000d4a: 80000737 lui a4,0x80000
+20000d4e: c7d8 sw a4,12(a5)
+20000d50: 0141 addi sp,sp,16
+20000d52: 8082 ret
+
+Disassembly of section .text_itim:
+
+08000000 <spi_quad_mode>:
+ 8000000: 1141 addi sp,sp,-16
+ 8000002: 0ff0000f fence
+ 8000006: 0000100f fence.i
+ 800000a: 4114 lw a3,0(a0)
+ 800000c: 4705 li a4,1
+ 800000e: 4785 li a5,1
+ 8000010: 00e68663 beq a3,a4,800001c <spi_quad_mode+0x1c>
+ 8000014: c11c sw a5,0(a0)
+ 8000016: 4118 lw a4,0(a0)
+ 8000018: fef71ee3 bne a4,a5,8000014 <spi_quad_mode+0x14>
+ 800001c: 5138 lw a4,96(a0)
+ 800001e: 06050793 addi a5,a0,96
+ 8000022: c709 beqz a4,800002c <spi_quad_mode+0x2c>
+ 8000024: 0007a023 sw zero,0(a5) # 10012000 <_stack+0x8010010>
+ 8000028: 4398 lw a4,0(a5)
+ 800002a: ff6d bnez a4,8000024 <spi_quad_mode+0x24>
+ 800002c: 04850693 addi a3,a0,72
+ 8000030: 4298 lw a4,0(a3)
+ 8000032: fe074fe3 bltz a4,8000030 <spi_quad_mode+0x30>
+ 8000036: 03500713 li a4,53
+ 800003a: c538 sw a4,72(a0)
+ 800003c: 000b3737 lui a4,0xb3
+ 8000040: a4770713 addi a4,a4,-1465 # b2a47 <spi_quad_mode-0x7f4d5b9>
+ 8000044: c63a sw a4,12(sp)
+ 8000046: 5174 lw a3,100(a0)
+ 8000048: 4632 lw a2,12(sp)
+ 800004a: 06450713 addi a4,a0,100
+ 800004e: 00d60863 beq a2,a3,800005e <spi_quad_mode+0x5e>
+ 8000052: 46b2 lw a3,12(sp)
+ 8000054: c314 sw a3,0(a4)
+ 8000056: 4310 lw a2,0(a4)
+ 8000058: 46b2 lw a3,12(sp)
+ 800005a: fed61ce3 bne a2,a3,8000052 <spi_quad_mode+0x52>
+ 800005e: 5130 lw a2,96(a0)
+ 8000060: 4685 li a3,1
+ 8000062: 4705 li a4,1
+ 8000064: 00d60663 beq a2,a3,8000070 <spi_quad_mode+0x70>
+ 8000068: c398 sw a4,0(a5)
+ 800006a: 4394 lw a3,0(a5)
+ 800006c: fee69ee3 bne a3,a4,8000068 <spi_quad_mode+0x68>
+ 8000070: 0141 addi sp,sp,16
+ 8000072: 8082 ret
diff --git a/verilog/dv/jtag/spi_flash.mem b/verilog/dv/jtag/spi_flash.mem
new file mode 100644
index 0000000..3a53bd0
--- /dev/null
+++ b/verilog/dv/jtag/spi_flash.mem
@@ -0,0 +1,4458 @@
+// /home/shc/Development/RISC-V/chipyard/vlsi/sim/testcase/jtag/spi_flash.mem
+// spi_flash.srec
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diff --git a/verilog/dv/jtag/stm.v b/verilog/dv/jtag/stm.v
new file mode 100644
index 0000000..51c3238
--- /dev/null
+++ b/verilog/dv/jtag/stm.v
@@ -0,0 +1,104 @@
+ localparam IR_IDCODE = 5'b00001;
+ localparam IR_DTMCS = 5'b10000;
+ localparam IR_DMI = 5'b10001;
+
+ localparam DM_DMCONTROL = 7'h10;
+ localparam DM_DMSTATUS = 7'h11;
+
+ localparam IDCODE_EX = 32'h20000913;
+ localparam DTMCS_EX = 32'h00005071;
+
+ reg [4:0] ir_o;
+ reg [63:0] dr_i;
+ reg [63:0] dr_o;
+ reg [6:0] abits;
+
+ initial begin
+ jtag_driver.stop();
+ while (`CORE.reset === 1'b1) begin
+ jtag_driver.test_logic_reset();
+ end
+ jtag_driver.stop();
+ jtag_driver.run_test_idle();
+
+ // IDCODE
+ jtag_driver.shift_ir(IR_IDCODE, ir_o);
+ jtag_driver.shift_dr(32, 0, dr_o);
+ $display("[%t] IDCODE = 0x%08x", $time, dr_o[31:0]);
+ $display(" Version = 0x%x", dr_o[31:28]);
+ $display(" PartNumber = 0x%04x", dr_o[27:12]);
+ $display(" ManufId = 0x%03x", dr_o[11:1]);
+/*
+ if (dr_o !== IDCODE_EX) begin
+ $display("[%t] Error: IDCODE 0x%08x != 0x%08x", $time, dr_o[31:0], IDCODE_EX);
+ $display("\n*** Test Fail ***");
+ repeat (100) @(posedge clock);
+ $finish;
+ end
+*/
+
+ // DTMCS
+ jtag_driver.shift_ir(IR_DTMCS, ir_o);
+ jtag_driver.shift_dr(32, 0, dr_o);
+ $display("[%t] DTMCS = 0x%08x", $time, dr_o[31:0]);
+ $display(" dmihardreset = 0b%b", dr_o[17]);
+ $display(" dmireset = 0b%b", dr_o[16]);
+ $display(" idle = 0x%x", dr_o[14:12]);
+ $display(" dmistat = 0x%x", dr_o[11:10]);
+ $display(" abits = 0x%02x", dr_o[9:4]);
+ $display(" version = 0x%x", dr_o[3:0]);
+ abits = dr_o[9:4];
+
+ if (dr_o !== DTMCS_EX) begin
+ $display("[%t] Error: DTMCS 0x%08x != 0x%08x", $time, dr_o[31:0], DTMCS_EX);
+ $display("\n*** Test Fail ***");
+ repeat (100) @(posedge clock);
+ $finish;
+ end
+
+ // Activate Debug Module(?)
+ dr_i = DM_DMCONTROL << 34 | (1 << 0) << 2 | 2; // DMCONTROL.dmactive = 1
+ jtag_driver.shift_ir(IR_DMI, ir_o);
+ jtag_driver.shift_dr(abits+34, dr_i, dr_o);
+
+ // Halt CPU
+ $display("[%t] Halt CPU", $time);
+ dr_i = DM_DMCONTROL << 34 | (1 << 31) << 2 | 2; // DMCONTROL.haltreq = 1
+ jtag_driver.shift_ir(IR_DMI, ir_o);
+ jtag_driver.shift_dr(abits+34, dr_i, dr_o);
+/*
+ // Wait until CPU halts
+ dr_i = DM_DMSTATUS << 34 | 1;
+ dr_o = 0;
+ while (dr_o[9+2] !== 1'b1) begin // DMSTATUS.allhalted == 1 ?
+ jtag_driver.shift_ir(IR_DMI, ir_o);
+ jtag_driver.shift_dr(abits+34, dr_i, dr_o);
+ end
+
+ $display("[%t] CPU halted", $time);
+ dr_i = DM_DMCONTROL << 34 | (0 << 31) << 2 | 2; // DMCONTROL.haltreq = 0
+ jtag_driver.shift_ir(IR_DMI, ir_o);
+ jtag_driver.shift_dr(abits+34, dr_i, dr_o);
+*/
+ // Resume CPU
+ $display("[%t] Resume CPU", $time);
+ dr_i = DM_DMCONTROL << 34 | (1 << 30) << 2 | 2; // DMCONTROL.resumereq = 1
+ jtag_driver.shift_ir(IR_DMI, ir_o);
+ jtag_driver.shift_dr(abits+34, dr_i, dr_o);
+
+ // Wait until CPU resumes
+ dr_i = DM_DMSTATUS << 34 | 1;
+ dr_o = 0;
+ while (dr_o[9+2] !== 1'b0) begin // DMSTATUS.allhalted == 0 ?
+ jtag_driver.shift_ir(IR_DMI, ir_o);
+ jtag_driver.shift_dr(abits+34, dr_i, dr_o);
+ end
+ $display("[%t] CPU resumed", $time);
+
+ jtag_driver.stop();
+
+ $display("\n*** Test Pass ***");
+ repeat (100) @(posedge clock);
+ $finish;
+ end
+
diff --git a/verilog/dv/jtag/wave.do b/verilog/dv/jtag/wave.do
new file mode 100644
index 0000000..aecbd98
--- /dev/null
+++ b/verilog/dv/jtag/wave.do
@@ -0,0 +1,92 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -expand -group CPU -radix decimal /testbench/cycle
+add wave -noupdate -expand -group CPU -expand -group coreMonitor /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc
+add wave -noupdate -expand -group CPU -expand -group coreMonitor /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst
+add wave -noupdate -expand -group CPU -expand -group coreMonitor /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_valid
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_valid
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_ready
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_bits_cmd
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_bits_addr
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_req_bits_size
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_valid
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_data
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_data_word_bypass
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_has_data
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_resp_bits_tag
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_s1_data_data
+add wave -noupdate -expand -group CPU -group io_dmem_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/core/io_dmem_s1_kill
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_valid
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_ready
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_opcode
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_size
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_param
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_address
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_corrupt
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_mask
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_data
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_a_bits_source
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_valid
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_ready
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_opcode
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_size
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_source
+add wave -noupdate -expand -group CPU -group auto_slave_in_ /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/tile_prci_domain/tile_reset_domain/tile/auto_slave_in_d_bits_data
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_valid
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_ready
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_opcode
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_param
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_address
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_corrupt
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_data
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_mask
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_size
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_a_bits_source
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_valid
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_ready
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_opcode
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_data
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_size
+add wave -noupdate -group SPI-PSRAM -expand -group qspi_ram /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/qspiClockDomainWrapper_1/qspi_ram_0/auto_mem_xing_in_d_bits_source
+add wave -noupdate -group SPI-PSRAM /testbench/spi_ram/SCK_i
+add wave -noupdate -group SPI-PSRAM /testbench/spi_ram/nCE_i
+add wave -noupdate -group SPI-PSRAM /testbench/spi_ram/NC_io
+add wave -noupdate -group SPI-PSRAM /testbench/spi_ram/nWP_io
+add wave -noupdate -group SPI-PSRAM /testbench/spi_ram/SI_io
+add wave -noupdate -group SPI-PSRAM /testbench/spi_ram/SO_io
+add wave -noupdate /testbench/uut/mprj/Marmot/io_oeb
+add wave -noupdate -group SPI-Flash /testbench/spi_flash/SCLK
+add wave -noupdate -group SPI-Flash /testbench/spi_flash/CS
+add wave -noupdate -group SPI-Flash /testbench/spi_flash/SI
+add wave -noupdate -group SPI-Flash /testbench/spi_flash/SO
+add wave -noupdate -group SPI-Flash /testbench/spi_flash/WP
+add wave -noupdate -group SPI-Flash /testbench/spi_flash/SIO3
+add wave -noupdate -expand -group JTAG /testbench/jtag_driver/tck
+add wave -noupdate -expand -group JTAG /testbench/jtag_driver/tms
+add wave -noupdate -expand -group JTAG /testbench/jtag_driver/tdi
+add wave -noupdate -expand -group JTAG /testbench/jtag_driver/tdo
+add wave -noupdate -expand -group DTM /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/dtm/io_jtag_reset
+add wave -noupdate -expand -group DTM /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/dtm/io_jtag_clock
+add wave -noupdate -expand -group DTM /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/dtm/io_jtag_TMS
+add wave -noupdate -expand -group DTM /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/dtm/io_jtag_TDI
+add wave -noupdate -expand -group DTM /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/dtm/io_jtag_TDO_data
+add wave -noupdate -expand -group DTM /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/dtm/io_jtag_TDO_driven
+add wave -noupdate -expand -group DTM /testbench/uut/mprj/Marmot/MarmotCaravelChip/dut/sys/dtm/tapIO_controllerInternal/stateMachine/currState
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1800344536 ps} 0} {{Cursor 2} {21100900000 ps} 0} {Trace {1784828183 ps} 0}
+quietly wave cursor active 3
+configure wave -namecolwidth 312
+configure wave -valuecolwidth 142
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1740692781 ps} {1859819309 ps}
diff --git a/verilog/dv/vip/jtag_driver.v b/verilog/dv/vip/jtag_driver.v
new file mode 100644
index 0000000..72ab65b
--- /dev/null
+++ b/verilog/dv/vip/jtag_driver.v
@@ -0,0 +1,116 @@
+`timescale 1ns/10ps
+
+module jtag_driver (
+ output reg tck,
+ output reg tms,
+ output reg tdi,
+ input wire tdo
+);
+
+ parameter TCK_PERIOD = 250;
+ parameter IR_LEN = 5;
+
+ // TCK free run
+ reg tck_free;
+ initial begin
+ tck_free = 1'b0;
+ forever #(TCK_PERIOD/2) tck_free = ~tck_free;
+ end
+
+ initial begin
+ tck = 1'b0;
+ tms = 1'b0;
+ tdi = 1'b0;
+ end
+
+ // Drive TMS and TDI
+ task drive;
+ input tms_i;
+ input tdi_i;
+ output reg tdo_o;
+ begin
+ @(negedge tck_free);
+ tck = 1'b0;
+ tms = tms_i;
+ tdi = tdi_i;
+ @(posedge tck_free);
+ tdo_o = tdo;
+ tck = 1'b1;
+ end
+ endtask
+
+ // Set TCK, TMS and TDI to 0
+ task stop;
+ begin
+ @(negedge tck_free);
+ tck = 1'b0;
+ tms = 1'b0;
+ tdi = 1'b0;
+ end
+ endtask
+
+ // Test-Loggic-Reset
+ task test_logic_reset;
+ reg tdo_o;
+ begin
+ repeat (6) drive(1,0,tdo_o);
+ end
+ endtask
+
+ // Run-Test-Idle
+ task run_test_idle;
+ reg tdo_o;
+ begin
+ test_logic_reset();
+ drive(0,0,tdo_o);
+ end
+ endtask
+
+ // Shift-IR (must be in Run-Teset/Idle state before calling this task)
+ task shift_ir;
+ input [IR_LEN-1:0] ir_i;
+ output reg [IR_LEN-1:0] ir_o;
+ reg tdo_o;
+ integer i;
+ begin
+ ir_o = 0;
+ drive(0,0,tdo_o); // Run-Test-Idle -> Run-Test-Idle
+ drive(1,0,tdo_o); // Run-Test-Idle -> Slect-DR-Scan
+ drive(1,0,tdo_o); // Select-DR-Scan -> Select-IR-Scan
+ drive(0,0,tdo_o); // Select-IR-Scan -> Capture-IR
+ drive(0,0,tdo_o); // Capture-IR -> Shift-IR
+ for (i = 0; i < IR_LEN-1; i = i + 1) begin
+ drive(0,ir_i[i],ir_o[i]); // Shift-IR -> Shift-IR
+ end
+ drive(1,ir_i[IR_LEN-1],ir_o[IR_LEN-1]); // Shift-IR -> Exit1-IR
+ drive(1,0,tdo_o); // Exit1-IR -> Update-IR
+ drive(0,0,tdo_o); // Update-IR -> Run-Test-Idle
+ stop(); // Run-Test-Idle
+ end
+ endtask
+
+ // Shift-DR (must be in Run-Teset/Idle state before calling this task)
+ task shift_dr;
+ input [5:0] dr_len;
+ input [63:0] dr_i;
+ output reg [63:0] dr_o;
+ reg tdo_o;
+ integer i;
+ begin
+ dr_o = 0;
+ drive(0,0,tdo_o); // Run-Test-Idle -> Run-Test-Idle
+ drive(1,0,tdo_o); // Run-Test-Idle -> Slect-DR-Scan
+ drive(0,0,tdo_o); // Select-DR-Scan -> Capture-DR
+ drive(0,0,tdo_o); // Capture-DR -> Shift-DR
+ for (i = 0; i < dr_len-1; i = i + 1) begin
+ drive(0,dr_i[i],dr_o[i]); // Shift-DR -> Shift-DR
+ end
+ drive(1,dr_i[dr_len-1],dr_o[dr_len-1]); // Shift-DR -> Exit1-DR
+ drive(1,0,tdo_o); // Exit1-DR -> Update-DR
+ drive(0,0,tdo_o); // Update-DR -> Run-Test-Idle
+ stop(); // Run-Test-Idle
+ end
+ endtask
+
+endmodule
+
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
index 1d68ec8..0d0e9f5 100644
--- a/verilog/includes/includes.gl+sdf.caravel_user_project
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -19,3 +19,5 @@
+incdir+$(USER_PROJECT_VERILOG)/dv/vip/uart
-v $(USER_PROJECT_VERILOG)/dv/vip/uart/uart_tb.v
+// JTAG driver
+-v $(USER_PROJECT_VERILOG)/dv/vip/jtag_driver.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 1d68ec8..0d0e9f5 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -19,3 +19,5 @@
+incdir+$(USER_PROJECT_VERILOG)/dv/vip/uart
-v $(USER_PROJECT_VERILOG)/dv/vip/uart/uart_tb.v
+// JTAG driver
+-v $(USER_PROJECT_VERILOG)/dv/vip/jtag_driver.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 35579a5..642241b 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -26,3 +26,5 @@
+incdir+$(USER_PROJECT_VERILOG)/dv/vip/uart
-v $(USER_PROJECT_VERILOG)/dv/vip/uart/uart_tb.v
+// JTAG driver
+-v $(USER_PROJECT_VERILOG)/dv/vip/jtag_driver.v
