Delete unused power and ground pins
diff --git a/verilog/rtl/marmot/Marmot.v b/verilog/rtl/marmot/Marmot.v
index fb76137..89c5ae0 100644
--- a/verilog/rtl/marmot/Marmot.v
+++ b/verilog/rtl/marmot/Marmot.v
@@ -18,14 +18,8 @@
module Marmot
(
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5705dd9..8cc0c6c 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -145,14 +145,8 @@
Marmot Marmot (
`ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V supply
- .vdda2(vdda2), // User area 2 3.3V supply
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
.vccd1(vccd1), // User area 1 1.8V supply
- .vccd2(vccd2), // User area 2 1.8v supply
.vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
`endif
// Clock and Reset
.wb_clk_i(wb_clk_i),
