modify config
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 4588029..b69b673 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -50,12 +50,12 @@ #set ::env(VDD_NETS) [list {vccd1}] #set ::env(GND_NETS) [list {vssd1}] -#set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} -#set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2} -#set ::env(VDD_NET) {vccd1} -#set ::env(VDD_PIN) {vccd1} -#set ::env(GND_NET) {vssd1} -#set ::env(GND_PIN) {vssd1} +set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} +set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2} +set ::env(VDD_NET) {vccd1} +set ::env(VDD_PIN) {vccd1} +set ::env(GND_NET) {vssd1} +set ::env(GND_PIN) {vssd1} set ::env(FP_PDN_ENABLE_MACROS_GRID) "1" #set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1" ### Macro Placement @@ -74,8 +74,13 @@ set ::env(CELL_PAD) {4} #set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {60} set ::env(ROUTING_CORES) {8} + set ::env(GLB_RT_OVERFLOW_ITERS) {50} -set ::env(GLB_RT_ALLOW_CONGESTION) 1 +# for newer openlanes +#set ::env(GRT_OVERFLOW_ITERS) {50} +set ::env(GLB_RT_ALLOW_CONGESTION) 1 +# for newer openlanes +#set ::env(GRT_ALLOW_CONGESTION) 1 ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ @@ -124,7 +129,7 @@ $script_dir/../../gds/axi_node_intf_wrap.gds" -# set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} # disable pdn check nodes becuase it hangs with multiple power domains.
diff --git a/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl index 71fe572..bc7343d 100644 --- a/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl +++ b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
@@ -16,8 +16,8 @@ # THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED # PDN Pitch -#set ::env(FP_PDN_VPITCH) 180 -set ::env(FP_PDN_VPITCH) 50 +set ::env(FP_PDN_VPITCH) 180 +#set ::env(FP_PDN_VPITCH) 50 set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH) # PDN Offset
diff --git a/verilog/rtl/rtl/clk_rst_gen.v b/verilog/rtl/rtl/clk_rst_gen.v index c19e804..cfb8383 100644 --- a/verilog/rtl/rtl/clk_rst_gen.v +++ b/verilog/rtl/rtl/clk_rst_gen.v
@@ -21,7 +21,15 @@ fll_r_data_o, fll_lock_o, clk_o, - rstn_o + rstn_o, +// MBA START +// constant assignments +io_oeb, +io_out, +wbs_ack_o, +wbs_dat_o, +la_data_out +// MBA END ); `ifdef USE_POWER_PINS inout wire vccd1; @@ -44,11 +52,25 @@ output wire fll_lock_o; output wire clk_o; output wire rstn_o; +// MBA START + output wire [37:0] io_oeb; + output wire [26:0] io_out; + output wire wbs_ack_o; + output wire [31:0] wbs_dat_o; + output wire [63:0] la_data_out; +// MBA END wire clk_fll_int; wire clk_int; // MBA START wire rstn; assign rstn = ~rstn_i; +// constant assignments + assign io_oeb[37:27] = 11'b00000000000; + assign io_out[26:0] = 27'b111111111111111111111111111; // does not have effect due to io_oeb + assign io_oeb[26:0] = 27'b111111111111111111111111111; + assign wbs_ack_o = 1'b0; + assign wbs_dat_o = 32'b00000000000000000000000000000000; + assign la_data_out[63:0] = 64'b0000000000000000000000000000000000000000000000000000000000000000; // MBA END assign clk_int = clk_i; assign fll_ack_o = fll_req_i;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index ed4a355..4ac32ea 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -457,6 +457,26 @@ wire [31:0] mba_data_mem_dout0_i; wire mba_data_mem_csb1_o; wire [31:0] mba_data_mem_addr1_o; + + // dummy assignments + wire spi_sdo1_o; + wire spi_sdo2_o; + wire spi_sdo3_o; + wire uart_rts; + wire uart_dtr; + wire spi_master_csn1; + wire spi_master_csn2; + wire spi_master_csn3; + wire spi_master_sdo1; + wire spi_master_sdo2; + wire spi_master_sdo3; + wire scl_padoen_o; + wire sda_padoen_o; + wire [191:0] gpio_padcfg; + wire [31:0] instr_ram_dout1; + wire [31:0] data_ram_dout1; + wire scan_o; + ////////////////////////////////////////// // MBA END @@ -467,12 +487,12 @@ // assign wbs_dat_o = 32'b00000000000000000000000000000000; // assign la_data_out[63:0] = 64'b0000000000000000000000000000000000000000000000000000000000000000; - assign io_oeb[37:27] = {11{wb_rst_i}}; - assign io_out[26:0] = {27{wb_rst_i}}; // does not have effect due to io_oeb - assign io_oeb[26:0] = {27{wb_rst_i}}; - assign wbs_ack_o = wb_rst_i; - assign wbs_dat_o = {32{wb_rst_i}}; - assign la_data_out[63:0] = {64{wb_rst_i}}; +// assign io_oeb[37:27] = {11{wb_rst_i}}; +// assign io_out[26:0] = {27{wb_rst_i}}; // does not have effect due to io_oeb +// assign io_oeb[26:0] = {27{wb_rst_i}}; +// assign wbs_ack_o = wb_rst_i; +// assign wbs_dat_o = {32{wb_rst_i}}; +// assign la_data_out[63:0] = {64{wb_rst_i}}; /*--------------------------------------*/ @@ -490,7 +510,7 @@ .testmode_i(la_data_in[2]), // .scan_i(1'b0), .scan_i(wb_dat_i[0]), - .scan_o(), + .scan_o(scan_o), .scan_en_i(la_data_in[3]), .fll_req_i(cfgreq_fll_int), .fll_wrn_i(cfgweb_n_fll_int), @@ -500,7 +520,15 @@ .fll_r_data_o(cfgq_fll_int), .fll_lock_o(lock_fll_int), .clk_o(clk_int), - .rstn_o(rstn_int) + .rstn_o(rstn_int), +// MBA START +// constant assignments + .io_oeb(io_oeb), + .io_out(io_out[26:0]), + .wbs_ack_o(wbs_ack_o), + .wbs_dat_o(wbs_dat_o), + .la_data_out(la_data_out) +// MBA END ); mba_core_region #( @@ -756,7 +784,7 @@ .clk1(wb_dat_i[0]), .csb1(mba_instr_mem_csb1_o), .addr1(mba_instr_mem_addr1_o[10:2]), - .dout1() + .dout1(instr_ram_dout1) ); ////////////////////////////////////////// // data memory @@ -775,7 +803,7 @@ .clk1(wb_dat_i[0]), .csb1(mba_data_mem_csb1_o), .addr1(mba_data_mem_addr1_o[10:2]), - .dout1() + .dout1(data_ram_dout1) ); ////////////////////////////////////////// // MBA END @@ -849,9 +877,9 @@ .spi_cs_i(io_in[18]), .spi_mode_o(io_out[37:36]), .spi_sdo0_o(io_out[35]), - .spi_sdo1_o(), - .spi_sdo2_o(), - .spi_sdo3_o(), + .spi_sdo1_o(spi_sdo1_o), + .spi_sdo2_o(spi_sdo2_o), + .spi_sdo3_o(spi_sdo3_o), .spi_sdi0_i(io_in[19]), .spi_sdi1_i(wb_dat_i[0]), .spi_sdi2_i(wb_dat_i[0]), @@ -902,34 +930,34 @@ .slave_b_valid(slaves_02_b_valid), .uart_tx(io_out[34]), .uart_rx(io_in[20]), - .uart_rts(), - .uart_dtr(), + .uart_rts(uart_rts), + .uart_dtr(uart_dtr), .uart_cts(la_data_in[4]), .uart_dsr(la_data_in[5]), .spi_master_clk(io_out[33]), .spi_master_csn0(io_out[32]), - .spi_master_csn1(), - .spi_master_csn2(), - .spi_master_csn3(), + .spi_master_csn1(spi_master_csn1), + .spi_master_csn2(spi_master_csn2), + .spi_master_csn3(spi_master_csn3), .spi_master_mode(io_out[31:30]), .spi_master_sdo0(io_out[29]), - .spi_master_sdo1(), - .spi_master_sdo2(), - .spi_master_sdo3(), + .spi_master_sdo1(spi_master_sdo1), + .spi_master_sdo2(spi_master_sdo2), + .spi_master_sdo3(spi_master_sdo3), .spi_master_sdi0(io_in[21]), .spi_master_sdi1(wb_dat_i[0]), .spi_master_sdi2(wb_dat_i[0]), .spi_master_sdi3(wb_dat_i[0]), .scl_pad_i(io_in[22]), .scl_pad_o(io_out[28]), - .scl_padoen_o(), + .scl_padoen_o(scl_padoen_o), .sda_pad_i(io_in[23]), .sda_pad_o(io_out[27]), - .sda_padoen_o(), + .sda_padoen_o(sda_padoen_o), .gpio_in(la_data_in[38:7]), .gpio_out(la_data_out[95:64]), .gpio_dir(la_data_out[127:96]), - .gpio_padcfg(), + .gpio_padcfg(gpio_padcfg), .core_busy_i(core_busy_int), .irq_o(irq_to_core_int), .fetch_enable_i(la_data_in[6]),