| ############################################################################### |
| # Created by write_sdc |
| # Wed Sep 7 14:55:29 2022 |
| ############################################################################### |
| current_design peripherals |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name clk -period 200.0000 |
| set_clock_uncertainty 0.2500 clk |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_resp[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_resp[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_user[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_user[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_user[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_user[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_user[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[32]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[33]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[34]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[35]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[36]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[37]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[38]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[39]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[40]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[41]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[42]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[43]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[44]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[45]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[46]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[47]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[48]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[49]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[50]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[51]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[52]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[53]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[54]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[55]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[56]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[57]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[58]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[59]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[60]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[61]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[62]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[63]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_data[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_last}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_resp[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_resp[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_user[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_user[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_user[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_user[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_user[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {clk_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {clk_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {clk_sel_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {clk_standalone_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_busy_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_gnt}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rvalid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fetch_enable_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_ack_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_lock_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_rdata_i[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_add_i_pll[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_add_i_pll[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_data_i_pll[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_req_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_wrn_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_in[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rst_n}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rstn_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {scan_en_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {scan_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {scl_pad_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sda_pad_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_addr[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_burst[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_burst[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_cache[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_cache[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_cache[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_cache[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_len[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_lock}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_prot[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_prot[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_prot[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_qos[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_qos[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_qos[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_qos[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_region[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_region[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_region[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_region[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_size[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_size[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_size[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_user[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_user[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_user[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_user[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_user[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_addr[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_burst[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_burst[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_cache[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_cache[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_cache[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_cache[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_len[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_lock}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_prot[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_prot[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_prot[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_qos[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_qos[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_qos[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_qos[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_region[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_region[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_region[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_region[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_size[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_size[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_size[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_user[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_user[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_user[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_user[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_user[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[32]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[33]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[34]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[35]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[36]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[37]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[38]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[39]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[40]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[41]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[42]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[43]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[44]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[45]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[46]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[47]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[48]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[49]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[50]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[51]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[52]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[53]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[54]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[55]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[56]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[57]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[58]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[59]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[60]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[61]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[62]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[63]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_data[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_last}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_strb[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_user[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_user[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_user[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_user[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_user[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_clk_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_cs_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdi0}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdi1}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdi2}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdi3}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdi0_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdi1_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdi2_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdi3_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {testmode_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {testmode_i_pll}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {uart_cts}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {uart_dsr}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {uart_rx}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {vccd1}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {vssd1}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_addr[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_burst[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_burst[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_cache[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_cache[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_cache[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_cache[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_len[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_lock}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_prot[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_prot[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_prot[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_qos[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_qos[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_qos[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_qos[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_region[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_region[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_region[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_region[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_size[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_size[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_size[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_user[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_user[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_user[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_user[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_user[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_ar_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_addr[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_burst[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_burst[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_cache[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_cache[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_cache[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_cache[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_len[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_lock}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_prot[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_prot[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_prot[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_qos[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_qos[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_qos[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_qos[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_region[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_region[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_region[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_region[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_size[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_size[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_size[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_user[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_user[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_user[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_user[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_user[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_aw_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_b_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_r_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_data[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_last}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_strb[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_user[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_user[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_user[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_user[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_user[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {axi_spi_master_w_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {clk_gate_core_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {clk_o_pll}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_req}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_we}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fetch_enable_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_add_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_add_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_req_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wdata_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll1_wrn_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_ack_o_pll}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_lock_o_pll}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fll_r_data_o_pll[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_dir[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_out[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[100]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[101]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[102]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[103]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[104]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[105]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[106]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[107]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[108]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[109]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[110]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[111]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[112]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[113]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[114]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[115]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[116]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[117]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[118]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[119]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[120]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[121]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[122]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[123]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[124]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[125]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[126]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[127]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[128]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[129]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[130]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[131]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[132]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[133]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[134]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[135]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[136]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[137]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[138]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[139]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[140]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[141]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[142]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[143]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[144]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[145]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[146]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[147]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[148]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[149]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[150]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[151]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[152]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[153]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[154]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[155]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[156]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[157]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[158]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[159]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[160]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[161]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[162]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[163]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[164]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[165]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[166]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[167]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[168]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[169]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[170]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[171]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[172]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[173]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[174]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[175]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[176]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[177]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[178]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[179]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[180]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[181]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[182]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[183]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[184]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[185]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[186]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[187]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[188]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[189]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[190]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[191]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[64]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[65]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[66]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[67]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[68]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[69]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[70]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[71]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[72]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[73]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[74]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[75]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[76]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[77]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[78]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[79]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[80]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[81]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[82]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[83]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[84]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[85]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[86]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[87]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[88]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[89]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[90]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[91]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[92]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[93]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[94]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[95]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[96]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[97]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[98]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[99]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {gpio_padcfg[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_oeb_pll[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {io_out_pll[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {la_data_out_pll[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rstn_o_pll}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {scan_o_pll}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {scl_pad_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {scl_padoen_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sda_pad_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sda_padoen_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_ar_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_aw_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_resp[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_resp[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_user[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_user[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_user[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_user[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_user[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_b_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_data[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_last}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_resp[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_resp[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_user[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_user[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_user[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_user[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_user[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_r_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {slave_w_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_clk}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_csn0}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_csn1}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_csn2}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_csn3}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_mode[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_mode[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdo0}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdo1}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdo2}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_master_sdo3}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_mode_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_mode_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdo0_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdo1_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdo2_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {spi_sdo3_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {uart_dtr}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {uart_rts}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {uart_tx}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {user_irq_pll[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {user_irq_pll[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {user_irq_pll[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {vccd1}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {vssd1}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_ack_o_pll}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wbs_dat_o_pll[9]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_lock}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_valid}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_lock}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_valid}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_b_ready}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_r_ready}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_last}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_valid}] |
| set_load -pin_load 0.0334 [get_ports {clk_gate_core_o}] |
| set_load -pin_load 0.0334 [get_ports {clk_o_pll}] |
| set_load -pin_load 0.0334 [get_ports {debug_req}] |
| set_load -pin_load 0.0334 [get_ports {debug_we}] |
| set_load -pin_load 0.0334 [get_ports {fetch_enable_o}] |
| set_load -pin_load 0.0334 [get_ports {fll1_req_o}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wrn_o}] |
| set_load -pin_load 0.0334 [get_ports {fll_ack_o_pll}] |
| set_load -pin_load 0.0334 [get_ports {fll_lock_o_pll}] |
| set_load -pin_load 0.0334 [get_ports {rstn_o_pll}] |
| set_load -pin_load 0.0334 [get_ports {scan_o_pll}] |
| set_load -pin_load 0.0334 [get_ports {scl_pad_o}] |
| set_load -pin_load 0.0334 [get_ports {scl_padoen_o}] |
| set_load -pin_load 0.0334 [get_ports {sda_pad_o}] |
| set_load -pin_load 0.0334 [get_ports {sda_padoen_o}] |
| set_load -pin_load 0.0334 [get_ports {slave_ar_ready}] |
| set_load -pin_load 0.0334 [get_ports {slave_aw_ready}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_valid}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_last}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_valid}] |
| set_load -pin_load 0.0334 [get_ports {slave_w_ready}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_clk}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_csn0}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_csn1}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_csn2}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_csn3}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_sdo0}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_sdo1}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_sdo2}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_sdo3}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo0_o}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo1_o}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo2_o}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo3_o}] |
| set_load -pin_load 0.0334 [get_ports {uart_dtr}] |
| set_load -pin_load 0.0334 [get_ports {uart_rts}] |
| set_load -pin_load 0.0334 [get_ports {uart_tx}] |
| set_load -pin_load 0.0334 [get_ports {vccd1}] |
| set_load -pin_load 0.0334 [get_ports {vssd1}] |
| set_load -pin_load 0.0334 [get_ports {wbs_ack_o_pll}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_burst[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_burst[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_cache[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_cache[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_cache[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_cache[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[7]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[6]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_len[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_prot[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_prot[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_prot[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_qos[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_qos[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_qos[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_qos[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_region[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_region[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_region[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_region[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_size[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_size[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_size[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_user[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_user[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_user[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_user[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_user[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_ar_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_burst[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_burst[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_cache[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_cache[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_cache[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_cache[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[7]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[6]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_len[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_prot[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_prot[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_prot[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_qos[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_qos[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_qos[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_qos[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_region[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_region[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_region[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_region[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_size[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_size[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_size[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_user[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_user[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_user[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_user[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_user[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_aw_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[63]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[62]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[61]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[60]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[59]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[58]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[57]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[56]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[55]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[54]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[53]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[52]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[51]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[50]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[49]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[48]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[47]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[46]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[45]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[44]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[43]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[42]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[41]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[40]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[39]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[38]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[37]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[36]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[35]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[34]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[33]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[32]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[31]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[30]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[29]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[28]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[27]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[26]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[25]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[24]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[23]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[22]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[21]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[20]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[19]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[18]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[17]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[16]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[15]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[14]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[13]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[12]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[11]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[10]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[9]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[8]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[7]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[6]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_data[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[7]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[6]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_strb[0]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_user[5]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_user[4]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_user[3]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_user[2]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_user[1]}] |
| set_load -pin_load 0.0334 [get_ports {axi_spi_master_w_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {boot_addr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {debug_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {debug_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_add_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_add_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {fll1_wdata_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[31]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[30]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[29]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[28]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[27]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[26]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[25]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[24]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[23]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[22]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[21]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[20]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[19]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[18]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[17]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[16]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[15]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[14]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[13]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[12]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[11]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[10]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[9]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[8]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[7]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[6]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[5]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[4]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[3]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[2]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[1]}] |
| set_load -pin_load 0.0334 [get_ports {fll_r_data_o_pll[0]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[31]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[30]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[29]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[28]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[27]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[26]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[25]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[24]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[23]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[22]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[21]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[20]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[19]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[18]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[17]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[16]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[15]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[14]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[13]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[12]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[11]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[10]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[9]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[8]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[7]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[6]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[5]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[4]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[3]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[2]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[1]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_dir[0]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[31]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[30]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[29]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[28]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[27]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[26]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[25]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[24]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[23]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[22]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[21]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[20]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[19]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[18]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[17]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[16]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[15]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[14]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[13]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[12]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[11]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[10]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[9]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[8]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[7]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[6]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[5]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[4]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[3]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[2]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[1]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_out[0]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[191]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[190]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[189]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[188]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[187]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[186]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[185]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[184]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[183]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[182]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[181]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[180]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[179]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[178]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[177]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[176]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[175]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[174]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[173]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[172]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[171]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[170]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[169]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[168]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[167]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[166]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[165]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[164]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[163]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[162]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[161]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[160]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[159]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[158]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[157]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[156]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[155]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[154]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[153]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[152]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[151]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[150]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[149]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[148]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[147]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[146]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[145]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[144]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[143]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[142]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[141]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[140]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[139]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[138]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[137]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[136]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[135]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[134]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[133]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[132]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[131]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[130]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[129]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[128]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[127]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[126]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[125]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[124]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[123]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[122]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[121]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[120]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[119]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[118]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[117]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[116]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[115]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[114]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[113]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[112]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[111]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[110]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[109]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[108]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[107]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[106]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[105]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[104]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[103]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[102]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[101]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[100]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[99]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[98]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[97]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[96]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[95]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[94]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[93]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[92]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[91]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[90]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[89]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[88]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[87]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[86]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[85]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[84]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[83]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[82]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[81]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[80]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[79]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[78]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[77]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[76]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[75]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[74]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[73]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[72]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[71]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[70]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[69]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[68]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[67]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[66]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[65]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[64]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[63]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[62]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[61]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[60]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[59]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[58]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[57]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[56]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[55]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[54]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[53]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[52]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[51]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[50]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[49]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[48]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[47]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[46]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[45]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[44]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[43]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[42]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[41]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[40]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[39]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[38]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[37]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[36]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[35]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[34]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[33]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[32]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[31]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[30]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[29]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[28]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[27]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[26]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[25]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[24]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[23]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[22]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[21]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[20]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[19]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[18]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[17]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[16]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[15]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[14]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[13]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[12]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[11]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[10]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[9]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[8]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[7]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[6]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[5]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[4]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[3]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[2]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[1]}] |
| set_load -pin_load 0.0334 [get_ports {gpio_padcfg[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[37]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[36]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[35]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[34]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[33]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[32]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb_pll[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_out_pll[0]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {irq_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[63]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[62]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[61]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[60]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[59]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[58]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[57]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[56]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[55]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[54]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[53]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[52]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[51]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[50]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[49]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[48]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[47]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[46]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[45]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[44]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[43]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[42]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[41]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[40]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[39]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[38]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[37]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[36]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[35]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[34]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[33]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[32]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[31]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[30]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[29]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[28]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[27]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[26]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[25]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[24]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[23]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[22]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[21]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[20]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[19]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[18]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[17]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[16]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[15]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[14]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[13]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[12]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[11]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[10]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[9]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[8]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[7]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[6]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[5]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[4]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[3]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[2]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[1]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out_pll[0]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_user[5]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_user[4]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_user[3]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_user[2]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_user[1]}] |
| set_load -pin_load 0.0334 [get_ports {slave_b_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[63]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[62]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[61]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[60]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[59]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[58]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[57]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[56]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[55]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[54]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[53]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[52]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[51]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[50]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[49]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[48]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[47]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[46]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[45]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[44]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[43]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[42]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[41]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[40]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[39]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[38]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[37]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[36]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[35]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[34]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[33]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[32]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[31]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[30]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[29]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[28]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[27]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[26]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[25]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[24]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[23]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[22]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[21]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[20]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[19]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[18]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[17]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[16]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[15]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[14]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[13]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[12]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[11]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[10]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[9]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[8]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[7]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[6]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[5]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[4]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[3]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[2]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[1]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_data[0]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_user[5]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_user[4]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_user[3]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_user[2]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_user[1]}] |
| set_load -pin_load 0.0334 [get_ports {slave_r_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_mode[1]}] |
| set_load -pin_load 0.0334 [get_ports {spi_master_mode[0]}] |
| set_load -pin_load 0.0334 [get_ports {spi_mode_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {spi_mode_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq_pll[2]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq_pll[1]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq_pll[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o_pll[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_ar_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_aw_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_last}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_w_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_sel_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_standalone_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_busy_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_gnt}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rvalid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fetch_enable_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_lock_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_req_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_wrn_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rstn_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_en_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scl_pad_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sda_pad_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_lock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_lock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_b_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_r_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_last}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_clk_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_cs_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_master_sdi0}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_master_sdi1}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_master_sdi2}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_master_sdi3}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi0_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi1_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi2_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi3_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {testmode_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {testmode_i_pll}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_cts}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_dsr}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rx}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vccd1}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {vssd1}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_user[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_user[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_user[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_user[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_user[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_b_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_data[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_user[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_user[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_user[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_user[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_user[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {axi_spi_master_r_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll1_rdata_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_add_i_pll[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_add_i_pll[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i_pll[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_in[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_burst[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_burst[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_cache[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_cache[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_cache[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_cache[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_len[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_prot[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_prot[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_prot[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_qos[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_qos[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_qos[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_qos[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_region[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_region[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_region[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_region[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_size[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_size[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_size[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_user[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_user[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_user[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_user[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_user[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_ar_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_burst[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_burst[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_cache[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_cache[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_cache[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_cache[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_len[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_prot[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_prot[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_prot[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_qos[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_qos[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_qos[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_qos[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_region[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_region[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_region[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_region[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_size[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_size[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_size[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_user[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_user[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_user[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_user[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_user[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_aw_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_data[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_strb[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_user[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_user[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_user[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_user[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_user[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave_w_user[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
