| ############################################################################### |
| # Created by write_sdc |
| # Tue Aug 30 08:04:44 2022 |
| ############################################################################### |
| current_design mba_core_region |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name clk -period 200.0000 [get_ports {clk}] |
| set_clock_transition 0.1500 [get_clocks {clk}] |
| set_clock_uncertainty 0.2500 clk |
| set_propagated_clock [get_clocks {clk}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {boot_addr_i[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {clock_gating_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_resp[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_resp[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[32]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[33]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[34]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[35]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[36]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[37]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[38]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[39]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[40]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[41]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[42]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[43]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[44]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[45]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[46]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[47]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[48]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[49]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[50]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[51]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[52]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[53]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[54]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[55]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[56]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[57]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[58]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[59]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[60]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[61]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[62]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[63]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_data[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_last}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_resp[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_resp[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_addr[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_burst[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_burst[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_cache[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_cache[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_cache[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_cache[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_len[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_lock}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_prot[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_prot[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_prot[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_qos[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_qos[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_qos[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_qos[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_region[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_region[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_region[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_region[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_size[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_size[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_size[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_addr[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_burst[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_burst[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_cache[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_cache[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_cache[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_cache[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_len[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_lock}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_prot[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_prot[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_prot[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_qos[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_qos[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_qos[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_qos[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_region[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_region[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_region[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_region[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_size[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_size[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_size[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[32]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[33]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[34]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[35]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[36]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[37]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[38]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[39]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[40]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[41]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[42]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[43]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[44]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[45]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[46]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[47]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[48]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[49]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[50]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[51]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[52]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[53]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[54]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[55]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[56]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[57]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[58]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[59]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[60]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[61]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[62]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[63]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_data[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_last}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_strb[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_resp[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_resp[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[32]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[33]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[34]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[35]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[36]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[37]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[38]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[39]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[40]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[41]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[42]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[43]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[44]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[45]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[46]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[47]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[48]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[49]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[50]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[51]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[52]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[53]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[54]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[55]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[56]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[57]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[58]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[59]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[60]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[61]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[62]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[63]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_data[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_last}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_resp[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_resp[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_addr[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_req}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_wdata[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_we}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {fetch_enable_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_addr[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_burst[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_burst[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_cache[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_cache[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_cache[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_cache[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_len[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_lock}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_prot[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_prot[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_prot[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_qos[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_qos[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_qos[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_qos[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_region[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_region[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_region[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_region[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_size[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_size[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_size[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_addr[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_burst[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_burst[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_cache[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_cache[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_cache[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_cache[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_id[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_len[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_lock}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_prot[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_prot[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_prot[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_qos[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_qos[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_qos[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_qos[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_region[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_region[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_region[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_region[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_size[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_size[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_size[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_ready}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[32]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[33]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[34]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[35]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[36]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[37]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[38]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[39]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[40]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[41]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[42]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[43]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[44]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[45]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[46]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[47]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[48]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[49]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[50]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[51]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[52]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[53]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[54]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[55]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[56]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[57]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[58]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[59]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[60]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[61]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[62]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[63]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_data[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_last}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_strb[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_user[-1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_user[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_valid}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_dout0_i[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[0]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[10]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[11]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[12]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[13]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[14]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[15]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[16]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[17]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[18]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[19]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[1]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[20]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[21]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[22]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[23]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[24]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[25]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[26]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[27]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[28]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[29]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[2]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[30]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[31]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[3]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[4]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[5]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[6]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[7]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[8]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_dout0_i[9]}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rst_n}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {tck_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {tdi_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {testmode_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {tms_i}] |
| set_input_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {trstn_i}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_busy_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_addr[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_burst[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_burst[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_cache[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_cache[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_cache[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_cache[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_len[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_lock}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_prot[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_prot[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_prot[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_qos[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_qos[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_qos[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_qos[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_region[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_region[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_region[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_region[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_size[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_size[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_size[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_ar_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_addr[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_burst[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_burst[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_cache[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_cache[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_cache[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_cache[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_len[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_lock}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_prot[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_prot[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_prot[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_qos[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_qos[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_qos[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_qos[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_region[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_region[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_region[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_region[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_size[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_size[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_size[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_aw_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_b_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_r_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_data[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_last}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_strb[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {core_master_w_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_ar_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_aw_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_resp[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_resp[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_b_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_data[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_last}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_resp[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_resp[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_r_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {data_slave_w_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_addr[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_burst[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_burst[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_cache[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_cache[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_cache[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_cache[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_len[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_lock}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_prot[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_prot[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_prot[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_qos[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_qos[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_qos[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_qos[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_region[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_region[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_region[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_region[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_size[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_size[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_size[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_ar_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_addr[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_burst[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_burst[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_cache[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_cache[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_cache[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_cache[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_len[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_lock}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_prot[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_prot[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_prot[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_qos[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_qos[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_qos[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_qos[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_region[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_region[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_region[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_region[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_size[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_size[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_size[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_aw_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_b_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_r_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_data[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_last}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_strb[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbg_master_w_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_gnt}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rdata[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {debug_rvalid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_ar_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_aw_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_resp[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_resp[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_b_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[32]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[33]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[34]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[35]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[36]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[37]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[38]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[39]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[40]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[41]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[42]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[43]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[44]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[45]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[46]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[47]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[48]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[49]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[50]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[51]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[52]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[53]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[54]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[55]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[56]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[57]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[58]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[59]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[60]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[61]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[62]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[63]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_data[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_id[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_last}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_resp[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_resp[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_user[-1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_user[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_r_valid}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {instr_slave_w_ready}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr0_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_addr1_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_csb0_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_csb1_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_din0_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_web0_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_wmask0_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_wmask0_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_wmask0_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_data_mem_wmask0_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr0_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_addr1_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_csb0_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_csb1_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[10]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[11]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[12]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[13]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[14]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[15]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[16]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[17]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[18]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[19]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[20]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[21]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[22]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[23]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[24]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[25]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[26]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[27]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[28]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[29]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[30]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[31]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[4]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[5]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[6]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[7]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[8]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_din0_o[9]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_web0_o}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_wmask0_o[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_wmask0_o[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_wmask0_o[2]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {mba_instr_mem_wmask0_o[3]}] |
| set_output_delay 40.0000 -clock [get_clocks {clk}] -add_delay [get_ports {tdo_o}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {core_busy_o}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_lock}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_valid}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_lock}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_valid}] |
| set_load -pin_load 0.0334 [get_ports {core_master_b_ready}] |
| set_load -pin_load 0.0334 [get_ports {core_master_r_ready}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_last}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_valid}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_ar_ready}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_aw_ready}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_valid}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_last}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_valid}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_w_ready}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_lock}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_valid}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_lock}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_valid}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_b_ready}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_r_ready}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_last}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_valid}] |
| set_load -pin_load 0.0334 [get_ports {debug_gnt}] |
| set_load -pin_load 0.0334 [get_ports {debug_rvalid}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_ar_ready}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_aw_ready}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_valid}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_last}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_valid}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_w_ready}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_csb0_o}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_csb1_o}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_web0_o}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_csb0_o}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_csb1_o}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_web0_o}] |
| set_load -pin_load 0.0334 [get_ports {tdo_o}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_burst[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_burst[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_cache[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_cache[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_cache[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_cache[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_len[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_prot[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_prot[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_prot[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_qos[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_qos[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_qos[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_qos[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_region[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_region[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_region[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_region[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_size[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_size[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_size[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_ar_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_burst[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_burst[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_cache[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_cache[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_cache[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_cache[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_len[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_prot[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_prot[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_prot[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_qos[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_qos[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_qos[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_qos[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_region[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_region[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_region[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_region[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_size[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_size[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_size[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_aw_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[63]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[62]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[61]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[60]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[59]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[58]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[57]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[56]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[55]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[54]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[53]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[52]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[51]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[50]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[49]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[48]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[47]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[46]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[45]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[44]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[43]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[42]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[41]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[40]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[39]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[38]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[37]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[36]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[35]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[34]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[33]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[32]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_data[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_strb[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_master_w_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_b_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[63]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[62]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[61]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[60]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[59]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[58]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[57]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[56]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[55]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[54]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[53]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[52]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[51]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[50]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[49]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[48]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[47]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[46]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[45]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[44]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[43]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[42]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[41]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[40]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[39]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[38]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[37]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[36]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[35]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[34]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[33]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[32]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[31]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[30]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[29]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[28]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[27]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[26]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[25]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[24]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[23]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[22]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[21]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[20]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[19]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[18]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[17]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[16]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[15]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[14]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[13]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[12]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[11]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[10]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[9]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[8]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[7]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[6]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[5]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[4]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[3]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[2]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[1]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_data[0]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {data_slave_r_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_burst[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_burst[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_cache[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_cache[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_cache[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_cache[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_len[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_prot[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_prot[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_prot[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_qos[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_qos[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_qos[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_qos[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_region[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_region[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_region[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_region[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_size[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_size[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_size[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_ar_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_burst[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_burst[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_cache[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_cache[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_cache[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_cache[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_len[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_prot[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_prot[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_prot[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_qos[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_qos[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_qos[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_qos[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_region[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_region[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_region[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_region[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_size[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_size[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_size[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_aw_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[63]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[62]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[61]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[60]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[59]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[58]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[57]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[56]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[55]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[54]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[53]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[52]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[51]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[50]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[49]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[48]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[47]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[46]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[45]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[44]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[43]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[42]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[41]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[40]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[39]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[38]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[37]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[36]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[35]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[34]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[33]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[32]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[31]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[30]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[29]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[28]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[27]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[26]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[25]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[24]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[23]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[22]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[21]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[20]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[19]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[18]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[17]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[16]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[15]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[14]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[13]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[12]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[11]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[10]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[9]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[8]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_data[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[7]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[6]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[5]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[4]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[3]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[2]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[1]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_strb[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {dbg_master_w_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {debug_rdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_b_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[63]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[62]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[61]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[60]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[59]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[58]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[57]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[56]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[55]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[54]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[53]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[52]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[51]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[50]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[49]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[48]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[47]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[46]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[45]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[44]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[43]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[42]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[41]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[40]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[39]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[38]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[37]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[36]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[35]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[34]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[33]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[32]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[31]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[30]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[29]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[28]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[27]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[26]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[25]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[24]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[23]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[22]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[21]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[20]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[19]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[18]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[17]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[16]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[15]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[14]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[13]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[12]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[11]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[10]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[9]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[8]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[7]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[6]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[5]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[4]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[3]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[2]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[1]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_data[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[9]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[8]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[7]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[6]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[5]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[4]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[3]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[2]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[1]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_id[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_user[0]}] |
| set_load -pin_load 0.0334 [get_ports {instr_slave_r_user[-1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr0_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_addr1_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_din0_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_wmask0_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_wmask0_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_wmask0_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_data_mem_wmask0_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr0_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_addr1_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_din0_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_wmask0_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_wmask0_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_wmask0_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {mba_instr_mem_wmask0_o[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clock_gating_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_ar_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_aw_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_last}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_w_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_lock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_lock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_b_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_r_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_last}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_ar_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_aw_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_last}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_w_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_req}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_we}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fetch_enable_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_lock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_lock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_b_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_r_ready}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_last}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {tck_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {tdi_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {testmode_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {tms_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {trstn_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {boot_addr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_b_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_data[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_master_r_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_burst[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_burst[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_cache[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_cache[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_cache[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_cache[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_len[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_prot[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_prot[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_prot[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_qos[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_qos[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_qos[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_qos[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_region[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_region[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_region[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_region[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_size[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_size[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_size[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_ar_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_burst[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_burst[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_cache[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_cache[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_cache[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_cache[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_len[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_prot[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_prot[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_prot[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_qos[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_qos[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_qos[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_qos[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_region[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_region[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_region[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_region[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_size[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_size[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_size[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_aw_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_data[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_strb[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {data_slave_w_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_b_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_data[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_master_r_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_wdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_burst[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_burst[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_cache[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_cache[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_cache[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_cache[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_len[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_prot[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_prot[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_prot[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_qos[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_qos[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_qos[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_qos[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_region[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_region[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_region[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_region[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_size[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_size[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_size[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_ar_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_burst[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_burst[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_cache[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_cache[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_cache[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_cache[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_id[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_len[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_prot[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_prot[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_prot[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_qos[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_qos[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_qos[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_qos[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_region[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_region[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_region[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_region[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_size[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_size[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_size[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_aw_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_data[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_strb[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_user[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {instr_slave_w_user[-1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_data_mem_dout0_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mba_instr_mem_dout0_i[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
