Add axi directory
diff --git a/verilog/rtl/ips/axi/axi2apb/AXI_2_APB.v b/verilog/rtl/ips/axi/axi2apb/AXI_2_APB.v new file mode 100644 index 0000000..6930760 --- /dev/null +++ b/verilog/rtl/ips/axi/axi2apb/AXI_2_APB.v
@@ -0,0 +1,644 @@ +`define log2(VALUE) ((VALUE) < ( 1 ) ? 0 : (VALUE) < ( 2 ) ? 1 : (VALUE) < ( 4 ) ? 2 : (VALUE) < ( 8 ) ? 3 : (VALUE) < ( 16 ) ? 4 : (VALUE) < ( 32 ) ? 5 : (VALUE) < ( 64 ) ? 6 : (VALUE) < ( 128 ) ? 7 : (VALUE) < ( 256 ) ? 8 : (VALUE) < ( 512 ) ? 9 : (VALUE) < ( 1024 ) ? 10 : (VALUE) < ( 2048 ) ? 11 : (VALUE) < ( 4096 ) ? 12 : (VALUE) < ( 8192 ) ? 13 : (VALUE) < ( 16384 ) ? 14 : (VALUE) < ( 32768 ) ? 15 : (VALUE) < ( 65536 ) ? 16 : (VALUE) < ( 131072 ) ? 17 : (VALUE) < ( 262144 ) ? 18 : (VALUE) < ( 524288 ) ? 19 : (VALUE) < ( 1048576 ) ? 20 : (VALUE) < ( 1048576 * 2 ) ? 21 : (VALUE) < ( 1048576 * 4 ) ? 22 : (VALUE) < ( 1048576 * 8 ) ? 23 : (VALUE) < ( 1048576 * 16 ) ? 24 : 25) + +module AXI_2_APB +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + + parameter BUFF_DEPTH_SLAVE = 4, + parameter APB_NUM_SLAVES = 8, + parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default +) +( + ACLK, + ARESETn, + test_en_i, + AWID_i, + AWADDR_i, + AWLEN_i, + AWSIZE_i, + AWBURST_i, + AWLOCK_i, + AWCACHE_i, + AWPROT_i, + AWREGION_i, + AWUSER_i, + AWQOS_i, + AWVALID_i, + AWREADY_o, + WDATA_i, + WSTRB_i, + WLAST_i, + WUSER_i, + WVALID_i, + WREADY_o, + BID_o, + BRESP_o, + BVALID_o, + BUSER_o, + BREADY_i, + ARID_i, + ARADDR_i, + ARLEN_i, + ARSIZE_i, + ARBURST_i, + ARLOCK_i, + ARCACHE_i, + ARPROT_i, + ARREGION_i, + ARUSER_i, + ARQOS_i, + ARVALID_i, + ARREADY_o, + RID_o, + RDATA_o, + RRESP_o, + RLAST_o, + RUSER_o, + RVALID_o, + RREADY_i, + PENABLE, + PWRITE, + PADDR, + PSEL, + PWDATA, + PRDATA, + PREADY, + PSLVERR +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter BUFF_DEPTH_SLAVE = 4; + //parameter APB_NUM_SLAVES = 8; + //parameter APB_ADDR_WIDTH = 12; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR_i; + input wire [7:0] AWLEN_i; + input wire [2:0] AWSIZE_i; + input wire [1:0] AWBURST_i; + input wire AWLOCK_i; + input wire [3:0] AWCACHE_i; + input wire [2:0] AWPROT_i; + input wire [3:0] AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] AWUSER_i; + input wire [3:0] AWQOS_i; + input wire AWVALID_i; + output wire AWREADY_o; + input wire [(AXI_NUMBYTES * 8) - 1:0] WDATA_i; + input wire [AXI_NUMBYTES - 1:0] WSTRB_i; + input wire WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] WUSER_i; + input wire WVALID_i; + output wire WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] BID_o; + output wire [1:0] BRESP_o; + output wire BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] BUSER_o; + input wire BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR_i; + input wire [7:0] ARLEN_i; + input wire [2:0] ARSIZE_i; + input wire [1:0] ARBURST_i; + input wire ARLOCK_i; + input wire [3:0] ARCACHE_i; + input wire [2:0] ARPROT_i; + input wire [3:0] ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] ARUSER_i; + input wire [3:0] ARQOS_i; + input wire ARVALID_i; + output wire ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] RDATA_o; + output wire [1:0] RRESP_o; + output wire RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] RUSER_o; + output wire RVALID_o; + input wire RREADY_i; + output wire PENABLE; + output wire PWRITE; + output wire [APB_ADDR_WIDTH - 1:0] PADDR; + output reg [APB_NUM_SLAVES - 1:0] PSEL; + output wire [31:0] PWDATA; + input wire [(APB_NUM_SLAVES * 32) - 1:0] PRDATA; + input wire [APB_NUM_SLAVES - 1:0] PREADY; + input wire [APB_NUM_SLAVES - 1:0] PSLVERR; + localparam OFFSET_BIT = 2; + wire [AXI4_ID_WIDTH - 1:0] AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR; + wire [7:0] AWLEN; + wire [2:0] AWSIZE; + wire [1:0] AWBURST; + wire AWLOCK; + wire [3:0] AWCACHE; + wire [2:0] AWPROT; + wire [3:0] AWREGION; + wire [AXI4_USER_WIDTH - 1:0] AWUSER; + wire [3:0] AWQOS; + wire AWVALID; + reg AWREADY; + wire [63:0] WDATA; + wire [AXI_NUMBYTES - 1:0] WSTRB; + wire WLAST; + wire [AXI4_USER_WIDTH - 1:0] WUSER; + wire WVALID; + reg WREADY; + reg [AXI4_ID_WIDTH - 1:0] BID; + reg [1:0] BRESP; + reg BVALID; + reg [AXI4_USER_WIDTH - 1:0] BUSER; + wire BREADY; + wire [AXI4_ID_WIDTH - 1:0] ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR; + wire [7:0] ARLEN; + wire [2:0] ARSIZE; + wire [1:0] ARBURST; + wire ARLOCK; + wire [3:0] ARCACHE; + wire [2:0] ARPROT; + wire [3:0] ARREGION; + wire [AXI4_USER_WIDTH - 1:0] ARUSER; + wire [3:0] ARQOS; + wire ARVALID; + reg ARREADY; + reg [AXI4_ID_WIDTH - 1:0] RID; + reg [63:0] RDATA; + reg [1:0] RRESP; + reg RLAST; + reg [AXI4_USER_WIDTH - 1:0] RUSER; + reg RVALID; + wire RREADY; + reg [3:0] CS; + reg [3:0] NS; + reg W_word_sel; + reg [(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0] address; + wire [31:0] wdata; + wire [31:0] rdata; + reg read_req; + reg write_req; + reg sample_AR; + reg [7:0] ARLEN_Q; + reg decr_ARLEN; + reg sample_AW; + reg [7:0] AWLEN_Q; + reg decr_AWLEN; + wire [((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) - 1:0] TARGET_SLAVE; + reg sample_RDATA_0; + reg sample_RDATA_1; + reg [31:0] RDATA_Q_0; + reg [31:0] RDATA_Q_1; + assign PENABLE = write_req | read_req; + assign PWRITE = write_req; + assign PADDR = address[APB_ADDR_WIDTH - 1:0]; + assign PWDATA = WDATA[W_word_sel * 32+:32]; + assign TARGET_SLAVE = address[(APB_ADDR_WIDTH + ((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25)))))))))))))))))))))))))) - 1:APB_ADDR_WIDTH]; + always @(*) begin + PSEL = 1'sb0; + PSEL[TARGET_SLAVE] = 1'b1; + end + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(AWVALID_i), + .slave_addr_i(AWADDR_i), + .slave_prot_i(AWPROT_i), + .slave_region_i(AWREGION_i), + .slave_len_i(AWLEN_i), + .slave_size_i(AWSIZE_i), + .slave_burst_i(AWBURST_i), + .slave_lock_i(AWLOCK_i), + .slave_cache_i(AWCACHE_i), + .slave_qos_i(AWQOS_i), + .slave_id_i(AWID_i), + .slave_user_i(AWUSER_i), + .slave_ready_o(AWREADY_o), + .master_valid_o(AWVALID), + .master_addr_o(AWADDR), + .master_prot_o(AWPROT), + .master_region_o(AWREGION), + .master_len_o(AWLEN), + .master_size_o(AWSIZE), + .master_burst_o(AWBURST), + .master_lock_o(AWLOCK), + .master_cache_o(AWCACHE), + .master_qos_o(AWQOS), + .master_id_o(AWID), + .master_user_o(AWUSER), + .master_ready_i(AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(ARVALID_i), + .slave_addr_i(ARADDR_i), + .slave_prot_i(ARPROT_i), + .slave_region_i(ARREGION_i), + .slave_len_i(ARLEN_i), + .slave_size_i(ARSIZE_i), + .slave_burst_i(ARBURST_i), + .slave_lock_i(ARLOCK_i), + .slave_cache_i(ARCACHE_i), + .slave_qos_i(ARQOS_i), + .slave_id_i(ARID_i), + .slave_user_i(ARUSER_i), + .slave_ready_o(ARREADY_o), + .master_valid_o(ARVALID), + .master_addr_o(ARADDR), + .master_prot_o(ARPROT), + .master_region_o(ARREGION), + .master_len_o(ARLEN), + .master_size_o(ARSIZE), + .master_burst_o(ARBURST), + .master_lock_o(ARLOCK), + .master_cache_o(ARCACHE), + .master_qos_o(ARQOS), + .master_id_o(ARID), + .master_user_o(ARUSER), + .master_ready_i(ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(WVALID_i), + .slave_data_i(WDATA_i), + .slave_strb_i(WSTRB_i), + .slave_user_i(WUSER_i), + .slave_last_i(WLAST_i), + .slave_ready_o(WREADY_o), + .master_valid_o(WVALID), + .master_data_o(WDATA), + .master_strb_o(WSTRB), + .master_user_o(WUSER), + .master_last_o(WLAST), + .master_ready_i(WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(RVALID), + .slave_data_i(RDATA), + .slave_resp_i(RRESP), + .slave_user_i(RUSER), + .slave_id_i(RID), + .slave_last_i(RLAST), + .slave_ready_o(RREADY), + .master_valid_o(RVALID_o), + .master_data_o(RDATA_o), + .master_resp_o(RRESP_o), + .master_user_o(RUSER_o), + .master_id_o(RID_o), + .master_last_o(RLAST_o), + .master_ready_i(RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(BVALID), + .slave_resp_i(BRESP), + .slave_id_i(BID), + .slave_user_i(BUSER), + .slave_ready_o(BREADY), + .master_valid_o(BVALID_o), + .master_resp_o(BRESP_o), + .master_id_o(BID_o), + .master_user_o(BUSER_o), + .master_ready_i(BREADY_i) + ); + always @(posedge ACLK or negedge ARESETn) + if (ARESETn == 1'b0) begin + CS <= 4'd0; + ARLEN_Q <= 1'sb0; + AWLEN_Q <= 1'sb0; + RDATA_Q_0 <= 1'sb0; + RDATA_Q_1 <= 1'sb0; + end + else begin + CS <= NS; + if (sample_AR) + ARLEN_Q <= ARLEN + 1; + else if (decr_ARLEN) + ARLEN_Q <= ARLEN_Q - 1'b1; + if (sample_RDATA_0) + RDATA_Q_0 <= PRDATA[TARGET_SLAVE * 32+:32]; + if (sample_RDATA_1) + RDATA_Q_1 <= PRDATA[TARGET_SLAVE * 32+:32]; + case ({sample_AW, decr_AWLEN}) + 2'b00: AWLEN_Q <= AWLEN_Q; + 2'b01: AWLEN_Q <= AWLEN_Q - 1'b1; + 2'b10: AWLEN_Q <= AWLEN + 1; + 2'b11: AWLEN_Q <= AWLEN; + endcase + end + always @(*) begin + read_req = 1'b0; + write_req = 1'b0; + W_word_sel = 1'b0; + sample_AW = 1'b0; + decr_AWLEN = 1'b0; + sample_AR = 1'b0; + decr_ARLEN = 1'b0; + sample_RDATA_0 = 1'b0; + sample_RDATA_1 = 1'b0; + ARREADY = 1'b0; + AWREADY = 1'b0; + WREADY = 1'b0; + RDATA = 1'sb0; + BVALID = 1'b0; + BRESP = 2'b00; + BID = AWID; + BUSER = AWUSER; + RVALID = 1'b0; + RLAST = 1'b0; + RID = ARID; + RUSER = ARUSER; + RRESP = 2'b00; + case (CS) + 4'd11: begin + sample_AR = 1'b0; + read_req = 1'b1; + address = ARADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (PREADY[TARGET_SLAVE] == 1'b1) begin + if (ARLEN == 0) + case (ARSIZE) + 3: begin + NS = 4'd2; + sample_RDATA_0 = 1'b1; + end + default: begin + NS = 4'd1; + if (ARADDR[2:0] == 4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + endcase + else begin + NS = 4'd5; + sample_RDATA_0 = 1'b1; + end + end + else + NS = 4'd11; + end + 4'd12: begin + address = AWADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + write_req = 1'b1; + if (AWADDR[2:0] == 4) + W_word_sel = 1'b1; + else + W_word_sel = 1'b0; + if (PREADY[TARGET_SLAVE] == 1'b1) begin + if (AWLEN == 0) begin : _SINGLE_WRITE_ + case (AWSIZE) + 3: NS = 4'd10; + default: NS = 4'd9; + endcase + end + else begin + sample_AW = 1'b1; + NS = 4'd7; + end + end + else + NS = 4'd12; + end + 4'd0: + if (ARVALID == 1'b1) begin + sample_AR = 1'b1; + read_req = 1'b1; + address = ARADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (PREADY[TARGET_SLAVE] == 1'b1) begin : _RDATA_AVAILABLE + if (ARLEN == 0) + case (ARSIZE) + 3: begin + NS = 4'd2; + sample_RDATA_0 = 1'b1; + end + default: begin + NS = 4'd1; + if (ARADDR[2:0] == 4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + endcase + else begin + NS = 4'd5; + sample_RDATA_0 = 1'b1; + end + end + else + NS = 4'd11; + end + else if (AWVALID) begin : _VALID_AW_REQ_ + address = AWADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (WVALID) begin : _VALID_W_REQ_ + write_req = 1'b1; + if (AWADDR[2:0] == 4) + W_word_sel = 1'b1; + else + W_word_sel = 1'b0; + if (PREADY[TARGET_SLAVE] == 1'b1) begin : _APB_SLAVE_READY_ + if (AWLEN == 0) begin : _SINGLE_WRITE_ + case (AWSIZE) + 3: NS = 4'd10; + default: NS = 4'd9; + endcase + end + else begin : _B_WRITE_ + sample_AW = 1'b1; + NS = 4'd7; + end + end + else begin : _APB_SLAVE_NOT_READY_ + NS = 4'd12; + end + end + else begin + write_req = 1'b0; + address = 1'sb0; + NS = 4'd0; + end + end + else begin + NS = 4'd0; + address = 1'sb0; + end + 4'd10: begin + address = AWADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0] + 4; + W_word_sel = 1'b1; + write_req = WVALID; + if (WVALID) begin + if (PREADY[TARGET_SLAVE] == 1'b1) + NS = 4'd9; + else + NS = 4'd10; + end + else + NS = 4'd10; + end + 4'd9: begin + BVALID = 1'b1; + address = 1'sb0; + if (BREADY) begin + NS = 4'd0; + AWREADY = 1'b1; + WREADY = 1'b1; + end + else + NS = 4'd9; + end + 4'd7: begin + W_word_sel = 1'b1; + write_req = WVALID; + address = AWADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (WVALID) begin + if (PREADY[TARGET_SLAVE] == 1'b1) begin + NS = 4'd6; + WREADY = 1'b1; + decr_AWLEN = 1'b1; + end + else + NS = 4'd7; + end + else + NS = 4'd7; + end + 4'd6: begin + address = AWADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (AWLEN_Q == 0) begin : _BURST_COMPLETED_ + BVALID = 1'b1; + if (BREADY) begin + NS = 4'd0; + AWREADY = 1'b1; + end + else + NS = 4'd6; + end + else begin : _BUSRST_NOT_COMPLETED_ + W_word_sel = 1'b0; + write_req = WVALID; + if (WVALID) begin + if (PREADY[TARGET_SLAVE] == 1'b1) + NS = 4'd7; + else + NS = 4'd6; + end + else + NS = 4'd7; + end + end + 4'd5: begin + read_req = 1'b1; + address = ARADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (PREADY[TARGET_SLAVE] == 1'b1) begin + decr_ARLEN = 1'b1; + sample_RDATA_1 = 1'b1; + NS = 4'd4; + end + else + NS = 4'd5; + end + 4'd4: begin + RVALID = 1'b1; + RDATA[0+:32] = RDATA_Q_0; + RDATA[32+:32] = RDATA_Q_1; + RLAST = (ARLEN_Q == 0 ? 1 : 0); + address = ARADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (RREADY) begin + if (ARLEN_Q == 0) begin : _READ_BURST_COMPLETED_ + NS = 4'd0; + ARREADY = 1'b1; + end + else begin : _READ_BUSRST_NOT_COMPLETED_ + read_req = 1'b1; + if (PREADY[TARGET_SLAVE] == 1'b1) begin + sample_RDATA_0 = 1'b1; + NS = 4'd5; + end + else + NS = 4'd3; + end + end + else + NS = 4'd4; + end + 4'd3: begin + read_req = 1'b1; + address = ARADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0]; + if (PREADY[TARGET_SLAVE] == 1'b1) begin + sample_RDATA_0 = 1'b1; + NS = 4'd5; + end + else + NS = 4'd3; + end + 4'd1: begin + RVALID = 1'b1; + RDATA[0+:32] = RDATA_Q_0; + RDATA[32+:32] = RDATA_Q_1; + RLAST = 1; + address = 1'sb0; + if (RREADY) begin + NS = 4'd0; + ARREADY = 1'b1; + end + else + NS = 4'd1; + end + 4'd2: begin + read_req = 1'b1; + address = ARADDR[(((APB_NUM_SLAVES - 1) < 1 ? 0 : ((APB_NUM_SLAVES - 1) < 2 ? 1 : ((APB_NUM_SLAVES - 1) < 4 ? 2 : ((APB_NUM_SLAVES - 1) < 8 ? 3 : ((APB_NUM_SLAVES - 1) < 16 ? 4 : ((APB_NUM_SLAVES - 1) < 32 ? 5 : ((APB_NUM_SLAVES - 1) < 64 ? 6 : ((APB_NUM_SLAVES - 1) < 128 ? 7 : ((APB_NUM_SLAVES - 1) < 256 ? 8 : ((APB_NUM_SLAVES - 1) < 512 ? 9 : ((APB_NUM_SLAVES - 1) < 1024 ? 10 : ((APB_NUM_SLAVES - 1) < 2048 ? 11 : ((APB_NUM_SLAVES - 1) < 4096 ? 12 : ((APB_NUM_SLAVES - 1) < 8192 ? 13 : ((APB_NUM_SLAVES - 1) < 16384 ? 14 : ((APB_NUM_SLAVES - 1) < 32768 ? 15 : ((APB_NUM_SLAVES - 1) < 65536 ? 16 : ((APB_NUM_SLAVES - 1) < 131072 ? 17 : ((APB_NUM_SLAVES - 1) < 262144 ? 18 : ((APB_NUM_SLAVES - 1) < 524288 ? 19 : ((APB_NUM_SLAVES - 1) < 1048576 ? 20 : ((APB_NUM_SLAVES - 1) < 2097152 ? 21 : ((APB_NUM_SLAVES - 1) < 4194304 ? 22 : ((APB_NUM_SLAVES - 1) < 8388608 ? 23 : ((APB_NUM_SLAVES - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) + APB_ADDR_WIDTH) - 1:0] + 4; + if (PREADY[TARGET_SLAVE] == 1'b1) begin + NS = 4'd1; + sample_RDATA_1 = 1'b1; + end + else + NS = 4'd2; + end + default: begin + NS = 4'd0; + address = 0; + end + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi2apb/AXI_2_APB_32.v b/verilog/rtl/ips/axi/axi2apb/AXI_2_APB_32.v new file mode 100644 index 0000000..dd71d6a --- /dev/null +++ b/verilog/rtl/ips/axi/axi2apb/AXI_2_APB_32.v
@@ -0,0 +1,432 @@ +module AXI_2_APB_32 +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 32, + parameter AXI4_WDATA_WIDTH = 32, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + + parameter BUFF_DEPTH_SLAVE = 4, + parameter APB_NUM_SLAVES = 8, + parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default +) +( + ACLK, + ARESETn, + test_en_i, + AWID_i, + AWADDR_i, + AWLEN_i, + AWSIZE_i, + AWBURST_i, + AWLOCK_i, + AWCACHE_i, + AWPROT_i, + AWREGION_i, + AWUSER_i, + AWQOS_i, + AWVALID_i, + AWREADY_o, + WDATA_i, + WSTRB_i, + WLAST_i, + WUSER_i, + WVALID_i, + WREADY_o, + BID_o, + BRESP_o, + BVALID_o, + BUSER_o, + BREADY_i, + ARID_i, + ARADDR_i, + ARLEN_i, + ARSIZE_i, + ARBURST_i, + ARLOCK_i, + ARCACHE_i, + ARPROT_i, + ARREGION_i, + ARUSER_i, + ARQOS_i, + ARVALID_i, + ARREADY_o, + RID_o, + RDATA_o, + RRESP_o, + RLAST_o, + RUSER_o, + RVALID_o, + RREADY_i, + PENABLE, + PWRITE, + PADDR, + PSEL, + PWDATA, + PRDATA, + PREADY, + PSLVERR +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 32; + //parameter AXI4_WDATA_WIDTH = 32; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter BUFF_DEPTH_SLAVE = 4; + //parameter APB_NUM_SLAVES = 8; + //parameter APB_ADDR_WIDTH = 12; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR_i; + input wire [7:0] AWLEN_i; + input wire [2:0] AWSIZE_i; + input wire [1:0] AWBURST_i; + input wire AWLOCK_i; + input wire [3:0] AWCACHE_i; + input wire [2:0] AWPROT_i; + input wire [3:0] AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] AWUSER_i; + input wire [3:0] AWQOS_i; + input wire AWVALID_i; + output wire AWREADY_o; + input wire [AXI4_WDATA_WIDTH - 1:0] WDATA_i; + input wire [AXI_NUMBYTES - 1:0] WSTRB_i; + input wire WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] WUSER_i; + input wire WVALID_i; + output wire WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] BID_o; + output wire [1:0] BRESP_o; + output wire BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] BUSER_o; + input wire BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR_i; + input wire [7:0] ARLEN_i; + input wire [2:0] ARSIZE_i; + input wire [1:0] ARBURST_i; + input wire ARLOCK_i; + input wire [3:0] ARCACHE_i; + input wire [2:0] ARPROT_i; + input wire [3:0] ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] ARUSER_i; + input wire [3:0] ARQOS_i; + input wire ARVALID_i; + output wire ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] RDATA_o; + output wire [1:0] RRESP_o; + output wire RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] RUSER_o; + output wire RVALID_o; + input wire RREADY_i; + output wire PENABLE; + output wire PWRITE; + output wire [APB_ADDR_WIDTH - 1:0] PADDR; + output reg [APB_NUM_SLAVES - 1:0] PSEL; + output wire [31:0] PWDATA; + input wire [(APB_NUM_SLAVES * 32) - 1:0] PRDATA; + input wire [APB_NUM_SLAVES - 1:0] PREADY; + input wire [APB_NUM_SLAVES - 1:0] PSLVERR; + wire [AXI4_ID_WIDTH - 1:0] AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR; + wire [7:0] AWLEN; + wire [2:0] AWSIZE; + wire [1:0] AWBURST; + wire AWLOCK; + wire [3:0] AWCACHE; + wire [2:0] AWPROT; + wire [3:0] AWREGION; + wire [AXI4_USER_WIDTH - 1:0] AWUSER; + wire [3:0] AWQOS; + wire AWVALID; + reg AWREADY; + wire [AXI4_WDATA_WIDTH - 1:0] WDATA; + wire [AXI_NUMBYTES - 1:0] WSTRB; + wire WLAST; + wire [AXI4_USER_WIDTH - 1:0] WUSER; + wire WVALID; + reg WREADY; + reg [AXI4_ID_WIDTH - 1:0] BID; + reg [1:0] BRESP; + reg BVALID; + reg [AXI4_USER_WIDTH - 1:0] BUSER; + wire BREADY; + wire [AXI4_ID_WIDTH - 1:0] ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR; + wire [7:0] ARLEN; + wire [2:0] ARSIZE; + wire [1:0] ARBURST; + wire ARLOCK; + wire [3:0] ARCACHE; + wire [2:0] ARPROT; + wire [3:0] ARREGION; + wire [AXI4_USER_WIDTH - 1:0] ARUSER; + wire [3:0] ARQOS; + wire ARVALID; + reg ARREADY; + reg [AXI4_ID_WIDTH - 1:0] RID; + reg [AXI4_RDATA_WIDTH - 1:0] RDATA; + reg [1:0] RRESP; + reg RLAST; + reg [AXI4_USER_WIDTH - 1:0] RUSER; + reg RVALID; + wire RREADY; + reg [2:0] CS; + reg [2:0] NS; + reg [($clog2(APB_NUM_SLAVES) + APB_ADDR_WIDTH) - 1:0] address; + reg sample_RDATA; + reg [31:0] RDATA_Q; + reg read_req; + reg write_req; + wire [$clog2(APB_NUM_SLAVES) - 1:0] TARGET_SLAVE; + assign PENABLE = write_req | read_req; + assign PWRITE = write_req; + assign PADDR = address[APB_ADDR_WIDTH - 1:0]; + assign PWDATA = WDATA; + assign TARGET_SLAVE = address[(APB_ADDR_WIDTH + $clog2(APB_NUM_SLAVES)) - 1:APB_ADDR_WIDTH]; + always @(*) begin + PSEL = 1'sb0; + PSEL[TARGET_SLAVE] = 1'b1; + end + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(AWVALID_i), + .slave_addr_i(AWADDR_i), + .slave_prot_i(AWPROT_i), + .slave_region_i(AWREGION_i), + .slave_len_i(AWLEN_i), + .slave_size_i(AWSIZE_i), + .slave_burst_i(AWBURST_i), + .slave_lock_i(AWLOCK_i), + .slave_cache_i(AWCACHE_i), + .slave_qos_i(AWQOS_i), + .slave_id_i(AWID_i), + .slave_user_i(AWUSER_i), + .slave_ready_o(AWREADY_o), + .master_valid_o(AWVALID), + .master_addr_o(AWADDR), + .master_prot_o(AWPROT), + .master_region_o(AWREGION), + .master_len_o(AWLEN), + .master_size_o(AWSIZE), + .master_burst_o(AWBURST), + .master_lock_o(AWLOCK), + .master_cache_o(AWCACHE), + .master_qos_o(AWQOS), + .master_id_o(AWID), + .master_user_o(AWUSER), + .master_ready_i(AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(ARVALID_i), + .slave_addr_i(ARADDR_i), + .slave_prot_i(ARPROT_i), + .slave_region_i(ARREGION_i), + .slave_len_i(ARLEN_i), + .slave_size_i(ARSIZE_i), + .slave_burst_i(ARBURST_i), + .slave_lock_i(ARLOCK_i), + .slave_cache_i(ARCACHE_i), + .slave_qos_i(ARQOS_i), + .slave_id_i(ARID_i), + .slave_user_i(ARUSER_i), + .slave_ready_o(ARREADY_o), + .master_valid_o(ARVALID), + .master_addr_o(ARADDR), + .master_prot_o(ARPROT), + .master_region_o(ARREGION), + .master_len_o(ARLEN), + .master_size_o(ARSIZE), + .master_burst_o(ARBURST), + .master_lock_o(ARLOCK), + .master_cache_o(ARCACHE), + .master_qos_o(ARQOS), + .master_id_o(ARID), + .master_user_o(ARUSER), + .master_ready_i(ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(WVALID_i), + .slave_data_i(WDATA_i), + .slave_strb_i(WSTRB_i), + .slave_user_i(WUSER_i), + .slave_last_i(WLAST_i), + .slave_ready_o(WREADY_o), + .master_valid_o(WVALID), + .master_data_o(WDATA), + .master_strb_o(WSTRB), + .master_user_o(WUSER), + .master_last_o(WLAST), + .master_ready_i(WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(RVALID), + .slave_data_i(RDATA), + .slave_resp_i(RRESP), + .slave_user_i(RUSER), + .slave_id_i(RID), + .slave_last_i(RLAST), + .slave_ready_o(RREADY), + .master_valid_o(RVALID_o), + .master_data_o(RDATA_o), + .master_resp_o(RRESP_o), + .master_user_o(RUSER_o), + .master_id_o(RID_o), + .master_last_o(RLAST_o), + .master_ready_i(RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(BVALID), + .slave_resp_i(BRESP), + .slave_id_i(BID), + .slave_user_i(BUSER), + .slave_ready_o(BREADY), + .master_valid_o(BVALID_o), + .master_resp_o(BRESP_o), + .master_id_o(BID_o), + .master_user_o(BUSER_o), + .master_ready_i(BREADY_i) + ); + always @(posedge ACLK or negedge ARESETn) + if (ARESETn == 1'b0) begin + CS <= 3'd0; + RDATA_Q <= 1'sb0; + end + else begin + CS <= NS; + if (sample_RDATA) + RDATA_Q <= PRDATA[TARGET_SLAVE * 32+:32]; + end + always @(*) begin + read_req = 1'b0; + write_req = 1'b0; + address = 1'sbx; + sample_RDATA = 1'b0; + ARREADY = 1'b0; + AWREADY = 1'b0; + WREADY = 1'b0; + BVALID = 1'b0; + BRESP = 2'b00; + BID = AWID; + BUSER = AWUSER; + RVALID = 1'b0; + RLAST = 1'b0; + RID = ARID; + RUSER = ARUSER; + RRESP = 2'b00; + RDATA = RDATA_Q; + case (CS) + 3'd3: begin + read_req = 1'b1; + address = ARADDR[($clog2(APB_NUM_SLAVES) + APB_ADDR_WIDTH) - 1:0]; + sample_RDATA = PREADY[TARGET_SLAVE]; + if (PREADY[TARGET_SLAVE] == 1'b1) + NS = 3'd1; + else + NS = 3'd3; + end + 3'd2: begin + write_req = 1'b1; + address = AWADDR[($clog2(APB_NUM_SLAVES) + APB_ADDR_WIDTH) - 1:0]; + if (PREADY[TARGET_SLAVE] == 1'b1) + NS = 3'd4; + else + NS = 3'd2; + end + 3'd0: + if (ARVALID == 1'b1) begin + read_req = 1'b1; + address = ARADDR[($clog2(APB_NUM_SLAVES) + APB_ADDR_WIDTH) - 1:0]; + sample_RDATA = PREADY[TARGET_SLAVE]; + if (PREADY[TARGET_SLAVE] == 1'b1) + NS = 3'd1; + else + NS = 3'd3; + end + else if (AWVALID) begin + address = AWADDR[($clog2(APB_NUM_SLAVES) + APB_ADDR_WIDTH) - 1:0]; + if (WVALID) begin + write_req = 1'b1; + if (PREADY[TARGET_SLAVE] == 1'b1) + NS = 3'd4; + else + NS = 3'd2; + end + else begin + write_req = 1'b0; + address = 1'sb0; + NS = 3'd0; + end + end + else begin + NS = 3'd0; + address = 1'sb0; + end + 3'd4: begin + BVALID = 1'b1; + address = 1'sb0; + if (BREADY) begin + NS = 3'd0; + AWREADY = 1'b1; + WREADY = 1'b1; + end + else + NS = 3'd4; + end + 3'd1: begin + RVALID = 1'b1; + RLAST = 1; + address = 1'sb0; + if (RREADY) begin + NS = 3'd0; + ARREADY = 1'b1; + end + else + NS = 3'd1; + end + default: NS = 3'd0; + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi2apb/axi2apb.v b/verilog/rtl/ips/axi/axi2apb/axi2apb.v new file mode 100644 index 0000000..db22a05 --- /dev/null +++ b/verilog/rtl/ips/axi/axi2apb/axi2apb.v
@@ -0,0 +1,694 @@ +module axi2apb +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + + parameter BUFF_DEPTH_SLAVE = 4, + parameter APB_NUM_SLAVES = 8, + parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default +) +( + ACLK, + ARESETn, + test_en_i, + AWID_i, + AWADDR_i, + AWLEN_i, + AWSIZE_i, + AWBURST_i, + AWLOCK_i, + AWCACHE_i, + AWPROT_i, + AWREGION_i, + AWUSER_i, + AWQOS_i, + AWVALID_i, + AWREADY_o, + WDATA_i, + WSTRB_i, + WLAST_i, + WUSER_i, + WVALID_i, + WREADY_o, + BID_o, + BRESP_o, + BVALID_o, + BUSER_o, + BREADY_i, + ARID_i, + ARADDR_i, + ARLEN_i, + ARSIZE_i, + ARBURST_i, + ARLOCK_i, + ARCACHE_i, + ARPROT_i, + ARREGION_i, + ARUSER_i, + ARQOS_i, + ARVALID_i, + ARREADY_o, + RID_o, + RDATA_o, + RRESP_o, + RLAST_o, + RUSER_o, + RVALID_o, + RREADY_i, + PENABLE, + PWRITE, + PADDR, + PSEL, + PWDATA, + PRDATA, + PREADY, + PSLVERR +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter BUFF_DEPTH_SLAVE = 4; + //parameter APB_NUM_SLAVES = 8; + //parameter APB_ADDR_WIDTH = 12; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR_i; + input wire [7:0] AWLEN_i; + input wire [2:0] AWSIZE_i; + input wire [1:0] AWBURST_i; + input wire AWLOCK_i; + input wire [3:0] AWCACHE_i; + input wire [2:0] AWPROT_i; + input wire [3:0] AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] AWUSER_i; + input wire [3:0] AWQOS_i; + input wire AWVALID_i; + output wire AWREADY_o; + input wire [(AXI_NUMBYTES * 8) - 1:0] WDATA_i; + input wire [AXI_NUMBYTES - 1:0] WSTRB_i; + input wire WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] WUSER_i; + input wire WVALID_i; + output wire WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] BID_o; + output wire [1:0] BRESP_o; + output wire BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] BUSER_o; + input wire BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR_i; + input wire [7:0] ARLEN_i; + input wire [2:0] ARSIZE_i; + input wire [1:0] ARBURST_i; + input wire ARLOCK_i; + input wire [3:0] ARCACHE_i; + input wire [2:0] ARPROT_i; + input wire [3:0] ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] ARUSER_i; + input wire [3:0] ARQOS_i; + input wire ARVALID_i; + output wire ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] RDATA_o; + output wire [1:0] RRESP_o; + output wire RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] RUSER_o; + output wire RVALID_o; + input wire RREADY_i; + output wire PENABLE; + output wire PWRITE; + output wire [31:0] PADDR; + output reg PSEL; + output wire [31:0] PWDATA; + input wire [31:0] PRDATA; + input wire PREADY; + input wire PSLVERR; + localparam OFFSET_BIT = 2; + wire [AXI4_ID_WIDTH - 1:0] AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR; + wire [7:0] AWLEN; + wire [2:0] AWSIZE; + wire [1:0] AWBURST; + wire AWLOCK; + wire [3:0] AWCACHE; + wire [2:0] AWPROT; + wire [3:0] AWREGION; + wire [AXI4_USER_WIDTH - 1:0] AWUSER; + wire [3:0] AWQOS; + wire AWVALID; + reg AWREADY; + wire [63:0] WDATA; + wire [AXI_NUMBYTES - 1:0] WSTRB; + wire WLAST; + wire [AXI4_USER_WIDTH - 1:0] WUSER; + wire WVALID; + reg WREADY; + reg [AXI4_ID_WIDTH - 1:0] BID; + reg [1:0] BRESP; + reg BVALID; + reg [AXI4_USER_WIDTH - 1:0] BUSER; + wire BREADY; + wire [AXI4_ID_WIDTH - 1:0] ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR; + wire [7:0] ARLEN; + wire [2:0] ARSIZE; + wire [1:0] ARBURST; + wire ARLOCK; + wire [3:0] ARCACHE; + wire [2:0] ARPROT; + wire [3:0] ARREGION; + wire [AXI4_USER_WIDTH - 1:0] ARUSER; + wire [3:0] ARQOS; + wire ARVALID; + reg ARREADY; + reg [AXI4_ID_WIDTH - 1:0] RID; + reg [63:0] RDATA; + reg [1:0] RRESP; + reg RLAST; + reg [AXI4_USER_WIDTH - 1:0] RUSER; + reg RVALID; + wire RREADY; + reg [3:0] CS; + reg [3:0] NS; + reg W_word_sel; + reg [31:0] address; + reg read_req; + reg write_req; + reg sample_AR; + reg [8:0] ARLEN_Q; + reg decr_ARLEN; + reg sample_AW; + reg [8:0] AWLEN_Q; + reg decr_AWLEN; + reg [AXI4_ADDRESS_WIDTH - 1:0] ARADDR_Q; + reg incr_ARADDR; + reg [AXI4_ADDRESS_WIDTH - 1:0] AWADDR_Q; + reg incr_AWADDR; + reg sample_RDATA_0; + reg sample_RDATA_1; + reg [31:0] RDATA_Q_0; + reg [31:0] RDATA_Q_1; + assign PENABLE = write_req | read_req; + assign PWRITE = write_req; + assign PADDR = address; + assign PWDATA = WDATA[W_word_sel * 32+:32]; + always @(*) PSEL = 1'b1; + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(AWVALID_i), + .slave_addr_i(AWADDR_i), + .slave_prot_i(AWPROT_i), + .slave_region_i(AWREGION_i), + .slave_len_i(AWLEN_i), + .slave_size_i(AWSIZE_i), + .slave_burst_i(AWBURST_i), + .slave_lock_i(AWLOCK_i), + .slave_cache_i(AWCACHE_i), + .slave_qos_i(AWQOS_i), + .slave_id_i(AWID_i), + .slave_user_i(AWUSER_i), + .slave_ready_o(AWREADY_o), + .master_valid_o(AWVALID), + .master_addr_o(AWADDR), + .master_prot_o(AWPROT), + .master_region_o(AWREGION), + .master_len_o(AWLEN), + .master_size_o(AWSIZE), + .master_burst_o(AWBURST), + .master_lock_o(AWLOCK), + .master_cache_o(AWCACHE), + .master_qos_o(AWQOS), + .master_id_o(AWID), + .master_user_o(AWUSER), + .master_ready_i(AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(ARVALID_i), + .slave_addr_i(ARADDR_i), + .slave_prot_i(ARPROT_i), + .slave_region_i(ARREGION_i), + .slave_len_i(ARLEN_i), + .slave_size_i(ARSIZE_i), + .slave_burst_i(ARBURST_i), + .slave_lock_i(ARLOCK_i), + .slave_cache_i(ARCACHE_i), + .slave_qos_i(ARQOS_i), + .slave_id_i(ARID_i), + .slave_user_i(ARUSER_i), + .slave_ready_o(ARREADY_o), + .master_valid_o(ARVALID), + .master_addr_o(ARADDR), + .master_prot_o(ARPROT), + .master_region_o(ARREGION), + .master_len_o(ARLEN), + .master_size_o(ARSIZE), + .master_burst_o(ARBURST), + .master_lock_o(ARLOCK), + .master_cache_o(ARCACHE), + .master_qos_o(ARQOS), + .master_id_o(ARID), + .master_user_o(ARUSER), + .master_ready_i(ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(WVALID_i), + .slave_data_i(WDATA_i), + .slave_strb_i(WSTRB_i), + .slave_user_i(WUSER_i), + .slave_last_i(WLAST_i), + .slave_ready_o(WREADY_o), + .master_valid_o(WVALID), + .master_data_o(WDATA), + .master_strb_o(WSTRB), + .master_user_o(WUSER), + .master_last_o(WLAST), + .master_ready_i(WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(RVALID), + .slave_data_i(RDATA), + .slave_resp_i(RRESP), + .slave_user_i(RUSER), + .slave_id_i(RID), + .slave_last_i(RLAST), + .slave_ready_o(RREADY), + .master_valid_o(RVALID_o), + .master_data_o(RDATA_o), + .master_resp_o(RRESP_o), + .master_user_o(RUSER_o), + .master_id_o(RID_o), + .master_last_o(RLAST_o), + .master_ready_i(RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(BVALID), + .slave_resp_i(BRESP), + .slave_id_i(BID), + .slave_user_i(BUSER), + .slave_ready_o(BREADY), + .master_valid_o(BVALID_o), + .master_resp_o(BRESP_o), + .master_id_o(BID_o), + .master_user_o(BUSER_o), + .master_ready_i(BREADY_i) + ); + always @(posedge ACLK or negedge ARESETn) + if (ARESETn == 1'b0) begin + CS <= 4'd0; + ARLEN_Q <= 1'sb0; + AWADDR_Q <= 1'sb0; + AWLEN_Q <= 1'sb0; + RDATA_Q_0 <= 1'sb0; + RDATA_Q_1 <= 1'sb0; + ARADDR_Q <= 1'sb0; + end + else begin + CS <= NS; + if (sample_AR) + ARLEN_Q <= {ARLEN, 1'b0} + 2; + else if (decr_ARLEN) + ARLEN_Q <= ARLEN_Q - 1; + if (sample_RDATA_0) + RDATA_Q_0 <= PRDATA; + if (sample_RDATA_1) + RDATA_Q_1 <= PRDATA; + case ({sample_AW, decr_AWLEN}) + 2'b00: AWLEN_Q <= AWLEN_Q; + 2'b01: AWLEN_Q <= AWLEN_Q - 1; + 2'b10: AWLEN_Q <= {AWLEN, 1'b0} + 1; + 2'b11: AWLEN_Q <= {AWLEN, 1'b0}; + endcase + case ({sample_AW, incr_AWADDR}) + 2'b00: AWADDR_Q <= AWADDR_Q; + 2'b01: AWADDR_Q <= AWADDR_Q + 4; + 2'b10: AWADDR_Q <= {AWADDR[31:3], 3'b000}; + 2'b11: AWADDR_Q <= {AWADDR[31:3], 3'b000} + 4; + endcase + case ({sample_AR, incr_ARADDR}) + 2'b00: ARADDR_Q <= ARADDR_Q; + 2'b01: ARADDR_Q <= ARADDR_Q + 4; + 2'b10: ARADDR_Q <= {ARADDR[31:3], 3'b000}; + 2'b11: ARADDR_Q <= {ARADDR[31:3], 3'b000} + 4; + endcase + end + always @(*) begin + read_req = 1'b0; + write_req = 1'b0; + W_word_sel = 1'b0; + sample_AW = 1'b0; + decr_AWLEN = 1'b0; + sample_AR = 1'b0; + decr_ARLEN = 1'b0; + incr_AWADDR = 1'b0; + incr_ARADDR = 1'b0; + sample_RDATA_0 = 1'b0; + sample_RDATA_1 = 1'b0; + ARREADY = 1'b0; + AWREADY = 1'b0; + WREADY = 1'b0; + RDATA = 1'sb0; + BVALID = 1'b0; + BRESP = 2'b00; + BID = AWID; + BUSER = AWUSER; + RVALID = 1'b0; + RLAST = 1'b0; + RID = ARID; + RUSER = ARUSER; + RRESP = 2'b00; + case (CS) + 4'd10: begin + sample_AR = 1'b0; + read_req = 1'b1; + address = ARADDR; + if (PREADY == 1'b1) begin + if (ARLEN == 0) + case (ARSIZE) + 3'h3: begin + NS = 4'd2; + if (ARADDR[2:0] == 3'h4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + default: begin + NS = 4'd1; + if (ARADDR[2:0] == 3'h4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + endcase + else begin + NS = 4'd5; + sample_RDATA_0 = 1'b1; + decr_ARLEN = 1'b1; + incr_ARADDR = 1'b1; + end + end + else + NS = 4'd10; + end + 4'd11: begin + address = AWADDR; + write_req = 1'b1; + if (AWADDR[2:0] == 3'h4) + W_word_sel = 1'b1; + else + W_word_sel = 1'b0; + if (PREADY == 1'b1) begin + if (AWLEN == 0) begin : _SINGLE_WRITE_ + case (AWSIZE) + 3'h3: NS = 4'd9; + default: NS = 4'd8; + endcase + end + else begin + sample_AW = 1'b1; + NS = 4'd7; + end + end + else + NS = 4'd11; + end + 4'd0: + if (ARVALID == 1'b1) begin + sample_AR = 1'b1; + read_req = 1'b1; + address = ARADDR; + if (PREADY == 1'b1) begin : _RDATA_AVAILABLE + if (ARLEN == 0) + case (ARSIZE) + 3'h3: begin + NS = 4'd2; + if (ARADDR[2:0] == 4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + default: begin + NS = 4'd1; + if (ARADDR[2:0] == 4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + endcase + else begin + NS = 4'd5; + sample_RDATA_0 = 1'b1; + end + end + else + NS = 4'd10; + end + else if (AWVALID) begin : _VALID_AW_REQ_ + if (WVALID) begin : _VALID_W_REQ_ + write_req = 1'b1; + address = AWADDR; + if (AWADDR[2:0] == 3'h4) + W_word_sel = 1'b1; + else + W_word_sel = 1'b0; + if (PREADY == 1'b1) begin : _APB_SLAVE_READY_ + if (AWLEN == 0) begin : _SINGLE_WRITE_ + case (AWSIZE) + 3'h3: NS = 4'd9; + default: NS = 4'd8; + endcase + end + else begin : _B_WRITE_ + sample_AW = 1'b1; + if ((AWADDR[2:0] == 3'h4) && (WSTRB[7:4] == 0)) + incr_AWADDR = 1'b0; + else + incr_AWADDR = 1'b1; + NS = 4'd7; + end + end + else begin : _APB_SLAVE_NOT_READY_ + NS = 4'd11; + end + end + else begin + write_req = 1'b0; + address = 1'sb0; + NS = 4'd0; + end + end + else begin + NS = 4'd0; + address = 1'sb0; + end + 4'd9: begin + address = AWADDR + 4; + W_word_sel = 1'b1; + write_req = WVALID; + if (WVALID) begin + if (PREADY == 1'b1) + NS = 4'd8; + else + NS = 4'd9; + end + else + NS = 4'd9; + end + 4'd8: begin + BVALID = 1'b1; + address = 1'sb0; + if (BREADY) begin + NS = 4'd0; + AWREADY = 1'b1; + WREADY = 1'b1; + end + else + NS = 4'd8; + end + 4'd7: begin + W_word_sel = 1'b1; + write_req = WVALID & |WSTRB[7:4]; + address = AWADDR_Q; + if (WVALID) begin + if (&WSTRB[7:4]) begin + if (PREADY == 1'b1) begin + NS = 4'd6; + WREADY = 1'b1; + decr_AWLEN = 1'b1; + incr_AWADDR = 1'b1; + end + else + NS = 4'd7; + end + else begin + NS = 4'd6; + WREADY = 1'b1; + decr_AWLEN = 1'b1; + incr_AWADDR = 1'b1; + end + end + else + NS = 4'd7; + end + 4'd6: begin + address = AWADDR_Q; + if (AWLEN_Q == 0) begin : _BURST_COMPLETED_ + BVALID = 1'b1; + if (BREADY) begin + NS = 4'd0; + AWREADY = 1'b1; + end + else + NS = 4'd6; + end + else begin : _BUSRST_NOT_COMPLETED_ + W_word_sel = 1'b0; + write_req = WVALID & &WSTRB[3:0]; + if (WVALID) begin + if (PREADY == 1'b1) begin + NS = 4'd7; + incr_AWADDR = 1'b1; + decr_AWLEN = 1'b1; + end + else + NS = 4'd6; + end + else + NS = 4'd7; + end + end + 4'd5: begin + read_req = 1'b1; + address = ARADDR_Q; + if (ARLEN_Q == 0) begin + NS = 4'd0; + ARREADY = 1'b1; + end + else if (PREADY == 1'b1) begin + decr_ARLEN = 1'b1; + sample_RDATA_1 = 1'b1; + NS = 4'd4; + if (ARADDR_Q[2:0] == 3'h4) + incr_ARADDR = 1'b1; + else + incr_ARADDR = 1'b0; + end + else + NS = 4'd5; + end + 4'd4: begin + RVALID = 1'b1; + RDATA[0+:32] = RDATA_Q_0; + RDATA[32+:32] = RDATA_Q_1; + RLAST = (ARLEN_Q == 0 ? 1'b1 : 1'b0); + address = ARADDR_Q; + if (RREADY) begin + if (ARLEN_Q == 0) begin : _READ_BURST_COMPLETED_ + NS = 4'd0; + ARREADY = 1'b1; + end + else begin : _READ_BUSRST_NOT_COMPLETED_ + read_req = 1'b1; + if (PREADY == 1'b1) begin + sample_RDATA_0 = 1'b1; + NS = 4'd5; + incr_ARADDR = 1'b1; + decr_ARLEN = 1'b1; + end + else + NS = 4'd3; + end + end + else + NS = 4'd4; + end + 4'd3: begin + read_req = 1'b1; + address = ARADDR_Q; + if (PREADY == 1'b1) begin + sample_RDATA_0 = 1'b1; + NS = 4'd5; + incr_ARADDR = 1'b1; + decr_ARLEN = 1'b1; + end + else + NS = 4'd3; + end + 4'd1: begin + RVALID = 1'b1; + RDATA[0+:32] = RDATA_Q_0; + RDATA[32+:32] = RDATA_Q_1; + RLAST = 1; + address = 1'sb0; + if (RREADY) begin + NS = 4'd0; + ARREADY = 1'b1; + end + else + NS = 4'd1; + end + 4'd2: begin + read_req = 1'b1; + address = ARADDR + 4; + if (PREADY == 1'b1) begin + NS = 4'd1; + if (ARADDR[2:0] == 3'h4) + sample_RDATA_0 = 1'b1; + else + sample_RDATA_1 = 1'b1; + end + else + NS = 4'd2; + end + default: begin + NS = 4'd0; + address = 0; + end + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi2apb/axi2apb32.v b/verilog/rtl/ips/axi/axi2apb/axi2apb32.v new file mode 100644 index 0000000..d4ef8c7 --- /dev/null +++ b/verilog/rtl/ips/axi/axi2apb/axi2apb32.v
@@ -0,0 +1,425 @@ +module axi2apb32 +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 32, + parameter AXI4_WDATA_WIDTH = 32, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + + parameter BUFF_DEPTH_SLAVE = 4, + parameter APB_ADDR_WIDTH = 32 +) +( + ACLK, + ARESETn, + test_en_i, + AWID_i, + AWADDR_i, + AWLEN_i, + AWSIZE_i, + AWBURST_i, + AWLOCK_i, + AWCACHE_i, + AWPROT_i, + AWREGION_i, + AWUSER_i, + AWQOS_i, + AWVALID_i, + AWREADY_o, + WDATA_i, + WSTRB_i, + WLAST_i, + WUSER_i, + WVALID_i, + WREADY_o, + BID_o, + BRESP_o, + BVALID_o, + BUSER_o, + BREADY_i, + ARID_i, + ARADDR_i, + ARLEN_i, + ARSIZE_i, + ARBURST_i, + ARLOCK_i, + ARCACHE_i, + ARPROT_i, + ARREGION_i, + ARUSER_i, + ARQOS_i, + ARVALID_i, + ARREADY_o, + RID_o, + RDATA_o, + RRESP_o, + RLAST_o, + RUSER_o, + RVALID_o, + RREADY_i, + PENABLE, + PWRITE, + PADDR, + PSEL, + PWDATA, + PRDATA, + PREADY, + PSLVERR +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 32; + //parameter AXI4_WDATA_WIDTH = 32; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter BUFF_DEPTH_SLAVE = 4; + //parameter APB_ADDR_WIDTH = 32; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR_i; + input wire [7:0] AWLEN_i; + input wire [2:0] AWSIZE_i; + input wire [1:0] AWBURST_i; + input wire AWLOCK_i; + input wire [3:0] AWCACHE_i; + input wire [2:0] AWPROT_i; + input wire [3:0] AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] AWUSER_i; + input wire [3:0] AWQOS_i; + input wire AWVALID_i; + output wire AWREADY_o; + input wire [AXI4_WDATA_WIDTH - 1:0] WDATA_i; + input wire [AXI_NUMBYTES - 1:0] WSTRB_i; + input wire WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] WUSER_i; + input wire WVALID_i; + output wire WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] BID_o; + output wire [1:0] BRESP_o; + output wire BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] BUSER_o; + input wire BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR_i; + input wire [7:0] ARLEN_i; + input wire [2:0] ARSIZE_i; + input wire [1:0] ARBURST_i; + input wire ARLOCK_i; + input wire [3:0] ARCACHE_i; + input wire [2:0] ARPROT_i; + input wire [3:0] ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] ARUSER_i; + input wire [3:0] ARQOS_i; + input wire ARVALID_i; + output wire ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] RDATA_o; + output wire [1:0] RRESP_o; + output wire RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] RUSER_o; + output wire RVALID_o; + input wire RREADY_i; + output wire PENABLE; + output wire PWRITE; + output wire [APB_ADDR_WIDTH - 1:0] PADDR; + output wire PSEL; + output wire [31:0] PWDATA; + input wire [31:0] PRDATA; + input wire PREADY; + input wire PSLVERR; + wire [AXI4_ID_WIDTH - 1:0] AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR; + wire [7:0] AWLEN; + wire [2:0] AWSIZE; + wire [1:0] AWBURST; + wire AWLOCK; + wire [3:0] AWCACHE; + wire [2:0] AWPROT; + wire [3:0] AWREGION; + wire [AXI4_USER_WIDTH - 1:0] AWUSER; + wire [3:0] AWQOS; + wire AWVALID; + reg AWREADY; + wire [AXI4_WDATA_WIDTH - 1:0] WDATA; + wire [AXI_NUMBYTES - 1:0] WSTRB; + wire WLAST; + wire [AXI4_USER_WIDTH - 1:0] WUSER; + wire WVALID; + reg WREADY; + reg [AXI4_ID_WIDTH - 1:0] BID; + reg [1:0] BRESP; + reg BVALID; + reg [AXI4_USER_WIDTH - 1:0] BUSER; + wire BREADY; + wire [AXI4_ID_WIDTH - 1:0] ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR; + wire [7:0] ARLEN; + wire [2:0] ARSIZE; + wire [1:0] ARBURST; + wire ARLOCK; + wire [3:0] ARCACHE; + wire [2:0] ARPROT; + wire [3:0] ARREGION; + wire [AXI4_USER_WIDTH - 1:0] ARUSER; + wire [3:0] ARQOS; + wire ARVALID; + reg ARREADY; + reg [AXI4_ID_WIDTH - 1:0] RID; + reg [AXI4_RDATA_WIDTH - 1:0] RDATA; + reg [1:0] RRESP; + reg RLAST; + reg [AXI4_USER_WIDTH - 1:0] RUSER; + reg RVALID; + wire RREADY; + reg [2:0] CS; + reg [2:0] NS; + reg [31:0] address; + reg sample_RDATA; + reg [31:0] RDATA_Q; + reg read_req; + reg write_req; + assign PENABLE = write_req | read_req; + assign PWRITE = write_req; + assign PADDR = address[APB_ADDR_WIDTH - 1:0]; + assign PWDATA = WDATA; + assign PSEL = 1'b1; + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(AWVALID_i), + .slave_addr_i(AWADDR_i), + .slave_prot_i(AWPROT_i), + .slave_region_i(AWREGION_i), + .slave_len_i(AWLEN_i), + .slave_size_i(AWSIZE_i), + .slave_burst_i(AWBURST_i), + .slave_lock_i(AWLOCK_i), + .slave_cache_i(AWCACHE_i), + .slave_qos_i(AWQOS_i), + .slave_id_i(AWID_i), + .slave_user_i(AWUSER_i), + .slave_ready_o(AWREADY_o), + .master_valid_o(AWVALID), + .master_addr_o(AWADDR), + .master_prot_o(AWPROT), + .master_region_o(AWREGION), + .master_len_o(AWLEN), + .master_size_o(AWSIZE), + .master_burst_o(AWBURST), + .master_lock_o(AWLOCK), + .master_cache_o(AWCACHE), + .master_qos_o(AWQOS), + .master_id_o(AWID), + .master_user_o(AWUSER), + .master_ready_i(AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(ARVALID_i), + .slave_addr_i(ARADDR_i), + .slave_prot_i(ARPROT_i), + .slave_region_i(ARREGION_i), + .slave_len_i(ARLEN_i), + .slave_size_i(ARSIZE_i), + .slave_burst_i(ARBURST_i), + .slave_lock_i(ARLOCK_i), + .slave_cache_i(ARCACHE_i), + .slave_qos_i(ARQOS_i), + .slave_id_i(ARID_i), + .slave_user_i(ARUSER_i), + .slave_ready_o(ARREADY_o), + .master_valid_o(ARVALID), + .master_addr_o(ARADDR), + .master_prot_o(ARPROT), + .master_region_o(ARREGION), + .master_len_o(ARLEN), + .master_size_o(ARSIZE), + .master_burst_o(ARBURST), + .master_lock_o(ARLOCK), + .master_cache_o(ARCACHE), + .master_qos_o(ARQOS), + .master_id_o(ARID), + .master_user_o(ARUSER), + .master_ready_i(ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(WVALID_i), + .slave_data_i(WDATA_i), + .slave_strb_i(WSTRB_i), + .slave_user_i(WUSER_i), + .slave_last_i(WLAST_i), + .slave_ready_o(WREADY_o), + .master_valid_o(WVALID), + .master_data_o(WDATA), + .master_strb_o(WSTRB), + .master_user_o(WUSER), + .master_last_o(WLAST), + .master_ready_i(WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(RVALID), + .slave_data_i(RDATA), + .slave_resp_i(RRESP), + .slave_user_i(RUSER), + .slave_id_i(RID), + .slave_last_i(RLAST), + .slave_ready_o(RREADY), + .master_valid_o(RVALID_o), + .master_data_o(RDATA_o), + .master_resp_o(RRESP_o), + .master_user_o(RUSER_o), + .master_id_o(RID_o), + .master_last_o(RLAST_o), + .master_ready_i(RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(BVALID), + .slave_resp_i(BRESP), + .slave_id_i(BID), + .slave_user_i(BUSER), + .slave_ready_o(BREADY), + .master_valid_o(BVALID_o), + .master_resp_o(BRESP_o), + .master_id_o(BID_o), + .master_user_o(BUSER_o), + .master_ready_i(BREADY_i) + ); + always @(posedge ACLK or negedge ARESETn) + if (ARESETn == 1'b0) begin + CS <= 3'd0; + RDATA_Q <= 1'sb0; + end + else begin + CS <= NS; + if (sample_RDATA) + RDATA_Q <= PRDATA; + end + always @(*) begin + read_req = 1'b0; + write_req = 1'b0; + address = 1'sbx; + sample_RDATA = 1'b0; + ARREADY = 1'b0; + AWREADY = 1'b0; + WREADY = 1'b0; + BVALID = 1'b0; + BRESP = 2'b00; + BID = AWID; + BUSER = AWUSER; + RVALID = 1'b0; + RLAST = 1'b0; + RID = ARID; + RUSER = ARUSER; + RRESP = 2'b00; + RDATA = RDATA_Q; + case (CS) + 3'd3: begin + read_req = 1'b1; + address = ARADDR[APB_ADDR_WIDTH - 1:0]; + sample_RDATA = PREADY; + if (PREADY == 1'b1) + NS = 3'd1; + else + NS = 3'd3; + end + 3'd2: begin + write_req = 1'b1; + address = AWADDR[APB_ADDR_WIDTH - 1:0]; + if (PREADY == 1'b1) + NS = 3'd4; + else + NS = 3'd2; + end + 3'd0: + if (ARVALID == 1'b1) begin + read_req = 1'b1; + address = ARADDR[APB_ADDR_WIDTH - 1:0]; + sample_RDATA = PREADY; + if (PREADY == 1'b1) + NS = 3'd1; + else + NS = 3'd3; + end + else if (AWVALID) begin + address = AWADDR[APB_ADDR_WIDTH - 1:0]; + if (WVALID) begin + write_req = 1'b1; + if (PREADY == 1'b1) + NS = 3'd4; + else + NS = 3'd2; + end + else begin + write_req = 1'b0; + address = 1'sb0; + NS = 3'd0; + end + end + else begin + NS = 3'd0; + address = 1'sb0; + end + 3'd4: begin + BVALID = 1'b1; + address = 1'sb0; + if (BREADY) begin + NS = 3'd0; + AWREADY = 1'b1; + WREADY = 1'b1; + end + else + NS = 3'd4; + end + 3'd1: begin + RVALID = 1'b1; + RLAST = 1; + address = 1'sb0; + if (RREADY) begin + NS = 3'd0; + ARREADY = 1'b1; + end + else + NS = 3'd1; + end + default: NS = 3'd0; + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_DP.v b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_DP.v new file mode 100644 index 0000000..dbdc31d --- /dev/null +++ b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_DP.v
@@ -0,0 +1,874 @@ +module axi_mem_if_DP +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + parameter MEM_ADDR_WIDTH = 13, + parameter BUFF_DEPTH_SLAVE = 4 +) +( + ACLK, + ARESETn, + test_en_i, + LP_AWID_i, + LP_AWADDR_i, + LP_AWLEN_i, + LP_AWSIZE_i, + LP_AWBURST_i, + LP_AWLOCK_i, + LP_AWCACHE_i, + LP_AWPROT_i, + LP_AWREGION_i, + LP_AWUSER_i, + LP_AWQOS_i, + LP_AWVALID_i, + LP_AWREADY_o, + LP_WDATA_i, + LP_WSTRB_i, + LP_WLAST_i, + LP_WUSER_i, + LP_WVALID_i, + LP_WREADY_o, + LP_BID_o, + LP_BRESP_o, + LP_BVALID_o, + LP_BUSER_o, + LP_BREADY_i, + LP_ARID_i, + LP_ARADDR_i, + LP_ARLEN_i, + LP_ARSIZE_i, + LP_ARBURST_i, + LP_ARLOCK_i, + LP_ARCACHE_i, + LP_ARPROT_i, + LP_ARREGION_i, + LP_ARUSER_i, + LP_ARQOS_i, + LP_ARVALID_i, + LP_ARREADY_o, + LP_RID_o, + LP_RDATA_o, + LP_RRESP_o, + LP_RLAST_o, + LP_RUSER_o, + LP_RVALID_o, + LP_RREADY_i, + HP_AWID_i, + HP_AWADDR_i, + HP_AWLEN_i, + HP_AWSIZE_i, + HP_AWBURST_i, + HP_AWLOCK_i, + HP_AWCACHE_i, + HP_AWPROT_i, + HP_AWREGION_i, + HP_AWUSER_i, + HP_AWQOS_i, + HP_AWVALID_i, + HP_AWREADY_o, + HP_WDATA_i, + HP_WSTRB_i, + HP_WLAST_i, + HP_WUSER_i, + HP_WVALID_i, + HP_WREADY_o, + HP_BID_o, + HP_BRESP_o, + HP_BVALID_o, + HP_BUSER_o, + HP_BREADY_i, + HP_ARID_i, + HP_ARADDR_i, + HP_ARLEN_i, + HP_ARSIZE_i, + HP_ARBURST_i, + HP_ARLOCK_i, + HP_ARCACHE_i, + HP_ARPROT_i, + HP_ARREGION_i, + HP_ARUSER_i, + HP_ARQOS_i, + HP_ARVALID_i, + HP_ARREADY_o, + HP_RID_o, + HP_RDATA_o, + HP_RRESP_o, + HP_RLAST_o, + HP_RUSER_o, + HP_RVALID_o, + HP_RREADY_i, + CEN, + WEN, + A, + D, + BE, + Q +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter MEM_ADDR_WIDTH = 13; + //parameter BUFF_DEPTH_SLAVE = 4; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] LP_AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] LP_AWADDR_i; + input wire [7:0] LP_AWLEN_i; + input wire [2:0] LP_AWSIZE_i; + input wire [1:0] LP_AWBURST_i; + input wire LP_AWLOCK_i; + input wire [3:0] LP_AWCACHE_i; + input wire [2:0] LP_AWPROT_i; + input wire [3:0] LP_AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_AWUSER_i; + input wire [3:0] LP_AWQOS_i; + input wire LP_AWVALID_i; + output wire LP_AWREADY_o; + input wire [(AXI_NUMBYTES * 8) - 1:0] LP_WDATA_i; + input wire [AXI_NUMBYTES - 1:0] LP_WSTRB_i; + input wire LP_WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_WUSER_i; + input wire LP_WVALID_i; + output wire LP_WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] LP_BID_o; + output wire [1:0] LP_BRESP_o; + output wire LP_BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] LP_BUSER_o; + input wire LP_BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] LP_ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] LP_ARADDR_i; + input wire [7:0] LP_ARLEN_i; + input wire [2:0] LP_ARSIZE_i; + input wire [1:0] LP_ARBURST_i; + input wire LP_ARLOCK_i; + input wire [3:0] LP_ARCACHE_i; + input wire [2:0] LP_ARPROT_i; + input wire [3:0] LP_ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_ARUSER_i; + input wire [3:0] LP_ARQOS_i; + input wire LP_ARVALID_i; + output wire LP_ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] LP_RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] LP_RDATA_o; + output wire [1:0] LP_RRESP_o; + output wire LP_RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] LP_RUSER_o; + output wire LP_RVALID_o; + input wire LP_RREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] HP_AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] HP_AWADDR_i; + input wire [7:0] HP_AWLEN_i; + input wire [2:0] HP_AWSIZE_i; + input wire [1:0] HP_AWBURST_i; + input wire HP_AWLOCK_i; + input wire [3:0] HP_AWCACHE_i; + input wire [2:0] HP_AWPROT_i; + input wire [3:0] HP_AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] HP_AWUSER_i; + input wire [3:0] HP_AWQOS_i; + input wire HP_AWVALID_i; + output wire HP_AWREADY_o; + input wire [(AXI_NUMBYTES * 8) - 1:0] HP_WDATA_i; + input wire [AXI_NUMBYTES - 1:0] HP_WSTRB_i; + input wire HP_WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] HP_WUSER_i; + input wire HP_WVALID_i; + output wire HP_WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] HP_BID_o; + output wire [1:0] HP_BRESP_o; + output wire HP_BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] HP_BUSER_o; + input wire HP_BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] HP_ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] HP_ARADDR_i; + input wire [7:0] HP_ARLEN_i; + input wire [2:0] HP_ARSIZE_i; + input wire [1:0] HP_ARBURST_i; + input wire HP_ARLOCK_i; + input wire [3:0] HP_ARCACHE_i; + input wire [2:0] HP_ARPROT_i; + input wire [3:0] HP_ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] HP_ARUSER_i; + input wire [3:0] HP_ARQOS_i; + input wire HP_ARVALID_i; + output wire HP_ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] HP_RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] HP_RDATA_o; + output wire [1:0] HP_RRESP_o; + output wire HP_RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] HP_RUSER_o; + output wire HP_RVALID_o; + input wire HP_RREADY_i; + output reg CEN; + output reg WEN; + output reg [MEM_ADDR_WIDTH - 1:0] A; + output reg [AXI4_WDATA_WIDTH - 1:0] D; + output reg [AXI_NUMBYTES - 1:0] BE; + input wire [AXI4_RDATA_WIDTH - 1:0] Q; + localparam OFFSET_BIT = $clog2(AXI4_WDATA_WIDTH) - 3; + wire [AXI4_ID_WIDTH - 1:0] LP_AWID; + wire [AXI4_ID_WIDTH - 1:0] HP_AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] LP_AWADDR; + wire [AXI4_ADDRESS_WIDTH - 1:0] HP_AWADDR; + wire [7:0] LP_AWLEN; + wire [7:0] HP_AWLEN; + wire [2:0] LP_AWSIZE; + wire [2:0] HP_AWSIZE; + wire [1:0] LP_AWBURST; + wire [1:0] HP_AWBURST; + wire LP_AWLOCK; + wire HP_AWLOCK; + wire [3:0] LP_AWCACHE; + wire [3:0] HP_AWCACHE; + wire [2:0] LP_AWPROT; + wire [2:0] HP_AWPROT; + wire [3:0] LP_AWREGION; + wire [3:0] HP_AWREGION; + wire [AXI4_USER_WIDTH - 1:0] LP_AWUSER; + wire [AXI4_USER_WIDTH - 1:0] HP_AWUSER; + wire [3:0] LP_AWQOS; + wire [3:0] HP_AWQOS; + wire LP_AWVALID; + wire HP_AWVALID; + wire LP_AWREADY; + wire HP_AWREADY; + wire [(AXI_NUMBYTES * 8) - 1:0] LP_WDATA; + wire [(AXI_NUMBYTES * 8) - 1:0] HP_WDATA; + wire [AXI_NUMBYTES - 1:0] LP_WSTRB; + wire [AXI_NUMBYTES - 1:0] HP_WSTRB; + wire LP_WLAST; + wire HP_WLAST; + wire [AXI4_USER_WIDTH - 1:0] LP_WUSER; + wire [AXI4_USER_WIDTH - 1:0] HP_WUSER; + wire LP_WVALID; + wire HP_WVALID; + wire LP_WREADY; + wire HP_WREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_BID; + wire [AXI4_ID_WIDTH - 1:0] HP_BID; + wire [1:0] LP_BRESP; + wire [1:0] HP_BRESP; + wire LP_BVALID; + wire HP_BVALID; + wire [AXI4_USER_WIDTH - 1:0] LP_BUSER; + wire [AXI4_USER_WIDTH - 1:0] HP_BUSER; + wire LP_BREADY; + wire HP_BREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_ARID; + wire [AXI4_ID_WIDTH - 1:0] HP_ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] LP_ARADDR; + wire [AXI4_ADDRESS_WIDTH - 1:0] HP_ARADDR; + wire [7:0] LP_ARLEN; + wire [7:0] HP_ARLEN; + wire [2:0] LP_ARSIZE; + wire [2:0] HP_ARSIZE; + wire [1:0] LP_ARBURST; + wire [1:0] HP_ARBURST; + wire LP_ARLOCK; + wire HP_ARLOCK; + wire [3:0] LP_ARCACHE; + wire [3:0] HP_ARCACHE; + wire [2:0] LP_ARPROT; + wire [2:0] HP_ARPROT; + wire [3:0] LP_ARREGION; + wire [3:0] HP_ARREGION; + wire [AXI4_USER_WIDTH - 1:0] LP_ARUSER; + wire [AXI4_USER_WIDTH - 1:0] HP_ARUSER; + wire [3:0] LP_ARQOS; + wire [3:0] HP_ARQOS; + wire LP_ARVALID; + wire HP_ARVALID; + wire LP_ARREADY; + wire HP_ARREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_RID; + wire [AXI4_ID_WIDTH - 1:0] HP_RID; + wire [AXI4_RDATA_WIDTH - 1:0] LP_RDATA; + wire [AXI4_RDATA_WIDTH - 1:0] HP_RDATA; + wire [1:0] LP_RRESP; + wire [1:0] HP_RRESP; + wire LP_RLAST; + wire HP_RLAST; + wire [AXI4_USER_WIDTH - 1:0] LP_RUSER; + wire [AXI4_USER_WIDTH - 1:0] HP_RUSER; + wire LP_RVALID; + wire HP_RVALID; + wire LP_RREADY; + wire HP_RREADY; + wire valid_R_HP; + wire valid_W_HP; + wire valid_R_LP; + wire valid_W_LP; + reg grant_R_HP; + reg grant_W_HP; + reg grant_R_LP; + reg grant_W_LP; + reg RR_FLAG_HP; + reg RR_FLAG_LP; + reg main_grant_LP; + reg main_grant_HP; + reg destination; + wire HP_W_cen; + wire HP_R_cen; + wire LP_W_cen; + wire LP_R_cen; + reg LP_cen; + reg HP_cen; + wire HP_W_wen; + wire HP_R_wen; + wire LP_W_wen; + wire LP_R_wen; + reg LP_wen; + reg HP_wen; + wire [MEM_ADDR_WIDTH - 1:0] HP_W_addr; + wire [MEM_ADDR_WIDTH - 1:0] HP_R_addr; + wire [MEM_ADDR_WIDTH - 1:0] LP_W_addr; + wire [MEM_ADDR_WIDTH - 1:0] LP_R_addr; + reg [MEM_ADDR_WIDTH - 1:0] LP_addr; + reg [MEM_ADDR_WIDTH - 1:0] HP_addr; + wire [AXI4_WDATA_WIDTH - 1:0] LP_wdata; + wire [AXI4_WDATA_WIDTH - 1:0] HP_wdata; + wire [AXI_NUMBYTES - 1:0] LP_be; + wire [AXI_NUMBYTES - 1:0] HP_be; + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_AWVALID_i), + .slave_addr_i(LP_AWADDR_i), + .slave_prot_i(LP_AWPROT_i), + .slave_region_i(LP_AWREGION_i), + .slave_len_i(LP_AWLEN_i), + .slave_size_i(LP_AWSIZE_i), + .slave_burst_i(LP_AWBURST_i), + .slave_lock_i(LP_AWLOCK_i), + .slave_cache_i(LP_AWCACHE_i), + .slave_qos_i(LP_AWQOS_i), + .slave_id_i(LP_AWID_i), + .slave_user_i(LP_AWUSER_i), + .slave_ready_o(LP_AWREADY_o), + .master_valid_o(LP_AWVALID), + .master_addr_o(LP_AWADDR), + .master_prot_o(LP_AWPROT), + .master_region_o(LP_AWREGION), + .master_len_o(LP_AWLEN), + .master_size_o(LP_AWSIZE), + .master_burst_o(LP_AWBURST), + .master_lock_o(LP_AWLOCK), + .master_cache_o(LP_AWCACHE), + .master_qos_o(LP_AWQOS), + .master_id_o(LP_AWID), + .master_user_o(LP_AWUSER), + .master_ready_i(LP_AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_ARVALID_i), + .slave_addr_i(LP_ARADDR_i), + .slave_prot_i(LP_ARPROT_i), + .slave_region_i(LP_ARREGION_i), + .slave_len_i(LP_ARLEN_i), + .slave_size_i(LP_ARSIZE_i), + .slave_burst_i(LP_ARBURST_i), + .slave_lock_i(LP_ARLOCK_i), + .slave_cache_i(LP_ARCACHE_i), + .slave_qos_i(LP_ARQOS_i), + .slave_id_i(LP_ARID_i), + .slave_user_i(LP_ARUSER_i), + .slave_ready_o(LP_ARREADY_o), + .master_valid_o(LP_ARVALID), + .master_addr_o(LP_ARADDR), + .master_prot_o(LP_ARPROT), + .master_region_o(LP_ARREGION), + .master_len_o(LP_ARLEN), + .master_size_o(LP_ARSIZE), + .master_burst_o(LP_ARBURST), + .master_lock_o(LP_ARLOCK), + .master_cache_o(LP_ARCACHE), + .master_qos_o(LP_ARQOS), + .master_id_o(LP_ARID), + .master_user_o(LP_ARUSER), + .master_ready_i(LP_ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_WVALID_i), + .slave_data_i(LP_WDATA_i), + .slave_strb_i(LP_WSTRB_i), + .slave_user_i(LP_WUSER_i), + .slave_last_i(LP_WLAST_i), + .slave_ready_o(LP_WREADY_o), + .master_valid_o(LP_WVALID), + .master_data_o(LP_WDATA), + .master_strb_o(LP_WSTRB), + .master_user_o(LP_WUSER), + .master_last_o(LP_WLAST), + .master_ready_i(LP_WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_RVALID), + .slave_data_i(LP_RDATA), + .slave_resp_i(LP_RRESP), + .slave_user_i(LP_RUSER), + .slave_id_i(LP_RID), + .slave_last_i(LP_RLAST), + .slave_ready_o(LP_RREADY), + .master_valid_o(LP_RVALID_o), + .master_data_o(LP_RDATA_o), + .master_resp_o(LP_RRESP_o), + .master_user_o(LP_RUSER_o), + .master_id_o(LP_RID_o), + .master_last_o(LP_RLAST_o), + .master_ready_i(LP_RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_BVALID), + .slave_resp_i(LP_BRESP), + .slave_id_i(LP_BID), + .slave_user_i(LP_BUSER), + .slave_ready_o(LP_BREADY), + .master_valid_o(LP_BVALID_o), + .master_resp_o(LP_BRESP_o), + .master_id_o(LP_BID_o), + .master_user_o(LP_BUSER_o), + .master_ready_i(LP_BREADY_i) + ); + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer_HP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(HP_AWVALID_i), + .slave_addr_i(HP_AWADDR_i), + .slave_prot_i(HP_AWPROT_i), + .slave_region_i(HP_AWREGION_i), + .slave_len_i(HP_AWLEN_i), + .slave_size_i(HP_AWSIZE_i), + .slave_burst_i(HP_AWBURST_i), + .slave_lock_i(HP_AWLOCK_i), + .slave_cache_i(HP_AWCACHE_i), + .slave_qos_i(HP_AWQOS_i), + .slave_id_i(HP_AWID_i), + .slave_user_i(HP_AWUSER_i), + .slave_ready_o(HP_AWREADY_o), + .master_valid_o(HP_AWVALID), + .master_addr_o(HP_AWADDR), + .master_prot_o(HP_AWPROT), + .master_region_o(HP_AWREGION), + .master_len_o(HP_AWLEN), + .master_size_o(HP_AWSIZE), + .master_burst_o(HP_AWBURST), + .master_lock_o(HP_AWLOCK), + .master_cache_o(HP_AWCACHE), + .master_qos_o(HP_AWQOS), + .master_id_o(HP_AWID), + .master_user_o(HP_AWUSER), + .master_ready_i(HP_AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer_HP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(HP_ARVALID_i), + .slave_addr_i(HP_ARADDR_i), + .slave_prot_i(HP_ARPROT_i), + .slave_region_i(HP_ARREGION_i), + .slave_len_i(HP_ARLEN_i), + .slave_size_i(HP_ARSIZE_i), + .slave_burst_i(HP_ARBURST_i), + .slave_lock_i(HP_ARLOCK_i), + .slave_cache_i(HP_ARCACHE_i), + .slave_qos_i(HP_ARQOS_i), + .slave_id_i(HP_ARID_i), + .slave_user_i(HP_ARUSER_i), + .slave_ready_o(HP_ARREADY_o), + .master_valid_o(HP_ARVALID), + .master_addr_o(HP_ARADDR), + .master_prot_o(HP_ARPROT), + .master_region_o(HP_ARREGION), + .master_len_o(HP_ARLEN), + .master_size_o(HP_ARSIZE), + .master_burst_o(HP_ARBURST), + .master_lock_o(HP_ARLOCK), + .master_cache_o(HP_ARCACHE), + .master_qos_o(HP_ARQOS), + .master_id_o(HP_ARID), + .master_user_o(HP_ARUSER), + .master_ready_i(HP_ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer_HP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(HP_WVALID_i), + .slave_data_i(HP_WDATA_i), + .slave_strb_i(HP_WSTRB_i), + .slave_user_i(HP_WUSER_i), + .slave_last_i(HP_WLAST_i), + .slave_ready_o(HP_WREADY_o), + .master_valid_o(HP_WVALID), + .master_data_o(HP_WDATA), + .master_strb_o(HP_WSTRB), + .master_user_o(HP_WUSER), + .master_last_o(HP_WLAST), + .master_ready_i(HP_WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer_HP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(HP_RVALID), + .slave_data_i(HP_RDATA), + .slave_resp_i(HP_RRESP), + .slave_user_i(HP_RUSER), + .slave_id_i(HP_RID), + .slave_last_i(HP_RLAST), + .slave_ready_o(HP_RREADY), + .master_valid_o(HP_RVALID_o), + .master_data_o(HP_RDATA_o), + .master_resp_o(HP_RRESP_o), + .master_user_o(HP_RUSER_o), + .master_id_o(HP_RID_o), + .master_last_o(HP_RLAST_o), + .master_ready_i(HP_RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer_HP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(HP_BVALID), + .slave_resp_i(HP_BRESP), + .slave_id_i(HP_BID), + .slave_user_i(HP_BUSER), + .slave_ready_o(HP_BREADY), + .master_valid_o(HP_BVALID_o), + .master_resp_o(HP_BRESP_o), + .master_id_o(HP_BID_o), + .master_user_o(HP_BUSER_o), + .master_ready_i(HP_BREADY_i) + ); + axi_write_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) W_CTRL_HP( + .clk(ACLK), + .rst_n(ARESETn), + .AWID_i(HP_AWID), + .AWADDR_i(HP_AWADDR), + .AWLEN_i(HP_AWLEN), + .AWSIZE_i(HP_AWSIZE), + .AWBURST_i(HP_AWBURST), + .AWLOCK_i(HP_AWLOCK), + .AWCACHE_i(HP_AWCACHE), + .AWPROT_i(HP_AWPROT), + .AWREGION_i(HP_AWREGION), + .AWUSER_i(HP_AWUSER), + .AWQOS_i(HP_AWQOS), + .AWVALID_i(HP_AWVALID), + .AWREADY_o(HP_AWREADY), + .WDATA_i(HP_WDATA), + .WSTRB_i(HP_WSTRB), + .WLAST_i(HP_WLAST), + .WUSER_i(HP_WUSER), + .WVALID_i(HP_WVALID), + .WREADY_o(HP_WREADY), + .BID_o(HP_BID), + .BRESP_o(HP_BRESP), + .BVALID_o(HP_BVALID), + .BUSER_o(HP_BUSER), + .BREADY_i(HP_BREADY), + .MEM_CEN_o(HP_W_cen), + .MEM_WEN_o(HP_W_wen), + .MEM_A_o(HP_W_addr), + .MEM_D_o(HP_wdata), + .MEM_BE_o(HP_be), + .MEM_Q_i(1'sb0), + .grant_i(grant_W_HP), + .valid_o(valid_W_HP) + ); + axi_read_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) R_CTRL_HP( + .clk(ACLK), + .rst_n(ARESETn), + .ARID_i(HP_ARID), + .ARADDR_i(HP_ARADDR), + .ARLEN_i(HP_ARLEN), + .ARSIZE_i(HP_ARSIZE), + .ARBURST_i(HP_ARBURST), + .ARLOCK_i(HP_ARLOCK), + .ARCACHE_i(HP_ARCACHE), + .ARPROT_i(HP_ARPROT), + .ARREGION_i(HP_ARREGION), + .ARUSER_i(HP_ARUSER), + .ARQOS_i(HP_ARQOS), + .ARVALID_i(HP_ARVALID), + .ARREADY_o(HP_ARREADY), + .RID_o(HP_RID), + .RDATA_o(HP_RDATA), + .RRESP_o(HP_RRESP), + .RLAST_o(HP_RLAST), + .RUSER_o(HP_RUSER), + .RVALID_o(HP_RVALID), + .RREADY_i(HP_RREADY), + .MEM_CEN_o(HP_R_cen), + .MEM_WEN_o(HP_R_wen), + .MEM_A_o(HP_R_addr), + .MEM_D_o(), + .MEM_BE_o(), + .MEM_Q_i(Q), + .grant_i(grant_R_HP), + .valid_o(valid_R_HP) + ); + axi_write_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) W_CTRL_LP( + .clk(ACLK), + .rst_n(ARESETn), + .AWID_i(LP_AWID), + .AWADDR_i(LP_AWADDR), + .AWLEN_i(LP_AWLEN), + .AWSIZE_i(LP_AWSIZE), + .AWBURST_i(LP_AWBURST), + .AWLOCK_i(LP_AWLOCK), + .AWCACHE_i(LP_AWCACHE), + .AWPROT_i(LP_AWPROT), + .AWREGION_i(LP_AWREGION), + .AWUSER_i(LP_AWUSER), + .AWQOS_i(LP_AWQOS), + .AWVALID_i(LP_AWVALID), + .AWREADY_o(LP_AWREADY), + .WDATA_i(LP_WDATA), + .WSTRB_i(LP_WSTRB), + .WLAST_i(LP_WLAST), + .WUSER_i(LP_WUSER), + .WVALID_i(LP_WVALID), + .WREADY_o(LP_WREADY), + .BID_o(LP_BID), + .BRESP_o(LP_BRESP), + .BVALID_o(LP_BVALID), + .BUSER_o(LP_BUSER), + .BREADY_i(LP_BREADY), + .MEM_CEN_o(LP_W_cen), + .MEM_WEN_o(LP_W_wen), + .MEM_A_o(LP_W_addr), + .MEM_D_o(LP_wdata), + .MEM_BE_o(LP_be), + .MEM_Q_i(1'sb0), + .grant_i(grant_W_LP), + .valid_o(valid_W_LP) + ); + axi_read_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) R_CTRL_LP( + .clk(ACLK), + .rst_n(ARESETn), + .ARID_i(LP_ARID), + .ARADDR_i(LP_ARADDR), + .ARLEN_i(LP_ARLEN), + .ARSIZE_i(LP_ARSIZE), + .ARBURST_i(LP_ARBURST), + .ARLOCK_i(LP_ARLOCK), + .ARCACHE_i(LP_ARCACHE), + .ARPROT_i(LP_ARPROT), + .ARREGION_i(LP_ARREGION), + .ARUSER_i(LP_ARUSER), + .ARQOS_i(LP_ARQOS), + .ARVALID_i(LP_ARVALID), + .ARREADY_o(LP_ARREADY), + .RID_o(LP_RID), + .RDATA_o(LP_RDATA), + .RRESP_o(LP_RRESP), + .RLAST_o(LP_RLAST), + .RUSER_o(LP_RUSER), + .RVALID_o(LP_RVALID), + .RREADY_i(LP_RREADY), + .MEM_CEN_o(LP_R_cen), + .MEM_WEN_o(LP_R_wen), + .MEM_A_o(LP_R_addr), + .MEM_D_o(), + .MEM_BE_o(), + .MEM_Q_i(Q), + .grant_i(grant_R_LP), + .valid_o(valid_R_LP) + ); + always @(*) begin : _MUX_MEM_ + if (valid_R_HP & grant_R_HP) begin + HP_cen = HP_R_cen; + HP_wen = 1'b1; + HP_addr = HP_R_addr; + end + else begin + HP_cen = HP_W_cen; + HP_wen = 1'b0; + HP_addr = HP_W_addr; + end + if (valid_R_LP & grant_R_LP) begin + LP_cen = LP_R_cen; + LP_wen = 1'b1; + LP_addr = LP_R_addr; + end + else begin + LP_cen = LP_W_cen; + LP_wen = 1'b0; + LP_addr = LP_W_addr; + end + if ((valid_R_HP | valid_W_HP) & main_grant_HP) begin + CEN = HP_cen; + WEN = HP_wen; + A = HP_addr; + D = HP_wdata; + BE = HP_be; + end + else begin + CEN = LP_cen; + WEN = LP_wen; + A = LP_addr; + D = LP_wdata; + BE = LP_be; + end + end + always @(posedge ACLK or negedge ARESETn) begin : MUX_RDATA_MEM + if (~ARESETn) + destination <= 1'sb0; + else if (valid_R_HP & main_grant_HP) + destination <= 1'b1; + else + destination <= 1'b0; + end + always @(posedge ACLK or negedge ARESETn) + if (~ARESETn) + RR_FLAG_HP <= 0; + else + RR_FLAG_HP <= ~RR_FLAG_HP; + always @(posedge ACLK or negedge ARESETn) + if (~ARESETn) + RR_FLAG_LP <= 0; + else + RR_FLAG_LP <= ~RR_FLAG_LP; + always @(*) begin + grant_R_HP = 1'b0; + grant_W_HP = 1'b0; + case (RR_FLAG_HP) + 1'b0: + if (valid_W_HP) + grant_W_HP = main_grant_HP; + else + grant_R_HP = main_grant_HP; + 1'b1: + if (valid_R_HP) + grant_R_HP = main_grant_HP; + else + grant_W_HP = main_grant_HP; + endcase + end + always @(*) begin + grant_R_LP = 1'b0; + grant_W_LP = 1'b0; + case (RR_FLAG_LP) + 1'b0: + if (valid_W_LP) + grant_W_LP = main_grant_LP; + else + grant_R_LP = main_grant_LP; + 1'b1: + if (valid_R_LP) + grant_R_LP = main_grant_LP; + else + grant_W_LP = main_grant_LP; + endcase + end + always @(*) begin + main_grant_LP = 1'b0; + main_grant_HP = 1'b0; + if (valid_R_HP | valid_W_HP) + main_grant_HP = 1'b1; + else + main_grant_LP = 1'b1; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_DP_hybr.v b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_DP_hybr.v new file mode 100644 index 0000000..a623ee5 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_DP_hybr.v
@@ -0,0 +1,484 @@ +module axi_mem_if_DP_hybr +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + parameter MEM_ADDR_WIDTH = 13, + parameter BUFF_DEPTH_SLAVE = 4 +) +( + ACLK, + ARESETn, + test_en_i, + LP_AWID_i, + LP_AWADDR_i, + LP_AWLEN_i, + LP_AWSIZE_i, + LP_AWBURST_i, + LP_AWLOCK_i, + LP_AWCACHE_i, + LP_AWPROT_i, + LP_AWREGION_i, + LP_AWUSER_i, + LP_AWQOS_i, + LP_AWVALID_i, + LP_AWREADY_o, + LP_WDATA_i, + LP_WSTRB_i, + LP_WLAST_i, + LP_WUSER_i, + LP_WVALID_i, + LP_WREADY_o, + LP_BID_o, + LP_BRESP_o, + LP_BVALID_o, + LP_BUSER_o, + LP_BREADY_i, + LP_ARID_i, + LP_ARADDR_i, + LP_ARLEN_i, + LP_ARSIZE_i, + LP_ARBURST_i, + LP_ARLOCK_i, + LP_ARCACHE_i, + LP_ARPROT_i, + LP_ARREGION_i, + LP_ARUSER_i, + LP_ARQOS_i, + LP_ARVALID_i, + LP_ARREADY_o, + LP_RID_o, + LP_RDATA_o, + LP_RRESP_o, + LP_RLAST_o, + LP_RUSER_o, + LP_RVALID_o, + LP_RREADY_i, + HP_cen_i, + HP_wen_i, + HP_addr_i, + HP_wdata_i, + HP_be_i, + HP_Q_o, + CEN, + WEN, + A, + D, + BE, + Q +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter MEM_ADDR_WIDTH = 13; + //parameter BUFF_DEPTH_SLAVE = 4; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] LP_AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] LP_AWADDR_i; + input wire [7:0] LP_AWLEN_i; + input wire [2:0] LP_AWSIZE_i; + input wire [1:0] LP_AWBURST_i; + input wire LP_AWLOCK_i; + input wire [3:0] LP_AWCACHE_i; + input wire [2:0] LP_AWPROT_i; + input wire [3:0] LP_AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_AWUSER_i; + input wire [3:0] LP_AWQOS_i; + input wire LP_AWVALID_i; + output wire LP_AWREADY_o; + input wire [(AXI_NUMBYTES * 8) - 1:0] LP_WDATA_i; + input wire [AXI_NUMBYTES - 1:0] LP_WSTRB_i; + input wire LP_WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_WUSER_i; + input wire LP_WVALID_i; + output wire LP_WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] LP_BID_o; + output wire [1:0] LP_BRESP_o; + output wire LP_BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] LP_BUSER_o; + input wire LP_BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] LP_ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] LP_ARADDR_i; + input wire [7:0] LP_ARLEN_i; + input wire [2:0] LP_ARSIZE_i; + input wire [1:0] LP_ARBURST_i; + input wire LP_ARLOCK_i; + input wire [3:0] LP_ARCACHE_i; + input wire [2:0] LP_ARPROT_i; + input wire [3:0] LP_ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_ARUSER_i; + input wire [3:0] LP_ARQOS_i; + input wire LP_ARVALID_i; + output wire LP_ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] LP_RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] LP_RDATA_o; + output wire [1:0] LP_RRESP_o; + output wire LP_RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] LP_RUSER_o; + output wire LP_RVALID_o; + input wire LP_RREADY_i; + input wire HP_cen_i; + input wire HP_wen_i; + input wire [MEM_ADDR_WIDTH - 1:0] HP_addr_i; + input wire [AXI4_WDATA_WIDTH - 1:0] HP_wdata_i; + input wire [AXI_NUMBYTES - 1:0] HP_be_i; + output wire [AXI4_RDATA_WIDTH - 1:0] HP_Q_o; + output reg CEN; + output reg WEN; + output reg [MEM_ADDR_WIDTH - 1:0] A; + output reg [AXI4_WDATA_WIDTH - 1:0] D; + output reg [AXI_NUMBYTES - 1:0] BE; + input wire [AXI4_RDATA_WIDTH - 1:0] Q; + localparam OFFSET_BIT = $clog2(AXI4_WDATA_WIDTH) - 3; + wire [AXI4_ID_WIDTH - 1:0] LP_AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] LP_AWADDR; + wire [7:0] LP_AWLEN; + wire [2:0] LP_AWSIZE; + wire [1:0] LP_AWBURST; + wire LP_AWLOCK; + wire [3:0] LP_AWCACHE; + wire [2:0] LP_AWPROT; + wire [3:0] LP_AWREGION; + wire [AXI4_USER_WIDTH - 1:0] LP_AWUSER; + wire [3:0] LP_AWQOS; + wire LP_AWVALID; + wire LP_AWREADY; + wire [(AXI_NUMBYTES * 8) - 1:0] LP_WDATA; + wire [AXI_NUMBYTES - 1:0] LP_WSTRB; + wire LP_WLAST; + wire [AXI4_USER_WIDTH - 1:0] LP_WUSER; + wire LP_WVALID; + wire LP_WREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_BID; + wire [1:0] LP_BRESP; + wire LP_BVALID; + wire [AXI4_USER_WIDTH - 1:0] LP_BUSER; + wire LP_BREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] LP_ARADDR; + wire [7:0] LP_ARLEN; + wire [2:0] LP_ARSIZE; + wire [1:0] LP_ARBURST; + wire LP_ARLOCK; + wire [3:0] LP_ARCACHE; + wire [2:0] LP_ARPROT; + wire [3:0] LP_ARREGION; + wire [AXI4_USER_WIDTH - 1:0] LP_ARUSER; + wire [3:0] LP_ARQOS; + wire LP_ARVALID; + wire LP_ARREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_RID; + wire [AXI4_RDATA_WIDTH - 1:0] LP_RDATA; + wire [1:0] LP_RRESP; + wire LP_RLAST; + wire [AXI4_USER_WIDTH - 1:0] LP_RUSER; + wire LP_RVALID; + wire LP_RREADY; + wire valid_R_LP; + wire valid_W_LP; + reg grant_R_LP; + reg grant_W_LP; + reg RR_FLAG_LP; + reg main_grant_LP; + wire LP_W_cen; + wire LP_R_cen; + reg LP_cen; + wire LP_W_wen; + wire LP_R_wen; + reg LP_wen; + wire [MEM_ADDR_WIDTH - 1:0] LP_W_addr; + wire [MEM_ADDR_WIDTH - 1:0] LP_R_addr; + reg [MEM_ADDR_WIDTH - 1:0] LP_addr; + wire [AXI4_WDATA_WIDTH - 1:0] LP_W_wdata; + wire [AXI4_WDATA_WIDTH - 1:0] LP_R_wdata; + wire [AXI4_WDATA_WIDTH - 1:0] LP_wdata; + wire [AXI_NUMBYTES - 1:0] LP_W_be; + wire [AXI_NUMBYTES - 1:0] LP_R_be; + wire [AXI_NUMBYTES - 1:0] LP_be; + wire [AXI_NUMBYTES - 1:0] LP_W_rdata; + wire [AXI_NUMBYTES - 1:0] LP_R_rdata; + wire [AXI_NUMBYTES - 1:0] LP_rdata; + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_AWVALID_i), + .slave_addr_i(LP_AWADDR_i), + .slave_prot_i(LP_AWPROT_i), + .slave_region_i(LP_AWREGION_i), + .slave_len_i(LP_AWLEN_i), + .slave_size_i(LP_AWSIZE_i), + .slave_burst_i(LP_AWBURST_i), + .slave_lock_i(LP_AWLOCK_i), + .slave_cache_i(LP_AWCACHE_i), + .slave_qos_i(LP_AWQOS_i), + .slave_id_i(LP_AWID_i), + .slave_user_i(LP_AWUSER_i), + .slave_ready_o(LP_AWREADY_o), + .master_valid_o(LP_AWVALID), + .master_addr_o(LP_AWADDR), + .master_prot_o(LP_AWPROT), + .master_region_o(LP_AWREGION), + .master_len_o(LP_AWLEN), + .master_size_o(LP_AWSIZE), + .master_burst_o(LP_AWBURST), + .master_lock_o(LP_AWLOCK), + .master_cache_o(LP_AWCACHE), + .master_qos_o(LP_AWQOS), + .master_id_o(LP_AWID), + .master_user_o(LP_AWUSER), + .master_ready_i(LP_AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_ARVALID_i), + .slave_addr_i(LP_ARADDR_i), + .slave_prot_i(LP_ARPROT_i), + .slave_region_i(LP_ARREGION_i), + .slave_len_i(LP_ARLEN_i), + .slave_size_i(LP_ARSIZE_i), + .slave_burst_i(LP_ARBURST_i), + .slave_lock_i(LP_ARLOCK_i), + .slave_cache_i(LP_ARCACHE_i), + .slave_qos_i(LP_ARQOS_i), + .slave_id_i(LP_ARID_i), + .slave_user_i(LP_ARUSER_i), + .slave_ready_o(LP_ARREADY_o), + .master_valid_o(LP_ARVALID), + .master_addr_o(LP_ARADDR), + .master_prot_o(LP_ARPROT), + .master_region_o(LP_ARREGION), + .master_len_o(LP_ARLEN), + .master_size_o(LP_ARSIZE), + .master_burst_o(LP_ARBURST), + .master_lock_o(LP_ARLOCK), + .master_cache_o(LP_ARCACHE), + .master_qos_o(LP_ARQOS), + .master_id_o(LP_ARID), + .master_user_o(LP_ARUSER), + .master_ready_i(LP_ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_WVALID_i), + .slave_data_i(LP_WDATA_i), + .slave_strb_i(LP_WSTRB_i), + .slave_user_i(LP_WUSER_i), + .slave_last_i(LP_WLAST_i), + .slave_ready_o(LP_WREADY_o), + .master_valid_o(LP_WVALID), + .master_data_o(LP_WDATA), + .master_strb_o(LP_WSTRB), + .master_user_o(LP_WUSER), + .master_last_o(LP_WLAST), + .master_ready_i(LP_WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_RVALID), + .slave_data_i(LP_RDATA), + .slave_resp_i(LP_RRESP), + .slave_user_i(LP_RUSER), + .slave_id_i(LP_RID), + .slave_last_i(LP_RLAST), + .slave_ready_o(LP_RREADY), + .master_valid_o(LP_RVALID_o), + .master_data_o(LP_RDATA_o), + .master_resp_o(LP_RRESP_o), + .master_user_o(LP_RUSER_o), + .master_id_o(LP_RID_o), + .master_last_o(LP_RLAST_o), + .master_ready_i(LP_RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_BVALID), + .slave_resp_i(LP_BRESP), + .slave_id_i(LP_BID), + .slave_user_i(LP_BUSER), + .slave_ready_o(LP_BREADY), + .master_valid_o(LP_BVALID_o), + .master_resp_o(LP_BRESP_o), + .master_id_o(LP_BID_o), + .master_user_o(LP_BUSER_o), + .master_ready_i(LP_BREADY_i) + ); + axi_write_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) W_CTRL_LP( + .clk(ACLK), + .rst_n(ARESETn), + .AWID_i(LP_AWID), + .AWADDR_i(LP_AWADDR), + .AWLEN_i(LP_AWLEN), + .AWSIZE_i(LP_AWSIZE), + .AWBURST_i(LP_AWBURST), + .AWLOCK_i(LP_AWLOCK), + .AWCACHE_i(LP_AWCACHE), + .AWPROT_i(LP_AWPROT), + .AWREGION_i(LP_AWREGION), + .AWUSER_i(LP_AWUSER), + .AWQOS_i(LP_AWQOS), + .AWVALID_i(LP_AWVALID), + .AWREADY_o(LP_AWREADY), + .WDATA_i(LP_WDATA), + .WSTRB_i(LP_WSTRB), + .WLAST_i(LP_WLAST), + .WUSER_i(LP_WUSER), + .WVALID_i(LP_WVALID), + .WREADY_o(LP_WREADY), + .BID_o(LP_BID), + .BRESP_o(LP_BRESP), + .BVALID_o(LP_BVALID), + .BUSER_o(LP_BUSER), + .BREADY_i(LP_BREADY), + .MEM_CEN_o(LP_W_cen), + .MEM_WEN_o(LP_W_wen), + .MEM_A_o(LP_W_addr), + .MEM_D_o(LP_W_wdata), + .MEM_BE_o(LP_W_be), + .MEM_Q_i(1'sb0), + .grant_i(grant_W_LP & HP_cen_i), + .valid_o(valid_W_LP) + ); + axi_read_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) R_CTRL_LP( + .clk(ACLK), + .rst_n(ARESETn), + .ARID_i(LP_ARID), + .ARADDR_i(LP_ARADDR), + .ARLEN_i(LP_ARLEN), + .ARSIZE_i(LP_ARSIZE), + .ARBURST_i(LP_ARBURST), + .ARLOCK_i(LP_ARLOCK), + .ARCACHE_i(LP_ARCACHE), + .ARPROT_i(LP_ARPROT), + .ARREGION_i(LP_ARREGION), + .ARUSER_i(LP_ARUSER), + .ARQOS_i(LP_ARQOS), + .ARVALID_i(LP_ARVALID), + .ARREADY_o(LP_ARREADY), + .RID_o(LP_RID), + .RDATA_o(LP_RDATA), + .RRESP_o(LP_RRESP), + .RLAST_o(LP_RLAST), + .RUSER_o(LP_RUSER), + .RVALID_o(LP_RVALID), + .RREADY_i(LP_RREADY), + .MEM_CEN_o(LP_R_cen), + .MEM_WEN_o(LP_R_wen), + .MEM_A_o(LP_R_addr), + .MEM_D_o(), + .MEM_BE_o(), + .MEM_Q_i(Q), + .grant_i(grant_R_LP & HP_cen_i), + .valid_o(valid_R_LP) + ); + assign LP_wdata = LP_W_wdata; + assign LP_be = LP_W_be; + always @(*) begin : _MUX_MEM_ + if (HP_cen_i == 1'b0) begin + CEN = HP_cen_i; + WEN = HP_wen_i; + A = HP_addr_i; + D = HP_wdata_i; + BE = HP_be_i; + end + else begin + if (grant_R_LP) begin + LP_cen = LP_R_cen; + LP_wen = 1'b1; + LP_addr = LP_R_addr; + end + else begin + LP_cen = LP_W_cen; + LP_wen = ~grant_W_LP; + LP_addr = LP_W_addr; + end + CEN = LP_cen; + WEN = LP_wen; + A = LP_addr; + D = LP_W_wdata; + BE = LP_W_be; + end + end + always @(posedge ACLK or negedge ARESETn) + if (~ARESETn) + RR_FLAG_LP <= 0; + else + RR_FLAG_LP <= ~RR_FLAG_LP; + always @(*) begin + grant_R_LP = 1'b0; + grant_W_LP = 1'b0; + case (RR_FLAG_LP) + 1'b0: + if (valid_W_LP) + grant_W_LP = 1'b1; + else + grant_R_LP = 1'b1; + 1'b1: + if (valid_R_LP) + grant_R_LP = 1'b1; + else + grant_W_LP = 1'b1; + endcase + end + always @(*) begin + main_grant_LP = 1'b0; + if (HP_cen_i == 1'b1) + main_grant_LP = 1'b1; + end + assign HP_Q_o = Q; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.v b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.v new file mode 100644 index 0000000..08aaaaa --- /dev/null +++ b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.v
@@ -0,0 +1,523 @@ +module axi_mem_if_MP_Hybrid_multi_bank +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + + parameter MEM_ADDR_WIDTH = 13, + parameter BUFF_DEPTH_SLAVE = 4, + parameter NB_L2_BANKS = 4, + + parameter N_CH0 = 1, + parameter N_CH1 = 3 +) +( + ACLK, + ARESETn, + test_en_i, + CH0_AWID_i, + CH0_AWADDR_i, + CH0_AWLEN_i, + CH0_AWSIZE_i, + CH0_AWBURST_i, + CH0_AWLOCK_i, + CH0_AWCACHE_i, + CH0_AWPROT_i, + CH0_AWREGION_i, + CH0_AWUSER_i, + CH0_AWQOS_i, + CH0_AWVALID_i, + CH0_AWREADY_o, + CH0_WDATA_i, + CH0_WSTRB_i, + CH0_WLAST_i, + CH0_WUSER_i, + CH0_WVALID_i, + CH0_WREADY_o, + CH0_BID_o, + CH0_BRESP_o, + CH0_BVALID_o, + CH0_BUSER_o, + CH0_BREADY_i, + CH0_ARID_i, + CH0_ARADDR_i, + CH0_ARLEN_i, + CH0_ARSIZE_i, + CH0_ARBURST_i, + CH0_ARLOCK_i, + CH0_ARCACHE_i, + CH0_ARPROT_i, + CH0_ARREGION_i, + CH0_ARUSER_i, + CH0_ARQOS_i, + CH0_ARVALID_i, + CH0_ARREADY_o, + CH0_RID_o, + CH0_RDATA_o, + CH0_RRESP_o, + CH0_RLAST_o, + CH0_RUSER_o, + CH0_RVALID_o, + CH0_RREADY_i, + CH1_req_i, + CH1_gnt_o, + CH1_wen_i, + CH1_addr_i, + CH1_wdata_i, + CH1_be_i, + CH1_rdata_o, + CH1_rvalid_o, + CEN, + WEN, + A, + D, + BE, + Q +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter MEM_ADDR_WIDTH = 13; + //parameter BUFF_DEPTH_SLAVE = 4; + //parameter NB_L2_BANKS = 4; + //parameter N_CH0 = 1; + //parameter N_CH1 = 3; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_AWID_i; + input wire [(N_CH0 * AXI4_ADDRESS_WIDTH) - 1:0] CH0_AWADDR_i; + input wire [(N_CH0 * 8) - 1:0] CH0_AWLEN_i; + input wire [(N_CH0 * 3) - 1:0] CH0_AWSIZE_i; + input wire [(N_CH0 * 2) - 1:0] CH0_AWBURST_i; + input wire [N_CH0 - 1:0] CH0_AWLOCK_i; + input wire [(N_CH0 * 4) - 1:0] CH0_AWCACHE_i; + input wire [(N_CH0 * 3) - 1:0] CH0_AWPROT_i; + input wire [(N_CH0 * 4) - 1:0] CH0_AWREGION_i; + input wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_AWUSER_i; + input wire [(N_CH0 * 4) - 1:0] CH0_AWQOS_i; + input wire [N_CH0 - 1:0] CH0_AWVALID_i; + output wire [N_CH0 - 1:0] CH0_AWREADY_o; + input wire [((N_CH0 * AXI_NUMBYTES) * 8) - 1:0] CH0_WDATA_i; + input wire [(N_CH0 * AXI_NUMBYTES) - 1:0] CH0_WSTRB_i; + input wire [N_CH0 - 1:0] CH0_WLAST_i; + input wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_WUSER_i; + input wire [N_CH0 - 1:0] CH0_WVALID_i; + output wire [N_CH0 - 1:0] CH0_WREADY_o; + output wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_BID_o; + output wire [(N_CH0 * 2) - 1:0] CH0_BRESP_o; + output wire [N_CH0 - 1:0] CH0_BVALID_o; + output wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_BUSER_o; + input wire [N_CH0 - 1:0] CH0_BREADY_i; + input wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_ARID_i; + input wire [(N_CH0 * AXI4_ADDRESS_WIDTH) - 1:0] CH0_ARADDR_i; + input wire [(N_CH0 * 8) - 1:0] CH0_ARLEN_i; + input wire [(N_CH0 * 3) - 1:0] CH0_ARSIZE_i; + input wire [(N_CH0 * 2) - 1:0] CH0_ARBURST_i; + input wire [N_CH0 - 1:0] CH0_ARLOCK_i; + input wire [(N_CH0 * 4) - 1:0] CH0_ARCACHE_i; + input wire [(N_CH0 * 3) - 1:0] CH0_ARPROT_i; + input wire [(N_CH0 * 4) - 1:0] CH0_ARREGION_i; + input wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_ARUSER_i; + input wire [(N_CH0 * 4) - 1:0] CH0_ARQOS_i; + input wire [N_CH0 - 1:0] CH0_ARVALID_i; + output wire [N_CH0 - 1:0] CH0_ARREADY_o; + output wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_RID_o; + output wire [(N_CH0 * AXI4_RDATA_WIDTH) - 1:0] CH0_RDATA_o; + output wire [(N_CH0 * 2) - 1:0] CH0_RRESP_o; + output wire [N_CH0 - 1:0] CH0_RLAST_o; + output wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_RUSER_o; + output wire [N_CH0 - 1:0] CH0_RVALID_o; + input wire [N_CH0 - 1:0] CH0_RREADY_i; + input wire [N_CH1 - 1:0] CH1_req_i; + output wire [N_CH1 - 1:0] CH1_gnt_o; + input wire [N_CH1 - 1:0] CH1_wen_i; + input wire [(N_CH1 * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))) - 1:0] CH1_addr_i; + input wire [(N_CH1 * AXI4_WDATA_WIDTH) - 1:0] CH1_wdata_i; + input wire [(N_CH1 * AXI_NUMBYTES) - 1:0] CH1_be_i; + output wire [(N_CH1 * AXI4_RDATA_WIDTH) - 1:0] CH1_rdata_o; + output wire [N_CH1 - 1:0] CH1_rvalid_o; + output wire [NB_L2_BANKS - 1:0] CEN; + output wire [NB_L2_BANKS - 1:0] WEN; + output wire [(NB_L2_BANKS * MEM_ADDR_WIDTH) - 1:0] A; + output wire [(NB_L2_BANKS * AXI4_WDATA_WIDTH) - 1:0] D; + output wire [(NB_L2_BANKS * AXI_NUMBYTES) - 1:0] BE; + input wire [(NB_L2_BANKS * AXI4_RDATA_WIDTH) - 1:0] Q; + localparam OFFSET_BIT = $clog2(AXI4_WDATA_WIDTH) - 3; + wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_AWID; + wire [(N_CH0 * AXI4_ADDRESS_WIDTH) - 1:0] CH0_AWADDR; + wire [(N_CH0 * 8) - 1:0] CH0_AWLEN; + wire [(N_CH0 * 3) - 1:0] CH0_AWSIZE; + wire [(N_CH0 * 2) - 1:0] CH0_AWBURST; + wire [N_CH0 - 1:0] CH0_AWLOCK; + wire [(N_CH0 * 4) - 1:0] CH0_AWCACHE; + wire [(N_CH0 * 3) - 1:0] CH0_AWPROT; + wire [(N_CH0 * 4) - 1:0] CH0_AWREGION; + wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_AWUSER; + wire [(N_CH0 * 4) - 1:0] CH0_AWQOS; + wire [N_CH0 - 1:0] CH0_AWVALID; + wire [N_CH0 - 1:0] CH0_AWREADY; + wire [((N_CH0 * AXI_NUMBYTES) * 8) - 1:0] CH0_WDATA; + wire [(N_CH0 * AXI_NUMBYTES) - 1:0] CH0_WSTRB; + wire [N_CH0 - 1:0] CH0_WLAST; + wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_WUSER; + wire [N_CH0 - 1:0] CH0_WVALID; + wire [N_CH0 - 1:0] CH0_WREADY; + wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_BID; + wire [(N_CH0 * 2) - 1:0] CH0_BRESP; + wire [N_CH0 - 1:0] CH0_BVALID; + wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_BUSER; + wire [N_CH0 - 1:0] CH0_BREADY; + wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_ARID; + wire [(N_CH0 * AXI4_ADDRESS_WIDTH) - 1:0] CH0_ARADDR; + wire [(N_CH0 * 8) - 1:0] CH0_ARLEN; + wire [(N_CH0 * 3) - 1:0] CH0_ARSIZE; + wire [(N_CH0 * 2) - 1:0] CH0_ARBURST; + wire [N_CH0 - 1:0] CH0_ARLOCK; + wire [(N_CH0 * 4) - 1:0] CH0_ARCACHE; + wire [(N_CH0 * 3) - 1:0] CH0_ARPROT; + wire [(N_CH0 * 4) - 1:0] CH0_ARREGION; + wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_ARUSER; + wire [(N_CH0 * 4) - 1:0] CH0_ARQOS; + wire [N_CH0 - 1:0] CH0_ARVALID; + wire [N_CH0 - 1:0] CH0_ARREADY; + wire [(N_CH0 * AXI4_ID_WIDTH) - 1:0] CH0_RID; + wire [(N_CH0 * AXI4_RDATA_WIDTH) - 1:0] CH0_RDATA; + wire [(N_CH0 * 2) - 1:0] CH0_RRESP; + wire [N_CH0 - 1:0] CH0_RLAST; + wire [(N_CH0 * AXI4_USER_WIDTH) - 1:0] CH0_RUSER; + wire [N_CH0 - 1:0] CH0_RVALID; + wire [N_CH0 - 1:0] CH0_RREADY; + wire [N_CH0 - 1:0] valid_R_CH0; + wire [N_CH0 - 1:0] valid_W_CH0; + wire [N_CH0 - 1:0] grant_R_CH0; + wire [N_CH0 - 1:0] grant_W_CH0; + wire [N_CH1 - 1:0] valid_CH1; + wire [N_CH0 - 1:0] CH0_W_cen; + wire [N_CH0 - 1:0] CH0_R_cen; + wire [N_CH0 - 1:0] CH0_W_wen; + wire [N_CH0 - 1:0] CH0_R_wen; + wire [(N_CH0 * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))) - 1:0] CH0_W_addr; + wire [(N_CH0 * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))) - 1:0] CH0_R_addr; + wire [(N_CH0 * AXI4_WDATA_WIDTH) - 1:0] CH0_W_wdata; + wire [(N_CH0 * AXI4_WDATA_WIDTH) - 1:0] CH0_R_wdata; + wire [(N_CH0 * AXI_NUMBYTES) - 1:0] CH0_W_be; + wire [(N_CH0 * AXI_NUMBYTES) - 1:0] CH0_R_be; + wire [(N_CH0 * AXI4_WDATA_WIDTH) - 1:0] CH0_W_rdata; + wire [(N_CH0 * AXI4_WDATA_WIDTH) - 1:0] CH0_R_rdata; + wire [((2 * N_CH0) + N_CH1) - 1:0] req_int; + wire [(((2 * N_CH0) + N_CH1) * ((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS))) - 1:0] add_int; + wire [((2 * N_CH0) + N_CH1) - 1:0] wen_int; + wire [(((2 * N_CH0) + N_CH1) * AXI4_WDATA_WIDTH) - 1:0] wdata_int; + wire [(((2 * N_CH0) + N_CH1) * (AXI4_WDATA_WIDTH / 8)) - 1:0] be_int; + wire [((2 * N_CH0) + N_CH1) - 1:0] gnt_int; + wire [(((2 * N_CH0) + N_CH1) * AXI4_WDATA_WIDTH) - 1:0] r_rdata_int; + wire [((2 * N_CH0) + N_CH1) - 1:0] r_valid_int; + wire [(NB_L2_BANKS * AXI4_WDATA_WIDTH) - 1:0] mem_wdata; + wire [(NB_L2_BANKS * MEM_ADDR_WIDTH) - 1:0] mem_add; + wire [NB_L2_BANKS - 1:0] mem_req; + wire [NB_L2_BANKS - 1:0] mem_wen; + wire [(NB_L2_BANKS * (AXI4_WDATA_WIDTH / 8)) - 1:0] mem_be; + wire [(NB_L2_BANKS * AXI4_WDATA_WIDTH) - 1:0] mem_rdata; + genvar i; + generate + for (i = 0; i < N_CH0; i = i + 1) begin : AW_BUF + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(CH0_AWVALID_i[i]), + .slave_addr_i(CH0_AWADDR_i[i * AXI4_ADDRESS_WIDTH+:AXI4_ADDRESS_WIDTH]), + .slave_prot_i(CH0_AWPROT_i[i * 3+:3]), + .slave_region_i(CH0_AWREGION_i[i * 4+:4]), + .slave_len_i(CH0_AWLEN_i[i * 8+:8]), + .slave_size_i(CH0_AWSIZE_i[i * 3+:3]), + .slave_burst_i(CH0_AWBURST_i[i * 2+:2]), + .slave_lock_i(CH0_AWLOCK_i[i]), + .slave_cache_i(CH0_AWCACHE_i[i * 4+:4]), + .slave_qos_i(CH0_AWQOS_i[i * 4+:4]), + .slave_id_i(CH0_AWID_i[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .slave_user_i(CH0_AWUSER_i[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .slave_ready_o(CH0_AWREADY_o[i]), + .master_valid_o(CH0_AWVALID[i]), + .master_addr_o(CH0_AWADDR[i * AXI4_ADDRESS_WIDTH+:AXI4_ADDRESS_WIDTH]), + .master_prot_o(CH0_AWPROT[i * 3+:3]), + .master_region_o(CH0_AWREGION[i * 4+:4]), + .master_len_o(CH0_AWLEN[i * 8+:8]), + .master_size_o(CH0_AWSIZE[i * 3+:3]), + .master_burst_o(CH0_AWBURST[i * 2+:2]), + .master_lock_o(CH0_AWLOCK[i]), + .master_cache_o(CH0_AWCACHE[i * 4+:4]), + .master_qos_o(CH0_AWQOS[i * 4+:4]), + .master_id_o(CH0_AWID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .master_user_o(CH0_AWUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .master_ready_i(CH0_AWREADY[i]) + ); + end + for (i = 0; i < N_CH0; i = i + 1) begin : AR_BUF + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(CH0_ARVALID_i[i]), + .slave_addr_i(CH0_ARADDR_i[i * AXI4_ADDRESS_WIDTH+:AXI4_ADDRESS_WIDTH]), + .slave_prot_i(CH0_ARPROT_i[i * 3+:3]), + .slave_region_i(CH0_ARREGION_i[i * 4+:4]), + .slave_len_i(CH0_ARLEN_i[i * 8+:8]), + .slave_size_i(CH0_ARSIZE_i[i * 3+:3]), + .slave_burst_i(CH0_ARBURST_i[i * 2+:2]), + .slave_lock_i(CH0_ARLOCK_i[i]), + .slave_cache_i(CH0_ARCACHE_i[i * 4+:4]), + .slave_qos_i(CH0_ARQOS_i[i * 4+:4]), + .slave_id_i(CH0_ARID_i[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .slave_user_i(CH0_ARUSER_i[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .slave_ready_o(CH0_ARREADY_o[i]), + .master_valid_o(CH0_ARVALID[i]), + .master_addr_o(CH0_ARADDR[i * AXI4_ADDRESS_WIDTH+:AXI4_ADDRESS_WIDTH]), + .master_prot_o(CH0_ARPROT[i * 3+:3]), + .master_region_o(CH0_ARREGION[i * 4+:4]), + .master_len_o(CH0_ARLEN[i * 8+:8]), + .master_size_o(CH0_ARSIZE[i * 3+:3]), + .master_burst_o(CH0_ARBURST[i * 2+:2]), + .master_lock_o(CH0_ARLOCK[i]), + .master_cache_o(CH0_ARCACHE[i * 4+:4]), + .master_qos_o(CH0_ARQOS[i * 4+:4]), + .master_id_o(CH0_ARID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .master_user_o(CH0_ARUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .master_ready_i(CH0_ARREADY[i]) + ); + end + for (i = 0; i < N_CH0; i = i + 1) begin : W_BUF + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(CH0_WVALID_i[i]), + .slave_data_i(CH0_WDATA_i[8 * (i * AXI_NUMBYTES)+:8 * AXI_NUMBYTES]), + .slave_strb_i(CH0_WSTRB_i[i * AXI_NUMBYTES+:AXI_NUMBYTES]), + .slave_user_i(CH0_WUSER_i[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .slave_last_i(CH0_WLAST_i[i]), + .slave_ready_o(CH0_WREADY_o[i]), + .master_valid_o(CH0_WVALID[i]), + .master_data_o(CH0_WDATA[8 * (i * AXI_NUMBYTES)+:8 * AXI_NUMBYTES]), + .master_strb_o(CH0_WSTRB[i * AXI_NUMBYTES+:AXI_NUMBYTES]), + .master_user_o(CH0_WUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .master_last_o(CH0_WLAST[i]), + .master_ready_i(CH0_WREADY[i]) + ); + end + for (i = 0; i < N_CH0; i = i + 1) begin : R_BUF + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(CH0_RVALID[i]), + .slave_data_i(CH0_RDATA[i * AXI4_RDATA_WIDTH+:AXI4_RDATA_WIDTH]), + .slave_resp_i(CH0_RRESP[i * 2+:2]), + .slave_user_i(CH0_RUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .slave_id_i(CH0_RID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .slave_last_i(CH0_RLAST[i]), + .slave_ready_o(CH0_RREADY[i]), + .master_valid_o(CH0_RVALID_o[i]), + .master_data_o(CH0_RDATA_o[i * AXI4_RDATA_WIDTH+:AXI4_RDATA_WIDTH]), + .master_resp_o(CH0_RRESP_o[i * 2+:2]), + .master_user_o(CH0_RUSER_o[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .master_id_o(CH0_RID_o[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .master_last_o(CH0_RLAST_o[i]), + .master_ready_i(CH0_RREADY_i[i]) + ); + end + for (i = 0; i < N_CH0; i = i + 1) begin : B_BUF + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(CH0_BVALID[i]), + .slave_resp_i(CH0_BRESP[i * 2+:2]), + .slave_id_i(CH0_BID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .slave_user_i(CH0_BUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .slave_ready_o(CH0_BREADY[i]), + .master_valid_o(CH0_BVALID_o[i]), + .master_resp_o(CH0_BRESP_o[i * 2+:2]), + .master_id_o(CH0_BID_o[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .master_user_o(CH0_BUSER_o[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .master_ready_i(CH0_BREADY_i[i]) + ); + end + for (i = 0; i < N_CH0; i = i + 1) begin : WO_CTRL + axi_write_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)) + ) W_CTRL( + .clk(ACLK), + .rst_n(ARESETn), + .AWID_i(CH0_AWID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .AWADDR_i(CH0_AWADDR[i * AXI4_ADDRESS_WIDTH+:AXI4_ADDRESS_WIDTH]), + .AWLEN_i(CH0_AWLEN[i * 8+:8]), + .AWSIZE_i(CH0_AWSIZE[i * 3+:3]), + .AWBURST_i(CH0_AWBURST[i * 2+:2]), + .AWLOCK_i(CH0_AWLOCK[i]), + .AWCACHE_i(CH0_AWCACHE[i * 4+:4]), + .AWPROT_i(CH0_AWPROT[i * 3+:3]), + .AWREGION_i(CH0_AWREGION[i * 4+:4]), + .AWUSER_i(CH0_AWUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .AWQOS_i(CH0_AWQOS[i * 4+:4]), + .AWVALID_i(CH0_AWVALID[i]), + .AWREADY_o(CH0_AWREADY[i]), + .WDATA_i(CH0_WDATA[8 * (i * AXI_NUMBYTES)+:8 * AXI_NUMBYTES]), + .WSTRB_i(CH0_WSTRB[i * AXI_NUMBYTES+:AXI_NUMBYTES]), + .WLAST_i(CH0_WLAST[i]), + .WUSER_i(CH0_WUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .WVALID_i(CH0_WVALID[i]), + .WREADY_o(CH0_WREADY[i]), + .BID_o(CH0_BID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .BRESP_o(CH0_BRESP[i * 2+:2]), + .BVALID_o(CH0_BVALID[i]), + .BUSER_o(CH0_BUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .BREADY_i(CH0_BREADY[i]), + .MEM_CEN_o(CH0_W_cen[i]), + .MEM_WEN_o(CH0_W_wen[i]), + .MEM_A_o(CH0_W_addr[i * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))+:MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)]), + .MEM_D_o(CH0_W_wdata[i * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH]), + .MEM_BE_o(CH0_W_be[i * AXI_NUMBYTES+:AXI_NUMBYTES]), + .MEM_Q_i(1'sb0), + .grant_i(grant_W_CH0[i]), + .valid_o(valid_W_CH0[i]) + ); + end + for (i = 0; i < N_CH0; i = i + 1) begin : RO_CTRL + axi_read_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)) + ) R_CTRL_LP( + .clk(ACLK), + .rst_n(ARESETn), + .ARID_i(CH0_ARID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .ARADDR_i(CH0_ARADDR[i * AXI4_ADDRESS_WIDTH+:AXI4_ADDRESS_WIDTH]), + .ARLEN_i(CH0_ARLEN[i * 8+:8]), + .ARSIZE_i(CH0_ARSIZE[i * 3+:3]), + .ARBURST_i(CH0_ARBURST[i * 2+:2]), + .ARLOCK_i(CH0_ARLOCK[i]), + .ARCACHE_i(CH0_ARCACHE[i * 4+:4]), + .ARPROT_i(CH0_ARPROT[i * 3+:3]), + .ARREGION_i(CH0_ARREGION[i * 4+:4]), + .ARUSER_i(CH0_ARUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .ARQOS_i(CH0_ARQOS[i * 4+:4]), + .ARVALID_i(CH0_ARVALID[i]), + .ARREADY_o(CH0_ARREADY[i]), + .RID_o(CH0_RID[i * AXI4_ID_WIDTH+:AXI4_ID_WIDTH]), + .RDATA_o(CH0_RDATA[i * AXI4_RDATA_WIDTH+:AXI4_RDATA_WIDTH]), + .RRESP_o(CH0_RRESP[i * 2+:2]), + .RLAST_o(CH0_RLAST[i]), + .RUSER_o(CH0_RUSER[i * AXI4_USER_WIDTH+:AXI4_USER_WIDTH]), + .RVALID_o(CH0_RVALID[i]), + .RREADY_i(CH0_RREADY[i]), + .MEM_CEN_o(CH0_R_cen[i]), + .MEM_WEN_o(CH0_R_wen[i]), + .MEM_A_o(CH0_R_addr[i * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))+:MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)]), + .MEM_D_o(), + .MEM_BE_o(), + .MEM_Q_i(CH0_R_rdata[i * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH]), + .grant_i(grant_R_CH0[i]), + .valid_o(valid_R_CH0[i]) + ); + end + for (i = 0; i < N_CH0; i = i + 1) begin : BINDING_AXI_IF + assign req_int[2 * i] = valid_W_CH0[i]; + assign req_int[(2 * i) + 1] = valid_R_CH0[i]; + assign grant_W_CH0[i] = gnt_int[2 * i]; + assign grant_R_CH0[i] = gnt_int[(2 * i) + 1]; + assign add_int[(2 * i) * ((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS))+:(MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)] = {CH0_W_addr[i * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))+:MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)], 3'b000}; + assign add_int[((2 * i) + 1) * ((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS))+:(MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)] = {CH0_R_addr[i * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))+:MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)], 3'b000}; + assign wen_int[2 * i] = 1'b0; + assign wen_int[(2 * i) + 1] = 1'b1; + assign wdata_int[(2 * i) * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH] = CH0_W_wdata[i * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH]; + assign wdata_int[((2 * i) + 1) * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH] = 1'sb0; + assign be_int[(2 * i) * (AXI4_WDATA_WIDTH / 8)+:AXI4_WDATA_WIDTH / 8] = CH0_W_be[i * AXI_NUMBYTES+:AXI_NUMBYTES]; + assign be_int[((2 * i) + 1) * (AXI4_WDATA_WIDTH / 8)+:AXI4_WDATA_WIDTH / 8] = 1'sb0; + assign CH0_W_rdata[i * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH] = r_rdata_int[(2 * i) * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH]; + assign CH0_R_rdata[i * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH] = r_rdata_int[((2 * i) + 1) * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH]; + end + for (i = 0; i < N_CH1; i = i + 1) begin : BINDING_TCDM_IF + assign req_int[(2 * N_CH0) + i] = CH1_req_i[i]; + assign CH1_gnt_o[i] = gnt_int[(2 * N_CH0) + i]; + assign add_int[((2 * N_CH0) + i) * ((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS))+:(MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)] = {CH1_addr_i[i * (MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS))+:MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)], 3'b000}; + assign wen_int[(2 * N_CH0) + i] = CH1_wen_i[i]; + assign wdata_int[((2 * N_CH0) + i) * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH] = CH1_wdata_i[i * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH]; + assign be_int[((2 * N_CH0) + i) * (AXI4_WDATA_WIDTH / 8)+:AXI4_WDATA_WIDTH / 8] = CH1_be_i[i * AXI_NUMBYTES+:AXI_NUMBYTES]; + assign CH1_rdata_o[i * AXI4_RDATA_WIDTH+:AXI4_RDATA_WIDTH] = r_rdata_int[((2 * N_CH0) + i) * AXI4_WDATA_WIDTH+:AXI4_WDATA_WIDTH]; + assign CH1_rvalid_o[i] = r_valid_int[(2 * N_CH0) + i]; + end + endgenerate + XBAR_TCDM_FC #( + .N_CH0(2 * N_CH0), + .N_CH1(N_CH1), + .N_SLAVE(NB_L2_BANKS), + .ADDR_WIDTH((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)), + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .ADDR_MEM_WIDTH(MEM_ADDR_WIDTH), + .CH0_CH1_POLICY("RR") + ) L2_MB_INTERCO( + .data_req_i(req_int), + .data_add_i(add_int), + .data_wen_i(wen_int), + .data_wdata_i(wdata_int), + .data_be_i(be_int), + .data_gnt_o(gnt_int), + .data_r_valid_o(r_valid_int), + .data_r_rdata_o(r_rdata_int), + .data_req_o(mem_req), + .data_add_o(mem_add), + .data_wen_o(mem_wen), + .data_wdata_o(mem_wdata), + .data_be_o(mem_be), + .data_r_rdata_i(mem_rdata), + .clk(ACLK), + .rst_n(ARESETn) + ); + assign CEN = ~mem_req; + assign WEN = mem_wen; + assign A = mem_add; + assign D = mem_wdata; + assign BE = mem_be; + assign mem_rdata = Q; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_SP.v b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_SP.v new file mode 100644 index 0000000..31f6964 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_SP.v
@@ -0,0 +1,444 @@ +module axi_mem_if_SP +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 32, + parameter AXI4_WDATA_WIDTH = 32, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + parameter MEM_ADDR_WIDTH = 13, + parameter BUFF_DEPTH_SLAVE = 4 +) +( + ACLK, + ARESETn, + test_en_i, + AWID_i, + AWADDR_i, + AWLEN_i, + AWSIZE_i, + AWBURST_i, + AWLOCK_i, + AWCACHE_i, + AWPROT_i, + AWREGION_i, + AWUSER_i, + AWQOS_i, + AWVALID_i, + AWREADY_o, + WDATA_i, + WSTRB_i, + WLAST_i, + WUSER_i, + WVALID_i, + WREADY_o, + BID_o, + BRESP_o, + BVALID_o, + BUSER_o, + BREADY_i, + ARID_i, + ARADDR_i, + ARLEN_i, + ARSIZE_i, + ARBURST_i, + ARLOCK_i, + ARCACHE_i, + ARPROT_i, + ARREGION_i, + ARUSER_i, + ARQOS_i, + ARVALID_i, + ARREADY_o, + RID_o, + RDATA_o, + RRESP_o, + RLAST_o, + RUSER_o, + RVALID_o, + RREADY_i, + CEN_o, + WEN_o, + A_o, + D_o, + BE_o, + Q_i +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 32; + //parameter AXI4_WDATA_WIDTH = 32; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter MEM_ADDR_WIDTH = 13; + //parameter BUFF_DEPTH_SLAVE = 4; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR_i; + input wire [7:0] AWLEN_i; + input wire [2:0] AWSIZE_i; + input wire [1:0] AWBURST_i; + input wire AWLOCK_i; + input wire [3:0] AWCACHE_i; + input wire [2:0] AWPROT_i; + input wire [3:0] AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] AWUSER_i; + input wire [3:0] AWQOS_i; + input wire AWVALID_i; + output wire AWREADY_o; + input wire [(AXI_NUMBYTES * 8) - 1:0] WDATA_i; + input wire [AXI_NUMBYTES - 1:0] WSTRB_i; + input wire WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] WUSER_i; + input wire WVALID_i; + output wire WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] BID_o; + output wire [1:0] BRESP_o; + output wire BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] BUSER_o; + input wire BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR_i; + input wire [7:0] ARLEN_i; + input wire [2:0] ARSIZE_i; + input wire [1:0] ARBURST_i; + input wire ARLOCK_i; + input wire [3:0] ARCACHE_i; + input wire [2:0] ARPROT_i; + input wire [3:0] ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] ARUSER_i; + input wire [3:0] ARQOS_i; + input wire ARVALID_i; + output wire ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] RDATA_o; + output wire [1:0] RRESP_o; + output wire RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] RUSER_o; + output wire RVALID_o; + input wire RREADY_i; + output reg CEN_o; + output reg WEN_o; + output reg [MEM_ADDR_WIDTH - 1:0] A_o; + output reg [AXI4_WDATA_WIDTH - 1:0] D_o; + output reg [AXI_NUMBYTES - 1:0] BE_o; + input wire [AXI4_RDATA_WIDTH - 1:0] Q_i; + wire valid_R; + wire valid_W; + reg grant_R; + reg grant_W; + reg RR_FLAG; + wire [AXI4_ID_WIDTH - 1:0] AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR; + wire [7:0] AWLEN; + wire [2:0] AWSIZE; + wire [1:0] AWBURST; + wire AWLOCK; + wire [3:0] AWCACHE; + wire [2:0] AWPROT; + wire [3:0] AWREGION; + wire [AXI4_USER_WIDTH - 1:0] AWUSER; + wire [3:0] AWQOS; + wire AWVALID; + wire AWREADY; + wire [(AXI_NUMBYTES * 8) - 1:0] WDATA; + wire [AXI_NUMBYTES - 1:0] WSTRB; + wire WLAST; + wire [AXI4_USER_WIDTH - 1:0] WUSER; + wire WVALID; + wire WREADY; + wire [AXI4_ID_WIDTH - 1:0] BID; + wire [1:0] BRESP; + wire BVALID; + wire [AXI4_USER_WIDTH - 1:0] BUSER; + wire BREADY; + wire [AXI4_ID_WIDTH - 1:0] ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR; + wire [7:0] ARLEN; + wire [2:0] ARSIZE; + wire [1:0] ARBURST; + wire ARLOCK; + wire [3:0] ARCACHE; + wire [2:0] ARPROT; + wire [3:0] ARREGION; + wire [AXI4_USER_WIDTH - 1:0] ARUSER; + wire [3:0] ARQOS; + wire ARVALID; + wire ARREADY; + wire [AXI4_ID_WIDTH - 1:0] RID; + wire [AXI4_RDATA_WIDTH - 1:0] RDATA; + wire [1:0] RRESP; + wire RLAST; + wire [AXI4_USER_WIDTH - 1:0] RUSER; + wire RVALID; + wire RREADY; + wire W_cen; + wire R_cen; + wire W_wen; + wire R_wen; + wire [MEM_ADDR_WIDTH - 1:0] W_addr; + wire [MEM_ADDR_WIDTH - 1:0] R_addr; + wire [AXI4_WDATA_WIDTH - 1:0] W_wdata; + wire [AXI4_WDATA_WIDTH - 1:0] R_wdata; + wire [AXI_NUMBYTES - 1:0] W_be; + wire [AXI_NUMBYTES - 1:0] R_be; + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(AWVALID_i), + .slave_addr_i(AWADDR_i), + .slave_prot_i(AWPROT_i), + .slave_region_i(AWREGION_i), + .slave_len_i(AWLEN_i), + .slave_size_i(AWSIZE_i), + .slave_burst_i(AWBURST_i), + .slave_lock_i(AWLOCK_i), + .slave_cache_i(AWCACHE_i), + .slave_qos_i(AWQOS_i), + .slave_id_i(AWID_i), + .slave_user_i(AWUSER_i), + .slave_ready_o(AWREADY_o), + .master_valid_o(AWVALID), + .master_addr_o(AWADDR), + .master_prot_o(AWPROT), + .master_region_o(AWREGION), + .master_len_o(AWLEN), + .master_size_o(AWSIZE), + .master_burst_o(AWBURST), + .master_lock_o(AWLOCK), + .master_cache_o(AWCACHE), + .master_qos_o(AWQOS), + .master_id_o(AWID), + .master_user_o(AWUSER), + .master_ready_i(AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(ARVALID_i), + .slave_addr_i(ARADDR_i), + .slave_prot_i(ARPROT_i), + .slave_region_i(ARREGION_i), + .slave_len_i(ARLEN_i), + .slave_size_i(ARSIZE_i), + .slave_burst_i(ARBURST_i), + .slave_lock_i(ARLOCK_i), + .slave_cache_i(ARCACHE_i), + .slave_qos_i(ARQOS_i), + .slave_id_i(ARID_i), + .slave_user_i(ARUSER_i), + .slave_ready_o(ARREADY_o), + .master_valid_o(ARVALID), + .master_addr_o(ARADDR), + .master_prot_o(ARPROT), + .master_region_o(ARREGION), + .master_len_o(ARLEN), + .master_size_o(ARSIZE), + .master_burst_o(ARBURST), + .master_lock_o(ARLOCK), + .master_cache_o(ARCACHE), + .master_qos_o(ARQOS), + .master_id_o(ARID), + .master_user_o(ARUSER), + .master_ready_i(ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(WVALID_i), + .slave_data_i(WDATA_i), + .slave_strb_i(WSTRB_i), + .slave_user_i(WUSER_i), + .slave_last_i(WLAST_i), + .slave_ready_o(WREADY_o), + .master_valid_o(WVALID), + .master_data_o(WDATA), + .master_strb_o(WSTRB), + .master_user_o(WUSER), + .master_last_o(WLAST), + .master_ready_i(WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(RVALID), + .slave_data_i(RDATA), + .slave_resp_i(RRESP), + .slave_user_i(RUSER), + .slave_id_i(RID), + .slave_last_i(RLAST), + .slave_ready_o(RREADY), + .master_valid_o(RVALID_o), + .master_data_o(RDATA_o), + .master_resp_o(RRESP_o), + .master_user_o(RUSER_o), + .master_id_o(RID_o), + .master_last_o(RLAST_o), + .master_ready_i(RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(BVALID), + .slave_resp_i(BRESP), + .slave_id_i(BID), + .slave_user_i(BUSER), + .slave_ready_o(BREADY), + .master_valid_o(BVALID_o), + .master_resp_o(BRESP_o), + .master_id_o(BID_o), + .master_user_o(BUSER_o), + .master_ready_i(BREADY_i) + ); + axi_write_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) WRITE_CTRL( + .clk(ACLK), + .rst_n(ARESETn), + .AWID_i(AWID), + .AWADDR_i(AWADDR), + .AWLEN_i(AWLEN), + .AWSIZE_i(AWSIZE), + .AWBURST_i(AWBURST), + .AWLOCK_i(AWLOCK), + .AWCACHE_i(AWCACHE), + .AWPROT_i(AWPROT), + .AWREGION_i(AWREGION), + .AWUSER_i(AWUSER), + .AWQOS_i(AWQOS), + .AWVALID_i(AWVALID), + .AWREADY_o(AWREADY), + .WDATA_i(WDATA), + .WSTRB_i(WSTRB), + .WLAST_i(WLAST), + .WUSER_i(WUSER), + .WVALID_i(WVALID), + .WREADY_o(WREADY), + .BID_o(BID), + .BRESP_o(BRESP), + .BVALID_o(BVALID), + .BUSER_o(BUSER), + .BREADY_i(BREADY), + .MEM_CEN_o(W_cen), + .MEM_WEN_o(W_wen), + .MEM_A_o(W_addr), + .MEM_D_o(W_wdata), + .MEM_BE_o(W_be), + .MEM_Q_i({AXI4_RDATA_WIDTH{ 1'b0 }}), + .grant_i(grant_W), + .valid_o(valid_W) + ); + axi_read_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) READ_CTRL( + .clk(ACLK), + .rst_n(ARESETn), + .ARID_i(ARID), + .ARADDR_i(ARADDR), + .ARLEN_i(ARLEN), + .ARSIZE_i(ARSIZE), + .ARBURST_i(ARBURST), + .ARLOCK_i(ARLOCK), + .ARCACHE_i(ARCACHE), + .ARPROT_i(ARPROT), + .ARREGION_i(ARREGION), + .ARUSER_i(ARUSER), + .ARQOS_i(ARQOS), + .ARVALID_i(ARVALID), + .ARREADY_o(ARREADY), + .RID_o(RID), + .RDATA_o(RDATA), + .RRESP_o(RRESP), + .RLAST_o(RLAST), + .RUSER_o(RUSER), + .RVALID_o(RVALID), + .RREADY_i(RREADY), + .MEM_CEN_o(R_cen), + .MEM_WEN_o(R_wen), + .MEM_A_o(R_addr), + .MEM_D_o(R_wdata), + .MEM_BE_o(R_be), + .MEM_Q_i(Q_i), + .grant_i(grant_R), + .valid_o(valid_R) + ); + always @(*) begin : _MUX_MEM_ + if (valid_R & grant_R) begin + CEN_o = R_cen; + WEN_o = 1'b1; + A_o = R_addr; + D_o = R_wdata; + BE_o = R_be; + end + else begin + CEN_o = W_cen; + WEN_o = 1'b0; + A_o = W_addr; + D_o = W_wdata; + BE_o = W_be; + end + end + always @(*) begin + grant_R = 1'b0; + grant_W = 1'b0; + case (RR_FLAG) + 1'b0: + if (valid_W) + grant_W = 1'b1; + else + grant_R = 1'b1; + 1'b1: + if (valid_R) + grant_R = 1'b1; + else + grant_W = 1'b1; + endcase + end + always @(posedge ACLK or negedge ARESETn) + if (~ARESETn) + RR_FLAG <= 0; + else if (CEN_o == 1'b0) + RR_FLAG <= ~RR_FLAG; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_multi_bank.v b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_multi_bank.v new file mode 100644 index 0000000..80b6b4e --- /dev/null +++ b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_mem_if_multi_bank.v
@@ -0,0 +1,480 @@ +module axi_mem_if_DP_multi_bank +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + parameter MEM_ADDR_WIDTH = 13, + parameter BUFF_DEPTH_SLAVE = 4, + parameter NB_L2_BANKS = 4 +) +( + ACLK, + ARESETn, + test_en_i, + LP_AWID_i, + LP_AWADDR_i, + LP_AWLEN_i, + LP_AWSIZE_i, + LP_AWBURST_i, + LP_AWLOCK_i, + LP_AWCACHE_i, + LP_AWPROT_i, + LP_AWREGION_i, + LP_AWUSER_i, + LP_AWQOS_i, + LP_AWVALID_i, + LP_AWREADY_o, + LP_WDATA_i, + LP_WSTRB_i, + LP_WLAST_i, + LP_WUSER_i, + LP_WVALID_i, + LP_WREADY_o, + LP_BID_o, + LP_BRESP_o, + LP_BVALID_o, + LP_BUSER_o, + LP_BREADY_i, + LP_ARID_i, + LP_ARADDR_i, + LP_ARLEN_i, + LP_ARSIZE_i, + LP_ARBURST_i, + LP_ARLOCK_i, + LP_ARCACHE_i, + LP_ARPROT_i, + LP_ARREGION_i, + LP_ARUSER_i, + LP_ARQOS_i, + LP_ARVALID_i, + LP_ARREADY_o, + LP_RID_o, + LP_RDATA_o, + LP_RRESP_o, + LP_RLAST_o, + LP_RUSER_o, + LP_RVALID_o, + LP_RREADY_i, + HP_cen_i, + HP_wen_i, + HP_addr_i, + HP_wdata_i, + HP_be_i, + HP_Q_o, + CEN, + WEN, + A, + D, + BE, + Q +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter MEM_ADDR_WIDTH = 13; + //parameter BUFF_DEPTH_SLAVE = 4; + //parameter NB_L2_BANKS = 4; + input wire ACLK; + input wire ARESETn; + input wire test_en_i; + input wire [AXI4_ID_WIDTH - 1:0] LP_AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] LP_AWADDR_i; + input wire [7:0] LP_AWLEN_i; + input wire [2:0] LP_AWSIZE_i; + input wire [1:0] LP_AWBURST_i; + input wire LP_AWLOCK_i; + input wire [3:0] LP_AWCACHE_i; + input wire [2:0] LP_AWPROT_i; + input wire [3:0] LP_AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_AWUSER_i; + input wire [3:0] LP_AWQOS_i; + input wire LP_AWVALID_i; + output wire LP_AWREADY_o; + input wire [(AXI_NUMBYTES * 8) - 1:0] LP_WDATA_i; + input wire [AXI_NUMBYTES - 1:0] LP_WSTRB_i; + input wire LP_WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_WUSER_i; + input wire LP_WVALID_i; + output wire LP_WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] LP_BID_o; + output wire [1:0] LP_BRESP_o; + output wire LP_BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] LP_BUSER_o; + input wire LP_BREADY_i; + input wire [AXI4_ID_WIDTH - 1:0] LP_ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] LP_ARADDR_i; + input wire [7:0] LP_ARLEN_i; + input wire [2:0] LP_ARSIZE_i; + input wire [1:0] LP_ARBURST_i; + input wire LP_ARLOCK_i; + input wire [3:0] LP_ARCACHE_i; + input wire [2:0] LP_ARPROT_i; + input wire [3:0] LP_ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] LP_ARUSER_i; + input wire [3:0] LP_ARQOS_i; + input wire LP_ARVALID_i; + output wire LP_ARREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] LP_RID_o; + output wire [AXI4_RDATA_WIDTH - 1:0] LP_RDATA_o; + output wire [1:0] LP_RRESP_o; + output wire LP_RLAST_o; + output wire [AXI4_USER_WIDTH - 1:0] LP_RUSER_o; + output wire LP_RVALID_o; + input wire LP_RREADY_i; + input wire HP_cen_i; + input wire HP_wen_i; + input wire [(MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)) - 1:0] HP_addr_i; + input wire [AXI4_WDATA_WIDTH - 1:0] HP_wdata_i; + input wire [AXI_NUMBYTES - 1:0] HP_be_i; + output wire [AXI4_RDATA_WIDTH - 1:0] HP_Q_o; + output wire [NB_L2_BANKS - 1:0] CEN; + output wire [NB_L2_BANKS - 1:0] WEN; + output wire [(NB_L2_BANKS * MEM_ADDR_WIDTH) - 1:0] A; + output wire [(NB_L2_BANKS * AXI4_WDATA_WIDTH) - 1:0] D; + output wire [(NB_L2_BANKS * AXI_NUMBYTES) - 1:0] BE; + input wire [(NB_L2_BANKS * AXI4_RDATA_WIDTH) - 1:0] Q; + localparam OFFSET_BIT = $clog2(AXI4_WDATA_WIDTH) - 3; + wire [AXI4_ID_WIDTH - 1:0] LP_AWID; + wire [AXI4_ADDRESS_WIDTH - 1:0] LP_AWADDR; + wire [7:0] LP_AWLEN; + wire [2:0] LP_AWSIZE; + wire [1:0] LP_AWBURST; + wire LP_AWLOCK; + wire [3:0] LP_AWCACHE; + wire [2:0] LP_AWPROT; + wire [3:0] LP_AWREGION; + wire [AXI4_USER_WIDTH - 1:0] LP_AWUSER; + wire [3:0] LP_AWQOS; + wire LP_AWVALID; + wire LP_AWREADY; + wire [(AXI_NUMBYTES * 8) - 1:0] LP_WDATA; + wire [AXI_NUMBYTES - 1:0] LP_WSTRB; + wire LP_WLAST; + wire [AXI4_USER_WIDTH - 1:0] LP_WUSER; + wire LP_WVALID; + wire LP_WREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_BID; + wire [1:0] LP_BRESP; + wire LP_BVALID; + wire [AXI4_USER_WIDTH - 1:0] LP_BUSER; + wire LP_BREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_ARID; + wire [AXI4_ADDRESS_WIDTH - 1:0] LP_ARADDR; + wire [7:0] LP_ARLEN; + wire [2:0] LP_ARSIZE; + wire [1:0] LP_ARBURST; + wire LP_ARLOCK; + wire [3:0] LP_ARCACHE; + wire [2:0] LP_ARPROT; + wire [3:0] LP_ARREGION; + wire [AXI4_USER_WIDTH - 1:0] LP_ARUSER; + wire [3:0] LP_ARQOS; + wire LP_ARVALID; + wire LP_ARREADY; + wire [AXI4_ID_WIDTH - 1:0] LP_RID; + wire [AXI4_RDATA_WIDTH - 1:0] LP_RDATA; + wire [1:0] LP_RRESP; + wire LP_RLAST; + wire [AXI4_USER_WIDTH - 1:0] LP_RUSER; + wire LP_RVALID; + wire LP_RREADY; + wire valid_R_LP; + wire valid_W_LP; + wire grant_R_LP; + wire grant_W_LP; + wire RR_FLAG_LP; + wire LP_W_cen; + wire LP_R_cen; + wire LP_W_wen; + wire LP_R_wen; + wire [(MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)) - 1:0] LP_W_addr; + wire [(MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)) - 1:0] LP_R_addr; + wire [AXI4_WDATA_WIDTH - 1:0] LP_W_wdata; + wire [AXI4_WDATA_WIDTH - 1:0] LP_R_wdata; + wire [AXI_NUMBYTES - 1:0] LP_W_be; + wire [AXI_NUMBYTES - 1:0] LP_R_be; + wire [AXI4_WDATA_WIDTH - 1:0] LP_W_rdata; + wire [AXI4_WDATA_WIDTH - 1:0] LP_R_rdata; + wire [2:0] req_int; + wire [(3 * ((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS))) - 1:0] add_int; + wire [2:0] wen_int; + wire [(3 * AXI4_WDATA_WIDTH) - 1:0] wdata_int; + wire [(3 * (AXI4_WDATA_WIDTH / 8)) - 1:0] be_int; + wire [2:0] gnt_int; + wire [(3 * AXI4_WDATA_WIDTH) - 1:0] r_rdata_int; + wire [2:0] r_valid_int; + wire [(NB_L2_BANKS * AXI4_WDATA_WIDTH) - 1:0] mem_wdata; + wire [(NB_L2_BANKS * MEM_ADDR_WIDTH) - 1:0] mem_add; + wire [NB_L2_BANKS - 1:0] mem_req; + wire [NB_L2_BANKS - 1:0] mem_wen; + wire [(NB_L2_BANKS * (AXI4_WDATA_WIDTH / 8)) - 1:0] mem_be; + wire [(NB_L2_BANKS * AXI4_WDATA_WIDTH) - 1:0] mem_rdata; + axi_aw_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_aw_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_AWVALID_i), + .slave_addr_i(LP_AWADDR_i), + .slave_prot_i(LP_AWPROT_i), + .slave_region_i(LP_AWREGION_i), + .slave_len_i(LP_AWLEN_i), + .slave_size_i(LP_AWSIZE_i), + .slave_burst_i(LP_AWBURST_i), + .slave_lock_i(LP_AWLOCK_i), + .slave_cache_i(LP_AWCACHE_i), + .slave_qos_i(LP_AWQOS_i), + .slave_id_i(LP_AWID_i), + .slave_user_i(LP_AWUSER_i), + .slave_ready_o(LP_AWREADY_o), + .master_valid_o(LP_AWVALID), + .master_addr_o(LP_AWADDR), + .master_prot_o(LP_AWPROT), + .master_region_o(LP_AWREGION), + .master_len_o(LP_AWLEN), + .master_size_o(LP_AWSIZE), + .master_burst_o(LP_AWBURST), + .master_lock_o(LP_AWLOCK), + .master_cache_o(LP_AWCACHE), + .master_qos_o(LP_AWQOS), + .master_id_o(LP_AWID), + .master_user_o(LP_AWUSER), + .master_ready_i(LP_AWREADY) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .ADDR_WIDTH(AXI4_ADDRESS_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_ar_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_ARVALID_i), + .slave_addr_i(LP_ARADDR_i), + .slave_prot_i(LP_ARPROT_i), + .slave_region_i(LP_ARREGION_i), + .slave_len_i(LP_ARLEN_i), + .slave_size_i(LP_ARSIZE_i), + .slave_burst_i(LP_ARBURST_i), + .slave_lock_i(LP_ARLOCK_i), + .slave_cache_i(LP_ARCACHE_i), + .slave_qos_i(LP_ARQOS_i), + .slave_id_i(LP_ARID_i), + .slave_user_i(LP_ARUSER_i), + .slave_ready_o(LP_ARREADY_o), + .master_valid_o(LP_ARVALID), + .master_addr_o(LP_ARADDR), + .master_prot_o(LP_ARPROT), + .master_region_o(LP_ARREGION), + .master_len_o(LP_ARLEN), + .master_size_o(LP_ARSIZE), + .master_burst_o(LP_ARBURST), + .master_lock_o(LP_ARLOCK), + .master_cache_o(LP_ARCACHE), + .master_qos_o(LP_ARQOS), + .master_id_o(LP_ARID), + .master_user_o(LP_ARUSER), + .master_ready_i(LP_ARREADY) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_w_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_WVALID_i), + .slave_data_i(LP_WDATA_i), + .slave_strb_i(LP_WSTRB_i), + .slave_user_i(LP_WUSER_i), + .slave_last_i(LP_WLAST_i), + .slave_ready_o(LP_WREADY_o), + .master_valid_o(LP_WVALID), + .master_data_o(LP_WDATA), + .master_strb_o(LP_WSTRB), + .master_user_o(LP_WUSER), + .master_last_o(LP_WLAST), + .master_ready_i(LP_WREADY) + ); + axi_r_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .DATA_WIDTH(AXI4_RDATA_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_r_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_RVALID), + .slave_data_i(LP_RDATA), + .slave_resp_i(LP_RRESP), + .slave_user_i(LP_RUSER), + .slave_id_i(LP_RID), + .slave_last_i(LP_RLAST), + .slave_ready_o(LP_RREADY), + .master_valid_o(LP_RVALID_o), + .master_data_o(LP_RDATA_o), + .master_resp_o(LP_RRESP_o), + .master_user_o(LP_RUSER_o), + .master_id_o(LP_RID_o), + .master_last_o(LP_RLAST_o), + .master_ready_i(LP_RREADY_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI4_ID_WIDTH), + .USER_WIDTH(AXI4_USER_WIDTH), + .BUFFER_DEPTH(BUFF_DEPTH_SLAVE) + ) Slave_b_buffer_LP( + .clk_i(ACLK), + .rst_ni(ARESETn), + .test_en_i(test_en_i), + .slave_valid_i(LP_BVALID), + .slave_resp_i(LP_BRESP), + .slave_id_i(LP_BID), + .slave_user_i(LP_BUSER), + .slave_ready_o(LP_BREADY), + .master_valid_o(LP_BVALID_o), + .master_resp_o(LP_BRESP_o), + .master_id_o(LP_BID_o), + .master_user_o(LP_BUSER_o), + .master_ready_i(LP_BREADY_i) + ); + axi_write_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)) + ) W_CTRL_LP( + .clk(ACLK), + .rst_n(ARESETn), + .AWID_i(LP_AWID), + .AWADDR_i(LP_AWADDR), + .AWLEN_i(LP_AWLEN), + .AWSIZE_i(LP_AWSIZE), + .AWBURST_i(LP_AWBURST), + .AWLOCK_i(LP_AWLOCK), + .AWCACHE_i(LP_AWCACHE), + .AWPROT_i(LP_AWPROT), + .AWREGION_i(LP_AWREGION), + .AWUSER_i(LP_AWUSER), + .AWQOS_i(LP_AWQOS), + .AWVALID_i(LP_AWVALID), + .AWREADY_o(LP_AWREADY), + .WDATA_i(LP_WDATA), + .WSTRB_i(LP_WSTRB), + .WLAST_i(LP_WLAST), + .WUSER_i(LP_WUSER), + .WVALID_i(LP_WVALID), + .WREADY_o(LP_WREADY), + .BID_o(LP_BID), + .BRESP_o(LP_BRESP), + .BVALID_o(LP_BVALID), + .BUSER_o(LP_BUSER), + .BREADY_i(LP_BREADY), + .MEM_CEN_o(LP_W_cen), + .MEM_WEN_o(LP_W_wen), + .MEM_A_o(LP_W_addr), + .MEM_D_o(LP_W_wdata), + .MEM_BE_o(LP_W_be), + .MEM_Q_i(1'sb0), + .grant_i(grant_W_LP), + .valid_o(valid_W_LP) + ); + axi_read_only_ctrl #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI_NUMBYTES(AXI_NUMBYTES), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH + $clog2(NB_L2_BANKS)) + ) R_CTRL_LP( + .clk(ACLK), + .rst_n(ARESETn), + .ARID_i(LP_ARID), + .ARADDR_i(LP_ARADDR), + .ARLEN_i(LP_ARLEN), + .ARSIZE_i(LP_ARSIZE), + .ARBURST_i(LP_ARBURST), + .ARLOCK_i(LP_ARLOCK), + .ARCACHE_i(LP_ARCACHE), + .ARPROT_i(LP_ARPROT), + .ARREGION_i(LP_ARREGION), + .ARUSER_i(LP_ARUSER), + .ARQOS_i(LP_ARQOS), + .ARVALID_i(LP_ARVALID), + .ARREADY_o(LP_ARREADY), + .RID_o(LP_RID), + .RDATA_o(LP_RDATA), + .RRESP_o(LP_RRESP), + .RLAST_o(LP_RLAST), + .RUSER_o(LP_RUSER), + .RVALID_o(LP_RVALID), + .RREADY_i(LP_RREADY), + .MEM_CEN_o(LP_R_cen), + .MEM_WEN_o(LP_R_wen), + .MEM_A_o(LP_R_addr), + .MEM_D_o(), + .MEM_BE_o(), + .MEM_Q_i(LP_R_rdata), + .grant_i(grant_R_LP), + .valid_o(valid_R_LP) + ); + assign req_int = {~HP_cen_i, valid_R_LP, valid_W_LP}; + assign {grant_R_LP, grant_W_LP} = gnt_int[1:0]; + assign add_int[0+:(MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)] = {LP_W_addr, 3'b000}; + assign add_int[(MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)+:(MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)] = {LP_R_addr, 3'b000}; + assign add_int[2 * ((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS))+:(MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)] = {HP_addr_i, 3'b000}; + assign wen_int = {HP_wen_i, 1'b1, 1'b0}; + assign wdata_int = {HP_wdata_i, {AXI4_WDATA_WIDTH {1'b0}}, LP_W_wdata}; + assign be_int = {HP_be_i, {AXI4_WDATA_WIDTH / 8 {1'b0}}, LP_W_be}; + assign {HP_Q_o, LP_R_rdata, LP_W_rdata} = r_rdata_int; + XBAR_TCDM_FC #( + .N_CH0(2), + .N_CH1(1), + .N_SLAVE(NB_L2_BANKS), + .ADDR_WIDTH((MEM_ADDR_WIDTH + 3) + $clog2(NB_L2_BANKS)), + .DATA_WIDTH(AXI4_WDATA_WIDTH), + .ADDR_MEM_WIDTH(MEM_ADDR_WIDTH), + .CH0_CH1_POLICY("FIX_PRIO"), + .PRIO_CH(1) + ) L2_MB_INTERCO( + .data_req_i(req_int), + .data_add_i(add_int), + .data_wen_i(wen_int), + .data_wdata_i(wdata_int), + .data_be_i(be_int), + .data_gnt_o(gnt_int), + .data_r_valid_o(r_valid_int), + .data_r_rdata_o(r_rdata_int), + .data_req_o(mem_req), + .data_add_o(mem_add), + .data_wen_o(mem_wen), + .data_wdata_o(mem_wdata), + .data_be_o(mem_be), + .data_r_rdata_i(mem_rdata), + .clk(ACLK), + .rst_n(ARESETn) + ); + assign CEN = ~mem_req; + assign WEN = mem_wen; + assign A = mem_add; + assign D = mem_wdata; + assign BE = mem_be; + assign mem_rdata = Q; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_mem_if_DP/axi_read_only_ctrl.v b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_read_only_ctrl.v new file mode 100644 index 0000000..d20e049 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_read_only_ctrl.v
@@ -0,0 +1,351 @@ +module axi_read_only_ctrl +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + parameter MEM_ADDR_WIDTH = 13 +) +( + clk, + rst_n, + ARID_i, + ARADDR_i, + ARLEN_i, + ARSIZE_i, + ARBURST_i, + ARLOCK_i, + ARCACHE_i, + ARPROT_i, + ARREGION_i, + ARUSER_i, + ARQOS_i, + ARVALID_i, + ARREADY_o, + RID_o, + RDATA_o, + RRESP_o, + RLAST_o, + RUSER_o, + RVALID_o, + RREADY_i, + MEM_CEN_o, + MEM_WEN_o, + MEM_A_o, + MEM_D_o, + MEM_BE_o, + MEM_Q_i, + grant_i, + valid_o +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter MEM_ADDR_WIDTH = 13; + input wire clk; + input wire rst_n; + input wire [AXI4_ID_WIDTH - 1:0] ARID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] ARADDR_i; + input wire [7:0] ARLEN_i; + input wire [2:0] ARSIZE_i; + input wire [1:0] ARBURST_i; + input wire ARLOCK_i; + input wire [3:0] ARCACHE_i; + input wire [2:0] ARPROT_i; + input wire [3:0] ARREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] ARUSER_i; + input wire [3:0] ARQOS_i; + input wire ARVALID_i; + output reg ARREADY_o; + output reg [AXI4_ID_WIDTH - 1:0] RID_o; + output reg [AXI4_RDATA_WIDTH - 1:0] RDATA_o; + output reg [1:0] RRESP_o; + output reg RLAST_o; + output reg [AXI4_USER_WIDTH - 1:0] RUSER_o; + output reg RVALID_o; + input wire RREADY_i; + output reg MEM_CEN_o; + output reg MEM_WEN_o; + output reg [MEM_ADDR_WIDTH - 1:0] MEM_A_o; + output wire [AXI4_RDATA_WIDTH - 1:0] MEM_D_o; + output wire [AXI_NUMBYTES - 1:0] MEM_BE_o; + input wire [AXI4_RDATA_WIDTH - 1:0] MEM_Q_i; + input wire grant_i; + output reg valid_o; + localparam OFFSET_BIT = $clog2(AXI4_RDATA_WIDTH) - 3; + reg [2:0] CS; + reg [2:0] NS; + reg [8:0] CountBurst_CS; + reg [8:0] CountBurst_NS; + reg sample_rdata; + reg sample_ctrl; + reg [AXI4_RDATA_WIDTH - 1:0] RDATA_REG; + reg [AXI4_USER_WIDTH - 1:0] RUSER_REG; + reg [AXI4_ID_WIDTH - 1:0] RID_REG; + reg [MEM_ADDR_WIDTH - 1:0] ARADDR_REG; + reg [7:0] ARLEN_REG; + assign MEM_D_o = 1'sb0; + assign MEM_BE_o = 1'sb0; + always @(posedge clk or negedge rst_n) begin : _UPDATE_CS_ + if (~rst_n) begin + CS <= 3'd0; + CountBurst_CS <= 1'sb0; + RDATA_REG <= 1'sb0; + RID_REG <= 1'sb0; + RUSER_REG <= 1'sb0; + ARADDR_REG <= 1'sb0; + ARLEN_REG <= 1'sb0; + end + else begin + CS <= NS; + CountBurst_CS <= CountBurst_NS; + if (sample_ctrl) begin + RUSER_REG <= ARUSER_i; + RID_REG <= ARID_i; + ARADDR_REG <= ARADDR_i[(MEM_ADDR_WIDTH + OFFSET_BIT) - 1:OFFSET_BIT]; + ARLEN_REG <= ARLEN_i; + end + if (sample_rdata) + RDATA_REG <= MEM_Q_i; + end + end + always @(*) begin : COMPUTE_NS + ARREADY_o = 1'b0; + RDATA_o = MEM_Q_i; + RUSER_o = RUSER_REG; + RID_o = RID_REG; + RVALID_o = 1'b0; + RLAST_o = 1'b0; + RRESP_o = 2'b00; + MEM_CEN_o = 1'b1; + MEM_WEN_o = 1'b1; + MEM_A_o = ARADDR_i[(MEM_ADDR_WIDTH + OFFSET_BIT) - 1:OFFSET_BIT]; + valid_o = 1'b0; + sample_rdata = 1'b0; + sample_ctrl = 1'b0; + CountBurst_NS = CountBurst_CS; + case (CS) + 3'd0: begin + valid_o = ARVALID_i; + MEM_CEN_o = ~ARVALID_i; + ARREADY_o = grant_i; + if (ARVALID_i) begin + sample_ctrl = 1'b1; + if (grant_i) begin + ARREADY_o = 1'b1; + if (ARLEN_i == 0) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = 1'b1; + end + end + else + NS = 3'd0; + end + else + NS = 3'd0; + end + 3'd1: begin + sample_rdata = 1'b1; + RDATA_o = MEM_Q_i; + RVALID_o = 1'b1; + RLAST_o = 1'b1; + RRESP_o = 2'b00; + if (RREADY_i) begin + ARREADY_o = grant_i; + valid_o = ARVALID_i; + MEM_CEN_o = ~ARVALID_i; + if (ARVALID_i) begin + sample_ctrl = 1'b1; + if (grant_i) begin + ARREADY_o = 1'b1; + if (ARLEN_i == 0) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = 1'b1; + end + end + else + NS = 3'd0; + end + else + NS = 3'd0; + end + else + NS = 3'd3; + end + 3'd3: begin + RDATA_o = RDATA_REG; + RVALID_o = 1'b1; + RLAST_o = 1'b1; + RRESP_o = 2'b00; + if (RREADY_i) begin + ARREADY_o = grant_i; + valid_o = ARVALID_i; + MEM_CEN_o = ~ARVALID_i; + if (ARVALID_i) begin + sample_ctrl = 1'b1; + if (grant_i) begin + ARREADY_o = 1'b1; + if (ARLEN_i == 0) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = 1'b1; + end + end + else + NS = 3'd0; + end + else + NS = 3'd0; + end + else + NS = 3'd3; + end + 3'd2: begin + sample_rdata = 1'b1; + RDATA_o = MEM_Q_i; + RVALID_o = 1'b1; + RLAST_o = 1'b0; + RRESP_o = 2'b00; + MEM_A_o = ARADDR_REG + CountBurst_CS; + if (RREADY_i) begin + sample_ctrl = 1'b0; + MEM_CEN_o = 1'b0; + valid_o = 1'b1; + if (grant_i) begin + NS = 3'd2; + if (CountBurst_CS == ARLEN_REG) begin + CountBurst_NS = 1'sb0; + NS = 3'd4; + end + else begin + NS = 3'd2; + CountBurst_NS = CountBurst_CS + 1'b1; + end + end + else + NS = 3'd5; + end + else + NS = 3'd6; + end + 3'd5: begin + MEM_CEN_o = 1'b0; + MEM_A_o = ARADDR_REG + CountBurst_CS; + valid_o = 1'b1; + if (grant_i) begin + if (CountBurst_CS == ARLEN_REG) begin + NS = 3'd4; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = CountBurst_CS + 1; + end + end + else + NS = 3'd5; + end + 3'd6: begin + RDATA_o = RDATA_REG; + RVALID_o = 1'b1; + RLAST_o = 1'b0; + RRESP_o = 2'b00; + MEM_A_o = ARADDR_REG + CountBurst_CS; + if (RREADY_i) begin + valid_o = 1'b1; + MEM_CEN_o = 1'b0; + if (grant_i) begin + CountBurst_NS = CountBurst_CS + 1; + if (CountBurst_CS == ARLEN_REG) + NS = 3'd4; + else + NS = 3'd2; + end + else + NS = 3'd5; + end + else + NS = 3'd6; + end + 3'd4: begin + RVALID_o = 1'b1; + RLAST_o = 1'b1; + RDATA_o = MEM_Q_i; + sample_rdata = 1'b1; + if (RREADY_i) begin + valid_o = ARVALID_i; + MEM_CEN_o = ~ARVALID_i; + ARREADY_o = grant_i; + if (ARVALID_i) begin + sample_ctrl = 1'b1; + if (grant_i) begin + ARREADY_o = 1'b1; + if (ARLEN_i == 0) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = 1'b1; + end + end + else + NS = 3'd0; + end + else + NS = 3'd0; + end + else + NS = 3'd7; + end + 3'd7: begin + RVALID_o = 1'b1; + RLAST_o = 1'b1; + RDATA_o = RDATA_REG; + sample_rdata = 1'b0; + if (RREADY_i) begin + valid_o = ARVALID_i; + MEM_CEN_o = ~ARVALID_i; + ARREADY_o = grant_i; + if (ARVALID_i) begin + sample_ctrl = 1'b1; + if (grant_i) begin + ARREADY_o = 1'b1; + if (ARLEN_i == 0) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = 1'b1; + end + end + else + NS = 3'd0; + end + else + NS = 3'd0; + end + else + NS = 3'd7; + end + default: NS = 3'd0; + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_mem_if_DP/axi_write_only_ctrl.v b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_write_only_ctrl.v new file mode 100644 index 0000000..e6bfe6c --- /dev/null +++ b/verilog/rtl/ips/axi/axi_mem_if_DP/axi_write_only_ctrl.v
@@ -0,0 +1,245 @@ +module axi_write_only_ctrl +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 64, + parameter AXI4_WDATA_WIDTH = 64, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + parameter MEM_ADDR_WIDTH = 13 +) +( + clk, + rst_n, + AWID_i, + AWADDR_i, + AWLEN_i, + AWSIZE_i, + AWBURST_i, + AWLOCK_i, + AWCACHE_i, + AWPROT_i, + AWREGION_i, + AWUSER_i, + AWQOS_i, + AWVALID_i, + AWREADY_o, + WDATA_i, + WSTRB_i, + WLAST_i, + WUSER_i, + WVALID_i, + WREADY_o, + BID_o, + BRESP_o, + BVALID_o, + BUSER_o, + BREADY_i, + MEM_CEN_o, + MEM_WEN_o, + MEM_A_o, + MEM_D_o, + MEM_BE_o, + MEM_Q_i, + grant_i, + valid_o +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 64; + //parameter AXI4_WDATA_WIDTH = 64; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter AXI_NUMBYTES = AXI4_WDATA_WIDTH / 8; + //parameter MEM_ADDR_WIDTH = 13; + input wire clk; + input wire rst_n; + input wire [AXI4_ID_WIDTH - 1:0] AWID_i; + input wire [AXI4_ADDRESS_WIDTH - 1:0] AWADDR_i; + input wire [7:0] AWLEN_i; + input wire [2:0] AWSIZE_i; + input wire [1:0] AWBURST_i; + input wire AWLOCK_i; + input wire [3:0] AWCACHE_i; + input wire [2:0] AWPROT_i; + input wire [3:0] AWREGION_i; + input wire [AXI4_USER_WIDTH - 1:0] AWUSER_i; + input wire [3:0] AWQOS_i; + input wire AWVALID_i; + output reg AWREADY_o; + input wire [AXI4_WDATA_WIDTH - 1:0] WDATA_i; + input wire [AXI_NUMBYTES - 1:0] WSTRB_i; + input wire WLAST_i; + input wire [AXI4_USER_WIDTH - 1:0] WUSER_i; + input wire WVALID_i; + output reg WREADY_o; + output wire [AXI4_ID_WIDTH - 1:0] BID_o; + output reg [1:0] BRESP_o; + output reg BVALID_o; + output wire [AXI4_USER_WIDTH - 1:0] BUSER_o; + input wire BREADY_i; + output reg MEM_CEN_o; + output reg MEM_WEN_o; + output reg [MEM_ADDR_WIDTH - 1:0] MEM_A_o; + output reg [AXI4_RDATA_WIDTH - 1:0] MEM_D_o; + output reg [AXI_NUMBYTES - 1:0] MEM_BE_o; + input wire [AXI4_RDATA_WIDTH - 1:0] MEM_Q_i; + input wire grant_i; + output reg valid_o; + localparam OFFSET_BIT = $clog2(AXI4_WDATA_WIDTH) - 3; + reg [2:0] CS; + reg [2:0] NS; + reg [8:0] CountBurst_CS; + reg [8:0] CountBurst_NS; + reg sample_ctrl; + wire sample_backward; + reg [AXI4_USER_WIDTH - 1:0] AWUSER_REG; + reg [AXI4_ID_WIDTH - 1:0] AWID_REG; + reg [MEM_ADDR_WIDTH - 1:0] AWADDR_REG; + reg [MEM_ADDR_WIDTH - 1:0] AWADDR_REG_incr; + reg [7:0] AWLEN_REG; + always @(posedge clk or negedge rst_n) begin : _UPDATE_CS_ + if (~rst_n) begin + CS <= 3'd0; + CountBurst_CS <= 1'sb0; + AWADDR_REG_incr <= 1'sb0; + AWID_REG <= 1'sb0; + AWUSER_REG <= 1'sb0; + AWADDR_REG <= 1'sb0; + AWLEN_REG <= 1'sb0; + end + else begin + CS <= NS; + CountBurst_CS <= CountBurst_NS; + if (sample_ctrl) begin + AWUSER_REG <= AWUSER_i; + AWID_REG <= AWID_i; + AWADDR_REG <= AWADDR_i[(MEM_ADDR_WIDTH + OFFSET_BIT) - 1:OFFSET_BIT]; + AWLEN_REG <= AWLEN_i; + end + end + end + assign BUSER_o = AWUSER_REG; + assign BID_o = AWID_REG; + always @(*) begin : COMPUTE_NS + sample_ctrl = 1'b0; + valid_o = 1'b0; + AWREADY_o = 1'b0; + WREADY_o = 1'b0; + BRESP_o = 2'b00; + BVALID_o = 1'b0; + MEM_CEN_o = 1'b1; + MEM_WEN_o = 1'b0; + MEM_A_o = AWADDR_i[(MEM_ADDR_WIDTH + OFFSET_BIT) - 1:OFFSET_BIT]; + MEM_D_o = WDATA_i; + MEM_BE_o = WSTRB_i; + NS = CS; + CountBurst_NS = CountBurst_CS; + case (CS) + 3'd0: begin + AWREADY_o = 1'b1; + sample_ctrl = AWVALID_i; + MEM_A_o = AWADDR_i[(MEM_ADDR_WIDTH + OFFSET_BIT) - 1:OFFSET_BIT]; + if (AWVALID_i) begin + valid_o = WVALID_i; + MEM_CEN_o = ~WVALID_i; + WREADY_o = grant_i; + if (WVALID_i & grant_i) begin + if (AWLEN_i == 0) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = 1; + end + end + else begin + NS = 3'd3; + CountBurst_NS = 1'sb0; + end + end + else + NS = 3'd0; + end + 3'd3: begin + WREADY_o = grant_i; + valid_o = WVALID_i; + MEM_CEN_o = ~(WVALID_i & grant_i); + MEM_A_o = AWADDR_REG + CountBurst_CS; + if (grant_i & WVALID_i) begin + if (AWLEN_REG == CountBurst_CS) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd2; + CountBurst_NS = CountBurst_CS + 1; + end + end + else + NS = 3'd3; + end + 3'd1: begin + BRESP_o = 2'b00; + BVALID_o = 1'b1; + MEM_A_o = AWADDR_i[(MEM_ADDR_WIDTH + OFFSET_BIT) - 1:OFFSET_BIT]; + if (BREADY_i) begin + AWREADY_o = 1'b1; + sample_ctrl = AWVALID_i; + if (AWVALID_i) begin + valid_o = WVALID_i; + MEM_CEN_o = ~WVALID_i; + WREADY_o = grant_i; + if (WVALID_i & grant_i) begin + if (AWLEN_i == 0) begin + CountBurst_NS = 1'sb0; + if (WLAST_i == 1'b1) + NS = 3'd1; + else + NS = 3'd4; + end + else begin + NS = 3'd2; + CountBurst_NS = 1; + end + end + else begin + NS = 3'd3; + CountBurst_NS = 1'sb0; + end + end + else + NS = 3'd0; + end + else + NS = 3'd1; + end + 3'd2: begin + WREADY_o = grant_i; + MEM_CEN_o = ~WVALID_i; + valid_o = WVALID_i; + MEM_A_o = AWADDR_REG + CountBurst_CS; + if (WVALID_i & grant_i) begin + if (AWLEN_REG == CountBurst_CS) begin + if (WLAST_i == 1'b1) begin + NS = 3'd1; + CountBurst_NS = 1'sb0; + end + else begin + NS = 3'd4; + CountBurst_NS = 1'sb0; + end + end + else begin + NS = 3'd2; + CountBurst_NS = CountBurst_CS + 1; + end + end + else + NS = 3'd3; + end + 3'd4: NS = 3'd4; + default: NS = 3'd0; + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/apb_regs_top.v b/verilog/rtl/ips/axi/axi_node/apb_regs_top.v new file mode 100644 index 0000000..d6c930d --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/apb_regs_top.v
@@ -0,0 +1,82 @@ +module apb_regs_top +#( + parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default + parameter APB_DATA_WIDTH = 32, + parameter N_REGION_MAX = 4, + parameter N_MASTER_PORT = 16, + parameter N_SLAVE_PORT = 16 +) +( + HCLK, + HRESETn, + PADDR_i, + PWDATA_i, + PWRITE_i, + PSEL_i, + PENABLE_i, + PRDATA_o, + PREADY_o, + PSLVERR_o, + init_START_ADDR_i, + init_END_ADDR_i, + init_valid_rule_i, + init_connectivity_map_i, + START_ADDR_o, + END_ADDR_o, + valid_rule_o, + connectivity_map_o +); + //parameter APB_ADDR_WIDTH = 12; + //parameter APB_DATA_WIDTH = 32; + //parameter N_REGION_MAX = 4; + //parameter N_MASTER_PORT = 16; + //parameter N_SLAVE_PORT = 16; + input wire HCLK; + input wire HRESETn; + input wire [APB_ADDR_WIDTH - 1:0] PADDR_i; + input wire [APB_DATA_WIDTH - 1:0] PWDATA_i; + input wire PWRITE_i; + input wire PSEL_i; + input wire PENABLE_i; + output reg [APB_DATA_WIDTH - 1:0] PRDATA_o; + output wire PREADY_o; + output wire PSLVERR_o; + input wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] init_START_ADDR_i; + input wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] init_END_ADDR_i; + input wire [(N_REGION_MAX * N_MASTER_PORT) - 1:0] init_valid_rule_i; + input wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] init_connectivity_map_i; + output wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] START_ADDR_o; + output wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] END_ADDR_o; + output wire [(N_REGION_MAX * N_MASTER_PORT) - 1:0] valid_rule_o; + output wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] connectivity_map_o; + reg [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] cfg_req_START_ADDR; + reg [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] cfg_req_END_ADDR; + reg [(N_REGION_MAX * N_MASTER_PORT) - 1:0] cfg_req_valid_rule; + reg [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] cfg_req_connectivity_map; + always @(posedge HCLK) + if (~HRESETn) begin + cfg_req_START_ADDR <= init_START_ADDR_i; + cfg_req_END_ADDR <= init_END_ADDR_i; + cfg_req_valid_rule <= init_valid_rule_i; + cfg_req_connectivity_map <= init_connectivity_map_i; + end + else if ((PSEL_i && PENABLE_i) && PWRITE_i) + case (PADDR_i[9:8]) + 2'b00: cfg_req_START_ADDR[PADDR_i[7:2] * 32+:32] <= PWDATA_i[31:0]; + 2'b01: cfg_req_END_ADDR[PADDR_i[7:2] * 32+:32] <= PWDATA_i[31:0]; + 2'b10: cfg_req_valid_rule[PADDR_i[7:2] * N_MASTER_PORT+:N_MASTER_PORT] <= PWDATA_i[N_MASTER_PORT - 1:0]; + 2'b11: cfg_req_END_ADDR[PADDR_i[7:2] * 32+:32] <= PWDATA_i[N_MASTER_PORT - 1:0]; + endcase + always @(*) + if ((PSEL_i && PENABLE_i) && ~PWRITE_i) + case (PADDR_i[9:8]) + 2'b00: PRDATA_o[31:0] = cfg_req_START_ADDR[PADDR_i[7:2] * 32+:32]; + 2'b01: PRDATA_o[31:0] = cfg_req_END_ADDR[PADDR_i[7:2] * 32+:32]; + 2'b10: PRDATA_o[31:0] = cfg_req_valid_rule[PADDR_i[7:2] * N_MASTER_PORT+:N_MASTER_PORT]; + 2'b11: PRDATA_o[31:0] = cfg_req_END_ADDR[PADDR_i[7:2] * 32+:32]; + endcase + else + PRDATA_o = 1'sb0; + assign PREADY_o = 1'b1; + assign PSLVERR_o = 1'b0; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_AR_allocator.v b/verilog/rtl/ips/axi/axi_node/axi_AR_allocator.v new file mode 100644 index 0000000..3682649 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_AR_allocator.v
@@ -0,0 +1,109 @@ +module axi_AR_allocator +#( + parameter AXI_ADDRESS_W = 32, + parameter AXI_USER_W = 6, + parameter N_TARG_PORT = 7, + parameter LOG_N_TARG = $clog2(N_TARG_PORT), + parameter AXI_ID_IN = 16, + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT) +) +( + clk, + rst_n, + arid_i, + araddr_i, + arlen_i, + arsize_i, + arburst_i, + arlock_i, + arcache_i, + arprot_i, + arregion_i, + aruser_i, + arqos_i, + arvalid_i, + arready_o, + arid_o, + araddr_o, + arlen_o, + arsize_o, + arburst_o, + arlock_o, + arcache_o, + arprot_o, + arregion_o, + aruser_o, + arqos_o, + arvalid_o, + arready_i +); + //parameter AXI_ADDRESS_W = 32; + //parameter AXI_USER_W = 6; + //parameter N_TARG_PORT = 7; + //parameter LOG_N_TARG = $clog2(N_TARG_PORT); + //parameter AXI_ID_IN = 16; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT); + input wire clk; + input wire rst_n; + input wire [(N_TARG_PORT * AXI_ID_IN) - 1:0] arid_i; + input wire [(N_TARG_PORT * AXI_ADDRESS_W) - 1:0] araddr_i; + input wire [(N_TARG_PORT * 8) - 1:0] arlen_i; + input wire [(N_TARG_PORT * 3) - 1:0] arsize_i; + input wire [(N_TARG_PORT * 2) - 1:0] arburst_i; + input wire [N_TARG_PORT - 1:0] arlock_i; + input wire [(N_TARG_PORT * 4) - 1:0] arcache_i; + input wire [(N_TARG_PORT * 3) - 1:0] arprot_i; + input wire [(N_TARG_PORT * 4) - 1:0] arregion_i; + input wire [(N_TARG_PORT * AXI_USER_W) - 1:0] aruser_i; + input wire [(N_TARG_PORT * 4) - 1:0] arqos_i; + input wire [N_TARG_PORT - 1:0] arvalid_i; + output wire [N_TARG_PORT - 1:0] arready_o; + output wire [AXI_ID_OUT - 1:0] arid_o; + output wire [AXI_ADDRESS_W - 1:0] araddr_o; + output wire [7:0] arlen_o; + output wire [2:0] arsize_o; + output wire [1:0] arburst_o; + output wire arlock_o; + output wire [3:0] arcache_o; + output wire [2:0] arprot_o; + output wire [3:0] arregion_o; + output wire [AXI_USER_W - 1:0] aruser_o; + output wire [3:0] arqos_o; + output wire arvalid_o; + input wire arready_i; + localparam AUX_WIDTH = (((AXI_ID_IN + AXI_ADDRESS_W) + 25) + AXI_USER_W) + 4; + wire [(N_TARG_PORT * AUX_WIDTH) - 1:0] AUX_VECTOR_IN; + wire [AUX_WIDTH - 1:0] AUX_VECTOR_OUT; + wire [(N_TARG_PORT * (LOG_N_TARG + N_TARG_PORT)) - 1:0] ID_in; + wire [(LOG_N_TARG + N_TARG_PORT) - 1:0] ID_int; + genvar i; + assign {arqos_o, aruser_o, arregion_o, arprot_o, arcache_o, arlock_o, arburst_o, arsize_o, arlen_o, araddr_o, arid_o[AXI_ID_IN - 1:0]} = AUX_VECTOR_OUT; + assign arid_o[AXI_ID_OUT - 1:AXI_ID_IN] = ID_int[(LOG_N_TARG + N_TARG_PORT) - 1:N_TARG_PORT]; + generate + for (i = 0; i < N_TARG_PORT; i = i + 1) begin : AUX_VECTOR_BINDING + assign AUX_VECTOR_IN[i * AUX_WIDTH+:AUX_WIDTH] = {arqos_i[i * 4+:4], aruser_i[i * AXI_USER_W+:AXI_USER_W], arregion_i[i * 4+:4], arprot_i[i * 3+:3], arcache_i[i * 4+:4], arlock_i[i], arburst_i[i * 2+:2], arsize_i[i * 3+:3], arlen_i[i * 8+:8], araddr_i[i * AXI_ADDRESS_W+:AXI_ADDRESS_W], arid_i[i * AXI_ID_IN+:AXI_ID_IN]}; + end + for (i = 0; i < N_TARG_PORT; i = i + 1) begin : ID_VECTOR_BINDING + assign ID_in[(i * (LOG_N_TARG + N_TARG_PORT)) + (N_TARG_PORT - 1)-:N_TARG_PORT] = 2 ** i; + assign ID_in[(i * (LOG_N_TARG + N_TARG_PORT)) + (((LOG_N_TARG + N_TARG_PORT) - 1) >= N_TARG_PORT ? (LOG_N_TARG + N_TARG_PORT) - 1 : (((LOG_N_TARG + N_TARG_PORT) - 1) + (((LOG_N_TARG + N_TARG_PORT) - 1) >= N_TARG_PORT ? (((LOG_N_TARG + N_TARG_PORT) - 1) - N_TARG_PORT) + 1 : (N_TARG_PORT - ((LOG_N_TARG + N_TARG_PORT) - 1)) + 1)) - 1)-:(((LOG_N_TARG + N_TARG_PORT) - 1) >= N_TARG_PORT ? (((LOG_N_TARG + N_TARG_PORT) - 1) - N_TARG_PORT) + 1 : (N_TARG_PORT - ((LOG_N_TARG + N_TARG_PORT) - 1)) + 1)] = i; + end + endgenerate + axi_ArbitrationTree #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(LOG_N_TARG + N_TARG_PORT), + .N_MASTER(N_TARG_PORT) + ) AW_ARB_TREE( + .clk(clk), + .rst_n(rst_n), + .data_req_i(arvalid_i), + .data_AUX_i(AUX_VECTOR_IN), + .data_ID_i(ID_in), + .data_gnt_o(arready_o), + .data_req_o(arvalid_o), + .data_AUX_o(AUX_VECTOR_OUT), + .data_ID_o(ID_int), + .data_gnt_i(arready_i), + .lock(1'b0), + .SEL_EXCLUSIVE({$clog2(N_TARG_PORT) {1'b0}}) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_AW_allocator.v b/verilog/rtl/ips/axi/axi_node/axi_AW_allocator.v new file mode 100644 index 0000000..49273da --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_AW_allocator.v
@@ -0,0 +1,119 @@ +module axi_AW_allocator +#( + parameter AXI_ADDRESS_W = 32, + parameter AXI_USER_W = 6, + parameter N_TARG_PORT = 7, + parameter LOG_N_TARG = $clog2(N_TARG_PORT), + parameter AXI_ID_IN = 16, + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT) +) +( + clk, + rst_n, + awid_i, + awaddr_i, + awlen_i, + awsize_i, + awburst_i, + awlock_i, + awcache_i, + awprot_i, + awregion_i, + awuser_i, + awqos_i, + awvalid_i, + awready_o, + awid_o, + awaddr_o, + awlen_o, + awsize_o, + awburst_o, + awlock_o, + awcache_o, + awprot_o, + awregion_o, + awuser_o, + awqos_o, + awvalid_o, + awready_i, + push_ID_o, + ID_o, + grant_FIFO_ID_i +); + //parameter AXI_ADDRESS_W = 32; + //parameter AXI_USER_W = 6; + //parameter N_TARG_PORT = 7; + //parameter LOG_N_TARG = $clog2(N_TARG_PORT); + //parameter AXI_ID_IN = 16; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT); + input wire clk; + input wire rst_n; + input wire [(N_TARG_PORT * AXI_ID_IN) - 1:0] awid_i; + input wire [(N_TARG_PORT * AXI_ADDRESS_W) - 1:0] awaddr_i; + input wire [(N_TARG_PORT * 8) - 1:0] awlen_i; + input wire [(N_TARG_PORT * 3) - 1:0] awsize_i; + input wire [(N_TARG_PORT * 2) - 1:0] awburst_i; + input wire [N_TARG_PORT - 1:0] awlock_i; + input wire [(N_TARG_PORT * 4) - 1:0] awcache_i; + input wire [(N_TARG_PORT * 3) - 1:0] awprot_i; + input wire [(N_TARG_PORT * 4) - 1:0] awregion_i; + input wire [(N_TARG_PORT * AXI_USER_W) - 1:0] awuser_i; + input wire [(N_TARG_PORT * 4) - 1:0] awqos_i; + input wire [N_TARG_PORT - 1:0] awvalid_i; + output wire [N_TARG_PORT - 1:0] awready_o; + output wire [AXI_ID_OUT - 1:0] awid_o; + output wire [AXI_ADDRESS_W - 1:0] awaddr_o; + output wire [7:0] awlen_o; + output wire [2:0] awsize_o; + output wire [1:0] awburst_o; + output wire awlock_o; + output wire [3:0] awcache_o; + output wire [2:0] awprot_o; + output wire [3:0] awregion_o; + output wire [AXI_USER_W - 1:0] awuser_o; + output wire [3:0] awqos_o; + output wire awvalid_o; + input wire awready_i; + output wire push_ID_o; + output wire [(LOG_N_TARG + N_TARG_PORT) - 1:0] ID_o; + input wire grant_FIFO_ID_i; + localparam AUX_WIDTH = (((AXI_ID_IN + AXI_ADDRESS_W) + 25) + AXI_USER_W) + 4; + wire [(N_TARG_PORT * AUX_WIDTH) - 1:0] AUX_VECTOR_IN; + wire [AUX_WIDTH - 1:0] AUX_VECTOR_OUT; + wire [(N_TARG_PORT * (LOG_N_TARG + N_TARG_PORT)) - 1:0] ID_in; + wire [N_TARG_PORT - 1:0] awready_int; + wire awvalid_int; + genvar i; + assign {awqos_o, awuser_o, awregion_o, awprot_o, awcache_o, awlock_o, awburst_o, awsize_o, awlen_o, awaddr_o, awid_o[AXI_ID_IN - 1:0]} = AUX_VECTOR_OUT; + assign awid_o[AXI_ID_OUT - 1:AXI_ID_IN] = ID_o[(LOG_N_TARG + N_TARG_PORT) - 1:N_TARG_PORT]; + assign awready_o = {N_TARG_PORT {grant_FIFO_ID_i}} & awready_int; + assign awvalid_o = awvalid_int & grant_FIFO_ID_i; + assign push_ID_o = (awvalid_o & awready_i) & grant_FIFO_ID_i; + generate + for (i = 0; i < N_TARG_PORT; i = i + 1) begin : AUX_VECTOR_BINDING + assign AUX_VECTOR_IN[i * AUX_WIDTH+:AUX_WIDTH] = {awqos_i[i * 4+:4], awuser_i[i * AXI_USER_W+:AXI_USER_W], awregion_i[i * 4+:4], awprot_i[i * 3+:3], awcache_i[i * 4+:4], awlock_i[i], awburst_i[i * 2+:2], awsize_i[i * 3+:3], awlen_i[i * 8+:8], awaddr_i[i * AXI_ADDRESS_W+:AXI_ADDRESS_W], awid_i[i * AXI_ID_IN+:AXI_ID_IN]}; + end + for (i = 0; i < N_TARG_PORT; i = i + 1) begin : ID_VECTOR_BINDING + assign ID_in[(i * (LOG_N_TARG + N_TARG_PORT)) + (N_TARG_PORT - 1)-:N_TARG_PORT] = 2 ** i; + assign ID_in[(i * (LOG_N_TARG + N_TARG_PORT)) + (((LOG_N_TARG + N_TARG_PORT) - 1) >= N_TARG_PORT ? (LOG_N_TARG + N_TARG_PORT) - 1 : (((LOG_N_TARG + N_TARG_PORT) - 1) + (((LOG_N_TARG + N_TARG_PORT) - 1) >= N_TARG_PORT ? (((LOG_N_TARG + N_TARG_PORT) - 1) - N_TARG_PORT) + 1 : (N_TARG_PORT - ((LOG_N_TARG + N_TARG_PORT) - 1)) + 1)) - 1)-:(((LOG_N_TARG + N_TARG_PORT) - 1) >= N_TARG_PORT ? (((LOG_N_TARG + N_TARG_PORT) - 1) - N_TARG_PORT) + 1 : (N_TARG_PORT - ((LOG_N_TARG + N_TARG_PORT) - 1)) + 1)] = i; + end + endgenerate + axi_ArbitrationTree #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(LOG_N_TARG + N_TARG_PORT), + .N_MASTER(N_TARG_PORT) + ) AW_ARB_TREE( + .clk(clk), + .rst_n(rst_n), + .data_req_i(awvalid_i), + .data_AUX_i(AUX_VECTOR_IN), + .data_ID_i(ID_in), + .data_gnt_o(awready_int), + .data_req_o(awvalid_int), + .data_AUX_o(AUX_VECTOR_OUT), + .data_ID_o(ID_o), + .data_gnt_i(awready_i), + .lock(1'b0), + .SEL_EXCLUSIVE({$clog2(N_TARG_PORT) {1'b0}}) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_ArbitrationTree.v b/verilog/rtl/ips/axi/axi_node/axi_ArbitrationTree.v new file mode 100644 index 0000000..f511e67 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_ArbitrationTree.v
@@ -0,0 +1,194 @@ +module axi_ArbitrationTree +#( + parameter AUX_WIDTH = 64, + parameter ID_WIDTH = 20, + parameter N_MASTER = 5, + parameter LOG_MASTER = $clog2(N_MASTER) +) +( + clk, + rst_n, + data_req_i, + data_AUX_i, + data_ID_i, + data_gnt_o, + data_req_o, + data_AUX_o, + data_ID_o, + data_gnt_i, + lock, + SEL_EXCLUSIVE +); + //parameter AUX_WIDTH = 64; + //parameter ID_WIDTH = 20; + //parameter N_MASTER = 5; + //parameter LOG_MASTER = $clog2(N_MASTER); + input wire clk; + input wire rst_n; + input wire [N_MASTER - 1:0] data_req_i; + input wire [(N_MASTER * AUX_WIDTH) - 1:0] data_AUX_i; + input wire [(N_MASTER * ID_WIDTH) - 1:0] data_ID_i; + output wire [N_MASTER - 1:0] data_gnt_o; + output wire data_req_o; + output wire [AUX_WIDTH - 1:0] data_AUX_o; + output wire [ID_WIDTH - 1:0] data_ID_o; + input wire data_gnt_i; + input wire lock; + input wire [LOG_MASTER - 1:0] SEL_EXCLUSIVE; + localparam TOTAL_N_MASTER = 2 ** LOG_MASTER; + localparam N_WIRE = TOTAL_N_MASTER - 2; + wire [LOG_MASTER - 1:0] RR_FLAG; + reg [LOG_MASTER - 1:0] RR_FLAG_FLIPPED; + wire [TOTAL_N_MASTER - 1:0] data_req_int; + wire [(TOTAL_N_MASTER * AUX_WIDTH) - 1:0] data_AUX_int; + wire [(TOTAL_N_MASTER * ID_WIDTH) - 1:0] data_ID_int; + wire [TOTAL_N_MASTER - 1:0] data_gnt_int; + genvar j; + genvar k; + genvar index; + integer i; + always @(*) + for (i = 0; i < LOG_MASTER; i = i + 1) + RR_FLAG_FLIPPED[i] = RR_FLAG[(LOG_MASTER - i) - 1]; + generate + if (N_MASTER != TOTAL_N_MASTER) begin : ARRAY_INT + wire [TOTAL_N_MASTER - 1:N_MASTER] dummy_req_int; + wire [((TOTAL_N_MASTER - 1) >= N_MASTER ? ((((TOTAL_N_MASTER - 1) - N_MASTER) + 1) * AUX_WIDTH) + ((N_MASTER * AUX_WIDTH) - 1) : (((N_MASTER - (TOTAL_N_MASTER - 1)) + 1) * AUX_WIDTH) + (((TOTAL_N_MASTER - 1) * AUX_WIDTH) - 1)):((TOTAL_N_MASTER - 1) >= N_MASTER ? N_MASTER * AUX_WIDTH : (TOTAL_N_MASTER - 1) * AUX_WIDTH)] dummy_AUX_int; + wire [((TOTAL_N_MASTER - 1) >= N_MASTER ? ((((TOTAL_N_MASTER - 1) - N_MASTER) + 1) * ID_WIDTH) + ((N_MASTER * ID_WIDTH) - 1) : (((N_MASTER - (TOTAL_N_MASTER - 1)) + 1) * ID_WIDTH) + (((TOTAL_N_MASTER - 1) * ID_WIDTH) - 1)):((TOTAL_N_MASTER - 1) >= N_MASTER ? N_MASTER * ID_WIDTH : (TOTAL_N_MASTER - 1) * ID_WIDTH)] dummy_ID_int; + wire [TOTAL_N_MASTER - 1:N_MASTER] dummy_gnt_int; + for (index = N_MASTER; index < TOTAL_N_MASTER; index = index + 1) begin : ZERO_BINDING + assign dummy_req_int[index] = 1'b0; + assign dummy_AUX_int[((TOTAL_N_MASTER - 1) >= N_MASTER ? index : N_MASTER - (index - (TOTAL_N_MASTER - 1))) * AUX_WIDTH+:AUX_WIDTH] = 1'sb0; + assign dummy_ID_int[((TOTAL_N_MASTER - 1) >= N_MASTER ? index : N_MASTER - (index - (TOTAL_N_MASTER - 1))) * ID_WIDTH+:ID_WIDTH] = 1'sb0; + end + for (index = 0; index < N_MASTER; index = index + 1) begin : EXT_PORT + assign data_req_int[index] = data_req_i[index]; + assign data_AUX_int[index * AUX_WIDTH+:AUX_WIDTH] = data_AUX_i[index * AUX_WIDTH+:AUX_WIDTH]; + assign data_ID_int[index * ID_WIDTH+:ID_WIDTH] = data_ID_i[index * ID_WIDTH+:ID_WIDTH]; + assign data_gnt_o[index] = data_gnt_int[index]; + end + for (index = N_MASTER; index < TOTAL_N_MASTER; index = index + 1) begin : DUMMY_PORTS + assign data_req_int[index] = dummy_req_int[index]; + assign data_AUX_int[index * AUX_WIDTH+:AUX_WIDTH] = dummy_AUX_int[((TOTAL_N_MASTER - 1) >= N_MASTER ? index : N_MASTER - (index - (TOTAL_N_MASTER - 1))) * AUX_WIDTH+:AUX_WIDTH]; + assign data_ID_int[index * ID_WIDTH+:ID_WIDTH] = dummy_ID_int[((TOTAL_N_MASTER - 1) >= N_MASTER ? index : N_MASTER - (index - (TOTAL_N_MASTER - 1))) * ID_WIDTH+:ID_WIDTH]; + assign dummy_gnt_int[index] = data_gnt_int[index]; + end + end + else begin : genblk1 + for (index = 0; index < N_MASTER; index = index + 1) begin : EXT_PORT + assign data_req_int[index] = data_req_i[index]; + assign data_AUX_int[index * AUX_WIDTH+:AUX_WIDTH] = data_AUX_i[index * AUX_WIDTH+:AUX_WIDTH]; + assign data_ID_int[index * ID_WIDTH+:ID_WIDTH] = data_ID_i[index * ID_WIDTH+:ID_WIDTH]; + assign data_gnt_o[index] = data_gnt_int[index]; + end + end + if (TOTAL_N_MASTER == 2) begin : INCR + axi_FanInPrimitive_Req #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(ID_WIDTH) + ) FAN_IN_REQ( + .RR_FLAG(RR_FLAG_FLIPPED), + .data_AUX0_i(data_AUX_int[0+:AUX_WIDTH]), + .data_AUX1_i(data_AUX_int[AUX_WIDTH+:AUX_WIDTH]), + .data_req0_i(data_req_int[0]), + .data_req1_i(data_req_int[1]), + .data_ID0_i(data_ID_int[0+:ID_WIDTH]), + .data_ID1_i(data_ID_int[ID_WIDTH+:ID_WIDTH]), + .data_gnt0_o(data_gnt_int[0]), + .data_gnt1_o(data_gnt_int[1]), + .data_AUX_o(data_AUX_o), + .data_req_o(data_req_o), + .data_ID_o(data_ID_o), + .data_gnt_i(data_gnt_i), + .lock_EXCLUSIVE(lock), + .SEL_EXCLUSIVE(SEL_EXCLUSIVE) + ); + end + else begin : BINARY_TREE + wire [AUX_WIDTH - 1:0] data_AUX_LEVEL [N_WIRE - 1:0]; + wire data_req_LEVEL [N_WIRE - 1:0]; + wire [ID_WIDTH - 1:0] data_ID_LEVEL [N_WIRE - 1:0]; + wire data_gnt_LEVEL [N_WIRE - 1:0]; + for (j = 0; j < LOG_MASTER; j = j + 1) begin : STAGE + for (k = 0; k < (2 ** j); k = k + 1) begin : INCR_VERT + if (j == 0) begin : LAST_NODE + axi_FanInPrimitive_Req #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(ID_WIDTH) + ) FAN_IN_REQ( + .RR_FLAG(RR_FLAG_FLIPPED[(LOG_MASTER - j) - 1]), + .data_AUX0_i(data_AUX_LEVEL[2 * k]), + .data_AUX1_i(data_AUX_LEVEL[(2 * k) + 1]), + .data_req0_i(data_req_LEVEL[2 * k]), + .data_req1_i(data_req_LEVEL[(2 * k) + 1]), + .data_ID0_i(data_ID_LEVEL[2 * k]), + .data_ID1_i(data_ID_LEVEL[(2 * k) + 1]), + .data_gnt0_o(data_gnt_LEVEL[2 * k]), + .data_gnt1_o(data_gnt_LEVEL[(2 * k) + 1]), + .data_AUX_o(data_AUX_o), + .data_req_o(data_req_o), + .data_ID_o(data_ID_o), + .data_gnt_i(data_gnt_i), + .lock_EXCLUSIVE(lock), + .SEL_EXCLUSIVE(SEL_EXCLUSIVE[(LOG_MASTER - j) - 1]) + ); + end + else if (j < (LOG_MASTER - 1)) begin : MIDDLE_NODES + axi_FanInPrimitive_Req #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(ID_WIDTH) + ) FAN_IN_REQ( + .RR_FLAG(RR_FLAG_FLIPPED[(LOG_MASTER - j) - 1]), + .data_AUX0_i(data_AUX_LEVEL[(((2 ** j) * 2) - 2) + (2 * k)]), + .data_AUX1_i(data_AUX_LEVEL[((((2 ** j) * 2) - 2) + (2 * k)) + 1]), + .data_req0_i(data_req_LEVEL[(((2 ** j) * 2) - 2) + (2 * k)]), + .data_req1_i(data_req_LEVEL[((((2 ** j) * 2) - 2) + (2 * k)) + 1]), + .data_ID0_i(data_ID_LEVEL[(((2 ** j) * 2) - 2) + (2 * k)]), + .data_ID1_i(data_ID_LEVEL[((((2 ** j) * 2) - 2) + (2 * k)) + 1]), + .data_gnt0_o(data_gnt_LEVEL[(((2 ** j) * 2) - 2) + (2 * k)]), + .data_gnt1_o(data_gnt_LEVEL[((((2 ** j) * 2) - 2) + (2 * k)) + 1]), + .data_AUX_o(data_AUX_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .data_req_o(data_req_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .data_ID_o(data_ID_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .data_gnt_i(data_gnt_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .lock_EXCLUSIVE(lock), + .SEL_EXCLUSIVE(SEL_EXCLUSIVE[(LOG_MASTER - j) - 1]) + ); + end + else begin : LEAF_NODES + axi_FanInPrimitive_Req #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(ID_WIDTH) + ) FAN_IN_REQ( + .RR_FLAG(RR_FLAG_FLIPPED[(LOG_MASTER - j) - 1]), + .data_AUX0_i(data_AUX_int[(2 * k) * AUX_WIDTH+:AUX_WIDTH]), + .data_AUX1_i(data_AUX_int[((2 * k) + 1) * AUX_WIDTH+:AUX_WIDTH]), + .data_req0_i(data_req_int[2 * k]), + .data_req1_i(data_req_int[(2 * k) + 1]), + .data_ID0_i(data_ID_int[(2 * k) * ID_WIDTH+:ID_WIDTH]), + .data_ID1_i(data_ID_int[((2 * k) + 1) * ID_WIDTH+:ID_WIDTH]), + .data_gnt0_o(data_gnt_int[2 * k]), + .data_gnt1_o(data_gnt_int[(2 * k) + 1]), + .data_AUX_o(data_AUX_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .data_req_o(data_req_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .data_ID_o(data_ID_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .data_gnt_i(data_gnt_LEVEL[(((2 ** (j - 1)) * 2) - 2) + k]), + .lock_EXCLUSIVE(lock), + .SEL_EXCLUSIVE(SEL_EXCLUSIVE[(LOG_MASTER - j) - 1]) + ); + end + end + end + end + endgenerate + axi_RR_Flag_Req #( + .WIDTH(LOG_MASTER), + .MAX_COUNT(N_MASTER) + ) RR_REQ( + .clk(clk), + .rst_n(rst_n), + .RR_FLAG_o(RR_FLAG), + .data_req_i(data_req_o), + .data_gnt_i(data_gnt_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_BR_allocator.v b/verilog/rtl/ips/axi/axi_node/axi_BR_allocator.v new file mode 100644 index 0000000..92530fb --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_BR_allocator.v
@@ -0,0 +1,255 @@ +module axi_BR_allocator +#( + parameter AXI_USER_W = 6, + parameter N_INIT_PORT = 1, + parameter N_TARG_PORT = 7, + parameter AXI_DATA_W = 64, + parameter AXI_ID_IN = 16, + parameter LOG_N_TARG = $clog2(N_TARG_PORT), + parameter LOG_N_INIT = $clog2(N_INIT_PORT), + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT) +) +( + clk, + rst_n, + rid_i, + rdata_i, + rresp_i, + rlast_i, + ruser_i, + rvalid_i, + rready_o, + rid_o, + rdata_o, + rresp_o, + rlast_o, + ruser_o, + rvalid_o, + rready_i, + incr_req_i, + full_counter_o, + outstanding_trans_o, + error_req_i, + error_gnt_o, + error_len_i, + error_user_i, + error_id_i, + sample_ardata_info_i +); + //parameter AXI_USER_W = 6; + //parameter N_INIT_PORT = 1; + //parameter N_TARG_PORT = 7; + //parameter AXI_DATA_W = 64; + //parameter AXI_ID_IN = 16; + //parameter LOG_N_TARG = $clog2(N_TARG_PORT); + //parameter LOG_N_INIT = $clog2(N_INIT_PORT); + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT); + input wire clk; + input wire rst_n; + input wire [(N_INIT_PORT * AXI_ID_OUT) - 1:0] rid_i; + input wire [(N_INIT_PORT * AXI_DATA_W) - 1:0] rdata_i; + input wire [(N_INIT_PORT * 2) - 1:0] rresp_i; + input wire [N_INIT_PORT - 1:0] rlast_i; + input wire [(N_INIT_PORT * AXI_USER_W) - 1:0] ruser_i; + input wire [N_INIT_PORT - 1:0] rvalid_i; + output wire [N_INIT_PORT - 1:0] rready_o; + output reg [AXI_ID_IN - 1:0] rid_o; + output reg [AXI_DATA_W - 1:0] rdata_o; + output reg [1:0] rresp_o; + output reg rlast_o; + output reg [AXI_USER_W - 1:0] ruser_o; + output reg rvalid_o; + input wire rready_i; + input wire incr_req_i; + output wire full_counter_o; + output wire outstanding_trans_o; + input wire error_req_i; + output reg error_gnt_o; + input wire [7:0] error_len_i; + input wire [AXI_USER_W - 1:0] error_user_i; + input wire [AXI_ID_IN - 1:0] error_id_i; + input wire sample_ardata_info_i; + localparam AUX_WIDTH = (AXI_DATA_W + 3) + AXI_USER_W; + wire [(N_INIT_PORT * AUX_WIDTH) - 1:0] AUX_VECTOR_IN; + wire [AUX_WIDTH - 1:0] AUX_VECTOR_OUT; + wire [(N_INIT_PORT * AXI_ID_IN) - 1:0] rid_int; + genvar i; + reg [9:0] outstanding_counter; + wire decr_req; + reg [1:0] CS; + reg [1:0] NS; + reg [7:0] CounterBurstCS; + reg [7:0] CounterBurstNS; + reg [7:0] error_len_S; + reg [AXI_USER_W - 1:0] error_user_S; + reg [AXI_ID_IN - 1:0] error_id_S; + wire [AXI_ID_IN - 1:0] rid_ARB_TREE; + wire [AXI_DATA_W - 1:0] rdata_ARB_TREE; + wire [1:0] rresp_ARB_TREE; + wire rlast_ARB_TREE; + wire [AXI_USER_W - 1:0] ruser_ARB_TREE; + wire rvalid_ARB_TREE; + reg rready_ARB_TREE; + assign outstanding_trans_o = (outstanding_counter == {10 {1'sb0}} ? 1'b0 : 1'b1); + assign decr_req = (rvalid_ARB_TREE & rready_ARB_TREE) & rlast_ARB_TREE; + assign full_counter_o = (outstanding_counter == {10 {1'sb1}} ? 1'b1 : 1'b0); + always @(posedge clk or negedge rst_n) + if (rst_n == 1'b0) + outstanding_counter <= 1'sb0; + else + case ({incr_req_i, decr_req}) + 2'b00: outstanding_counter <= outstanding_counter; + 2'b01: + if (outstanding_counter != {10 {1'sb0}}) + outstanding_counter <= outstanding_counter - 1'b1; + else + outstanding_counter <= 1'sb0; + 2'b10: + if (outstanding_counter != {10 {1'sb1}}) + outstanding_counter <= outstanding_counter + 1'b1; + else + outstanding_counter <= 1'sb1; + 2'b11: outstanding_counter <= outstanding_counter; + endcase + always @(posedge clk or negedge rst_n) + if (rst_n == 1'b0) begin + CS <= 2'd0; + CounterBurstCS <= 1'sb0; + error_user_S <= 1'sb0; + error_id_S <= 1'sb0; + error_len_S <= 1'sb0; + end + else begin + CS <= NS; + CounterBurstCS <= CounterBurstNS; + if (sample_ardata_info_i) begin + error_user_S <= error_user_i; + error_id_S <= error_id_i; + error_len_S <= error_len_i; + end + end + always @(*) begin + rid_o = rid_ARB_TREE; + rdata_o = rdata_ARB_TREE; + rresp_o = rresp_ARB_TREE; + rlast_o = rlast_ARB_TREE; + ruser_o = ruser_ARB_TREE; + rvalid_o = rvalid_ARB_TREE; + rready_ARB_TREE = rready_i; + CounterBurstNS = CounterBurstCS; + error_gnt_o = 1'b0; + case (CS) + 2'd0: begin + CounterBurstNS = 1'sb0; + rready_ARB_TREE = rready_i; + error_gnt_o = 1'b0; + if (error_req_i == 1'b1) begin + if (outstanding_trans_o == 1'b0) begin + if (error_len_i == {8 {1'sb0}}) + NS = 2'd1; + else + NS = 2'd2; + end + else + NS = 2'd3; + end + else + NS = 2'd0; + end + 2'd3: begin + CounterBurstNS = 1'sb0; + rready_ARB_TREE = rready_i; + error_gnt_o = 1'b0; + if (outstanding_trans_o == 1'b0) begin + if (error_len_S == {8 {1'sb0}}) + NS = 2'd1; + else + NS = 2'd2; + end + else + NS = 2'd3; + end + 2'd1: begin + rready_ARB_TREE = 1'b0; + CounterBurstNS = 1'sb0; + error_gnt_o = 1'b1; + rresp_o = 2'b11; + rdata_o = {AXI_DATA_W / 32 {32'hdeadbeef}}; + rvalid_o = 1'b1; + ruser_o = error_user_S; + rlast_o = 1'b1; + rid_o = error_id_S; + if (rready_i) + NS = 2'd0; + else + NS = 2'd1; + end + 2'd2: begin + rready_ARB_TREE = 1'b0; + rresp_o = 2'b11; + rdata_o = {AXI_DATA_W / 32 {32'hdeadbeef}}; + rvalid_o = 1'b1; + ruser_o = error_user_S; + rid_o = error_id_S; + if (rready_i) begin + if (CounterBurstCS < error_len_i) begin + CounterBurstNS = CounterBurstCS + 1'b1; + error_gnt_o = 1'b0; + rlast_o = 1'b0; + NS = 2'd2; + end + else begin + error_gnt_o = 1'b1; + CounterBurstNS = 1'sb0; + NS = 2'd0; + rlast_o = 1'b1; + end + end + else begin + NS = 2'd2; + error_gnt_o = 1'b0; + end + end + default: begin + CounterBurstNS = 1'sb0; + NS = 2'd0; + error_gnt_o = 1'b0; + end + endcase + end + assign {ruser_ARB_TREE, rlast_ARB_TREE, rresp_ARB_TREE, rdata_ARB_TREE} = AUX_VECTOR_OUT; + generate + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : AUX_VECTOR_BINDING + assign AUX_VECTOR_IN[i * AUX_WIDTH+:AUX_WIDTH] = {ruser_i[i * AXI_USER_W+:AXI_USER_W], rlast_i[i], rresp_i[i * 2+:2], rdata_i[i * AXI_DATA_W+:AXI_DATA_W]}; + end + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : RID_VECTOR_BINDING + assign rid_int[i * AXI_ID_IN+:AXI_ID_IN] = rid_i[(i * AXI_ID_OUT) + (AXI_ID_IN - 1)-:AXI_ID_IN]; + end + if (N_INIT_PORT == 1) begin : DIRECT_BINDING + assign rvalid_ARB_TREE = rvalid_i; + assign AUX_VECTOR_OUT = AUX_VECTOR_IN; + assign rid_ARB_TREE = rid_int; + assign rready_o = rready_i; + end + else begin : ARB_TREE + axi_ArbitrationTree #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(AXI_ID_IN), + .N_MASTER(N_INIT_PORT) + ) BR_ARB_TREE( + .clk(clk), + .rst_n(rst_n), + .data_req_i(rvalid_i), + .data_AUX_i(AUX_VECTOR_IN), + .data_ID_i(rid_int), + .data_gnt_o(rready_o), + .data_req_o(rvalid_ARB_TREE), + .data_AUX_o(AUX_VECTOR_OUT), + .data_ID_o(rid_ARB_TREE), + .data_gnt_i(rready_ARB_TREE), + .lock(1'b0), + .SEL_EXCLUSIVE({$clog2(N_INIT_PORT) {1'b0}}) + ); + end + endgenerate +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_BW_allocator.v b/verilog/rtl/ips/axi/axi_node/axi_BW_allocator.v new file mode 100644 index 0000000..d7f0721 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_BW_allocator.v
@@ -0,0 +1,178 @@ +module axi_BW_allocator +#( + parameter AXI_USER_W = 6, + parameter N_INIT_PORT = 1, + parameter N_TARG_PORT = 7, + parameter AXI_DATA_W = 64, + parameter AXI_ID_IN = 16, + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT) +) +( + clk, + rst_n, + bid_i, + bresp_i, + buser_i, + bvalid_i, + bready_o, + bid_o, + bresp_o, + buser_o, + bvalid_o, + bready_i, + incr_req_i, + full_counter_o, + outstanding_trans_o, + sample_awdata_info_i, + error_req_i, + error_gnt_o, + error_user_i, + error_id_i +); + //parameter AXI_USER_W = 6; + //parameter N_INIT_PORT = 1; + //parameter N_TARG_PORT = 7; + //parameter AXI_DATA_W = 64; + //parameter AXI_ID_IN = 16; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT); + input wire clk; + input wire rst_n; + input wire [(N_INIT_PORT * AXI_ID_OUT) - 1:0] bid_i; + input wire [(N_INIT_PORT * 2) - 1:0] bresp_i; + input wire [(N_INIT_PORT * AXI_USER_W) - 1:0] buser_i; + input wire [N_INIT_PORT - 1:0] bvalid_i; + output wire [N_INIT_PORT - 1:0] bready_o; + output reg [AXI_ID_IN - 1:0] bid_o; + output reg [1:0] bresp_o; + output reg [AXI_USER_W - 1:0] buser_o; + output reg bvalid_o; + input wire bready_i; + input wire incr_req_i; + output wire full_counter_o; + output wire outstanding_trans_o; + input wire sample_awdata_info_i; + input wire error_req_i; + output reg error_gnt_o; + input wire [AXI_USER_W - 1:0] error_user_i; + input wire [AXI_ID_IN - 1:0] error_id_i; + localparam AUX_WIDTH = 2 + AXI_USER_W; + wire [(N_INIT_PORT * AUX_WIDTH) - 1:0] AUX_VECTOR_IN; + wire [AUX_WIDTH - 1:0] AUX_VECTOR_OUT; + wire [(N_INIT_PORT * AXI_ID_IN) - 1:0] bid_int; + genvar i; + reg [9:0] outstanding_counter; + wire decr_req; + reg [AXI_USER_W - 1:0] error_user_S; + reg [AXI_ID_IN - 1:0] error_id_S; + reg [1:0] CS; + reg [1:0] NS; + wire [AXI_ID_IN - 1:0] bid_ARB_TREE; + wire [1:0] bresp_ARB_TREE; + wire [AXI_USER_W - 1:0] buser_ARB_TREE; + wire bvalid_ARB_TREE; + reg bready_ARB_TREE; + assign {buser_ARB_TREE, bresp_ARB_TREE} = AUX_VECTOR_OUT; + assign outstanding_trans_o = (outstanding_counter == {10 {1'sb0}} ? 1'b0 : 1'b1); + assign decr_req = bvalid_o & bready_i; + assign full_counter_o = (outstanding_counter == {10 {1'sb1}} ? 1'b1 : 1'b0); + always @(posedge clk or negedge rst_n) + if (rst_n == 1'b0) + outstanding_counter <= 1'sb0; + else + case ({incr_req_i, decr_req}) + 2'b00: outstanding_counter <= outstanding_counter; + 2'b01: + if (outstanding_counter != {10 {1'sb0}}) + outstanding_counter <= outstanding_counter - 1'b1; + else + outstanding_counter <= 1'sb0; + 2'b10: + if (outstanding_counter != {10 {1'sb1}}) + outstanding_counter <= outstanding_counter + 1'b1; + else + outstanding_counter <= 1'sb1; + 2'b11: outstanding_counter <= outstanding_counter; + endcase + always @(posedge clk or negedge rst_n) + if (rst_n == 1'b0) begin + error_user_S <= 1'sb0; + error_id_S <= 1'sb0; + end + else if (sample_awdata_info_i) begin + error_user_S <= error_user_i; + error_id_S <= error_id_i; + end + always @(posedge clk or negedge rst_n) + if (rst_n == 1'b0) + CS <= 2'd0; + else + CS <= NS; + always @(*) begin + bid_o = bid_ARB_TREE; + bresp_o = bresp_ARB_TREE; + buser_o = buser_ARB_TREE; + bvalid_o = bvalid_ARB_TREE; + bready_ARB_TREE = bready_i; + error_gnt_o = 1'b0; + case (CS) + 2'd0: begin + bready_ARB_TREE = bready_i; + error_gnt_o = 1'b0; + if ((error_req_i == 1'b1) && (outstanding_trans_o == 1'b0)) + NS = 2'd1; + else + NS = 2'd0; + end + 2'd1: begin + bready_ARB_TREE = 1'b0; + error_gnt_o = 1'b1; + bresp_o = 2'b11; + bvalid_o = 1'b1; + buser_o = error_user_S; + bid_o = error_id_S; + if (bready_i) + NS = 2'd0; + else + NS = 2'd1; + end + default: begin + NS = 2'd0; + error_gnt_o = 1'b0; + end + endcase + end + generate + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : AUX_VECTOR_BINDING + assign AUX_VECTOR_IN[i * AUX_WIDTH+:AUX_WIDTH] = {buser_i[i * AXI_USER_W+:AXI_USER_W], bresp_i[i * 2+:2]}; + end + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : BID_VECTOR_BINDING + assign bid_int[i * AXI_ID_IN+:AXI_ID_IN] = bid_i[(i * AXI_ID_OUT) + (AXI_ID_IN - 1)-:AXI_ID_IN]; + end + if (N_INIT_PORT == 1) begin : DIRECT_BINDING + assign bvalid_ARB_TREE = bvalid_i; + assign AUX_VECTOR_OUT = AUX_VECTOR_IN; + assign bid_ARB_TREE = bid_int; + assign bready_o = bready_i; + end + else begin : ARB_TREE + axi_ArbitrationTree #( + .AUX_WIDTH(AUX_WIDTH), + .ID_WIDTH(AXI_ID_IN), + .N_MASTER(N_INIT_PORT) + ) BW_ARB_TREE( + .clk(clk), + .rst_n(rst_n), + .data_req_i(bvalid_i), + .data_AUX_i(AUX_VECTOR_IN), + .data_ID_i(bid_int), + .data_gnt_o(bready_o), + .data_req_o(bvalid_ARB_TREE), + .data_AUX_o(AUX_VECTOR_OUT), + .data_ID_o(bid_ARB_TREE), + .data_gnt_i(bready_ARB_TREE), + .lock(1'b0), + .SEL_EXCLUSIVE({$clog2(N_INIT_PORT) {1'b0}}) + ); + end + endgenerate +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_DW_allocator.v b/verilog/rtl/ips/axi/axi_node/axi_DW_allocator.v new file mode 100644 index 0000000..3f9bad5 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_DW_allocator.v
@@ -0,0 +1,159 @@ +module axi_DW_allocator +#( + parameter AXI_USER_W = 6, + parameter N_TARG_PORT = 7, + parameter LOG_N_TARG = $clog2(N_TARG_PORT), + parameter FIFO_DEPTH = 8, + + parameter AXI_DATA_W = 64, + parameter AXI_NUMBYTES = AXI_DATA_W/8 +) +( + clk, + rst_n, + test_en_i, + wdata_i, + wstrb_i, + wlast_i, + wuser_i, + wvalid_i, + wready_o, + wdata_o, + wstrb_o, + wlast_o, + wuser_o, + wvalid_o, + wready_i, + push_ID_i, + ID_i, + grant_FIFO_ID_o +); + //parameter AXI_USER_W = 6; + //parameter N_TARG_PORT = 7; + //parameter LOG_N_TARG = $clog2(N_TARG_PORT); + //parameter FIFO_DEPTH = 8; + //parameter AXI_DATA_W = 64; + //parameter AXI_NUMBYTES = AXI_DATA_W / 8; + input wire clk; + input wire rst_n; + input wire test_en_i; + input wire [(N_TARG_PORT * AXI_DATA_W) - 1:0] wdata_i; + input wire [(N_TARG_PORT * AXI_NUMBYTES) - 1:0] wstrb_i; + input wire [N_TARG_PORT - 1:0] wlast_i; + input wire [(N_TARG_PORT * AXI_USER_W) - 1:0] wuser_i; + input wire [N_TARG_PORT - 1:0] wvalid_i; + output reg [N_TARG_PORT - 1:0] wready_o; + output wire [AXI_DATA_W - 1:0] wdata_o; + output wire [AXI_NUMBYTES - 1:0] wstrb_o; + output wire wlast_o; + output wire [AXI_USER_W - 1:0] wuser_o; + output reg wvalid_o; + input wire wready_i; + input wire push_ID_i; + input wire [(LOG_N_TARG + N_TARG_PORT) - 1:0] ID_i; + output wire grant_FIFO_ID_o; + localparam AUX_WIDTH = ((AXI_DATA_W + AXI_NUMBYTES) + 1) + AXI_USER_W; + reg pop_from_ID_FIFO; + wire valid_ID; + wire [(LOG_N_TARG + N_TARG_PORT) - 1:0] ID_int; + wire [LOG_N_TARG - 1:0] ID_int_BIN; + wire [N_TARG_PORT - 1:0] ID_int_OH; + wire [AUX_WIDTH - 1:0] AUX_VECTOR_OUT; + wire [(N_TARG_PORT * AUX_WIDTH) - 1:0] AUX_VECTOR_IN; + reg CS; + reg NS; + genvar i; + generate + for (i = 0; i < N_TARG_PORT; i = i + 1) begin : AUX_VECTOR_BINDING + assign AUX_VECTOR_IN[i * AUX_WIDTH+:AUX_WIDTH] = {wdata_i[i * AXI_DATA_W+:AXI_DATA_W], wstrb_i[i * AXI_NUMBYTES+:AXI_NUMBYTES], wlast_i[i], wuser_i[i * AXI_USER_W+:AXI_USER_W]}; + end + endgenerate + assign {wdata_o, wstrb_o, wlast_o, wuser_o} = AUX_VECTOR_OUT; + generic_fifo #( + .DATA_WIDTH(LOG_N_TARG + N_TARG_PORT), + .DATA_DEPTH(FIFO_DEPTH) + ) MASTER_ID_FIFO( + .clk(clk), + .rst_n(rst_n), + .test_mode_i(test_en_i), + .data_i(ID_i), + .valid_i(push_ID_i), + .grant_o(grant_FIFO_ID_o), + .data_o(ID_int), + .valid_o(valid_ID), + .grant_i(pop_from_ID_FIFO) + ); + assign ID_int_BIN = ID_int[(LOG_N_TARG + N_TARG_PORT) - 1:N_TARG_PORT]; + assign ID_int_OH = ID_int[N_TARG_PORT - 1:0]; + always @(posedge clk or negedge rst_n) begin : UPDATE_STATE_FSM + if (rst_n == 1'b0) + CS <= 1'd0; + else + CS <= NS; + end + always @(*) begin : NEXT_STATE_FSM + pop_from_ID_FIFO = 1'b0; + wvalid_o = 1'b0; + wready_o = 1'sb0; + case (CS) + 1'd0: begin : _CS_IN_SINGLE_IDLE + if (valid_ID) begin : _valid_ID + wvalid_o = wvalid_i[ID_int_BIN]; + wready_o = {N_TARG_PORT {wready_i}} & ID_int_OH; + if (wvalid_i[ID_int_BIN] & wready_i) begin : _granted_request + if (wlast_i[ID_int_BIN]) begin : _last_packet + NS = 1'd0; + pop_from_ID_FIFO = 1'b1; + end + else begin : _payload_packet + NS = 1'd1; + pop_from_ID_FIFO = 1'b0; + end + end + else begin : _not_granted_request + NS = 1'd0; + pop_from_ID_FIFO = 1'b0; + end + end + else begin : _not_valid_ID + NS = 1'd0; + pop_from_ID_FIFO = 1'b0; + wvalid_o = 1'b0; + wready_o = 1'sb0; + end + end + 1'd1: begin : _CS_IN_BUSRT + wvalid_o = wvalid_i[ID_int_BIN]; + wready_o = ({N_TARG_PORT {wready_i}} & ID_int_OH) & {N_TARG_PORT {valid_ID}}; + if (wvalid_i[ID_int_BIN] & wready_i) begin + if (wlast_i[ID_int_BIN]) begin + NS = 1'd0; + pop_from_ID_FIFO = 1'b1; + end + else begin + NS = 1'd1; + pop_from_ID_FIFO = 1'b0; + end + end + else begin + NS = 1'd1; + pop_from_ID_FIFO = 1'b0; + end + end + default: begin + NS = 1'd0; + pop_from_ID_FIFO = 1'b0; + wvalid_o = 1'b0; + wready_o = 1'sb0; + end + endcase + end + axi_multiplexer #( + .DATA_WIDTH(AUX_WIDTH), + .N_IN(N_TARG_PORT) + ) WRITE_DATA_MUX( + .IN_DATA(AUX_VECTOR_IN), + .OUT_DATA(AUX_VECTOR_OUT), + .SEL(ID_int_BIN) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_FanInPrimitive_Req.v b/verilog/rtl/ips/axi/axi_node/axi_FanInPrimitive_Req.v new file mode 100644 index 0000000..ab7d399 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_FanInPrimitive_Req.v
@@ -0,0 +1,66 @@ +module axi_FanInPrimitive_Req +#( + parameter AUX_WIDTH = 32, + parameter ID_WIDTH = 16 +) +( + RR_FLAG, + data_AUX0_i, + data_AUX1_i, + data_req0_i, + data_req1_i, + data_ID0_i, + data_ID1_i, + data_gnt0_o, + data_gnt1_o, + data_AUX_o, + data_req_o, + data_ID_o, + data_gnt_i, + lock_EXCLUSIVE, + SEL_EXCLUSIVE +); + //parameter AUX_WIDTH = 32; + //parameter ID_WIDTH = 16; + input wire RR_FLAG; + input wire [AUX_WIDTH - 1:0] data_AUX0_i; + input wire [AUX_WIDTH - 1:0] data_AUX1_i; + input wire data_req0_i; + input wire data_req1_i; + input wire [ID_WIDTH - 1:0] data_ID0_i; + input wire [ID_WIDTH - 1:0] data_ID1_i; + output reg data_gnt0_o; + output reg data_gnt1_o; + output reg [AUX_WIDTH - 1:0] data_AUX_o; + output reg data_req_o; + output reg [ID_WIDTH - 1:0] data_ID_o; + input wire data_gnt_i; + input wire lock_EXCLUSIVE; + input wire SEL_EXCLUSIVE; + reg SEL; + always @(*) + if (lock_EXCLUSIVE) begin + data_req_o = (SEL_EXCLUSIVE ? data_req1_i : data_req0_i); + data_gnt0_o = (SEL_EXCLUSIVE ? 1'b0 : data_gnt_i); + data_gnt1_o = (SEL_EXCLUSIVE ? data_gnt_i : 1'b0); + SEL = SEL_EXCLUSIVE; + end + else begin + data_req_o = data_req0_i | data_req1_i; + data_gnt0_o = ((data_req0_i & ~data_req1_i) | (data_req0_i & ~RR_FLAG)) & data_gnt_i; + data_gnt1_o = ((~data_req0_i & data_req1_i) | (data_req1_i & RR_FLAG)) & data_gnt_i; + SEL = ~data_req0_i | (RR_FLAG & data_req1_i); + end + always @(*) begin : FanIn_MUX2 + case (SEL) + 1'b0: begin + data_AUX_o = data_AUX0_i; + data_ID_o = data_ID0_i; + end + 1'b1: begin + data_AUX_o = data_AUX1_i; + data_ID_o = data_ID1_i; + end + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_RR_Flag_Req.v b/verilog/rtl/ips/axi/axi_node/axi_RR_Flag_Req.v new file mode 100644 index 0000000..b14e8da --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_RR_Flag_Req.v
@@ -0,0 +1,30 @@ +module axi_RR_Flag_Req +#( + + parameter MAX_COUNT = 8, + parameter WIDTH = $clog2(MAX_COUNT) +) +( + clk, + rst_n, + RR_FLAG_o, + data_req_i, + data_gnt_i +); + //parameter MAX_COUNT = 8; + //parameter WIDTH = $clog2(MAX_COUNT); + input wire clk; + input wire rst_n; + output reg [WIDTH - 1:0] RR_FLAG_o; + input wire data_req_i; + input wire data_gnt_i; + always @(posedge clk or negedge rst_n) begin : RR_Flag_Req_SEQ + if (rst_n == 1'b0) + RR_FLAG_o <= 1'sb0; + else if (data_req_i & data_gnt_i) + if (RR_FLAG_o < (MAX_COUNT - 1)) + RR_FLAG_o <= RR_FLAG_o + 1'b1; + else + RR_FLAG_o <= 1'sb0; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_address_decoder_AR.v b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_AR.v new file mode 100644 index 0000000..44cf744 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_AR.v
@@ -0,0 +1,123 @@ +module axi_address_decoder_AR +#( + parameter ADDR_WIDTH = 32, + parameter N_INIT_PORT = 8, + parameter N_REGION = 4 +) +( + clk, + rst_n, + arvalid_i, + araddr_i, + arready_o, + arvalid_o, + arready_i, + START_ADDR_i, + END_ADDR_i, + enable_region_i, + connectivity_map_i, + incr_req_o, + full_counter_i, + outstanding_trans_i, + error_req_o, + error_gnt_i, + sample_ardata_info_o +); + //parameter ADDR_WIDTH = 32; + //parameter N_INIT_PORT = 8; + //parameter N_REGION = 4; + input wire clk; + input wire rst_n; + input wire arvalid_i; + input wire [ADDR_WIDTH - 1:0] araddr_i; + output reg arready_o; + output reg [N_INIT_PORT - 1:0] arvalid_o; + input wire [N_INIT_PORT - 1:0] arready_i; + input wire [((N_REGION * N_INIT_PORT) * ADDR_WIDTH) - 1:0] START_ADDR_i; + input wire [((N_REGION * N_INIT_PORT) * ADDR_WIDTH) - 1:0] END_ADDR_i; + input wire [(N_REGION * N_INIT_PORT) - 1:0] enable_region_i; + input wire [N_INIT_PORT - 1:0] connectivity_map_i; + output reg incr_req_o; + input wire full_counter_i; + input wire outstanding_trans_i; + output reg error_req_o; + input wire error_gnt_i; + output reg sample_ardata_info_o; + wire [N_INIT_PORT - 1:0] match_region; + wire [N_INIT_PORT:0] match_region_masked; + wire [(N_REGION * N_INIT_PORT) - 1:0] match_region_int; + wire [(N_INIT_PORT * N_REGION) - 1:0] match_region_rev; + reg arready_int; + reg [N_INIT_PORT - 1:0] arvalid_int; + genvar i; + genvar j; + reg CS; + reg NS; + generate + for (j = 0; j < N_REGION; j = j + 1) begin : genblk1 + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : genblk1 + assign match_region_int[(j * N_INIT_PORT) + i] = (enable_region_i[(j * N_INIT_PORT) + i] == 1'b1 ? (araddr_i >= START_ADDR_i[((j * N_INIT_PORT) + i) * ADDR_WIDTH+:ADDR_WIDTH]) && (araddr_i <= END_ADDR_i[((j * N_INIT_PORT) + i) * ADDR_WIDTH+:ADDR_WIDTH]) : 1'b0); + end + end + for (j = 0; j < N_INIT_PORT; j = j + 1) begin : genblk2 + for (i = 0; i < N_REGION; i = i + 1) begin : genblk1 + assign match_region_rev[(j * N_REGION) + i] = match_region_int[(i * N_INIT_PORT) + j]; + end + end + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : genblk3 + assign match_region[i] = |match_region_rev[i * N_REGION+:N_REGION]; + end + endgenerate + assign match_region_masked[N_INIT_PORT - 1:0] = match_region & connectivity_map_i; + assign match_region_masked[N_INIT_PORT] = ~(|match_region_masked[N_INIT_PORT - 1:0]); + always @(*) begin + if (arvalid_i) + {error_req_o, arvalid_int} = {N_INIT_PORT + 1 {arvalid_i}} & match_region_masked; + else begin + arvalid_int = 1'sb0; + error_req_o = 1'b0; + end + arready_int = |({error_gnt_i, arready_i} & match_region_masked); + end + always @(posedge clk or negedge rst_n) + if (rst_n == 1'b0) + CS <= 1'd0; + else + CS <= NS; + always @(*) begin + arready_o = 1'b0; + arvalid_o = arvalid_int; + sample_ardata_info_o = 1'b0; + incr_req_o = 1'b0; + case (CS) + 1'd0: + if (error_req_o) begin + NS = 1'd1; + arready_o = 1'b1; + sample_ardata_info_o = 1'b1; + arvalid_o = 1'sb0; + end + else begin + NS = 1'd0; + arready_o = arready_int; + sample_ardata_info_o = 1'b0; + incr_req_o = |(arvalid_o & arready_i); + arvalid_o = arvalid_int; + end + 1'd1: begin + arready_o = 1'b0; + arvalid_o = 1'sb0; + if (outstanding_trans_i) + NS = 1'd1; + else if (error_gnt_i) + NS = 1'd0; + else + NS = 1'd1; + end + default: begin + NS = 1'd0; + arready_o = arready_int; + end + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_address_decoder_AW.v b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_AW.v new file mode 100644 index 0000000..04f9c6f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_AW.v
@@ -0,0 +1,166 @@ +module axi_address_decoder_AW +#( + parameter ADDR_WIDTH = 32, + parameter N_INIT_PORT = 8, + parameter N_REGION = 2 +) +( + clk, + rst_n, + awvalid_i, + awaddr_i, + awready_o, + awvalid_o, + awready_i, + grant_FIFO_DEST_i, + DEST_o, + push_DEST_o, + START_ADDR_i, + END_ADDR_i, + enable_region_i, + connectivity_map_i, + incr_req_o, + full_counter_i, + outstanding_trans_i, + error_req_o, + error_gnt_i, + handle_error_o, + wdata_error_completed_i, + sample_awdata_info_o +); + //parameter ADDR_WIDTH = 32; + //parameter N_INIT_PORT = 8; + //parameter N_REGION = 2; + input wire clk; + input wire rst_n; + input wire awvalid_i; + input wire [ADDR_WIDTH - 1:0] awaddr_i; + output reg awready_o; + output reg [N_INIT_PORT - 1:0] awvalid_o; + input wire [N_INIT_PORT - 1:0] awready_i; + input wire grant_FIFO_DEST_i; + output wire [N_INIT_PORT - 1:0] DEST_o; + output wire push_DEST_o; + input wire [((N_REGION * N_INIT_PORT) * ADDR_WIDTH) - 1:0] START_ADDR_i; + input wire [((N_REGION * N_INIT_PORT) * ADDR_WIDTH) - 1:0] END_ADDR_i; + input wire [(N_REGION * N_INIT_PORT) - 1:0] enable_region_i; + input wire [N_INIT_PORT - 1:0] connectivity_map_i; + output reg incr_req_o; + input wire full_counter_i; + input wire outstanding_trans_i; + output reg error_req_o; + input wire error_gnt_i; + output reg handle_error_o; + input wire wdata_error_completed_i; + output reg sample_awdata_info_o; + wire [N_INIT_PORT - 1:0] match_region; + wire [N_INIT_PORT:0] match_region_masked; + wire [(N_REGION * N_INIT_PORT) - 1:0] match_region_int; + wire [(N_INIT_PORT * N_REGION) - 1:0] match_region_rev; + reg awready_int; + reg [N_INIT_PORT - 1:0] awvalid_int; + reg error_detected; + wire local_increm; + genvar i; + genvar j; + assign DEST_o = match_region[N_INIT_PORT - 1:0]; + assign push_DEST_o = |(awvalid_i & awready_o) & ~error_detected; + reg [1:0] CS; + reg [1:0] NS; + generate + for (j = 0; j < N_REGION; j = j + 1) begin : genblk1 + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : genblk1 + assign match_region_int[(j * N_INIT_PORT) + i] = (enable_region_i[(j * N_INIT_PORT) + i] == 1'b1 ? (awaddr_i >= START_ADDR_i[((j * N_INIT_PORT) + i) * ADDR_WIDTH+:ADDR_WIDTH]) && (awaddr_i <= END_ADDR_i[((j * N_INIT_PORT) + i) * ADDR_WIDTH+:ADDR_WIDTH]) : 1'b0); + end + end + for (j = 0; j < N_INIT_PORT; j = j + 1) begin : genblk2 + for (i = 0; i < N_REGION; i = i + 1) begin : genblk1 + assign match_region_rev[(j * N_REGION) + i] = match_region_int[(i * N_INIT_PORT) + j]; + end + end + for (i = 0; i < N_INIT_PORT; i = i + 1) begin : genblk3 + assign match_region[i] = |match_region_rev[i * N_REGION+:N_REGION]; + end + endgenerate + assign match_region_masked[N_INIT_PORT - 1:0] = match_region & connectivity_map_i; + assign match_region_masked[N_INIT_PORT] = ~(|match_region_masked[N_INIT_PORT - 1:0]); + always @(*) + if (grant_FIFO_DEST_i == 1'b1) begin + if (awvalid_i) + {error_detected, awvalid_int} = {N_INIT_PORT + 1 {awvalid_i}} & match_region_masked; + else begin + awvalid_int = 1'sb0; + error_detected = 1'b0; + end + awready_int = |({error_gnt_i, awready_i} & match_region_masked); + end + else begin + awvalid_int = 1'sb0; + awready_int = 1'b0; + error_detected = 1'b0; + end + always @(posedge clk or negedge rst_n) + if (rst_n == 1'b0) + CS <= 2'd0; + else + CS <= NS; + assign local_increm = |(awvalid_o & awready_i); + always @(*) begin + awready_o = 1'b0; + handle_error_o = 1'b0; + sample_awdata_info_o = 1'b0; + error_req_o = 1'b0; + incr_req_o = 1'b0; + awvalid_o = 1'sb0; + case (CS) + 2'd0: begin + handle_error_o = 1'b0; + incr_req_o = local_increm; + if (error_detected) begin + NS = 2'd1; + awready_o = 1'b1; + sample_awdata_info_o = 1'b1; + awvalid_o = 1'sb0; + end + else begin + NS = 2'd0; + awready_o = awready_int; + awvalid_o = awvalid_int; + end + end + 2'd1: begin + awready_o = 1'b0; + handle_error_o = 1'b0; + if (outstanding_trans_i) begin + NS = 2'd1; + awready_o = 1'b0; + end + else begin + awready_o = 1'b0; + NS = 2'd2; + end + end + 2'd2: begin + awready_o = 1'b0; + handle_error_o = 1'b1; + if (wdata_error_completed_i) + NS = 2'd3; + else + NS = 2'd2; + end + 2'd3: begin + handle_error_o = 1'b0; + error_req_o = 1'b1; + if (error_gnt_i) + NS = 2'd0; + else + NS = 2'd3; + end + default: begin + NS = 2'd0; + awready_o = awready_int; + handle_error_o = 1'b0; + end + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BR.v b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BR.v new file mode 100644 index 0000000..d215e1c --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BR.v
@@ -0,0 +1,36 @@ +module axi_address_decoder_BR +#( + parameter N_TARG_PORT = 8, + parameter AXI_ID_IN = 16, + parameter AXI_ID_OUT = AXI_ID_IN+$clog2(N_TARG_PORT) +) +( + rid_i, + rvalid_i, + rready_o, + rvalid_o, + rready_i +); + //parameter N_TARG_PORT = 8; + //parameter AXI_ID_IN = 16; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT); + input wire [AXI_ID_OUT - 1:0] rid_i; + input wire rvalid_i; + output reg rready_o; + output reg [N_TARG_PORT - 1:0] rvalid_o; + input wire [N_TARG_PORT - 1:0] rready_i; + reg [N_TARG_PORT - 1:0] req_mask; + wire [$clog2(N_TARG_PORT) - 1:0] ROUTING; + assign ROUTING = rid_i[(AXI_ID_IN + $clog2(N_TARG_PORT)) - 1:AXI_ID_IN]; + always @(*) begin + req_mask = 1'sb0; + req_mask[ROUTING] = 1'b1; + end + always @(*) begin + if (rvalid_i) + rvalid_o = {N_TARG_PORT {rvalid_i}} & req_mask; + else + rvalid_o = 1'sb0; + rready_o = |(rready_i & req_mask); + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BW.v b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BW.v new file mode 100644 index 0000000..28d45ea --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BW.v
@@ -0,0 +1,36 @@ +module axi_address_decoder_BW +#( + parameter N_TARG_PORT = 3, + parameter AXI_ID_IN = 3, + parameter AXI_ID_OUT = AXI_ID_IN+$clog2(N_TARG_PORT) +) +( + bid_i, + bvalid_i, + bready_o, + bvalid_o, + bready_i +); + //parameter N_TARG_PORT = 3; + //parameter AXI_ID_IN = 3; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT); + input wire [AXI_ID_OUT - 1:0] bid_i; + input wire bvalid_i; + output reg bready_o; + output reg [N_TARG_PORT - 1:0] bvalid_o; + input wire [N_TARG_PORT - 1:0] bready_i; + reg [N_TARG_PORT - 1:0] req_mask; + wire [$clog2(N_TARG_PORT) - 1:0] ROUTING; + assign ROUTING = bid_i[(AXI_ID_IN + $clog2(N_TARG_PORT)) - 1:AXI_ID_IN]; + always @(*) begin + req_mask = 1'sb0; + req_mask[ROUTING] = 1'b1; + end + always @(*) begin + if (bvalid_i) + bvalid_o = {N_TARG_PORT {bvalid_i}} & req_mask; + else + bvalid_o = 1'sb0; + bready_o = |(bready_i & req_mask); + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_address_decoder_DW.v b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_DW.v new file mode 100644 index 0000000..f84dae6 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_address_decoder_DW.v
@@ -0,0 +1,68 @@ +module axi_address_decoder_DW +#( + parameter N_INIT_PORT = 4, + parameter FIFO_DEPTH = 8 +) +( + clk, + rst_n, + test_en_i, + wvalid_i, + wlast_i, + wready_o, + wvalid_o, + wready_i, + grant_FIFO_DEST_o, + DEST_i, + push_DEST_i, + handle_error_i, + wdata_error_completed_o +); + //parameter N_INIT_PORT = 4; + //parameter FIFO_DEPTH = 8; + input wire clk; + input wire rst_n; + input wire test_en_i; + input wire wvalid_i; + input wire wlast_i; + output reg wready_o; + output reg [N_INIT_PORT - 1:0] wvalid_o; + input wire [N_INIT_PORT - 1:0] wready_i; + output wire grant_FIFO_DEST_o; + input wire [N_INIT_PORT - 1:0] DEST_i; + input wire push_DEST_i; + input wire handle_error_i; + output reg wdata_error_completed_o; + wire valid_DEST; + wire pop_from_DEST_FIFO; + wire [N_INIT_PORT - 1:0] DEST_int; + generic_fifo #( + .DATA_WIDTH(N_INIT_PORT), + .DATA_DEPTH(FIFO_DEPTH) + ) MASTER_ID_FIFO( + .clk(clk), + .rst_n(rst_n), + .test_mode_i(test_en_i), + .data_i(DEST_i), + .valid_i(push_DEST_i), + .grant_o(grant_FIFO_DEST_o), + .data_o(DEST_int), + .valid_o(valid_DEST), + .grant_i(pop_from_DEST_FIFO) + ); + assign pop_from_DEST_FIFO = (wlast_i & wvalid_i) & wready_o; + always @(*) + if (handle_error_i) begin + wready_o = 1'b1; + wvalid_o = 1'sb0; + wdata_error_completed_o = wlast_i & wvalid_i; + end + else begin + wready_o = |(wready_i & DEST_int); + wdata_error_completed_o = 1'b0; + if (wvalid_i & valid_DEST) + wvalid_o = {N_INIT_PORT {wvalid_i}} & DEST_int; + else + wvalid_o = 1'sb0; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_multiplexer.v b/verilog/rtl/ips/axi/axi_node/axi_multiplexer.v new file mode 100644 index 0000000..ffa3afa --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_multiplexer.v
@@ -0,0 +1,19 @@ +module axi_multiplexer +#( + parameter DATA_WIDTH = 64, + parameter N_IN = 16, + parameter SEL_WIDTH = $clog2(N_IN) +) +( + IN_DATA, + OUT_DATA, + SEL +); + //parameter DATA_WIDTH = 64; + //parameter N_IN = 16; + //parameter SEL_WIDTH = $clog2(N_IN); + input wire [(N_IN * DATA_WIDTH) - 1:0] IN_DATA; + output wire [DATA_WIDTH - 1:0] OUT_DATA; + input wire [SEL_WIDTH - 1:0] SEL; + assign OUT_DATA = IN_DATA[SEL * DATA_WIDTH+:DATA_WIDTH]; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_node.v b/verilog/rtl/ips/axi/axi_node/axi_node.v new file mode 100644 index 0000000..4b14eb8 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_node.v
@@ -0,0 +1,432 @@ +module axi_node +#( + parameter AXI_ADDRESS_W = 32, + parameter AXI_DATA_W = 64, + parameter AXI_NUMBYTES = AXI_DATA_W/8, + parameter AXI_USER_W = 6, +`ifdef USE_CFG_BLOCK + `ifdef USE_AXI_LITE + parameter AXI_LITE_ADDRESS_W = 32, + parameter AXI_LITE_DATA_W = 32, + parameter AXI_LITE_BE_W = AXI_LITE_DATA_W/8, + `else + parameter APB_ADDR_WIDTH = 32, + parameter APB_DATA_WIDTH = 32, + `endif +`endif + parameter N_MASTER_PORT = 8, + parameter N_SLAVE_PORT = 4, + parameter AXI_ID_IN = 16, + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_SLAVE_PORT), + parameter FIFO_DEPTH_DW = 8, + parameter N_REGION = 2 +) +( + clk, + rst_n, + test_en_i, + slave_awid_i, + slave_awaddr_i, + slave_awlen_i, + slave_awsize_i, + slave_awburst_i, + slave_awlock_i, + slave_awcache_i, + slave_awprot_i, + slave_awregion_i, + slave_awuser_i, + slave_awqos_i, + slave_awvalid_i, + slave_awready_o, + slave_wdata_i, + slave_wstrb_i, + slave_wlast_i, + slave_wuser_i, + slave_wvalid_i, + slave_wready_o, + slave_bid_o, + slave_bresp_o, + slave_bvalid_o, + slave_buser_o, + slave_bready_i, + slave_arid_i, + slave_araddr_i, + slave_arlen_i, + slave_arsize_i, + slave_arburst_i, + slave_arlock_i, + slave_arcache_i, + slave_arprot_i, + slave_arregion_i, + slave_aruser_i, + slave_arqos_i, + slave_arvalid_i, + slave_arready_o, + slave_rid_o, + slave_rdata_o, + slave_rresp_o, + slave_rlast_o, + slave_ruser_o, + slave_rvalid_o, + slave_rready_i, + master_awid_o, + master_awaddr_o, + master_awlen_o, + master_awsize_o, + master_awburst_o, + master_awlock_o, + master_awcache_o, + master_awprot_o, + master_awregion_o, + master_awuser_o, + master_awqos_o, + master_awvalid_o, + master_awready_i, + master_wdata_o, + master_wstrb_o, + master_wlast_o, + master_wuser_o, + master_wvalid_o, + master_wready_i, + master_bid_i, + master_bresp_i, + master_buser_i, + master_bvalid_i, + master_bready_o, + master_arid_o, + master_araddr_o, + master_arlen_o, + master_arsize_o, + master_arburst_o, + master_arlock_o, + master_arcache_o, + master_arprot_o, + master_arregion_o, + master_aruser_o, + master_arqos_o, + master_arvalid_o, + master_arready_i, + master_rid_i, + master_rdata_i, + master_rresp_i, + master_rlast_i, + master_ruser_i, + master_rvalid_i, + master_rready_o, + cfg_START_ADDR_i, + cfg_END_ADDR_i, + cfg_valid_rule_i, + cfg_connectivity_map_i +); + //parameter AXI_ADDRESS_W = 32; + //parameter AXI_DATA_W = 64; + //parameter AXI_NUMBYTES = AXI_DATA_W / 8; + //parameter AXI_USER_W = 6; + //parameter N_MASTER_PORT = 8; + //parameter N_SLAVE_PORT = 4; + //parameter AXI_ID_IN = 16; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_SLAVE_PORT); + //parameter FIFO_DEPTH_DW = 8; + //parameter N_REGION = 2; + input wire clk; + input wire rst_n; + input wire test_en_i; + input wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_awid_i; + input wire [(N_SLAVE_PORT * AXI_ADDRESS_W) - 1:0] slave_awaddr_i; + input wire [(N_SLAVE_PORT * 8) - 1:0] slave_awlen_i; + input wire [(N_SLAVE_PORT * 3) - 1:0] slave_awsize_i; + input wire [(N_SLAVE_PORT * 2) - 1:0] slave_awburst_i; + input wire [N_SLAVE_PORT - 1:0] slave_awlock_i; + input wire [(N_SLAVE_PORT * 4) - 1:0] slave_awcache_i; + input wire [(N_SLAVE_PORT * 3) - 1:0] slave_awprot_i; + input wire [(N_SLAVE_PORT * 4) - 1:0] slave_awregion_i; + input wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_awuser_i; + input wire [(N_SLAVE_PORT * 4) - 1:0] slave_awqos_i; + input wire [N_SLAVE_PORT - 1:0] slave_awvalid_i; + output wire [N_SLAVE_PORT - 1:0] slave_awready_o; + input wire [(N_SLAVE_PORT * AXI_DATA_W) - 1:0] slave_wdata_i; + input wire [(N_SLAVE_PORT * AXI_NUMBYTES) - 1:0] slave_wstrb_i; + input wire [N_SLAVE_PORT - 1:0] slave_wlast_i; + input wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_wuser_i; + input wire [N_SLAVE_PORT - 1:0] slave_wvalid_i; + output wire [N_SLAVE_PORT - 1:0] slave_wready_o; + output wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_bid_o; + output wire [(N_SLAVE_PORT * 2) - 1:0] slave_bresp_o; + output wire [N_SLAVE_PORT - 1:0] slave_bvalid_o; + output wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_buser_o; + input wire [N_SLAVE_PORT - 1:0] slave_bready_i; + input wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_arid_i; + input wire [(N_SLAVE_PORT * AXI_ADDRESS_W) - 1:0] slave_araddr_i; + input wire [(N_SLAVE_PORT * 8) - 1:0] slave_arlen_i; + input wire [(N_SLAVE_PORT * 3) - 1:0] slave_arsize_i; + input wire [(N_SLAVE_PORT * 2) - 1:0] slave_arburst_i; + input wire [N_SLAVE_PORT - 1:0] slave_arlock_i; + input wire [(N_SLAVE_PORT * 4) - 1:0] slave_arcache_i; + input wire [(N_SLAVE_PORT * 3) - 1:0] slave_arprot_i; + input wire [(N_SLAVE_PORT * 4) - 1:0] slave_arregion_i; + input wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_aruser_i; + input wire [(N_SLAVE_PORT * 4) - 1:0] slave_arqos_i; + input wire [N_SLAVE_PORT - 1:0] slave_arvalid_i; + output wire [N_SLAVE_PORT - 1:0] slave_arready_o; + output wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_rid_o; + output wire [(N_SLAVE_PORT * AXI_DATA_W) - 1:0] slave_rdata_o; + output wire [(N_SLAVE_PORT * 2) - 1:0] slave_rresp_o; + output wire [N_SLAVE_PORT - 1:0] slave_rlast_o; + output wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_ruser_o; + output wire [N_SLAVE_PORT - 1:0] slave_rvalid_o; + input wire [N_SLAVE_PORT - 1:0] slave_rready_i; + output wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_awid_o; + output wire [(N_MASTER_PORT * AXI_ADDRESS_W) - 1:0] master_awaddr_o; + output wire [(N_MASTER_PORT * 8) - 1:0] master_awlen_o; + output wire [(N_MASTER_PORT * 3) - 1:0] master_awsize_o; + output wire [(N_MASTER_PORT * 2) - 1:0] master_awburst_o; + output wire [N_MASTER_PORT - 1:0] master_awlock_o; + output wire [(N_MASTER_PORT * 4) - 1:0] master_awcache_o; + output wire [(N_MASTER_PORT * 3) - 1:0] master_awprot_o; + output wire [(N_MASTER_PORT * 4) - 1:0] master_awregion_o; + output wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_awuser_o; + output wire [(N_MASTER_PORT * 4) - 1:0] master_awqos_o; + output wire [N_MASTER_PORT - 1:0] master_awvalid_o; + input wire [N_MASTER_PORT - 1:0] master_awready_i; + output wire [(N_MASTER_PORT * AXI_DATA_W) - 1:0] master_wdata_o; + output wire [(N_MASTER_PORT * AXI_NUMBYTES) - 1:0] master_wstrb_o; + output wire [N_MASTER_PORT - 1:0] master_wlast_o; + output wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_wuser_o; + output wire [N_MASTER_PORT - 1:0] master_wvalid_o; + input wire [N_MASTER_PORT - 1:0] master_wready_i; + input wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_bid_i; + input wire [(N_MASTER_PORT * 2) - 1:0] master_bresp_i; + input wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_buser_i; + input wire [N_MASTER_PORT - 1:0] master_bvalid_i; + output wire [N_MASTER_PORT - 1:0] master_bready_o; + output wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_arid_o; + output wire [(N_MASTER_PORT * AXI_ADDRESS_W) - 1:0] master_araddr_o; + output wire [(N_MASTER_PORT * 8) - 1:0] master_arlen_o; + output wire [(N_MASTER_PORT * 3) - 1:0] master_arsize_o; + output wire [(N_MASTER_PORT * 2) - 1:0] master_arburst_o; + output wire [N_MASTER_PORT - 1:0] master_arlock_o; + output wire [(N_MASTER_PORT * 4) - 1:0] master_arcache_o; + output wire [(N_MASTER_PORT * 3) - 1:0] master_arprot_o; + output wire [(N_MASTER_PORT * 4) - 1:0] master_arregion_o; + output wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_aruser_o; + output wire [(N_MASTER_PORT * 4) - 1:0] master_arqos_o; + output wire [N_MASTER_PORT - 1:0] master_arvalid_o; + input wire [N_MASTER_PORT - 1:0] master_arready_i; + input wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_rid_i; + input wire [(N_MASTER_PORT * AXI_DATA_W) - 1:0] master_rdata_i; + input wire [(N_MASTER_PORT * 2) - 1:0] master_rresp_i; + input wire [N_MASTER_PORT - 1:0] master_rlast_i; + input wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_ruser_i; + input wire [N_MASTER_PORT - 1:0] master_rvalid_i; + output wire [N_MASTER_PORT - 1:0] master_rready_o; + input wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] cfg_START_ADDR_i; + input wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] cfg_END_ADDR_i; + input wire [(N_REGION * N_MASTER_PORT) - 1:0] cfg_valid_rule_i; + input wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] cfg_connectivity_map_i; + genvar i; + genvar j; + genvar k; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] arvalid_int; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] arready_int; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] arvalid_int_reverse; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] arready_int_reverse; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] awvalid_int; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] awready_int; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] awvalid_int_reverse; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] awready_int_reverse; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] wvalid_int; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] wready_int; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] wvalid_int_reverse; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] wready_int_reverse; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] bvalid_int; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] bready_int; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] bvalid_int_reverse; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] bready_int_reverse; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] rvalid_int; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] rready_int; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] rvalid_int_reverse; + wire [(N_MASTER_PORT * N_SLAVE_PORT) - 1:0] rready_int_reverse; + wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] START_ADDR; + wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] END_ADDR; + wire [(N_REGION * N_MASTER_PORT) - 1:0] valid_rule; + wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] connectivity_map; + generate + for (i = 0; i < N_MASTER_PORT; i = i + 1) begin : _REVERSING_VALID_READY_MASTER + for (j = 0; j < N_SLAVE_PORT; j = j + 1) begin : _REVERSING_VALID_READY_SLAVE + assign arvalid_int_reverse[(i * N_SLAVE_PORT) + j] = arvalid_int[(j * N_MASTER_PORT) + i]; + assign awvalid_int_reverse[(i * N_SLAVE_PORT) + j] = awvalid_int[(j * N_MASTER_PORT) + i]; + assign wvalid_int_reverse[(i * N_SLAVE_PORT) + j] = wvalid_int[(j * N_MASTER_PORT) + i]; + assign bvalid_int_reverse[(j * N_MASTER_PORT) + i] = bvalid_int[(i * N_SLAVE_PORT) + j]; + assign rvalid_int_reverse[(j * N_MASTER_PORT) + i] = rvalid_int[(i * N_SLAVE_PORT) + j]; + assign arready_int_reverse[(j * N_MASTER_PORT) + i] = arready_int[(i * N_SLAVE_PORT) + j]; + assign awready_int_reverse[(j * N_MASTER_PORT) + i] = awready_int[(i * N_SLAVE_PORT) + j]; + assign wready_int_reverse[(j * N_MASTER_PORT) + i] = wready_int[(i * N_SLAVE_PORT) + j]; + assign bready_int_reverse[(i * N_SLAVE_PORT) + j] = bready_int[(j * N_MASTER_PORT) + i]; + assign rready_int_reverse[(i * N_SLAVE_PORT) + j] = rready_int[(j * N_MASTER_PORT) + i]; + end + end + for (i = 0; i < N_MASTER_PORT; i = i + 1) begin : _REQ_BLOCK_GEN + axi_request_block #( + .AXI_ADDRESS_W(AXI_ADDRESS_W), + .AXI_DATA_W(AXI_DATA_W), + .AXI_USER_W(AXI_USER_W), + .N_INIT_PORT(N_MASTER_PORT), + .N_TARG_PORT(N_SLAVE_PORT), + .FIFO_DW_DEPTH(FIFO_DEPTH_DW), + .AXI_ID_IN(AXI_ID_IN) + ) REQ_BLOCK( + .clk(clk), + .rst_n(rst_n), + .test_en_i(test_en_i), + .awid_i(slave_awid_i), + .awaddr_i(slave_awaddr_i), + .awlen_i(slave_awlen_i), + .awsize_i(slave_awsize_i), + .awburst_i(slave_awburst_i), + .awlock_i(slave_awlock_i), + .awcache_i(slave_awcache_i), + .awprot_i(slave_awprot_i), + .awregion_i(slave_awregion_i), + .awuser_i(slave_awuser_i), + .awqos_i(slave_awqos_i), + .awvalid_i(awvalid_int_reverse[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .awready_o(awready_int[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .wdata_i(slave_wdata_i), + .wstrb_i(slave_wstrb_i), + .wlast_i(slave_wlast_i), + .wuser_i(slave_wuser_i), + .wvalid_i(wvalid_int_reverse[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .wready_o(wready_int[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .arid_i(slave_arid_i), + .araddr_i(slave_araddr_i), + .arlen_i(slave_arlen_i), + .arsize_i(slave_arsize_i), + .arburst_i(slave_arburst_i), + .arlock_i(slave_arlock_i), + .arcache_i(slave_arcache_i), + .arprot_i(slave_arprot_i), + .arregion_i(slave_arregion_i), + .aruser_i(slave_aruser_i), + .arqos_i(slave_arqos_i), + .arvalid_i(arvalid_int_reverse[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .arready_o(arready_int[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .bid_i(master_bid_i[i * AXI_ID_OUT+:AXI_ID_OUT]), + .bvalid_i(master_bvalid_i[i]), + .bready_o(master_bready_o[i]), + .bvalid_o(bvalid_int[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .bready_i(bready_int_reverse[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .rid_i(master_rid_i[i * AXI_ID_OUT+:AXI_ID_OUT]), + .rvalid_i(master_rvalid_i[i]), + .rready_o(master_rready_o[i]), + .rvalid_o(rvalid_int[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .rready_i(rready_int_reverse[i * N_SLAVE_PORT+:N_SLAVE_PORT]), + .awid_o(master_awid_o[i * AXI_ID_OUT+:AXI_ID_OUT]), + .awaddr_o(master_awaddr_o[i * AXI_ADDRESS_W+:AXI_ADDRESS_W]), + .awlen_o(master_awlen_o[i * 8+:8]), + .awsize_o(master_awsize_o[i * 3+:3]), + .awburst_o(master_awburst_o[i * 2+:2]), + .awlock_o(master_awlock_o[i]), + .awcache_o(master_awcache_o[i * 4+:4]), + .awprot_o(master_awprot_o[i * 3+:3]), + .awregion_o(master_awregion_o[i * 4+:4]), + .awuser_o(master_awuser_o[i * AXI_USER_W+:AXI_USER_W]), + .awqos_o(master_awqos_o[i * 4+:4]), + .awvalid_o(master_awvalid_o[i]), + .awready_i(master_awready_i[i]), + .wdata_o(master_wdata_o[i * AXI_DATA_W+:AXI_DATA_W]), + .wstrb_o(master_wstrb_o[i * AXI_NUMBYTES+:AXI_NUMBYTES]), + .wlast_o(master_wlast_o[i]), + .wuser_o(master_wuser_o[i * AXI_USER_W+:AXI_USER_W]), + .wvalid_o(master_wvalid_o[i]), + .wready_i(master_wready_i[i]), + .arid_o(master_arid_o[i * AXI_ID_OUT+:AXI_ID_OUT]), + .araddr_o(master_araddr_o[i * AXI_ADDRESS_W+:AXI_ADDRESS_W]), + .arlen_o(master_arlen_o[i * 8+:8]), + .arsize_o(master_arsize_o[i * 3+:3]), + .arburst_o(master_arburst_o[i * 2+:2]), + .arlock_o(master_arlock_o[i]), + .arcache_o(master_arcache_o[i * 4+:4]), + .arprot_o(master_arprot_o[i * 3+:3]), + .arregion_o(master_arregion_o[i * 4+:4]), + .aruser_o(master_aruser_o[i * AXI_USER_W+:AXI_USER_W]), + .arqos_o(master_arqos_o[i * 4+:4]), + .arvalid_o(master_arvalid_o[i]), + .arready_i(master_arready_i[i]) + ); + end + for (i = 0; i < N_SLAVE_PORT; i = i + 1) begin : _RESP_BLOCK_GEN + axi_response_block #( + .AXI_ADDRESS_W(AXI_ADDRESS_W), + .AXI_DATA_W(AXI_DATA_W), + .AXI_USER_W(AXI_USER_W), + .N_INIT_PORT(N_MASTER_PORT), + .N_TARG_PORT(N_SLAVE_PORT), + .FIFO_DEPTH_DW(FIFO_DEPTH_DW), + .AXI_ID_IN(AXI_ID_IN), + .N_REGION(N_REGION) + ) RESP_BLOCK( + .clk(clk), + .rst_n(rst_n), + .test_en_i(test_en_i), + .rid_i(master_rid_i), + .rdata_i(master_rdata_i), + .rresp_i(master_rresp_i), + .rlast_i(master_rlast_i), + .ruser_i(master_ruser_i), + .rvalid_i(rvalid_int_reverse[i * N_MASTER_PORT+:N_MASTER_PORT]), + .rready_o(rready_int[i * N_MASTER_PORT+:N_MASTER_PORT]), + .bid_i(master_bid_i), + .bresp_i(master_bresp_i), + .buser_i(master_buser_i), + .bvalid_i(bvalid_int_reverse[i * N_MASTER_PORT+:N_MASTER_PORT]), + .bready_o(bready_int[i * N_MASTER_PORT+:N_MASTER_PORT]), + .rid_o(slave_rid_o[i * AXI_ID_IN+:AXI_ID_IN]), + .rdata_o(slave_rdata_o[i * AXI_DATA_W+:AXI_DATA_W]), + .rresp_o(slave_rresp_o[i * 2+:2]), + .rlast_o(slave_rlast_o[i]), + .ruser_o(slave_ruser_o[i * AXI_USER_W+:AXI_USER_W]), + .rvalid_o(slave_rvalid_o[i]), + .rready_i(slave_rready_i[i]), + .bid_o(slave_bid_o[i * AXI_ID_IN+:AXI_ID_IN]), + .bresp_o(slave_bresp_o[i * 2+:2]), + .buser_o(slave_buser_o[i * AXI_USER_W+:AXI_USER_W]), + .bvalid_o(slave_bvalid_o[i]), + .bready_i(slave_bready_i[i]), + .arvalid_i(slave_arvalid_i[i]), + .araddr_i(slave_araddr_i[i * AXI_ADDRESS_W+:AXI_ADDRESS_W]), + .arready_o(slave_arready_o[i]), + .arlen_i(slave_arlen_i[i * 8+:8]), + .aruser_i(slave_aruser_i[i * AXI_USER_W+:AXI_USER_W]), + .arid_i(slave_arid_i[i * AXI_ID_IN+:AXI_ID_IN]), + .arvalid_o(arvalid_int[i * N_MASTER_PORT+:N_MASTER_PORT]), + .arready_i(arready_int_reverse[i * N_MASTER_PORT+:N_MASTER_PORT]), + .awvalid_i(slave_awvalid_i[i]), + .awaddr_i(slave_awaddr_i[i * AXI_ADDRESS_W+:AXI_ADDRESS_W]), + .awready_o(slave_awready_o[i]), + .awuser_i(slave_awuser_i[i * AXI_USER_W+:AXI_USER_W]), + .awid_i(slave_awid_i[i * AXI_ID_IN+:AXI_ID_IN]), + .awvalid_o(awvalid_int[i * N_MASTER_PORT+:N_MASTER_PORT]), + .awready_i(awready_int_reverse[i * N_MASTER_PORT+:N_MASTER_PORT]), + .wvalid_i(slave_wvalid_i[i]), + .wlast_i(slave_wlast_i[i]), + .wready_o(slave_wready_o[i]), + .wvalid_o(wvalid_int[i * N_MASTER_PORT+:N_MASTER_PORT]), + .wready_i(wready_int_reverse[i * N_MASTER_PORT+:N_MASTER_PORT]), + .START_ADDR_i(START_ADDR), + .END_ADDR_i(END_ADDR), + .enable_region_i(valid_rule), + .connectivity_map_i(connectivity_map[i * N_MASTER_PORT+:N_MASTER_PORT]) + ); + end + endgenerate + assign START_ADDR = cfg_START_ADDR_i; + assign END_ADDR = cfg_END_ADDR_i; + assign connectivity_map = cfg_connectivity_map_i; + generate + for (i = 0; i < N_REGION; i = i + 1) begin : _VALID_RULE_REGION + for (j = 0; j < N_MASTER_PORT; j = j + 1) begin : _VALID_RULE_MASTER + assign valid_rule[(i * N_MASTER_PORT) + j] = cfg_valid_rule_i[(i * N_MASTER_PORT) + j]; + end + end + endgenerate +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_node_wrap.v b/verilog/rtl/ips/axi/axi_node/axi_node_wrap.v new file mode 100644 index 0000000..ee57079 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_node_wrap.v
@@ -0,0 +1,1044 @@ +`include "defines.v" + +module axi_node_wrap +#( + + parameter AXI_ADDRESS_W = 32, + parameter AXI_DATA_W = 64, + parameter AXI_NUMBYTES = AXI_DATA_W/8, + parameter AXI_USER_W = 6, +`ifdef USE_CFG_BLOCK + `ifdef USE_AXI_LITE + parameter AXI_LITE_ADDRESS_W = 32, + parameter AXI_LITE_DATA_W = 32, + `else + parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default + parameter APB_DATA_WIDTH = 32, + `endif +`endif + parameter N_MASTER_PORT = 8, + parameter N_SLAVE_PORT = 4, + parameter AXI_ID_IN = 10, + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_SLAVE_PORT), + parameter FIFO_DEPTH_DW = 8, + parameter N_REGION = 2 +) +( + clk, + rst_n, + test_en_i, + slave_00_aw_addr, + slave_00_aw_prot, + slave_00_aw_region, + slave_00_aw_len, + slave_00_aw_size, + slave_00_aw_burst, + slave_00_aw_lock, + slave_00_aw_cache, + slave_00_aw_qos, + slave_00_aw_id, + slave_00_aw_user, + slave_00_aw_ready, + slave_00_aw_valid, + slave_00_ar_addr, + slave_00_ar_prot, + slave_00_ar_region, + slave_00_ar_len, + slave_00_ar_size, + slave_00_ar_burst, + slave_00_ar_lock, + slave_00_ar_cache, + slave_00_ar_qos, + slave_00_ar_id, + slave_00_ar_user, + slave_00_ar_ready, + slave_00_ar_valid, + slave_00_w_valid, + slave_00_w_data, + slave_00_w_strb, + slave_00_w_user, + slave_00_w_last, + slave_00_w_ready, + slave_00_r_data, + slave_00_r_resp, + slave_00_r_last, + slave_00_r_id, + slave_00_r_user, + slave_00_r_ready, + slave_00_r_valid, + slave_00_b_resp, + slave_00_b_id, + slave_00_b_user, + slave_00_b_ready, + slave_00_b_valid, + slave_01_aw_addr, + slave_01_aw_prot, + slave_01_aw_region, + slave_01_aw_len, + slave_01_aw_size, + slave_01_aw_burst, + slave_01_aw_lock, + slave_01_aw_cache, + slave_01_aw_qos, + slave_01_aw_id, + slave_01_aw_user, + slave_01_aw_ready, + slave_01_aw_valid, + slave_01_ar_addr, + slave_01_ar_prot, + slave_01_ar_region, + slave_01_ar_len, + slave_01_ar_size, + slave_01_ar_burst, + slave_01_ar_lock, + slave_01_ar_cache, + slave_01_ar_qos, + slave_01_ar_id, + slave_01_ar_user, + slave_01_ar_ready, + slave_01_ar_valid, + slave_01_w_valid, + slave_01_w_data, + slave_01_w_strb, + slave_01_w_user, + slave_01_w_last, + slave_01_w_ready, + slave_01_r_data, + slave_01_r_resp, + slave_01_r_last, + slave_01_r_id, + slave_01_r_user, + slave_01_r_ready, + slave_01_r_valid, + slave_01_b_resp, + slave_01_b_id, + slave_01_b_user, + slave_01_b_ready, + slave_01_b_valid, + slave_02_aw_addr, + slave_02_aw_prot, + slave_02_aw_region, + slave_02_aw_len, + slave_02_aw_size, + slave_02_aw_burst, + slave_02_aw_lock, + slave_02_aw_cache, + slave_02_aw_qos, + slave_02_aw_id, + slave_02_aw_user, + slave_02_aw_ready, + slave_02_aw_valid, + slave_02_ar_addr, + slave_02_ar_prot, + slave_02_ar_region, + slave_02_ar_len, + slave_02_ar_size, + slave_02_ar_burst, + slave_02_ar_lock, + slave_02_ar_cache, + slave_02_ar_qos, + slave_02_ar_id, + slave_02_ar_user, + slave_02_ar_ready, + slave_02_ar_valid, + slave_02_w_valid, + slave_02_w_data, + slave_02_w_strb, + slave_02_w_user, + slave_02_w_last, + slave_02_w_ready, + slave_02_r_data, + slave_02_r_resp, + slave_02_r_last, + slave_02_r_id, + slave_02_r_user, + slave_02_r_ready, + slave_02_r_valid, + slave_02_b_resp, + slave_02_b_id, + slave_02_b_user, + slave_02_b_ready, + slave_02_b_valid, + master_00_aw_addr, + master_00_aw_prot, + master_00_aw_region, + master_00_aw_len, + master_00_aw_size, + master_00_aw_burst, + master_00_aw_lock, + master_00_aw_cache, + master_00_aw_qos, + master_00_aw_id, + master_00_aw_user, + master_00_aw_ready, + master_00_aw_valid, + master_00_ar_addr, + master_00_ar_prot, + master_00_ar_region, + master_00_ar_len, + master_00_ar_size, + master_00_ar_burst, + master_00_ar_lock, + master_00_ar_cache, + master_00_ar_qos, + master_00_ar_id, + master_00_ar_user, + master_00_ar_ready, + master_00_ar_valid, + master_00_w_valid, + master_00_w_data, + master_00_w_strb, + master_00_w_user, + master_00_w_last, + master_00_w_ready, + master_00_r_data, + master_00_r_resp, + master_00_r_last, + master_00_r_id, + master_00_r_user, + master_00_r_ready, + master_00_r_valid, + master_00_b_resp, + master_00_b_id, + master_00_b_user, + master_00_b_ready, + master_00_b_valid, + master_01_aw_addr, + master_01_aw_prot, + master_01_aw_region, + master_01_aw_len, + master_01_aw_size, + master_01_aw_burst, + master_01_aw_lock, + master_01_aw_cache, + master_01_aw_qos, + master_01_aw_id, + master_01_aw_user, + master_01_aw_ready, + master_01_aw_valid, + master_01_ar_addr, + master_01_ar_prot, + master_01_ar_region, + master_01_ar_len, + master_01_ar_size, + master_01_ar_burst, + master_01_ar_lock, + master_01_ar_cache, + master_01_ar_qos, + master_01_ar_id, + master_01_ar_user, + master_01_ar_ready, + master_01_ar_valid, + master_01_w_valid, + master_01_w_data, + master_01_w_strb, + master_01_w_user, + master_01_w_last, + master_01_w_ready, + master_01_r_data, + master_01_r_resp, + master_01_r_last, + master_01_r_id, + master_01_r_user, + master_01_r_ready, + master_01_r_valid, + master_01_b_resp, + master_01_b_id, + master_01_b_user, + master_01_b_ready, + master_01_b_valid, + master_02_aw_addr, + master_02_aw_prot, + master_02_aw_region, + master_02_aw_len, + master_02_aw_size, + master_02_aw_burst, + master_02_aw_lock, + master_02_aw_cache, + master_02_aw_qos, + master_02_aw_id, + master_02_aw_user, + master_02_aw_ready, + master_02_aw_valid, + master_02_ar_addr, + master_02_ar_prot, + master_02_ar_region, + master_02_ar_len, + master_02_ar_size, + master_02_ar_burst, + master_02_ar_lock, + master_02_ar_cache, + master_02_ar_qos, + master_02_ar_id, + master_02_ar_user, + master_02_ar_ready, + master_02_ar_valid, + master_02_w_valid, + master_02_w_data, + master_02_w_strb, + master_02_w_user, + master_02_w_last, + master_02_w_ready, + master_02_r_data, + master_02_r_resp, + master_02_r_last, + master_02_r_id, + master_02_r_user, + master_02_r_ready, + master_02_r_valid, + master_02_b_resp, + master_02_b_id, + master_02_b_user, + master_02_b_ready, + master_02_b_valid, + cfg_START_ADDR_i, + cfg_END_ADDR_i, + cfg_valid_rule_i, + cfg_connectivity_map_i +); + //parameter AXI_ADDRESS_W = 32; + //parameter AXI_ADDR_WIDTH = 32; + //parameter AXI_DATA_W = 64; + //parameter AXI_NUMBYTES = AXI_DATA_W / 8; + //parameter AXI_USER_W = 6; + //parameter N_MASTER_PORT = 8; + //parameter N_SLAVE_PORT = 4; + //parameter AXI_ID_IN = 10; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_SLAVE_PORT); + //parameter FIFO_DEPTH_DW = 8; + //parameter N_REGION = 2; + parameter AXI_ADDR_WIDTH = AXI_ADDRESS_W; + parameter AXI_DATA_WIDTH = AXI_DATA_W; + parameter AXI_ID_WIDTH = 10; + parameter AXI_USER_WIDTH = 6; + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8; + input wire clk; + input wire rst_n; + input wire test_en_i; + input wire [AXI_ADDR_WIDTH - 1:0] slave_00_aw_addr; + input wire [2:0] slave_00_aw_prot; + input wire [3:0] slave_00_aw_region; + input wire [7:0] slave_00_aw_len; + input wire [2:0] slave_00_aw_size; + input wire [1:0] slave_00_aw_burst; + input wire slave_00_aw_lock; + input wire [3:0] slave_00_aw_cache; + input wire [3:0] slave_00_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_00_aw_id; + input wire [AXI_USER_WIDTH - 1:0] slave_00_aw_user; + output wire slave_00_aw_ready; + input wire slave_00_aw_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_00_ar_addr; + input wire [2:0] slave_00_ar_prot; + input wire [3:0] slave_00_ar_region; + input wire [7:0] slave_00_ar_len; + input wire [2:0] slave_00_ar_size; + input wire [1:0] slave_00_ar_burst; + input wire slave_00_ar_lock; + input wire [3:0] slave_00_ar_cache; + input wire [3:0] slave_00_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_00_ar_id; + input wire [AXI_USER_WIDTH - 1:0] slave_00_ar_user; + output wire slave_00_ar_ready; + input wire slave_00_ar_valid; + input wire slave_00_w_valid; + input wire [AXI_DATA_WIDTH - 1:0] slave_00_w_data; + input wire [AXI_STRB_WIDTH - 1:0] slave_00_w_strb; + input wire [AXI_USER_WIDTH - 1:0] slave_00_w_user; + input wire slave_00_w_last; + output wire slave_00_w_ready; + output wire [AXI_DATA_WIDTH - 1:0] slave_00_r_data; + output wire [1:0] slave_00_r_resp; + output wire slave_00_r_last; + output wire [AXI_ID_WIDTH - 1:0] slave_00_r_id; + output wire [AXI_USER_WIDTH - 1:0] slave_00_r_user; + input wire slave_00_r_ready; + output wire slave_00_r_valid; + output wire [1:0] slave_00_b_resp; + output wire [AXI_ID_WIDTH - 1:0] slave_00_b_id; + output wire [AXI_USER_WIDTH - 1:0] slave_00_b_user; + input wire slave_00_b_ready; + output wire slave_00_b_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_01_aw_addr; + input wire [2:0] slave_01_aw_prot; + input wire [3:0] slave_01_aw_region; + input wire [7:0] slave_01_aw_len; + input wire [2:0] slave_01_aw_size; + input wire [1:0] slave_01_aw_burst; + input wire slave_01_aw_lock; + input wire [3:0] slave_01_aw_cache; + input wire [3:0] slave_01_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_01_aw_id; + input wire [AXI_USER_WIDTH - 1:0] slave_01_aw_user; + output wire slave_01_aw_ready; + input wire slave_01_aw_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_01_ar_addr; + input wire [2:0] slave_01_ar_prot; + input wire [3:0] slave_01_ar_region; + input wire [7:0] slave_01_ar_len; + input wire [2:0] slave_01_ar_size; + input wire [1:0] slave_01_ar_burst; + input wire slave_01_ar_lock; + input wire [3:0] slave_01_ar_cache; + input wire [3:0] slave_01_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_01_ar_id; + input wire [AXI_USER_WIDTH - 1:0] slave_01_ar_user; + output wire slave_01_ar_ready; + input wire slave_01_ar_valid; + input wire slave_01_w_valid; + input wire [AXI_DATA_WIDTH - 1:0] slave_01_w_data; + input wire [AXI_STRB_WIDTH - 1:0] slave_01_w_strb; + input wire [AXI_USER_WIDTH - 1:0] slave_01_w_user; + input wire slave_01_w_last; + output wire slave_01_w_ready; + output wire [AXI_DATA_WIDTH - 1:0] slave_01_r_data; + output wire [1:0] slave_01_r_resp; + output wire slave_01_r_last; + output wire [AXI_ID_WIDTH - 1:0] slave_01_r_id; + output wire [AXI_USER_WIDTH - 1:0] slave_01_r_user; + input wire slave_01_r_ready; + output wire slave_01_r_valid; + output wire [1:0] slave_01_b_resp; + output wire [AXI_ID_WIDTH - 1:0] slave_01_b_id; + output wire [AXI_USER_WIDTH - 1:0] slave_01_b_user; + input wire slave_01_b_ready; + output wire slave_01_b_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_02_aw_addr; + input wire [2:0] slave_02_aw_prot; + input wire [3:0] slave_02_aw_region; + input wire [7:0] slave_02_aw_len; + input wire [2:0] slave_02_aw_size; + input wire [1:0] slave_02_aw_burst; + input wire slave_02_aw_lock; + input wire [3:0] slave_02_aw_cache; + input wire [3:0] slave_02_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_02_aw_id; + input wire [AXI_USER_WIDTH - 1:0] slave_02_aw_user; + output wire slave_02_aw_ready; + input wire slave_02_aw_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_02_ar_addr; + input wire [2:0] slave_02_ar_prot; + input wire [3:0] slave_02_ar_region; + input wire [7:0] slave_02_ar_len; + input wire [2:0] slave_02_ar_size; + input wire [1:0] slave_02_ar_burst; + input wire slave_02_ar_lock; + input wire [3:0] slave_02_ar_cache; + input wire [3:0] slave_02_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_02_ar_id; + input wire [AXI_USER_WIDTH - 1:0] slave_02_ar_user; + output wire slave_02_ar_ready; + input wire slave_02_ar_valid; + input wire slave_02_w_valid; + input wire [AXI_DATA_WIDTH - 1:0] slave_02_w_data; + input wire [AXI_STRB_WIDTH - 1:0] slave_02_w_strb; + input wire [AXI_USER_WIDTH - 1:0] slave_02_w_user; + input wire slave_02_w_last; + output wire slave_02_w_ready; + output wire [AXI_DATA_WIDTH - 1:0] slave_02_r_data; + output wire [1:0] slave_02_r_resp; + output wire slave_02_r_last; + output wire [AXI_ID_WIDTH - 1:0] slave_02_r_id; + output wire [AXI_USER_WIDTH - 1:0] slave_02_r_user; + input wire slave_02_r_ready; + output wire slave_02_r_valid; + output wire [1:0] slave_02_b_resp; + output wire [AXI_ID_WIDTH - 1:0] slave_02_b_id; + output wire [AXI_USER_WIDTH - 1:0] slave_02_b_user; + input wire slave_02_b_ready; + output wire slave_02_b_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_00_aw_addr; + output wire [2:0] master_00_aw_prot; + output wire [3:0] master_00_aw_region; + output wire [7:0] master_00_aw_len; + output wire [2:0] master_00_aw_size; + output wire [1:0] master_00_aw_burst; + output wire master_00_aw_lock; + output wire [3:0] master_00_aw_cache; + output wire [3:0] master_00_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] master_00_aw_id; + output wire [AXI_USER_WIDTH - 1:0] master_00_aw_user; + input wire master_00_aw_ready; + output wire master_00_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_00_ar_addr; + output wire [2:0] master_00_ar_prot; + output wire [3:0] master_00_ar_region; + output wire [7:0] master_00_ar_len; + output wire [2:0] master_00_ar_size; + output wire [1:0] master_00_ar_burst; + output wire master_00_ar_lock; + output wire [3:0] master_00_ar_cache; + output wire [3:0] master_00_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] master_00_ar_id; + output wire [AXI_USER_WIDTH - 1:0] master_00_ar_user; + input wire master_00_ar_ready; + output wire master_00_ar_valid; + output wire master_00_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] master_00_w_data; + output wire [AXI_STRB_WIDTH - 1:0] master_00_w_strb; + output wire [AXI_USER_WIDTH - 1:0] master_00_w_user; + output wire master_00_w_last; + input wire master_00_w_ready; + input wire [AXI_DATA_WIDTH - 1:0] master_00_r_data; + input wire [1:0] master_00_r_resp; + input wire master_00_r_last; + input wire [AXI_ID_WIDTH - 1:0] master_00_r_id; + input wire [AXI_USER_WIDTH - 1:0] master_00_r_user; + output wire master_00_r_ready; + input wire master_00_r_valid; + input wire [1:0] master_00_b_resp; + input wire [AXI_ID_WIDTH - 1:0] master_00_b_id; + input wire [AXI_USER_WIDTH - 1:0] master_00_b_user; + output wire master_00_b_ready; + input wire master_00_b_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_01_aw_addr; + output wire [2:0] master_01_aw_prot; + output wire [3:0] master_01_aw_region; + output wire [7:0] master_01_aw_len; + output wire [2:0] master_01_aw_size; + output wire [1:0] master_01_aw_burst; + output wire master_01_aw_lock; + output wire [3:0] master_01_aw_cache; + output wire [3:0] master_01_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] master_01_aw_id; + output wire [AXI_USER_WIDTH - 1:0] master_01_aw_user; + input wire master_01_aw_ready; + output wire master_01_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_01_ar_addr; + output wire [2:0] master_01_ar_prot; + output wire [3:0] master_01_ar_region; + output wire [7:0] master_01_ar_len; + output wire [2:0] master_01_ar_size; + output wire [1:0] master_01_ar_burst; + output wire master_01_ar_lock; + output wire [3:0] master_01_ar_cache; + output wire [3:0] master_01_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] master_01_ar_id; + output wire [AXI_USER_WIDTH - 1:0] master_01_ar_user; + input wire master_01_ar_ready; + output wire master_01_ar_valid; + output wire master_01_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] master_01_w_data; + output wire [AXI_STRB_WIDTH - 1:0] master_01_w_strb; + output wire [AXI_USER_WIDTH - 1:0] master_01_w_user; + output wire master_01_w_last; + input wire master_01_w_ready; + input wire [AXI_DATA_WIDTH - 1:0] master_01_r_data; + input wire [1:0] master_01_r_resp; + input wire master_01_r_last; + input wire [AXI_ID_WIDTH - 1:0] master_01_r_id; + input wire [AXI_USER_WIDTH - 1:0] master_01_r_user; + output wire master_01_r_ready; + input wire master_01_r_valid; + input wire [1:0] master_01_b_resp; + input wire [AXI_ID_WIDTH - 1:0] master_01_b_id; + input wire [AXI_USER_WIDTH - 1:0] master_01_b_user; + output wire master_01_b_ready; + input wire master_01_b_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_02_aw_addr; + output wire [2:0] master_02_aw_prot; + output wire [3:0] master_02_aw_region; + output wire [7:0] master_02_aw_len; + output wire [2:0] master_02_aw_size; + output wire [1:0] master_02_aw_burst; + output wire master_02_aw_lock; + output wire [3:0] master_02_aw_cache; + output wire [3:0] master_02_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] master_02_aw_id; + output wire [AXI_USER_WIDTH - 1:0] master_02_aw_user; + input wire master_02_aw_ready; + output wire master_02_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_02_ar_addr; + output wire [2:0] master_02_ar_prot; + output wire [3:0] master_02_ar_region; + output wire [7:0] master_02_ar_len; + output wire [2:0] master_02_ar_size; + output wire [1:0] master_02_ar_burst; + output wire master_02_ar_lock; + output wire [3:0] master_02_ar_cache; + output wire [3:0] master_02_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] master_02_ar_id; + output wire [AXI_USER_WIDTH - 1:0] master_02_ar_user; + input wire master_02_ar_ready; + output wire master_02_ar_valid; + output wire master_02_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] master_02_w_data; + output wire [AXI_STRB_WIDTH - 1:0] master_02_w_strb; + output wire [AXI_USER_WIDTH - 1:0] master_02_w_user; + output wire master_02_w_last; + input wire master_02_w_ready; + input wire [AXI_DATA_WIDTH - 1:0] master_02_r_data; + input wire [1:0] master_02_r_resp; + input wire master_02_r_last; + input wire [AXI_ID_WIDTH - 1:0] master_02_r_id; + input wire [AXI_USER_WIDTH - 1:0] master_02_r_user; + output wire master_02_r_ready; + input wire master_02_r_valid; + input wire [1:0] master_02_b_resp; + input wire [AXI_ID_WIDTH - 1:0] master_02_b_id; + input wire [AXI_USER_WIDTH - 1:0] master_02_b_user; + output wire master_02_b_ready; + input wire master_02_b_valid; + input wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] cfg_START_ADDR_i; + input wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] cfg_END_ADDR_i; + input wire [(N_REGION * N_MASTER_PORT) - 1:0] cfg_valid_rule_i; + input wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] cfg_connectivity_map_i; + wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_awid; + wire [(N_SLAVE_PORT * AXI_ADDRESS_W) - 1:0] slave_awaddr; + wire [(N_SLAVE_PORT * 8) - 1:0] slave_awlen; + wire [(N_SLAVE_PORT * 3) - 1:0] slave_awsize; + wire [(N_SLAVE_PORT * 2) - 1:0] slave_awburst; + wire [N_SLAVE_PORT - 1:0] slave_awlock; + wire [(N_SLAVE_PORT * 4) - 1:0] slave_awcache; + wire [(N_SLAVE_PORT * 3) - 1:0] slave_awprot; + wire [(N_SLAVE_PORT * 4) - 1:0] slave_awregion; + wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_awuser; + wire [(N_SLAVE_PORT * 4) - 1:0] slave_awqos; + wire [N_SLAVE_PORT - 1:0] slave_awvalid; + wire [N_SLAVE_PORT - 1:0] slave_awready; + wire [(N_SLAVE_PORT * AXI_DATA_W) - 1:0] slave_wdata; + wire [(N_SLAVE_PORT * AXI_NUMBYTES) - 1:0] slave_wstrb; + wire [N_SLAVE_PORT - 1:0] slave_wlast; + wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_wuser; + wire [N_SLAVE_PORT - 1:0] slave_wvalid; + wire [N_SLAVE_PORT - 1:0] slave_wready; + wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_bid; + wire [(N_SLAVE_PORT * 2) - 1:0] slave_bresp; + wire [N_SLAVE_PORT - 1:0] slave_bvalid; + wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_buser; + wire [N_SLAVE_PORT - 1:0] slave_bready; + wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_arid; + wire [(N_SLAVE_PORT * AXI_ADDRESS_W) - 1:0] slave_araddr; + wire [(N_SLAVE_PORT * 8) - 1:0] slave_arlen; + wire [(N_SLAVE_PORT * 3) - 1:0] slave_arsize; + wire [(N_SLAVE_PORT * 2) - 1:0] slave_arburst; + wire [N_SLAVE_PORT - 1:0] slave_arlock; + wire [(N_SLAVE_PORT * 4) - 1:0] slave_arcache; + wire [(N_SLAVE_PORT * 3) - 1:0] slave_arprot; + wire [(N_SLAVE_PORT * 4) - 1:0] slave_arregion; + wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_aruser; + wire [(N_SLAVE_PORT * 4) - 1:0] slave_arqos; + wire [N_SLAVE_PORT - 1:0] slave_arvalid; + wire [N_SLAVE_PORT - 1:0] slave_arready; + wire [(N_SLAVE_PORT * AXI_ID_IN) - 1:0] slave_rid; + wire [(N_SLAVE_PORT * AXI_DATA_W) - 1:0] slave_rdata; + wire [(N_SLAVE_PORT * 2) - 1:0] slave_rresp; + wire [N_SLAVE_PORT - 1:0] slave_rlast; + wire [(N_SLAVE_PORT * AXI_USER_W) - 1:0] slave_ruser; + wire [N_SLAVE_PORT - 1:0] slave_rvalid; + wire [N_SLAVE_PORT - 1:0] slave_rready; + wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_awid; + wire [(N_MASTER_PORT * AXI_ADDRESS_W) - 1:0] master_awaddr; + wire [(N_MASTER_PORT * 8) - 1:0] master_awlen; + wire [(N_MASTER_PORT * 3) - 1:0] master_awsize; + wire [(N_MASTER_PORT * 2) - 1:0] master_awburst; + wire [N_MASTER_PORT - 1:0] master_awlock; + wire [(N_MASTER_PORT * 4) - 1:0] master_awcache; + wire [(N_MASTER_PORT * 3) - 1:0] master_awprot; + wire [(N_MASTER_PORT * 4) - 1:0] master_awregion; + wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_awuser; + wire [(N_MASTER_PORT * 4) - 1:0] master_awqos; + wire [N_MASTER_PORT - 1:0] master_awvalid; + wire [N_MASTER_PORT - 1:0] master_awready; + wire [(N_MASTER_PORT * AXI_DATA_W) - 1:0] master_wdata; + wire [(N_MASTER_PORT * AXI_NUMBYTES) - 1:0] master_wstrb; + wire [N_MASTER_PORT - 1:0] master_wlast; + wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_wuser; + wire [N_MASTER_PORT - 1:0] master_wvalid; + wire [N_MASTER_PORT - 1:0] master_wready; + wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_bid; + wire [(N_MASTER_PORT * 2) - 1:0] master_bresp; + wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_buser; + wire [N_MASTER_PORT - 1:0] master_bvalid; + wire [N_MASTER_PORT - 1:0] master_bready; + wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_arid; + wire [(N_MASTER_PORT * AXI_ADDRESS_W) - 1:0] master_araddr; + wire [(N_MASTER_PORT * 8) - 1:0] master_arlen; + wire [(N_MASTER_PORT * 3) - 1:0] master_arsize; + wire [(N_MASTER_PORT * 2) - 1:0] master_arburst; + wire [N_MASTER_PORT - 1:0] master_arlock; + wire [(N_MASTER_PORT * 4) - 1:0] master_arcache; + wire [(N_MASTER_PORT * 3) - 1:0] master_arprot; + wire [(N_MASTER_PORT * 4) - 1:0] master_arregion; + wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_aruser; + wire [(N_MASTER_PORT * 4) - 1:0] master_arqos; + wire [N_MASTER_PORT - 1:0] master_arvalid; + wire [N_MASTER_PORT - 1:0] master_arready; + wire [(N_MASTER_PORT * AXI_ID_OUT) - 1:0] master_rid; + wire [(N_MASTER_PORT * AXI_DATA_W) - 1:0] master_rdata; + wire [(N_MASTER_PORT * 2) - 1:0] master_rresp; + wire [N_MASTER_PORT - 1:0] master_rlast; + wire [(N_MASTER_PORT * AXI_USER_W) - 1:0] master_ruser; + wire [N_MASTER_PORT - 1:0] master_rvalid; + wire [N_MASTER_PORT - 1:0] master_rready; + genvar i; + assign slave_awaddr[0+:AXI_ADDRESS_W] = slave_00_aw_addr; + assign slave_awprot[0+:3] = slave_00_aw_prot; + assign slave_awregion[0+:4] = slave_00_aw_region; + assign slave_awlen[0+:8] = slave_00_aw_len; + assign slave_awsize[0+:3] = slave_00_aw_size; + assign slave_awburst[0+:2] = slave_00_aw_burst; + assign slave_awlock[0] = slave_00_aw_lock; + assign slave_awcache[0+:4] = slave_00_aw_cache; + assign slave_awqos[0+:4] = slave_00_aw_qos; + assign slave_awid[0+:AXI_ID_IN] = slave_00_aw_id[AXI_ID_IN - 1:0]; + assign slave_awuser[0+:AXI_USER_W] = slave_00_aw_user; + assign slave_awvalid[0] = slave_00_aw_valid; + assign slave_00_aw_ready = slave_awready[0]; + assign slave_araddr[0+:AXI_ADDRESS_W] = slave_00_ar_addr; + assign slave_arprot[0+:3] = slave_00_ar_prot; + assign slave_arregion[0+:4] = slave_00_ar_region; + assign slave_arlen[0+:8] = slave_00_ar_len; + assign slave_arsize[0+:3] = slave_00_ar_size; + assign slave_arburst[0+:2] = slave_00_ar_burst; + assign slave_arlock[0] = slave_00_ar_lock; + assign slave_arcache[0+:4] = slave_00_ar_cache; + assign slave_arqos[0+:4] = slave_00_ar_qos; + assign slave_arid[0+:AXI_ID_IN] = slave_00_ar_id[AXI_ID_IN - 1:0]; + assign slave_aruser[0+:AXI_USER_W] = slave_00_ar_user; + assign slave_arvalid[0] = slave_00_ar_valid; + assign slave_00_ar_ready = slave_arready[0]; + assign slave_wvalid[0] = slave_00_w_valid; + assign slave_wdata[0+:AXI_DATA_W] = slave_00_w_data; + assign slave_wstrb[0+:AXI_NUMBYTES] = slave_00_w_strb; + assign slave_wuser[0+:AXI_USER_W] = slave_00_w_user; + assign slave_wlast[0] = slave_00_w_last; + assign slave_00_w_ready = slave_wready[0]; + assign slave_00_b_id[AXI_ID_IN - 1:0] = slave_bid[0+:AXI_ID_IN]; + assign slave_00_b_resp = slave_bresp[0+:2]; + assign slave_00_b_valid = slave_bvalid[0]; + assign slave_00_b_user = slave_buser[0+:AXI_USER_W]; + assign slave_bready[0] = slave_00_b_ready; + assign slave_00_r_data = slave_rdata[0+:AXI_DATA_W]; + assign slave_00_r_resp = slave_rresp[0+:2]; + assign slave_00_r_last = slave_rlast[0]; + assign slave_00_r_id[AXI_ID_IN - 1:0] = slave_rid[0+:AXI_ID_IN]; + assign slave_00_r_user = slave_ruser[0+:AXI_USER_W]; + assign slave_00_r_valid = slave_rvalid[0]; + assign slave_rready[0] = slave_00_r_ready; + assign slave_awaddr[AXI_ADDRESS_W+:AXI_ADDRESS_W] = slave_01_aw_addr; + assign slave_awprot[3+:3] = slave_01_aw_prot; + assign slave_awregion[4+:4] = slave_01_aw_region; + assign slave_awlen[8+:8] = slave_01_aw_len; + assign slave_awsize[3+:3] = slave_01_aw_size; + assign slave_awburst[2+:2] = slave_01_aw_burst; + assign slave_awlock[1] = slave_01_aw_lock; + assign slave_awcache[4+:4] = slave_01_aw_cache; + assign slave_awqos[4+:4] = slave_01_aw_qos; + assign slave_awid[AXI_ID_IN+:AXI_ID_IN] = slave_01_aw_id[AXI_ID_IN - 1:0]; + assign slave_awuser[AXI_USER_W+:AXI_USER_W] = slave_01_aw_user; + assign slave_awvalid[1] = slave_01_aw_valid; + assign slave_01_aw_ready = slave_awready[1]; + assign slave_araddr[AXI_ADDRESS_W+:AXI_ADDRESS_W] = slave_01_ar_addr; + assign slave_arprot[3+:3] = slave_01_ar_prot; + assign slave_arregion[4+:4] = slave_01_ar_region; + assign slave_arlen[8+:8] = slave_01_ar_len; + assign slave_arsize[3+:3] = slave_01_ar_size; + assign slave_arburst[2+:2] = slave_01_ar_burst; + assign slave_arlock[1] = slave_01_ar_lock; + assign slave_arcache[4+:4] = slave_01_ar_cache; + assign slave_arqos[4+:4] = slave_01_ar_qos; + assign slave_arid[AXI_ID_IN+:AXI_ID_IN] = slave_01_ar_id[AXI_ID_IN - 1:0]; + assign slave_aruser[AXI_USER_W+:AXI_USER_W] = slave_01_ar_user; + assign slave_arvalid[1] = slave_01_ar_valid; + assign slave_01_ar_ready = slave_arready[1]; + assign slave_wvalid[1] = slave_01_w_valid; + assign slave_wdata[AXI_DATA_W+:AXI_DATA_W] = slave_01_w_data; + assign slave_wstrb[AXI_NUMBYTES+:AXI_NUMBYTES] = slave_01_w_strb; + assign slave_wuser[AXI_USER_W+:AXI_USER_W] = slave_01_w_user; + assign slave_wlast[1] = slave_01_w_last; + assign slave_01_w_ready = slave_wready[1]; + assign slave_01_b_id[AXI_ID_IN - 1:0] = slave_bid[AXI_ID_IN+:AXI_ID_IN]; + assign slave_01_b_resp = slave_bresp[2+:2]; + assign slave_01_b_valid = slave_bvalid[1]; + assign slave_01_b_user = slave_buser[AXI_USER_W+:AXI_USER_W]; + assign slave_bready[1] = slave_01_b_ready; + assign slave_01_r_data = slave_rdata[AXI_DATA_W+:AXI_DATA_W]; + assign slave_01_r_resp = slave_rresp[2+:2]; + assign slave_01_r_last = slave_rlast[1]; + assign slave_01_r_id[AXI_ID_IN - 1:0] = slave_rid[AXI_ID_IN+:AXI_ID_IN]; + assign slave_01_r_user = slave_ruser[AXI_USER_W+:AXI_USER_W]; + assign slave_01_r_valid = slave_rvalid[1]; + assign slave_rready[1] = slave_01_r_ready; + assign slave_awaddr[2 * AXI_ADDRESS_W+:AXI_ADDRESS_W] = slave_02_aw_addr; + assign slave_awprot[6+:3] = slave_02_aw_prot; + assign slave_awregion[8+:4] = slave_02_aw_region; + assign slave_awlen[16+:8] = slave_02_aw_len; + assign slave_awsize[6+:3] = slave_02_aw_size; + assign slave_awburst[4+:2] = slave_02_aw_burst; + assign slave_awlock[2] = slave_02_aw_lock; + assign slave_awcache[8+:4] = slave_02_aw_cache; + assign slave_awqos[8+:4] = slave_02_aw_qos; + assign slave_awid[2 * AXI_ID_IN+:AXI_ID_IN] = slave_02_aw_id[AXI_ID_IN - 1:0]; + assign slave_awuser[2 * AXI_USER_W+:AXI_USER_W] = slave_02_aw_user; + assign slave_awvalid[2] = slave_02_aw_valid; + assign slave_02_aw_ready = slave_awready[2]; + assign slave_araddr[2 * AXI_ADDRESS_W+:AXI_ADDRESS_W] = slave_02_ar_addr; + assign slave_arprot[6+:3] = slave_02_ar_prot; + assign slave_arregion[8+:4] = slave_02_ar_region; + assign slave_arlen[16+:8] = slave_02_ar_len; + assign slave_arsize[6+:3] = slave_02_ar_size; + assign slave_arburst[4+:2] = slave_02_ar_burst; + assign slave_arlock[2] = slave_02_ar_lock; + assign slave_arcache[8+:4] = slave_02_ar_cache; + assign slave_arqos[8+:4] = slave_02_ar_qos; + assign slave_arid[2 * AXI_ID_IN+:AXI_ID_IN] = slave_02_ar_id[AXI_ID_IN - 1:0]; + assign slave_aruser[2 * AXI_USER_W+:AXI_USER_W] = slave_02_ar_user; + assign slave_arvalid[2] = slave_02_ar_valid; + assign slave_02_ar_ready = slave_arready[2]; + assign slave_wvalid[2] = slave_02_w_valid; + assign slave_wdata[2 * AXI_DATA_W+:AXI_DATA_W] = slave_02_w_data; + assign slave_wstrb[2 * AXI_NUMBYTES+:AXI_NUMBYTES] = slave_02_w_strb; + assign slave_wuser[2 * AXI_USER_W+:AXI_USER_W] = slave_02_w_user; + assign slave_wlast[2] = slave_02_w_last; + assign slave_02_w_ready = slave_wready[2]; + assign slave_02_b_id[AXI_ID_IN - 1:0] = slave_bid[2 * AXI_ID_IN+:AXI_ID_IN]; + assign slave_02_b_resp = slave_bresp[4+:2]; + assign slave_02_b_valid = slave_bvalid[2]; + assign slave_02_b_user = slave_buser[2 * AXI_USER_W+:AXI_USER_W]; + assign slave_bready[2] = slave_02_b_ready; + assign slave_02_r_data = slave_rdata[2 * AXI_DATA_W+:AXI_DATA_W]; + assign slave_02_r_resp = slave_rresp[4+:2]; + assign slave_02_r_last = slave_rlast[2]; + assign slave_02_r_id[AXI_ID_IN - 1:0] = slave_rid[2 * AXI_ID_IN+:AXI_ID_IN]; + assign slave_02_r_user = slave_ruser[2 * AXI_USER_W+:AXI_USER_W]; + assign slave_02_r_valid = slave_rvalid[2]; + assign slave_rready[2] = slave_02_r_ready; + assign master_00_aw_addr = master_awaddr[0+:AXI_ADDRESS_W]; + assign master_00_aw_prot = master_awprot[0+:3]; + assign master_00_aw_region = master_awregion[0+:4]; + assign master_00_aw_len = master_awlen[0+:8]; + assign master_00_aw_size = master_awsize[0+:3]; + assign master_00_aw_burst = master_awburst[0+:2]; + assign master_00_aw_lock = master_awlock[0]; + assign master_00_aw_cache = master_awcache[0+:4]; + assign master_00_aw_qos = master_awqos[0+:4]; + assign master_00_aw_id[AXI_ID_OUT - 1:0] = master_awid[0+:AXI_ID_OUT]; + assign master_00_aw_user = master_awuser[0+:AXI_USER_W]; + assign master_00_aw_valid = master_awvalid[0]; + assign master_awready[0] = master_00_aw_ready; + assign master_00_ar_addr = master_araddr[0+:AXI_ADDRESS_W]; + assign master_00_ar_prot = master_arprot[0+:3]; + assign master_00_ar_region = master_arregion[0+:4]; + assign master_00_ar_len = master_arlen[0+:8]; + assign master_00_ar_size = master_arsize[0+:3]; + assign master_00_ar_burst = master_arburst[0+:2]; + assign master_00_ar_lock = master_arlock[0]; + assign master_00_ar_cache = master_arcache[0+:4]; + assign master_00_ar_qos = master_arqos[0+:4]; + assign master_00_ar_id[AXI_ID_OUT - 1:0] = master_arid[0+:AXI_ID_OUT]; + assign master_00_ar_user = master_aruser[0+:AXI_USER_W]; + assign master_00_ar_valid = master_arvalid[0]; + assign master_arready[0] = master_00_ar_ready; + assign master_00_w_valid = master_wvalid[0]; + assign master_00_w_data = master_wdata[0+:AXI_DATA_W]; + assign master_00_w_strb = master_wstrb[0+:AXI_NUMBYTES]; + assign master_00_w_user = master_wuser[0+:AXI_USER_W]; + assign master_00_w_last = master_wlast[0]; + assign master_wready[0] = master_00_w_ready; + assign master_bid[0+:AXI_ID_OUT] = master_00_b_id[AXI_ID_OUT - 1:0]; + assign master_bresp[0+:2] = master_00_b_resp; + assign master_bvalid[0] = master_00_b_valid; + assign master_buser[0+:AXI_USER_W] = master_00_b_user; + assign master_00_b_ready = master_bready[0]; + assign master_rdata[0+:AXI_DATA_W] = master_00_r_data; + assign master_rresp[0+:2] = master_00_r_resp; + assign master_rlast[0] = master_00_r_last; + assign master_rid[0+:AXI_ID_OUT] = master_00_r_id[AXI_ID_OUT - 1:0]; + assign master_ruser[0+:AXI_USER_W] = master_00_r_user; + assign master_rvalid[0] = master_00_r_valid; + assign master_00_r_ready = master_rready[0]; + assign master_01_aw_addr = master_awaddr[AXI_ADDRESS_W+:AXI_ADDRESS_W]; + assign master_01_aw_prot = master_awprot[3+:3]; + assign master_01_aw_region = master_awregion[4+:4]; + assign master_01_aw_len = master_awlen[8+:8]; + assign master_01_aw_size = master_awsize[3+:3]; + assign master_01_aw_burst = master_awburst[2+:2]; + assign master_01_aw_lock = master_awlock[1]; + assign master_01_aw_cache = master_awcache[4+:4]; + assign master_01_aw_qos = master_awqos[4+:4]; + assign master_01_aw_id[AXI_ID_OUT - 1:0] = master_awid[AXI_ID_OUT+:AXI_ID_OUT]; + assign master_01_aw_user = master_awuser[AXI_USER_W+:AXI_USER_W]; + assign master_01_aw_valid = master_awvalid[1]; + assign master_awready[1] = master_01_aw_ready; + assign master_01_ar_addr = master_araddr[AXI_ADDRESS_W+:AXI_ADDRESS_W]; + assign master_01_ar_prot = master_arprot[3+:3]; + assign master_01_ar_region = master_arregion[4+:4]; + assign master_01_ar_len = master_arlen[8+:8]; + assign master_01_ar_size = master_arsize[3+:3]; + assign master_01_ar_burst = master_arburst[2+:2]; + assign master_01_ar_lock = master_arlock[1]; + assign master_01_ar_cache = master_arcache[4+:4]; + assign master_01_ar_qos = master_arqos[4+:4]; + assign master_01_ar_id[AXI_ID_OUT - 1:0] = master_arid[AXI_ID_OUT+:AXI_ID_OUT]; + assign master_01_ar_user = master_aruser[AXI_USER_W+:AXI_USER_W]; + assign master_01_ar_valid = master_arvalid[1]; + assign master_arready[1] = master_01_ar_ready; + assign master_01_w_valid = master_wvalid[1]; + assign master_01_w_data = master_wdata[AXI_DATA_W+:AXI_DATA_W]; + assign master_01_w_strb = master_wstrb[AXI_NUMBYTES+:AXI_NUMBYTES]; + assign master_01_w_user = master_wuser[AXI_USER_W+:AXI_USER_W]; + assign master_01_w_last = master_wlast[1]; + assign master_wready[1] = master_01_w_ready; + assign master_bid[AXI_ID_OUT+:AXI_ID_OUT] = master_01_b_id[AXI_ID_OUT - 1:0]; + assign master_bresp[2+:2] = master_01_b_resp; + assign master_bvalid[1] = master_01_b_valid; + assign master_buser[AXI_USER_W+:AXI_USER_W] = master_01_b_user; + assign master_01_b_ready = master_bready[1]; + assign master_rdata[AXI_DATA_W+:AXI_DATA_W] = master_01_r_data; + assign master_rresp[2+:2] = master_01_r_resp; + assign master_rlast[1] = master_01_r_last; + assign master_rid[AXI_ID_OUT+:AXI_ID_OUT] = master_01_r_id[AXI_ID_OUT - 1:0]; + assign master_ruser[AXI_USER_W+:AXI_USER_W] = master_01_r_user; + assign master_rvalid[1] = master_01_r_valid; + assign master_01_r_ready = master_rready[1]; + assign master_02_aw_addr = master_awaddr[2 * AXI_ADDRESS_W+:AXI_ADDRESS_W]; + assign master_02_aw_prot = master_awprot[6+:3]; + assign master_02_aw_region = master_awregion[8+:4]; + assign master_02_aw_len = master_awlen[16+:8]; + assign master_02_aw_size = master_awsize[6+:3]; + assign master_02_aw_burst = master_awburst[4+:2]; + assign master_02_aw_lock = master_awlock[2]; + assign master_02_aw_cache = master_awcache[8+:4]; + assign master_02_aw_qos = master_awqos[8+:4]; + assign master_02_aw_id[AXI_ID_OUT - 1:0] = master_awid[2 * AXI_ID_OUT+:AXI_ID_OUT]; + assign master_02_aw_user = master_awuser[2 * AXI_USER_W+:AXI_USER_W]; + assign master_02_aw_valid = master_awvalid[2]; + assign master_awready[2] = master_02_aw_ready; + assign master_02_ar_addr = master_araddr[2 * AXI_ADDRESS_W+:AXI_ADDRESS_W]; + assign master_02_ar_prot = master_arprot[6+:3]; + assign master_02_ar_region = master_arregion[8+:4]; + assign master_02_ar_len = master_arlen[16+:8]; + assign master_02_ar_size = master_arsize[6+:3]; + assign master_02_ar_burst = master_arburst[4+:2]; + assign master_02_ar_lock = master_arlock[2]; + assign master_02_ar_cache = master_arcache[8+:4]; + assign master_02_ar_qos = master_arqos[8+:4]; + assign master_02_ar_id[AXI_ID_OUT - 1:0] = master_arid[2 * AXI_ID_OUT+:AXI_ID_OUT]; + assign master_02_ar_user = master_aruser[2 * AXI_USER_W+:AXI_USER_W]; + assign master_02_ar_valid = master_arvalid[2]; + assign master_arready[2] = master_02_ar_ready; + assign master_02_w_valid = master_wvalid[2]; + assign master_02_w_data = master_wdata[2 * AXI_DATA_W+:AXI_DATA_W]; + assign master_02_w_strb = master_wstrb[2 * AXI_NUMBYTES+:AXI_NUMBYTES]; + assign master_02_w_user = master_wuser[2 * AXI_USER_W+:AXI_USER_W]; + assign master_02_w_last = master_wlast[2]; + assign master_wready[2] = master_02_w_ready; + assign master_bid[2 * AXI_ID_OUT+:AXI_ID_OUT] = master_02_b_id[AXI_ID_OUT - 1:0]; + assign master_bresp[4+:2] = master_02_b_resp; + assign master_bvalid[2] = master_02_b_valid; + assign master_buser[2 * AXI_USER_W+:AXI_USER_W] = master_02_b_user; + assign master_02_b_ready = master_bready[2]; + assign master_rdata[2 * AXI_DATA_W+:AXI_DATA_W] = master_02_r_data; + assign master_rresp[4+:2] = master_02_r_resp; + assign master_rlast[2] = master_02_r_last; + assign master_rid[2 * AXI_ID_OUT+:AXI_ID_OUT] = master_02_r_id[AXI_ID_OUT - 1:0]; + assign master_ruser[2 * AXI_USER_W+:AXI_USER_W] = master_02_r_user; + assign master_rvalid[2] = master_02_r_valid; + assign master_02_r_ready = master_rready[2]; + axi_node #( + .AXI_ADDRESS_W(AXI_ADDRESS_W), + .AXI_DATA_W(AXI_DATA_W), + .AXI_ID_IN(AXI_ID_IN), + .AXI_USER_W(AXI_USER_W), + .N_MASTER_PORT(N_MASTER_PORT), + .N_SLAVE_PORT(N_SLAVE_PORT), + .N_REGION(N_REGION) + ) AXI4_NODE( + .clk(clk), + .rst_n(rst_n), + .test_en_i(test_en_i), + .slave_awid_i(slave_awid), + .slave_awaddr_i(slave_awaddr), + .slave_awlen_i(slave_awlen), + .slave_awsize_i(slave_awsize), + .slave_awburst_i(slave_awburst), + .slave_awlock_i(slave_awlock), + .slave_awcache_i(slave_awcache), + .slave_awprot_i(slave_awprot), + .slave_awregion_i(slave_awregion), + .slave_awqos_i(slave_awqos), + .slave_awuser_i(slave_awuser), + .slave_awvalid_i(slave_awvalid), + .slave_awready_o(slave_awready), + .slave_wdata_i(slave_wdata), + .slave_wstrb_i(slave_wstrb), + .slave_wlast_i(slave_wlast), + .slave_wuser_i(slave_wuser), + .slave_wvalid_i(slave_wvalid), + .slave_wready_o(slave_wready), + .slave_bid_o(slave_bid), + .slave_bresp_o(slave_bresp), + .slave_buser_o(slave_buser), + .slave_bvalid_o(slave_bvalid), + .slave_bready_i(slave_bready), + .slave_arid_i(slave_arid), + .slave_araddr_i(slave_araddr), + .slave_arlen_i(slave_arlen), + .slave_arsize_i(slave_arsize), + .slave_arburst_i(slave_arburst), + .slave_arlock_i(slave_arlock), + .slave_arcache_i(slave_arcache), + .slave_arprot_i(slave_arprot), + .slave_arregion_i(slave_arregion), + .slave_aruser_i(slave_aruser), + .slave_arqos_i(slave_arqos), + .slave_arvalid_i(slave_arvalid), + .slave_arready_o(slave_arready), + .slave_rid_o(slave_rid), + .slave_rdata_o(slave_rdata), + .slave_rresp_o(slave_rresp), + .slave_rlast_o(slave_rlast), + .slave_ruser_o(slave_ruser), + .slave_rvalid_o(slave_rvalid), + .slave_rready_i(slave_rready), + .master_awid_o(master_awid), + .master_awaddr_o(master_awaddr), + .master_awlen_o(master_awlen), + .master_awsize_o(master_awsize), + .master_awburst_o(master_awburst), + .master_awlock_o(master_awlock), + .master_awcache_o(master_awcache), + .master_awprot_o(master_awprot), + .master_awregion_o(master_awregion), + .master_awuser_o(master_awuser), + .master_awqos_o(master_awqos), + .master_awvalid_o(master_awvalid), + .master_awready_i(master_awready), + .master_wdata_o(master_wdata), + .master_wstrb_o(master_wstrb), + .master_wlast_o(master_wlast), + .master_wuser_o(master_wuser), + .master_wvalid_o(master_wvalid), + .master_wready_i(master_wready), + .master_bid_i(master_bid), + .master_bresp_i(master_bresp), + .master_buser_i(master_buser), + .master_bvalid_i(master_bvalid), + .master_bready_o(master_bready), + .master_arid_o(master_arid), + .master_araddr_o(master_araddr), + .master_arlen_o(master_arlen), + .master_arsize_o(master_arsize), + .master_arburst_o(master_arburst), + .master_arlock_o(master_arlock), + .master_arcache_o(master_arcache), + .master_arprot_o(master_arprot), + .master_arregion_o(master_arregion), + .master_aruser_o(master_aruser), + .master_arqos_o(master_arqos), + .master_arvalid_o(master_arvalid), + .master_arready_i(master_arready), + .master_rid_i(master_rid), + .master_rdata_i(master_rdata), + .master_rresp_i(master_rresp), + .master_rlast_i(master_rlast), + .master_ruser_i(master_ruser), + .master_rvalid_i(master_rvalid), + .master_rready_o(master_rready), + .cfg_START_ADDR_i(cfg_START_ADDR_i), + .cfg_END_ADDR_i(cfg_END_ADDR_i), + .cfg_valid_rule_i(cfg_valid_rule_i), + .cfg_connectivity_map_i(cfg_connectivity_map_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_node_wrap_with_slices.v b/verilog/rtl/ips/axi/axi_node/axi_node_wrap_with_slices.v new file mode 100644 index 0000000..0fdfd4f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_node_wrap_with_slices.v
@@ -0,0 +1,1434 @@ +module axi_node_wrap_with_slices +#( + + parameter AXI_ADDRESS_W = 32, + parameter AXI_DATA_W = 64, + parameter AXI_NUMBYTES = AXI_DATA_W/8, + parameter AXI_USER_W = 6, +`ifdef USE_CFG_BLOCK + `ifdef USE_AXI_LITE + parameter AXI_LITE_ADDRESS_W = 32, + parameter AXI_LITE_DATA_W = 32, + parameter AXI_LITE_BE_W = AXI_LITE_DATA_W/8, + `else + parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default + parameter APB_DATA_WIDTH = 32, + `endif +`endif + parameter N_MASTER_PORT = 3, // 3 in pulpino + parameter N_SLAVE_PORT = 3, // 3 in pulpino + parameter AXI_ID_IN = 4, + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_SLAVE_PORT), + parameter FIFO_DEPTH_DW = 4, + parameter N_REGION = 4, + parameter MASTER_SLICE_DEPTH = 2, + parameter SLAVE_SLICE_DEPTH = 2 +) +( + clk, + rst_n, + test_en_i, + slave_00_aw_addr, + slave_00_aw_prot, + slave_00_aw_region, + slave_00_aw_len, + slave_00_aw_size, + slave_00_aw_burst, + slave_00_aw_lock, + slave_00_aw_cache, + slave_00_aw_qos, + slave_00_aw_id, + slave_00_aw_user, + slave_00_aw_ready, + slave_00_aw_valid, + slave_00_ar_addr, + slave_00_ar_prot, + slave_00_ar_region, + slave_00_ar_len, + slave_00_ar_size, + slave_00_ar_burst, + slave_00_ar_lock, + slave_00_ar_cache, + slave_00_ar_qos, + slave_00_ar_id, + slave_00_ar_user, + slave_00_ar_ready, + slave_00_ar_valid, + slave_00_w_valid, + slave_00_w_data, + slave_00_w_strb, + slave_00_w_user, + slave_00_w_last, + slave_00_w_ready, + slave_00_r_data, + slave_00_r_resp, + slave_00_r_last, + slave_00_r_id, + slave_00_r_user, + slave_00_r_ready, + slave_00_r_valid, + slave_00_b_resp, + slave_00_b_id, + slave_00_b_user, + slave_00_b_ready, + slave_00_b_valid, + slave_01_aw_addr, + slave_01_aw_prot, + slave_01_aw_region, + slave_01_aw_len, + slave_01_aw_size, + slave_01_aw_burst, + slave_01_aw_lock, + slave_01_aw_cache, + slave_01_aw_qos, + slave_01_aw_id, + slave_01_aw_user, + slave_01_aw_ready, + slave_01_aw_valid, + slave_01_ar_addr, + slave_01_ar_prot, + slave_01_ar_region, + slave_01_ar_len, + slave_01_ar_size, + slave_01_ar_burst, + slave_01_ar_lock, + slave_01_ar_cache, + slave_01_ar_qos, + slave_01_ar_id, + slave_01_ar_user, + slave_01_ar_ready, + slave_01_ar_valid, + slave_01_w_valid, + slave_01_w_data, + slave_01_w_strb, + slave_01_w_user, + slave_01_w_last, + slave_01_w_ready, + slave_01_r_data, + slave_01_r_resp, + slave_01_r_last, + slave_01_r_id, + slave_01_r_user, + slave_01_r_ready, + slave_01_r_valid, + slave_01_b_resp, + slave_01_b_id, + slave_01_b_user, + slave_01_b_ready, + slave_01_b_valid, + slave_02_aw_addr, + slave_02_aw_prot, + slave_02_aw_region, + slave_02_aw_len, + slave_02_aw_size, + slave_02_aw_burst, + slave_02_aw_lock, + slave_02_aw_cache, + slave_02_aw_qos, + slave_02_aw_id, + slave_02_aw_user, + slave_02_aw_ready, + slave_02_aw_valid, + slave_02_ar_addr, + slave_02_ar_prot, + slave_02_ar_region, + slave_02_ar_len, + slave_02_ar_size, + slave_02_ar_burst, + slave_02_ar_lock, + slave_02_ar_cache, + slave_02_ar_qos, + slave_02_ar_id, + slave_02_ar_user, + slave_02_ar_ready, + slave_02_ar_valid, + slave_02_w_valid, + slave_02_w_data, + slave_02_w_strb, + slave_02_w_user, + slave_02_w_last, + slave_02_w_ready, + slave_02_r_data, + slave_02_r_resp, + slave_02_r_last, + slave_02_r_id, + slave_02_r_user, + slave_02_r_ready, + slave_02_r_valid, + slave_02_b_resp, + slave_02_b_id, + slave_02_b_user, + slave_02_b_ready, + slave_02_b_valid, + master_00_aw_addr, + master_00_aw_prot, + master_00_aw_region, + master_00_aw_len, + master_00_aw_size, + master_00_aw_burst, + master_00_aw_lock, + master_00_aw_cache, + master_00_aw_qos, + master_00_aw_id, + master_00_aw_user, + master_00_aw_ready, + master_00_aw_valid, + master_00_ar_addr, + master_00_ar_prot, + master_00_ar_region, + master_00_ar_len, + master_00_ar_size, + master_00_ar_burst, + master_00_ar_lock, + master_00_ar_cache, + master_00_ar_qos, + master_00_ar_id, + master_00_ar_user, + master_00_ar_ready, + master_00_ar_valid, + master_00_w_valid, + master_00_w_data, + master_00_w_strb, + master_00_w_user, + master_00_w_last, + master_00_w_ready, + master_00_r_data, + master_00_r_resp, + master_00_r_last, + master_00_r_id, + master_00_r_user, + master_00_r_ready, + master_00_r_valid, + master_00_b_resp, + master_00_b_id, + master_00_b_user, + master_00_b_ready, + master_00_b_valid, + master_01_aw_addr, + master_01_aw_prot, + master_01_aw_region, + master_01_aw_len, + master_01_aw_size, + master_01_aw_burst, + master_01_aw_lock, + master_01_aw_cache, + master_01_aw_qos, + master_01_aw_id, + master_01_aw_user, + master_01_aw_ready, + master_01_aw_valid, + master_01_ar_addr, + master_01_ar_prot, + master_01_ar_region, + master_01_ar_len, + master_01_ar_size, + master_01_ar_burst, + master_01_ar_lock, + master_01_ar_cache, + master_01_ar_qos, + master_01_ar_id, + master_01_ar_user, + master_01_ar_ready, + master_01_ar_valid, + master_01_w_valid, + master_01_w_data, + master_01_w_strb, + master_01_w_user, + master_01_w_last, + master_01_w_ready, + master_01_r_data, + master_01_r_resp, + master_01_r_last, + master_01_r_id, + master_01_r_user, + master_01_r_ready, + master_01_r_valid, + master_01_b_resp, + master_01_b_id, + master_01_b_user, + master_01_b_ready, + master_01_b_valid, + master_02_aw_addr, + master_02_aw_prot, + master_02_aw_region, + master_02_aw_len, + master_02_aw_size, + master_02_aw_burst, + master_02_aw_lock, + master_02_aw_cache, + master_02_aw_qos, + master_02_aw_id, + master_02_aw_user, + master_02_aw_ready, + master_02_aw_valid, + master_02_ar_addr, + master_02_ar_prot, + master_02_ar_region, + master_02_ar_len, + master_02_ar_size, + master_02_ar_burst, + master_02_ar_lock, + master_02_ar_cache, + master_02_ar_qos, + master_02_ar_id, + master_02_ar_user, + master_02_ar_ready, + master_02_ar_valid, + master_02_w_valid, + master_02_w_data, + master_02_w_strb, + master_02_w_user, + master_02_w_last, + master_02_w_ready, + master_02_r_data, + master_02_r_resp, + master_02_r_last, + master_02_r_id, + master_02_r_user, + master_02_r_ready, + master_02_r_valid, + master_02_b_resp, + master_02_b_id, + master_02_b_user, + master_02_b_ready, + master_02_b_valid, + cfg_START_ADDR_i, + cfg_END_ADDR_i, + cfg_valid_rule_i, + cfg_connectivity_map_i +); + //parameter AXI_ADDRESS_W = 32; + //parameter AXI_DATA_W = 64; + //parameter AXI_NUMBYTES = AXI_DATA_W / 8; + //parameter AXI_USER_W = 6; + //parameter N_MASTER_PORT = 3; + //parameter N_SLAVE_PORT = 3; + //parameter AXI_ID_IN = 4; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_SLAVE_PORT); + //parameter FIFO_DEPTH_DW = 4; + //parameter N_REGION = 4; + //parameter MASTER_SLICE_DEPTH = 2; + //parameter SLAVE_SLICE_DEPTH = 2; + parameter AXI_ADDR_WIDTH = AXI_ADDRESS_W; + parameter AXI_DATA_WIDTH = AXI_DATA_W; + parameter AXI_ID_WIDTH = 10; + parameter AXI_USER_WIDTH = 6; + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8; + input wire clk; + input wire rst_n; + input wire test_en_i; + input wire [AXI_ADDR_WIDTH - 1:0] slave_00_aw_addr; + input wire [2:0] slave_00_aw_prot; + input wire [3:0] slave_00_aw_region; + input wire [7:0] slave_00_aw_len; + input wire [2:0] slave_00_aw_size; + input wire [1:0] slave_00_aw_burst; + input wire slave_00_aw_lock; + input wire [3:0] slave_00_aw_cache; + input wire [3:0] slave_00_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_00_aw_id; + input wire [AXI_USER_WIDTH - 1:0] slave_00_aw_user; + output wire slave_00_aw_ready; + input wire slave_00_aw_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_00_ar_addr; + input wire [2:0] slave_00_ar_prot; + input wire [3:0] slave_00_ar_region; + input wire [7:0] slave_00_ar_len; + input wire [2:0] slave_00_ar_size; + input wire [1:0] slave_00_ar_burst; + input wire slave_00_ar_lock; + input wire [3:0] slave_00_ar_cache; + input wire [3:0] slave_00_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_00_ar_id; + input wire [AXI_USER_WIDTH - 1:0] slave_00_ar_user; + output wire slave_00_ar_ready; + input wire slave_00_ar_valid; + input wire slave_00_w_valid; + input wire [AXI_DATA_WIDTH - 1:0] slave_00_w_data; + input wire [AXI_STRB_WIDTH - 1:0] slave_00_w_strb; + input wire [AXI_USER_WIDTH - 1:0] slave_00_w_user; + input wire slave_00_w_last; + output wire slave_00_w_ready; + output wire [AXI_DATA_WIDTH - 1:0] slave_00_r_data; + output wire [1:0] slave_00_r_resp; + output wire slave_00_r_last; + output wire [AXI_ID_WIDTH - 1:0] slave_00_r_id; + output wire [AXI_USER_WIDTH - 1:0] slave_00_r_user; + input wire slave_00_r_ready; + output wire slave_00_r_valid; + output wire [1:0] slave_00_b_resp; + output wire [AXI_ID_WIDTH - 1:0] slave_00_b_id; + output wire [AXI_USER_WIDTH - 1:0] slave_00_b_user; + input wire slave_00_b_ready; + output wire slave_00_b_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_01_aw_addr; + input wire [2:0] slave_01_aw_prot; + input wire [3:0] slave_01_aw_region; + input wire [7:0] slave_01_aw_len; + input wire [2:0] slave_01_aw_size; + input wire [1:0] slave_01_aw_burst; + input wire slave_01_aw_lock; + input wire [3:0] slave_01_aw_cache; + input wire [3:0] slave_01_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_01_aw_id; + input wire [AXI_USER_WIDTH - 1:0] slave_01_aw_user; + output wire slave_01_aw_ready; + input wire slave_01_aw_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_01_ar_addr; + input wire [2:0] slave_01_ar_prot; + input wire [3:0] slave_01_ar_region; + input wire [7:0] slave_01_ar_len; + input wire [2:0] slave_01_ar_size; + input wire [1:0] slave_01_ar_burst; + input wire slave_01_ar_lock; + input wire [3:0] slave_01_ar_cache; + input wire [3:0] slave_01_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_01_ar_id; + input wire [AXI_USER_WIDTH - 1:0] slave_01_ar_user; + output wire slave_01_ar_ready; + input wire slave_01_ar_valid; + input wire slave_01_w_valid; + input wire [AXI_DATA_WIDTH - 1:0] slave_01_w_data; + input wire [AXI_STRB_WIDTH - 1:0] slave_01_w_strb; + input wire [AXI_USER_WIDTH - 1:0] slave_01_w_user; + input wire slave_01_w_last; + output wire slave_01_w_ready; + output wire [AXI_DATA_WIDTH - 1:0] slave_01_r_data; + output wire [1:0] slave_01_r_resp; + output wire slave_01_r_last; + output wire [AXI_ID_WIDTH - 1:0] slave_01_r_id; + output wire [AXI_USER_WIDTH - 1:0] slave_01_r_user; + input wire slave_01_r_ready; + output wire slave_01_r_valid; + output wire [1:0] slave_01_b_resp; + output wire [AXI_ID_WIDTH - 1:0] slave_01_b_id; + output wire [AXI_USER_WIDTH - 1:0] slave_01_b_user; + input wire slave_01_b_ready; + output wire slave_01_b_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_02_aw_addr; + input wire [2:0] slave_02_aw_prot; + input wire [3:0] slave_02_aw_region; + input wire [7:0] slave_02_aw_len; + input wire [2:0] slave_02_aw_size; + input wire [1:0] slave_02_aw_burst; + input wire slave_02_aw_lock; + input wire [3:0] slave_02_aw_cache; + input wire [3:0] slave_02_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_02_aw_id; + input wire [AXI_USER_WIDTH - 1:0] slave_02_aw_user; + output wire slave_02_aw_ready; + input wire slave_02_aw_valid; + input wire [AXI_ADDR_WIDTH - 1:0] slave_02_ar_addr; + input wire [2:0] slave_02_ar_prot; + input wire [3:0] slave_02_ar_region; + input wire [7:0] slave_02_ar_len; + input wire [2:0] slave_02_ar_size; + input wire [1:0] slave_02_ar_burst; + input wire slave_02_ar_lock; + input wire [3:0] slave_02_ar_cache; + input wire [3:0] slave_02_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] slave_02_ar_id; + input wire [AXI_USER_WIDTH - 1:0] slave_02_ar_user; + output wire slave_02_ar_ready; + input wire slave_02_ar_valid; + input wire slave_02_w_valid; + input wire [AXI_DATA_WIDTH - 1:0] slave_02_w_data; + input wire [AXI_STRB_WIDTH - 1:0] slave_02_w_strb; + input wire [AXI_USER_WIDTH - 1:0] slave_02_w_user; + input wire slave_02_w_last; + output wire slave_02_w_ready; + output wire [AXI_DATA_WIDTH - 1:0] slave_02_r_data; + output wire [1:0] slave_02_r_resp; + output wire slave_02_r_last; + output wire [AXI_ID_WIDTH - 1:0] slave_02_r_id; + output wire [AXI_USER_WIDTH - 1:0] slave_02_r_user; + input wire slave_02_r_ready; + output wire slave_02_r_valid; + output wire [1:0] slave_02_b_resp; + output wire [AXI_ID_WIDTH - 1:0] slave_02_b_id; + output wire [AXI_USER_WIDTH - 1:0] slave_02_b_user; + input wire slave_02_b_ready; + output wire slave_02_b_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_00_aw_addr; + output wire [2:0] master_00_aw_prot; + output wire [3:0] master_00_aw_region; + output wire [7:0] master_00_aw_len; + output wire [2:0] master_00_aw_size; + output wire [1:0] master_00_aw_burst; + output wire master_00_aw_lock; + output wire [3:0] master_00_aw_cache; + output wire [3:0] master_00_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] master_00_aw_id; + output wire [AXI_USER_WIDTH - 1:0] master_00_aw_user; + input wire master_00_aw_ready; + output wire master_00_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_00_ar_addr; + output wire [2:0] master_00_ar_prot; + output wire [3:0] master_00_ar_region; + output wire [7:0] master_00_ar_len; + output wire [2:0] master_00_ar_size; + output wire [1:0] master_00_ar_burst; + output wire master_00_ar_lock; + output wire [3:0] master_00_ar_cache; + output wire [3:0] master_00_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] master_00_ar_id; + output wire [AXI_USER_WIDTH - 1:0] master_00_ar_user; + input wire master_00_ar_ready; + output wire master_00_ar_valid; + output wire master_00_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] master_00_w_data; + output wire [AXI_STRB_WIDTH - 1:0] master_00_w_strb; + output wire [AXI_USER_WIDTH - 1:0] master_00_w_user; + output wire master_00_w_last; + input wire master_00_w_ready; + input wire [AXI_DATA_WIDTH - 1:0] master_00_r_data; + input wire [1:0] master_00_r_resp; + input wire master_00_r_last; + input wire [AXI_ID_WIDTH - 1:0] master_00_r_id; + input wire [AXI_USER_WIDTH - 1:0] master_00_r_user; + output wire master_00_r_ready; + input wire master_00_r_valid; + input wire [1:0] master_00_b_resp; + input wire [AXI_ID_WIDTH - 1:0] master_00_b_id; + input wire [AXI_USER_WIDTH - 1:0] master_00_b_user; + output wire master_00_b_ready; + input wire master_00_b_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_01_aw_addr; + output wire [2:0] master_01_aw_prot; + output wire [3:0] master_01_aw_region; + output wire [7:0] master_01_aw_len; + output wire [2:0] master_01_aw_size; + output wire [1:0] master_01_aw_burst; + output wire master_01_aw_lock; + output wire [3:0] master_01_aw_cache; + output wire [3:0] master_01_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] master_01_aw_id; + output wire [AXI_USER_WIDTH - 1:0] master_01_aw_user; + input wire master_01_aw_ready; + output wire master_01_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_01_ar_addr; + output wire [2:0] master_01_ar_prot; + output wire [3:0] master_01_ar_region; + output wire [7:0] master_01_ar_len; + output wire [2:0] master_01_ar_size; + output wire [1:0] master_01_ar_burst; + output wire master_01_ar_lock; + output wire [3:0] master_01_ar_cache; + output wire [3:0] master_01_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] master_01_ar_id; + output wire [AXI_USER_WIDTH - 1:0] master_01_ar_user; + input wire master_01_ar_ready; + output wire master_01_ar_valid; + output wire master_01_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] master_01_w_data; + output wire [AXI_STRB_WIDTH - 1:0] master_01_w_strb; + output wire [AXI_USER_WIDTH - 1:0] master_01_w_user; + output wire master_01_w_last; + input wire master_01_w_ready; + input wire [AXI_DATA_WIDTH - 1:0] master_01_r_data; + input wire [1:0] master_01_r_resp; + input wire master_01_r_last; + input wire [AXI_ID_WIDTH - 1:0] master_01_r_id; + input wire [AXI_USER_WIDTH - 1:0] master_01_r_user; + output wire master_01_r_ready; + input wire master_01_r_valid; + input wire [1:0] master_01_b_resp; + input wire [AXI_ID_WIDTH - 1:0] master_01_b_id; + input wire [AXI_USER_WIDTH - 1:0] master_01_b_user; + output wire master_01_b_ready; + input wire master_01_b_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_02_aw_addr; + output wire [2:0] master_02_aw_prot; + output wire [3:0] master_02_aw_region; + output wire [7:0] master_02_aw_len; + output wire [2:0] master_02_aw_size; + output wire [1:0] master_02_aw_burst; + output wire master_02_aw_lock; + output wire [3:0] master_02_aw_cache; + output wire [3:0] master_02_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] master_02_aw_id; + output wire [AXI_USER_WIDTH - 1:0] master_02_aw_user; + input wire master_02_aw_ready; + output wire master_02_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] master_02_ar_addr; + output wire [2:0] master_02_ar_prot; + output wire [3:0] master_02_ar_region; + output wire [7:0] master_02_ar_len; + output wire [2:0] master_02_ar_size; + output wire [1:0] master_02_ar_burst; + output wire master_02_ar_lock; + output wire [3:0] master_02_ar_cache; + output wire [3:0] master_02_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] master_02_ar_id; + output wire [AXI_USER_WIDTH - 1:0] master_02_ar_user; + input wire master_02_ar_ready; + output wire master_02_ar_valid; + output wire master_02_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] master_02_w_data; + output wire [AXI_STRB_WIDTH - 1:0] master_02_w_strb; + output wire [AXI_USER_WIDTH - 1:0] master_02_w_user; + output wire master_02_w_last; + input wire master_02_w_ready; + input wire [AXI_DATA_WIDTH - 1:0] master_02_r_data; + input wire [1:0] master_02_r_resp; + input wire master_02_r_last; + input wire [AXI_ID_WIDTH - 1:0] master_02_r_id; + input wire [AXI_USER_WIDTH - 1:0] master_02_r_user; + output wire master_02_r_ready; + input wire master_02_r_valid; + input wire [1:0] master_02_b_resp; + input wire [AXI_ID_WIDTH - 1:0] master_02_b_id; + input wire [AXI_USER_WIDTH - 1:0] master_02_b_user; + output wire master_02_b_ready; + input wire master_02_b_valid; + input wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] cfg_START_ADDR_i; + input wire [((N_REGION * N_MASTER_PORT) * 32) - 1:0] cfg_END_ADDR_i; + input wire [(N_REGION * N_MASTER_PORT) - 1:0] cfg_valid_rule_i; + input wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] cfg_connectivity_map_i; + genvar i; + wire [AXI_ADDR_WIDTH - 1:0] axi_slave_00_aw_addr; + wire [2:0] axi_slave_00_aw_prot; + wire [3:0] axi_slave_00_aw_region; + wire [7:0] axi_slave_00_aw_len; + wire [2:0] axi_slave_00_aw_size; + wire [1:0] axi_slave_00_aw_burst; + wire axi_slave_00_aw_lock; + wire [3:0] axi_slave_00_aw_cache; + wire [3:0] axi_slave_00_aw_qos; + wire [AXI_ID_WIDTH - 1:0] axi_slave_00_aw_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_00_aw_user; + wire axi_slave_00_aw_ready; + wire axi_slave_00_aw_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_slave_00_ar_addr; + wire [2:0] axi_slave_00_ar_prot; + wire [3:0] axi_slave_00_ar_region; + wire [7:0] axi_slave_00_ar_len; + wire [2:0] axi_slave_00_ar_size; + wire [1:0] axi_slave_00_ar_burst; + wire axi_slave_00_ar_lock; + wire [3:0] axi_slave_00_ar_cache; + wire [3:0] axi_slave_00_ar_qos; + wire [AXI_ID_WIDTH - 1:0] axi_slave_00_ar_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_00_ar_user; + wire axi_slave_00_ar_ready; + wire axi_slave_00_ar_valid; + wire axi_slave_00_w_valid; + wire [AXI_DATA_WIDTH - 1:0] axi_slave_00_w_data; + wire [AXI_STRB_WIDTH - 1:0] axi_slave_00_w_strb; + wire [AXI_USER_WIDTH - 1:0] axi_slave_00_w_user; + wire axi_slave_00_w_last; + wire axi_slave_00_w_ready; + wire [AXI_DATA_WIDTH - 1:0] axi_slave_00_r_data; + wire [1:0] axi_slave_00_r_resp; + wire axi_slave_00_r_last; + wire [AXI_ID_WIDTH - 1:0] axi_slave_00_r_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_00_r_user; + wire axi_slave_00_r_ready; + wire axi_slave_00_r_valid; + wire [1:0] axi_slave_00_b_resp; + wire [AXI_ID_WIDTH - 1:0] axi_slave_00_b_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_00_b_user; + wire axi_slave_00_b_ready; + wire axi_slave_00_b_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_slave_01_aw_addr; + wire [2:0] axi_slave_01_aw_prot; + wire [3:0] axi_slave_01_aw_region; + wire [7:0] axi_slave_01_aw_len; + wire [2:0] axi_slave_01_aw_size; + wire [1:0] axi_slave_01_aw_burst; + wire axi_slave_01_aw_lock; + wire [3:0] axi_slave_01_aw_cache; + wire [3:0] axi_slave_01_aw_qos; + wire [AXI_ID_WIDTH - 1:0] axi_slave_01_aw_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_01_aw_user; + wire axi_slave_01_aw_ready; + wire axi_slave_01_aw_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_slave_01_ar_addr; + wire [2:0] axi_slave_01_ar_prot; + wire [3:0] axi_slave_01_ar_region; + wire [7:0] axi_slave_01_ar_len; + wire [2:0] axi_slave_01_ar_size; + wire [1:0] axi_slave_01_ar_burst; + wire axi_slave_01_ar_lock; + wire [3:0] axi_slave_01_ar_cache; + wire [3:0] axi_slave_01_ar_qos; + wire [AXI_ID_WIDTH - 1:0] axi_slave_01_ar_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_01_ar_user; + wire axi_slave_01_ar_ready; + wire axi_slave_01_ar_valid; + wire axi_slave_01_w_valid; + wire [AXI_DATA_WIDTH - 1:0] axi_slave_01_w_data; + wire [AXI_STRB_WIDTH - 1:0] axi_slave_01_w_strb; + wire [AXI_USER_WIDTH - 1:0] axi_slave_01_w_user; + wire axi_slave_01_w_last; + wire axi_slave_01_w_ready; + wire [AXI_DATA_WIDTH - 1:0] axi_slave_01_r_data; + wire [1:0] axi_slave_01_r_resp; + wire axi_slave_01_r_last; + wire [AXI_ID_WIDTH - 1:0] axi_slave_01_r_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_01_r_user; + wire axi_slave_01_r_ready; + wire axi_slave_01_r_valid; + wire [1:0] axi_slave_01_b_resp; + wire [AXI_ID_WIDTH - 1:0] axi_slave_01_b_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_01_b_user; + wire axi_slave_01_b_ready; + wire axi_slave_01_b_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_slave_02_aw_addr; + wire [2:0] axi_slave_02_aw_prot; + wire [3:0] axi_slave_02_aw_region; + wire [7:0] axi_slave_02_aw_len; + wire [2:0] axi_slave_02_aw_size; + wire [1:0] axi_slave_02_aw_burst; + wire axi_slave_02_aw_lock; + wire [3:0] axi_slave_02_aw_cache; + wire [3:0] axi_slave_02_aw_qos; + wire [AXI_ID_WIDTH - 1:0] axi_slave_02_aw_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_02_aw_user; + wire axi_slave_02_aw_ready; + wire axi_slave_02_aw_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_slave_02_ar_addr; + wire [2:0] axi_slave_02_ar_prot; + wire [3:0] axi_slave_02_ar_region; + wire [7:0] axi_slave_02_ar_len; + wire [2:0] axi_slave_02_ar_size; + wire [1:0] axi_slave_02_ar_burst; + wire axi_slave_02_ar_lock; + wire [3:0] axi_slave_02_ar_cache; + wire [3:0] axi_slave_02_ar_qos; + wire [AXI_ID_WIDTH - 1:0] axi_slave_02_ar_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_02_ar_user; + wire axi_slave_02_ar_ready; + wire axi_slave_02_ar_valid; + wire axi_slave_02_w_valid; + wire [AXI_DATA_WIDTH - 1:0] axi_slave_02_w_data; + wire [AXI_STRB_WIDTH - 1:0] axi_slave_02_w_strb; + wire [AXI_USER_WIDTH - 1:0] axi_slave_02_w_user; + wire axi_slave_02_w_last; + wire axi_slave_02_w_ready; + wire [AXI_DATA_WIDTH - 1:0] axi_slave_02_r_data; + wire [1:0] axi_slave_02_r_resp; + wire axi_slave_02_r_last; + wire [AXI_ID_WIDTH - 1:0] axi_slave_02_r_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_02_r_user; + wire axi_slave_02_r_ready; + wire axi_slave_02_r_valid; + wire [1:0] axi_slave_02_b_resp; + wire [AXI_ID_WIDTH - 1:0] axi_slave_02_b_id; + wire [AXI_USER_WIDTH - 1:0] axi_slave_02_b_user; + wire axi_slave_02_b_ready; + wire axi_slave_02_b_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_master_00_aw_addr; + wire [2:0] axi_master_00_aw_prot; + wire [3:0] axi_master_00_aw_region; + wire [7:0] axi_master_00_aw_len; + wire [2:0] axi_master_00_aw_size; + wire [1:0] axi_master_00_aw_burst; + wire axi_master_00_aw_lock; + wire [3:0] axi_master_00_aw_cache; + wire [3:0] axi_master_00_aw_qos; + wire [AXI_ID_WIDTH - 1:0] axi_master_00_aw_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_00_aw_user; + wire axi_master_00_aw_ready; + wire axi_master_00_aw_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_master_00_ar_addr; + wire [2:0] axi_master_00_ar_prot; + wire [3:0] axi_master_00_ar_region; + wire [7:0] axi_master_00_ar_len; + wire [2:0] axi_master_00_ar_size; + wire [1:0] axi_master_00_ar_burst; + wire axi_master_00_ar_lock; + wire [3:0] axi_master_00_ar_cache; + wire [3:0] axi_master_00_ar_qos; + wire [AXI_ID_WIDTH - 1:0] axi_master_00_ar_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_00_ar_user; + wire axi_master_00_ar_ready; + wire axi_master_00_ar_valid; + wire axi_master_00_w_valid; + wire [AXI_DATA_WIDTH - 1:0] axi_master_00_w_data; + wire [AXI_STRB_WIDTH - 1:0] axi_master_00_w_strb; + wire [AXI_USER_WIDTH - 1:0] axi_master_00_w_user; + wire axi_master_00_w_last; + wire axi_master_00_w_ready; + wire [AXI_DATA_WIDTH - 1:0] axi_master_00_r_data; + wire [1:0] axi_master_00_r_resp; + wire axi_master_00_r_last; + wire [AXI_ID_WIDTH - 1:0] axi_master_00_r_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_00_r_user; + wire axi_master_00_r_ready; + wire axi_master_00_r_valid; + wire [1:0] axi_master_00_b_resp; + wire [AXI_ID_WIDTH - 1:0] axi_master_00_b_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_00_b_user; + wire axi_master_00_b_ready; + wire axi_master_00_b_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_master_01_aw_addr; + wire [2:0] axi_master_01_aw_prot; + wire [3:0] axi_master_01_aw_region; + wire [7:0] axi_master_01_aw_len; + wire [2:0] axi_master_01_aw_size; + wire [1:0] axi_master_01_aw_burst; + wire axi_master_01_aw_lock; + wire [3:0] axi_master_01_aw_cache; + wire [3:0] axi_master_01_aw_qos; + wire [AXI_ID_WIDTH - 1:0] axi_master_01_aw_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_01_aw_user; + wire axi_master_01_aw_ready; + wire axi_master_01_aw_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_master_01_ar_addr; + wire [2:0] axi_master_01_ar_prot; + wire [3:0] axi_master_01_ar_region; + wire [7:0] axi_master_01_ar_len; + wire [2:0] axi_master_01_ar_size; + wire [1:0] axi_master_01_ar_burst; + wire axi_master_01_ar_lock; + wire [3:0] axi_master_01_ar_cache; + wire [3:0] axi_master_01_ar_qos; + wire [AXI_ID_WIDTH - 1:0] axi_master_01_ar_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_01_ar_user; + wire axi_master_01_ar_ready; + wire axi_master_01_ar_valid; + wire axi_master_01_w_valid; + wire [AXI_DATA_WIDTH - 1:0] axi_master_01_w_data; + wire [AXI_STRB_WIDTH - 1:0] axi_master_01_w_strb; + wire [AXI_USER_WIDTH - 1:0] axi_master_01_w_user; + wire axi_master_01_w_last; + wire axi_master_01_w_ready; + wire [AXI_DATA_WIDTH - 1:0] axi_master_01_r_data; + wire [1:0] axi_master_01_r_resp; + wire axi_master_01_r_last; + wire [AXI_ID_WIDTH - 1:0] axi_master_01_r_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_01_r_user; + wire axi_master_01_r_ready; + wire axi_master_01_r_valid; + wire [1:0] axi_master_01_b_resp; + wire [AXI_ID_WIDTH - 1:0] axi_master_01_b_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_01_b_user; + wire axi_master_01_b_ready; + wire axi_master_01_b_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_master_02_aw_addr; + wire [2:0] axi_master_02_aw_prot; + wire [3:0] axi_master_02_aw_region; + wire [7:0] axi_master_02_aw_len; + wire [2:0] axi_master_02_aw_size; + wire [1:0] axi_master_02_aw_burst; + wire axi_master_02_aw_lock; + wire [3:0] axi_master_02_aw_cache; + wire [3:0] axi_master_02_aw_qos; + wire [AXI_ID_WIDTH - 1:0] axi_master_02_aw_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_02_aw_user; + wire axi_master_02_aw_ready; + wire axi_master_02_aw_valid; + wire [AXI_ADDR_WIDTH - 1:0] axi_master_02_ar_addr; + wire [2:0] axi_master_02_ar_prot; + wire [3:0] axi_master_02_ar_region; + wire [7:0] axi_master_02_ar_len; + wire [2:0] axi_master_02_ar_size; + wire [1:0] axi_master_02_ar_burst; + wire axi_master_02_ar_lock; + wire [3:0] axi_master_02_ar_cache; + wire [3:0] axi_master_02_ar_qos; + wire [AXI_ID_WIDTH - 1:0] axi_master_02_ar_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_02_ar_user; + wire axi_master_02_ar_ready; + wire axi_master_02_ar_valid; + wire axi_master_02_w_valid; + wire [AXI_DATA_WIDTH - 1:0] axi_master_02_w_data; + wire [AXI_STRB_WIDTH - 1:0] axi_master_02_w_strb; + wire [AXI_USER_WIDTH - 1:0] axi_master_02_w_user; + wire axi_master_02_w_last; + wire axi_master_02_w_ready; + wire [AXI_DATA_WIDTH - 1:0] axi_master_02_r_data; + wire [1:0] axi_master_02_r_resp; + wire axi_master_02_r_last; + wire [AXI_ID_WIDTH - 1:0] axi_master_02_r_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_02_r_user; + wire axi_master_02_r_ready; + wire axi_master_02_r_valid; + wire [1:0] axi_master_02_b_resp; + wire [AXI_ID_WIDTH - 1:0] axi_master_02_b_id; + wire [AXI_USER_WIDTH - 1:0] axi_master_02_b_user; + wire axi_master_02_b_ready; + wire axi_master_02_b_valid; + wire axi_slave; + wire axi_master; + axi_node_wrap #( + .AXI_ADDRESS_W(AXI_ADDRESS_W), + .AXI_DATA_W(AXI_DATA_W), + .AXI_USER_W(AXI_USER_W), + .N_MASTER_PORT(N_MASTER_PORT), + .N_SLAVE_PORT(N_SLAVE_PORT), + .AXI_ID_IN(AXI_ID_IN), + .AXI_ID_OUT(AXI_ID_OUT), + .FIFO_DEPTH_DW(FIFO_DEPTH_DW), + .N_REGION(N_REGION) + ) i_axi_node_wrap( + .clk(clk), + .rst_n(rst_n), + .test_en_i(test_en_i), + .axi_port_slave(axi_slave), + .axi_port_master(axi_master), + .cfg_END_ADDR_i(cfg_END_ADDR_i), + .cfg_START_ADDR_i(cfg_START_ADDR_i), + .cfg_valid_rule_i(cfg_valid_rule_i), + .cfg_connectivity_map_i(cfg_connectivity_map_i) + ); + axi_slice_wrap i_axi_slice_wrap_master_00( + .clk_i(clk), + .rst_ni(rst_n), + .test_en_i(test_en_i), + .s00_aw_addr(axi_master_00_aw_addr), + .s00_aw_prot(axi_master_00_aw_prot), + .s00_aw_region(axi_master_00_aw_region), + .s00_aw_len(axi_master_00_aw_len), + .s00_aw_size(axi_master_00_aw_size), + .s00_aw_burst(axi_master_00_aw_burst), + .s00_aw_lock(axi_master_00_aw_lock), + .s00_aw_cache(axi_master_00_aw_cache), + .s00_aw_qos(axi_master_00_aw_qos), + .s00_aw_id(axi_master_00_aw_id), + .s00_aw_user(axi_master_00_aw_user), + .s00_aw_ready(axi_master_00_aw_ready), + .s00_aw_valid(axi_master_00_aw_valid), + .s00_ar_addr(axi_master_00_ar_addr), + .s00_ar_prot(axi_master_00_ar_prot), + .s00_ar_region(axi_master_00_ar_region), + .s00_ar_len(axi_master_00_ar_len), + .s00_ar_size(axi_master_00_ar_size), + .s00_ar_burst(axi_master_00_ar_burst), + .s00_ar_lock(axi_master_00_ar_lock), + .s00_ar_cache(axi_master_00_ar_cache), + .s00_ar_qos(axi_master_00_ar_qos), + .s00_ar_id(axi_master_00_ar_id), + .s00_ar_user(axi_master_00_ar_user), + .s00_ar_ready(axi_master_00_ar_ready), + .s00_ar_valid(axi_master_00_ar_valid), + .s00_w_valid(axi_master_00_w_valid), + .s00_w_data(axi_master_00_w_data), + .s00_w_strb(axi_master_00_w_strb), + .s00_w_user(axi_master_00_w_user), + .s00_w_last(axi_master_00_w_last), + .s00_w_ready(axi_master_00_w_ready), + .s00_r_data(axi_master_00_r_data), + .s00_r_resp(axi_master_00_r_resp), + .s00_r_last(axi_master_00_r_last), + .s00_r_id(axi_master_00_r_id), + .s00_r_user(axi_master_00_r_user), + .s00_r_ready(axi_master_00_r_ready), + .s00_r_valid(axi_master_00_r_valid), + .s00_b_resp(axi_master_00_b_resp), + .s00_b_id(axi_master_00_b_id), + .s00_b_user(axi_master_00_b_user), + .s00_b_ready(axi_master_00_b_ready), + .s00_b_valid(axi_master_00_b_valid), + .m00_aw_addr(master_00_aw_addr), + .m00_aw_prot(master_00_aw_prot), + .m00_aw_region(master_00_aw_region), + .m00_aw_len(master_00_aw_len), + .m00_aw_size(master_00_aw_size), + .m00_aw_burst(master_00_aw_burst), + .m00_aw_lock(master_00_aw_lock), + .m00_aw_cache(master_00_aw_cache), + .m00_aw_qos(master_00_aw_qos), + .m00_aw_id(master_00_aw_id), + .m00_aw_user(master_00_aw_user), + .m00_aw_ready(master_00_aw_ready), + .m00_aw_valid(master_00_aw_valid), + .m00_ar_addr(master_00_ar_addr), + .m00_ar_prot(master_00_ar_prot), + .m00_ar_region(master_00_ar_region), + .m00_ar_len(master_00_ar_len), + .m00_ar_size(master_00_ar_size), + .m00_ar_burst(master_00_ar_burst), + .m00_ar_lock(master_00_ar_lock), + .m00_ar_cache(master_00_ar_cache), + .m00_ar_qos(master_00_ar_qos), + .m00_ar_id(master_00_ar_id), + .m00_ar_user(master_00_ar_user), + .m00_ar_ready(master_00_ar_ready), + .m00_ar_valid(master_00_ar_valid), + .m00_w_valid(master_00_w_valid), + .m00_w_data(master_00_w_data), + .m00_w_strb(master_00_w_strb), + .m00_w_user(master_00_w_user), + .m00_w_last(master_00_w_last), + .m00_w_ready(master_00_w_ready), + .m00_r_data(master_00_r_data), + .m00_r_resp(master_00_r_resp), + .m00_r_last(master_00_r_last), + .m00_r_id(master_00_r_id), + .m00_r_user(master_00_r_user), + .m00_r_ready(master_00_r_ready), + .m00_r_valid(master_00_r_valid), + .m00_b_resp(master_00_b_resp), + .m00_b_id(master_00_b_id), + .m00_b_user(master_00_b_user), + .m00_b_ready(master_00_b_ready), + .m00_b_valid(master_00_b_valid) + ); + axi_slice_wrap i_axi_slice_wrap_master_01( + .clk_i(clk), + .rst_ni(rst_n), + .test_en_i(test_en_i), + .s00_aw_addr(axi_master_01_aw_addr), + .s00_aw_prot(axi_master_01_aw_prot), + .s00_aw_region(axi_master_01_aw_region), + .s00_aw_len(axi_master_01_aw_len), + .s00_aw_size(axi_master_01_aw_size), + .s00_aw_burst(axi_master_01_aw_burst), + .s00_aw_lock(axi_master_01_aw_lock), + .s00_aw_cache(axi_master_01_aw_cache), + .s00_aw_qos(axi_master_01_aw_qos), + .s00_aw_id(axi_master_01_aw_id), + .s00_aw_user(axi_master_01_aw_user), + .s00_aw_ready(axi_master_01_aw_ready), + .s00_aw_valid(axi_master_01_aw_valid), + .s00_ar_addr(axi_master_01_ar_addr), + .s00_ar_prot(axi_master_01_ar_prot), + .s00_ar_region(axi_master_01_ar_region), + .s00_ar_len(axi_master_01_ar_len), + .s00_ar_size(axi_master_01_ar_size), + .s00_ar_burst(axi_master_01_ar_burst), + .s00_ar_lock(axi_master_01_ar_lock), + .s00_ar_cache(axi_master_01_ar_cache), + .s00_ar_qos(axi_master_01_ar_qos), + .s00_ar_id(axi_master_01_ar_id), + .s00_ar_user(axi_master_01_ar_user), + .s00_ar_ready(axi_master_01_ar_ready), + .s00_ar_valid(axi_master_01_ar_valid), + .s00_w_valid(axi_master_01_w_valid), + .s00_w_data(axi_master_01_w_data), + .s00_w_strb(axi_master_01_w_strb), + .s00_w_user(axi_master_01_w_user), + .s00_w_last(axi_master_01_w_last), + .s00_w_ready(axi_master_01_w_ready), + .s00_r_data(axi_master_01_r_data), + .s00_r_resp(axi_master_01_r_resp), + .s00_r_last(axi_master_01_r_last), + .s00_r_id(axi_master_01_r_id), + .s00_r_user(axi_master_01_r_user), + .s00_r_ready(axi_master_01_r_ready), + .s00_r_valid(axi_master_01_r_valid), + .s00_b_resp(axi_master_01_b_resp), + .s00_b_id(axi_master_01_b_id), + .s00_b_user(axi_master_01_b_user), + .s00_b_ready(axi_master_01_b_ready), + .s00_b_valid(axi_master_01_b_valid), + .m00_aw_addr(master_01_aw_addr), + .m00_aw_prot(master_01_aw_prot), + .m00_aw_region(master_01_aw_region), + .m00_aw_len(master_01_aw_len), + .m00_aw_size(master_01_aw_size), + .m00_aw_burst(master_01_aw_burst), + .m00_aw_lock(master_01_aw_lock), + .m00_aw_cache(master_01_aw_cache), + .m00_aw_qos(master_01_aw_qos), + .m00_aw_id(master_01_aw_id), + .m00_aw_user(master_01_aw_user), + .m00_aw_ready(master_01_aw_ready), + .m00_aw_valid(master_01_aw_valid), + .m00_ar_addr(master_01_ar_addr), + .m00_ar_prot(master_01_ar_prot), + .m00_ar_region(master_01_ar_region), + .m00_ar_len(master_01_ar_len), + .m00_ar_size(master_01_ar_size), + .m00_ar_burst(master_01_ar_burst), + .m00_ar_lock(master_01_ar_lock), + .m00_ar_cache(master_01_ar_cache), + .m00_ar_qos(master_01_ar_qos), + .m00_ar_id(master_01_ar_id), + .m00_ar_user(master_01_ar_user), + .m00_ar_ready(master_01_ar_ready), + .m00_ar_valid(master_01_ar_valid), + .m00_w_valid(master_01_w_valid), + .m00_w_data(master_01_w_data), + .m00_w_strb(master_01_w_strb), + .m00_w_user(master_01_w_user), + .m00_w_last(master_01_w_last), + .m00_w_ready(master_01_w_ready), + .m00_r_data(master_01_r_data), + .m00_r_resp(master_01_r_resp), + .m00_r_last(master_01_r_last), + .m00_r_id(master_01_r_id), + .m00_r_user(master_01_r_user), + .m00_r_ready(master_01_r_ready), + .m00_r_valid(master_01_r_valid), + .m00_b_resp(master_01_b_resp), + .m00_b_id(master_01_b_id), + .m00_b_user(master_01_b_user), + .m00_b_ready(master_01_b_ready), + .m00_b_valid(master_01_b_valid) + ); + axi_slice_wrap i_axi_slice_wrap_master_02( + .clk_i(clk), + .rst_ni(rst_n), + .test_en_i(test_en_i), + .s00_aw_addr(axi_master_02_aw_addr), + .s00_aw_prot(axi_master_02_aw_prot), + .s00_aw_region(axi_master_02_aw_region), + .s00_aw_len(axi_master_02_aw_len), + .s00_aw_size(axi_master_02_aw_size), + .s00_aw_burst(axi_master_02_aw_burst), + .s00_aw_lock(axi_master_02_aw_lock), + .s00_aw_cache(axi_master_02_aw_cache), + .s00_aw_qos(axi_master_02_aw_qos), + .s00_aw_id(axi_master_02_aw_id), + .s00_aw_user(axi_master_02_aw_user), + .s00_aw_ready(axi_master_02_aw_ready), + .s00_aw_valid(axi_master_02_aw_valid), + .s00_ar_addr(axi_master_02_ar_addr), + .s00_ar_prot(axi_master_02_ar_prot), + .s00_ar_region(axi_master_02_ar_region), + .s00_ar_len(axi_master_02_ar_len), + .s00_ar_size(axi_master_02_ar_size), + .s00_ar_burst(axi_master_02_ar_burst), + .s00_ar_lock(axi_master_02_ar_lock), + .s00_ar_cache(axi_master_02_ar_cache), + .s00_ar_qos(axi_master_02_ar_qos), + .s00_ar_id(axi_master_02_ar_id), + .s00_ar_user(axi_master_02_ar_user), + .s00_ar_ready(axi_master_02_ar_ready), + .s00_ar_valid(axi_master_02_ar_valid), + .s00_w_valid(axi_master_02_w_valid), + .s00_w_data(axi_master_02_w_data), + .s00_w_strb(axi_master_02_w_strb), + .s00_w_user(axi_master_02_w_user), + .s00_w_last(axi_master_02_w_last), + .s00_w_ready(axi_master_02_w_ready), + .s00_r_data(axi_master_02_r_data), + .s00_r_resp(axi_master_02_r_resp), + .s00_r_last(axi_master_02_r_last), + .s00_r_id(axi_master_02_r_id), + .s00_r_user(axi_master_02_r_user), + .s00_r_ready(axi_master_02_r_ready), + .s00_r_valid(axi_master_02_r_valid), + .s00_b_resp(axi_master_02_b_resp), + .s00_b_id(axi_master_02_b_id), + .s00_b_user(axi_master_02_b_user), + .s00_b_ready(axi_master_02_b_ready), + .s00_b_valid(axi_master_02_b_valid), + .m00_aw_addr(master_02_aw_addr), + .m00_aw_prot(master_02_aw_prot), + .m00_aw_region(master_02_aw_region), + .m00_aw_len(master_02_aw_len), + .m00_aw_size(master_02_aw_size), + .m00_aw_burst(master_02_aw_burst), + .m00_aw_lock(master_02_aw_lock), + .m00_aw_cache(master_02_aw_cache), + .m00_aw_qos(master_02_aw_qos), + .m00_aw_id(master_02_aw_id), + .m00_aw_user(master_02_aw_user), + .m00_aw_ready(master_02_aw_ready), + .m00_aw_valid(master_02_aw_valid), + .m00_ar_addr(master_02_ar_addr), + .m00_ar_prot(master_02_ar_prot), + .m00_ar_region(master_02_ar_region), + .m00_ar_len(master_02_ar_len), + .m00_ar_size(master_02_ar_size), + .m00_ar_burst(master_02_ar_burst), + .m00_ar_lock(master_02_ar_lock), + .m00_ar_cache(master_02_ar_cache), + .m00_ar_qos(master_02_ar_qos), + .m00_ar_id(master_02_ar_id), + .m00_ar_user(master_02_ar_user), + .m00_ar_ready(master_02_ar_ready), + .m00_ar_valid(master_02_ar_valid), + .m00_w_valid(master_02_w_valid), + .m00_w_data(master_02_w_data), + .m00_w_strb(master_02_w_strb), + .m00_w_user(master_02_w_user), + .m00_w_last(master_02_w_last), + .m00_w_ready(master_02_w_ready), + .m00_r_data(master_02_r_data), + .m00_r_resp(master_02_r_resp), + .m00_r_last(master_02_r_last), + .m00_r_id(master_02_r_id), + .m00_r_user(master_02_r_user), + .m00_r_ready(master_02_r_ready), + .m00_r_valid(master_02_r_valid), + .m00_b_resp(master_02_b_resp), + .m00_b_id(master_02_b_id), + .m00_b_user(master_02_b_user), + .m00_b_ready(master_02_b_ready), + .m00_b_valid(master_02_b_valid) + ); + axi_slice_wrap i_axi_slice_wrap_slave_00( + .clk_i(clk), + .rst_ni(rst_n), + .test_en_i(test_en_i), + .s00_aw_addr(slave_00_aw_addr), + .s00_aw_prot(slave_00_aw_prot), + .s00_aw_region(slave_00_aw_region), + .s00_aw_len(slave_00_aw_len), + .s00_aw_size(slave_00_aw_size), + .s00_aw_burst(slave_00_aw_burst), + .s00_aw_lock(slave_00_aw_lock), + .s00_aw_cache(slave_00_aw_cache), + .s00_aw_qos(slave_00_aw_qos), + .s00_aw_id(slave_00_aw_id), + .s00_aw_user(slave_00_aw_user), + .s00_aw_ready(slave_00_aw_ready), + .s00_aw_valid(slave_00_aw_valid), + .s00_ar_addr(slave_00_ar_addr), + .s00_ar_prot(slave_00_ar_prot), + .s00_ar_region(slave_00_ar_region), + .s00_ar_len(slave_00_ar_len), + .s00_ar_size(slave_00_ar_size), + .s00_ar_burst(slave_00_ar_burst), + .s00_ar_lock(slave_00_ar_lock), + .s00_ar_cache(slave_00_ar_cache), + .s00_ar_qos(slave_00_ar_qos), + .s00_ar_id(slave_00_ar_id), + .s00_ar_user(slave_00_ar_user), + .s00_ar_ready(slave_00_ar_ready), + .s00_ar_valid(slave_00_ar_valid), + .s00_w_valid(slave_00_w_valid), + .s00_w_data(slave_00_w_data), + .s00_w_strb(slave_00_w_strb), + .s00_w_user(slave_00_w_user), + .s00_w_last(slave_00_w_last), + .s00_w_ready(slave_00_w_ready), + .s00_r_data(slave_00_r_data), + .s00_r_resp(slave_00_r_resp), + .s00_r_last(slave_00_r_last), + .s00_r_id(slave_00_r_id), + .s00_r_user(slave_00_r_user), + .s00_r_ready(slave_00_r_ready), + .s00_r_valid(slave_00_r_valid), + .s00_b_resp(slave_00_b_resp), + .s00_b_id(slave_00_b_id), + .s00_b_user(slave_00_b_user), + .s00_b_ready(slave_00_b_ready), + .s00_b_valid(slave_00_b_valid), + .m00_aw_addr(axi_slave_00_aw_addr), + .m00_aw_prot(axi_slave_00_aw_prot), + .m00_aw_region(axi_slave_00_aw_region), + .m00_aw_len(axi_slave_00_aw_len), + .m00_aw_size(axi_slave_00_aw_size), + .m00_aw_burst(axi_slave_00_aw_burst), + .m00_aw_lock(axi_slave_00_aw_lock), + .m00_aw_cache(axi_slave_00_aw_cache), + .m00_aw_qos(axi_slave_00_aw_qos), + .m00_aw_id(axi_slave_00_aw_id), + .m00_aw_user(axi_slave_00_aw_user), + .m00_aw_ready(axi_slave_00_aw_ready), + .m00_aw_valid(axi_slave_00_aw_valid), + .m00_ar_addr(axi_slave_00_ar_addr), + .m00_ar_prot(axi_slave_00_ar_prot), + .m00_ar_region(axi_slave_00_ar_region), + .m00_ar_len(axi_slave_00_ar_len), + .m00_ar_size(axi_slave_00_ar_size), + .m00_ar_burst(axi_slave_00_ar_burst), + .m00_ar_lock(axi_slave_00_ar_lock), + .m00_ar_cache(axi_slave_00_ar_cache), + .m00_ar_qos(axi_slave_00_ar_qos), + .m00_ar_id(axi_slave_00_ar_id), + .m00_ar_user(axi_slave_00_ar_user), + .m00_ar_ready(axi_slave_00_ar_ready), + .m00_ar_valid(axi_slave_00_ar_valid), + .m00_w_valid(axi_slave_00_w_valid), + .m00_w_data(axi_slave_00_w_data), + .m00_w_strb(axi_slave_00_w_strb), + .m00_w_user(axi_slave_00_w_user), + .m00_w_last(axi_slave_00_w_last), + .m00_w_ready(axi_slave_00_w_ready), + .m00_r_data(axi_slave_00_r_data), + .m00_r_resp(axi_slave_00_r_resp), + .m00_r_last(axi_slave_00_r_last), + .m00_r_id(axi_slave_00_r_id), + .m00_r_user(axi_slave_00_r_user), + .m00_r_ready(axi_slave_00_r_ready), + .m00_r_valid(axi_slave_00_r_valid), + .m00_b_resp(axi_slave_00_b_resp), + .m00_b_id(axi_slave_00_b_id), + .m00_b_user(axi_slave_00_b_user), + .m00_b_ready(axi_slave_00_b_ready), + .m00_b_valid(axi_slave_00_b_valid) + ); + axi_slice_wrap i_axi_slice_wrap_slave_01( + .clk_i(clk), + .rst_ni(rst_n), + .test_en_i(test_en_i), + .s00_aw_addr(slave_01_aw_addr), + .s00_aw_prot(slave_01_aw_prot), + .s00_aw_region(slave_01_aw_region), + .s00_aw_len(slave_01_aw_len), + .s00_aw_size(slave_01_aw_size), + .s00_aw_burst(slave_01_aw_burst), + .s00_aw_lock(slave_01_aw_lock), + .s00_aw_cache(slave_01_aw_cache), + .s00_aw_qos(slave_01_aw_qos), + .s00_aw_id(slave_01_aw_id), + .s00_aw_user(slave_01_aw_user), + .s00_aw_ready(slave_01_aw_ready), + .s00_aw_valid(slave_01_aw_valid), + .s00_ar_addr(slave_01_ar_addr), + .s00_ar_prot(slave_01_ar_prot), + .s00_ar_region(slave_01_ar_region), + .s00_ar_len(slave_01_ar_len), + .s00_ar_size(slave_01_ar_size), + .s00_ar_burst(slave_01_ar_burst), + .s00_ar_lock(slave_01_ar_lock), + .s00_ar_cache(slave_01_ar_cache), + .s00_ar_qos(slave_01_ar_qos), + .s00_ar_id(slave_01_ar_id), + .s00_ar_user(slave_01_ar_user), + .s00_ar_ready(slave_01_ar_ready), + .s00_ar_valid(slave_01_ar_valid), + .s00_w_valid(slave_01_w_valid), + .s00_w_data(slave_01_w_data), + .s00_w_strb(slave_01_w_strb), + .s00_w_user(slave_01_w_user), + .s00_w_last(slave_01_w_last), + .s00_w_ready(slave_01_w_ready), + .s00_r_data(slave_01_r_data), + .s00_r_resp(slave_01_r_resp), + .s00_r_last(slave_01_r_last), + .s00_r_id(slave_01_r_id), + .s00_r_user(slave_01_r_user), + .s00_r_ready(slave_01_r_ready), + .s00_r_valid(slave_01_r_valid), + .s00_b_resp(slave_01_b_resp), + .s00_b_id(slave_01_b_id), + .s00_b_user(slave_01_b_user), + .s00_b_ready(slave_01_b_ready), + .s00_b_valid(slave_01_b_valid), + .m00_aw_addr(axi_slave_01_aw_addr), + .m00_aw_prot(axi_slave_01_aw_prot), + .m00_aw_region(axi_slave_01_aw_region), + .m00_aw_len(axi_slave_01_aw_len), + .m00_aw_size(axi_slave_01_aw_size), + .m00_aw_burst(axi_slave_01_aw_burst), + .m00_aw_lock(axi_slave_01_aw_lock), + .m00_aw_cache(axi_slave_01_aw_cache), + .m00_aw_qos(axi_slave_01_aw_qos), + .m00_aw_id(axi_slave_01_aw_id), + .m00_aw_user(axi_slave_01_aw_user), + .m00_aw_ready(axi_slave_01_aw_ready), + .m00_aw_valid(axi_slave_01_aw_valid), + .m00_ar_addr(axi_slave_01_ar_addr), + .m00_ar_prot(axi_slave_01_ar_prot), + .m00_ar_region(axi_slave_01_ar_region), + .m00_ar_len(axi_slave_01_ar_len), + .m00_ar_size(axi_slave_01_ar_size), + .m00_ar_burst(axi_slave_01_ar_burst), + .m00_ar_lock(axi_slave_01_ar_lock), + .m00_ar_cache(axi_slave_01_ar_cache), + .m00_ar_qos(axi_slave_01_ar_qos), + .m00_ar_id(axi_slave_01_ar_id), + .m00_ar_user(axi_slave_01_ar_user), + .m00_ar_ready(axi_slave_01_ar_ready), + .m00_ar_valid(axi_slave_01_ar_valid), + .m00_w_valid(axi_slave_01_w_valid), + .m00_w_data(axi_slave_01_w_data), + .m00_w_strb(axi_slave_01_w_strb), + .m00_w_user(axi_slave_01_w_user), + .m00_w_last(axi_slave_01_w_last), + .m00_w_ready(axi_slave_01_w_ready), + .m00_r_data(axi_slave_01_r_data), + .m00_r_resp(axi_slave_01_r_resp), + .m00_r_last(axi_slave_01_r_last), + .m00_r_id(axi_slave_01_r_id), + .m00_r_user(axi_slave_01_r_user), + .m00_r_ready(axi_slave_01_r_ready), + .m00_r_valid(axi_slave_01_r_valid), + .m00_b_resp(axi_slave_01_b_resp), + .m00_b_id(axi_slave_01_b_id), + .m00_b_user(axi_slave_01_b_user), + .m00_b_ready(axi_slave_01_b_ready), + .m00_b_valid(axi_slave_01_b_valid) + ); + axi_slice_wrap i_axi_slice_wrap_slave_02( + .clk_i(clk), + .rst_ni(rst_n), + .test_en_i(test_en_i), + .s00_aw_addr(slave_02_aw_addr), + .s00_aw_prot(slave_02_aw_prot), + .s00_aw_region(slave_02_aw_region), + .s00_aw_len(slave_02_aw_len), + .s00_aw_size(slave_02_aw_size), + .s00_aw_burst(slave_02_aw_burst), + .s00_aw_lock(slave_02_aw_lock), + .s00_aw_cache(slave_02_aw_cache), + .s00_aw_qos(slave_02_aw_qos), + .s00_aw_id(slave_02_aw_id), + .s00_aw_user(slave_02_aw_user), + .s00_aw_ready(slave_02_aw_ready), + .s00_aw_valid(slave_02_aw_valid), + .s00_ar_addr(slave_02_ar_addr), + .s00_ar_prot(slave_02_ar_prot), + .s00_ar_region(slave_02_ar_region), + .s00_ar_len(slave_02_ar_len), + .s00_ar_size(slave_02_ar_size), + .s00_ar_burst(slave_02_ar_burst), + .s00_ar_lock(slave_02_ar_lock), + .s00_ar_cache(slave_02_ar_cache), + .s00_ar_qos(slave_02_ar_qos), + .s00_ar_id(slave_02_ar_id), + .s00_ar_user(slave_02_ar_user), + .s00_ar_ready(slave_02_ar_ready), + .s00_ar_valid(slave_02_ar_valid), + .s00_w_valid(slave_02_w_valid), + .s00_w_data(slave_02_w_data), + .s00_w_strb(slave_02_w_strb), + .s00_w_user(slave_02_w_user), + .s00_w_last(slave_02_w_last), + .s00_w_ready(slave_02_w_ready), + .s00_r_data(slave_02_r_data), + .s00_r_resp(slave_02_r_resp), + .s00_r_last(slave_02_r_last), + .s00_r_id(slave_02_r_id), + .s00_r_user(slave_02_r_user), + .s00_r_ready(slave_02_r_ready), + .s00_r_valid(slave_02_r_valid), + .s00_b_resp(slave_02_b_resp), + .s00_b_id(slave_02_b_id), + .s00_b_user(slave_02_b_user), + .s00_b_ready(slave_02_b_ready), + .s00_b_valid(slave_02_b_valid), + .m00_aw_addr(axi_slave_02_aw_addr), + .m00_aw_prot(axi_slave_02_aw_prot), + .m00_aw_region(axi_slave_02_aw_region), + .m00_aw_len(axi_slave_02_aw_len), + .m00_aw_size(axi_slave_02_aw_size), + .m00_aw_burst(axi_slave_02_aw_burst), + .m00_aw_lock(axi_slave_02_aw_lock), + .m00_aw_cache(axi_slave_02_aw_cache), + .m00_aw_qos(axi_slave_02_aw_qos), + .m00_aw_id(axi_slave_02_aw_id), + .m00_aw_user(axi_slave_02_aw_user), + .m00_aw_ready(axi_slave_02_aw_ready), + .m00_aw_valid(axi_slave_02_aw_valid), + .m00_ar_addr(axi_slave_02_ar_addr), + .m00_ar_prot(axi_slave_02_ar_prot), + .m00_ar_region(axi_slave_02_ar_region), + .m00_ar_len(axi_slave_02_ar_len), + .m00_ar_size(axi_slave_02_ar_size), + .m00_ar_burst(axi_slave_02_ar_burst), + .m00_ar_lock(axi_slave_02_ar_lock), + .m00_ar_cache(axi_slave_02_ar_cache), + .m00_ar_qos(axi_slave_02_ar_qos), + .m00_ar_id(axi_slave_02_ar_id), + .m00_ar_user(axi_slave_02_ar_user), + .m00_ar_ready(axi_slave_02_ar_ready), + .m00_ar_valid(axi_slave_02_ar_valid), + .m00_w_valid(axi_slave_02_w_valid), + .m00_w_data(axi_slave_02_w_data), + .m00_w_strb(axi_slave_02_w_strb), + .m00_w_user(axi_slave_02_w_user), + .m00_w_last(axi_slave_02_w_last), + .m00_w_ready(axi_slave_02_w_ready), + .m00_r_data(axi_slave_02_r_data), + .m00_r_resp(axi_slave_02_r_resp), + .m00_r_last(axi_slave_02_r_last), + .m00_r_id(axi_slave_02_r_id), + .m00_r_user(axi_slave_02_r_user), + .m00_r_ready(axi_slave_02_r_ready), + .m00_r_valid(axi_slave_02_r_valid), + .m00_b_resp(axi_slave_02_b_resp), + .m00_b_id(axi_slave_02_b_id), + .m00_b_user(axi_slave_02_b_user), + .m00_b_ready(axi_slave_02_b_ready), + .m00_b_valid(axi_slave_02_b_valid) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_regs_top.v b/verilog/rtl/ips/axi/axi_node/axi_regs_top.v new file mode 100644 index 0000000..2462f5f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_regs_top.v
@@ -0,0 +1,260 @@ +module axi_regs_top +#( + parameter C_S_AXI_ADDR_WIDTH = 32, + parameter C_S_AXI_DATA_WIDTH = 32, + + parameter N_REGION_MAX = 4, + parameter N_MASTER_PORT = 16, + parameter N_SLAVE_PORT = 16 +) +( + s_axi_aclk, + s_axi_aresetn, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bready, + s_axi_bresp, + s_axi_bvalid, + s_axi_rdata, + s_axi_rvalid, + s_axi_rready, + s_axi_rresp, + init_START_ADDR_i, + init_END_ADDR_i, + init_valid_rule_i, + init_connectivity_map_i, + START_ADDR_o, + END_ADDR_o, + valid_rule_o, + connectivity_map_o +); + //parameter C_S_AXI_ADDR_WIDTH = 32; + //parameter C_S_AXI_DATA_WIDTH = 32; + //parameter N_REGION_MAX = 4; + //parameter N_MASTER_PORT = 16; + //parameter N_SLAVE_PORT = 16; + input wire s_axi_aclk; + input wire s_axi_aresetn; + input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_awaddr; + input wire s_axi_awvalid; + output wire s_axi_awready; + input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_araddr; + input wire s_axi_arvalid; + output wire s_axi_arready; + input wire [C_S_AXI_DATA_WIDTH - 1:0] s_axi_wdata; + input wire [(C_S_AXI_DATA_WIDTH / 8) - 1:0] s_axi_wstrb; + input wire s_axi_wvalid; + output wire s_axi_wready; + input wire s_axi_bready; + output wire [1:0] s_axi_bresp; + output wire s_axi_bvalid; + output wire [C_S_AXI_DATA_WIDTH - 1:0] s_axi_rdata; + output wire s_axi_rvalid; + input wire s_axi_rready; + output wire [1:0] s_axi_rresp; + input wire [((N_REGION_MAX * N_MASTER_PORT) * C_S_AXI_DATA_WIDTH) - 1:0] init_START_ADDR_i; + input wire [((N_REGION_MAX * N_MASTER_PORT) * C_S_AXI_DATA_WIDTH) - 1:0] init_END_ADDR_i; + input wire [(N_REGION_MAX * N_MASTER_PORT) - 1:0] init_valid_rule_i; + input wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] init_connectivity_map_i; + output wire [((N_REGION_MAX * N_MASTER_PORT) * C_S_AXI_DATA_WIDTH) - 1:0] START_ADDR_o; + output wire [((N_REGION_MAX * N_MASTER_PORT) * C_S_AXI_DATA_WIDTH) - 1:0] END_ADDR_o; + output wire [(N_REGION_MAX * N_MASTER_PORT) - 1:0] valid_rule_o; + output wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] connectivity_map_o; + localparam NUM_REGS = ((N_MASTER_PORT * 4) * N_REGION_MAX) + N_SLAVE_PORT; + wire [(N_SLAVE_PORT * C_S_AXI_DATA_WIDTH) - 1:0] temp_reg; + reg awaddr_done_reg; + reg awaddr_done_reg_dly; + reg wdata_done_reg; + reg wdata_done_reg_dly; + reg wresp_done_reg; + reg wresp_running_reg; + reg araddr_done_reg; + reg rresp_done_reg; + reg rresp_running_reg; + reg awready; + reg wready; + reg bvalid; + reg arready; + reg rvalid; + reg [C_S_AXI_ADDR_WIDTH - 1:0] waddr_reg; + reg [C_S_AXI_DATA_WIDTH - 1:0] wdata_reg; + reg [3:0] wstrb_reg; + reg [C_S_AXI_ADDR_WIDTH - 1:0] raddr_reg; + reg [C_S_AXI_DATA_WIDTH - 1:0] data_out_reg; + wire write_en; + integer byte_index; + integer k; + integer y; + integer w; + genvar i; + genvar j; + wire wdata_done_rise; + wire awaddr_done_rise; + reg [((NUM_REGS * (C_S_AXI_DATA_WIDTH / 8)) * 8) - 1:0] cfg_reg; + reg [(N_SLAVE_PORT * C_S_AXI_DATA_WIDTH) - 1:0] init_connectivity_map_s; + assign write_en = (wdata_done_rise & awaddr_done_reg) | (awaddr_done_rise & wdata_done_reg); + assign wdata_done_rise = wdata_done_reg & ~wdata_done_reg_dly; + assign awaddr_done_rise = awaddr_done_reg & ~awaddr_done_reg_dly; + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (!s_axi_aresetn) begin + wdata_done_reg_dly <= 0; + awaddr_done_reg_dly <= 0; + end + else begin + wdata_done_reg_dly <= wdata_done_reg; + awaddr_done_reg_dly <= awaddr_done_reg; + end + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (!s_axi_aresetn) begin + awaddr_done_reg <= 0; + waddr_reg <= 0; + awready <= 1; + end + else if (awready && s_axi_awvalid) begin + awready <= 0; + awaddr_done_reg <= 1; + waddr_reg <= {2'b00, s_axi_awaddr[31:2]}; + end + else if (awaddr_done_reg && wresp_done_reg) begin + awready <= 1; + awaddr_done_reg <= 0; + end + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (!s_axi_aresetn) begin + wdata_done_reg <= 0; + wready <= 1; + wdata_reg <= 0; + wstrb_reg <= 0; + end + else if (wready && s_axi_wvalid) begin + wready <= 0; + wdata_done_reg <= 1; + wdata_reg <= s_axi_wdata; + wstrb_reg <= s_axi_wstrb; + end + else if (wdata_done_reg && wresp_done_reg) begin + wready <= 1; + wdata_done_reg <= 0; + end + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (!s_axi_aresetn) begin + bvalid <= 0; + wresp_done_reg <= 0; + wresp_running_reg <= 0; + end + else if ((awaddr_done_reg && wdata_done_reg) && !wresp_done_reg) begin + if (!wresp_running_reg) begin + bvalid <= 1; + wresp_running_reg <= 1; + end + else if (s_axi_bready) begin + bvalid <= 0; + wresp_done_reg <= 1; + wresp_running_reg <= 0; + end + end + else begin + bvalid <= 0; + wresp_done_reg <= 0; + wresp_running_reg <= 0; + end + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (!s_axi_aresetn) begin + araddr_done_reg <= 0; + arready <= 1; + raddr_reg <= 0; + end + else if (arready && s_axi_arvalid) begin + arready <= 0; + araddr_done_reg <= 1; + raddr_reg <= s_axi_araddr; + end + else if (araddr_done_reg && rresp_done_reg) begin + arready <= 1; + araddr_done_reg <= 0; + end + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (!s_axi_aresetn) begin + rresp_done_reg <= 0; + rvalid <= 0; + rresp_running_reg <= 0; + end + else if (araddr_done_reg && !rresp_done_reg) begin + if (!rresp_running_reg) begin + rvalid <= 1; + rresp_running_reg <= 1; + end + else if (s_axi_rready) begin + rvalid <= 0; + rresp_done_reg <= 1; + rresp_running_reg <= 0; + end + end + else begin + rvalid <= 0; + rresp_done_reg <= 0; + rresp_running_reg <= 0; + end + generate + if (N_MASTER_PORT < 32) begin : genblk1 + always @(*) + for (w = 0; w < N_SLAVE_PORT; w = w + 1) + begin + init_connectivity_map_s[(w * C_S_AXI_DATA_WIDTH) + (N_MASTER_PORT - 1)-:N_MASTER_PORT] = init_connectivity_map_i[w * N_MASTER_PORT+:N_MASTER_PORT]; + init_connectivity_map_s[(w * C_S_AXI_DATA_WIDTH) + ((C_S_AXI_DATA_WIDTH - 1) >= N_MASTER_PORT ? C_S_AXI_DATA_WIDTH - 1 : ((C_S_AXI_DATA_WIDTH - 1) + ((C_S_AXI_DATA_WIDTH - 1) >= N_MASTER_PORT ? ((C_S_AXI_DATA_WIDTH - 1) - N_MASTER_PORT) + 1 : (N_MASTER_PORT - (C_S_AXI_DATA_WIDTH - 1)) + 1)) - 1)-:((C_S_AXI_DATA_WIDTH - 1) >= N_MASTER_PORT ? ((C_S_AXI_DATA_WIDTH - 1) - N_MASTER_PORT) + 1 : (N_MASTER_PORT - (C_S_AXI_DATA_WIDTH - 1)) + 1)] = 1'sb0; + end + end + else begin : genblk1 + always @(*) + for (w = 0; w < N_SLAVE_PORT; w = w + 1) + init_connectivity_map_s[w * C_S_AXI_DATA_WIDTH+:C_S_AXI_DATA_WIDTH] = init_connectivity_map_i[w * N_MASTER_PORT+:N_MASTER_PORT]; + end + endgenerate + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (s_axi_aresetn == 1'b0) begin + for (y = 0; y < N_REGION_MAX; y = y + 1) + for (k = 0; k < N_MASTER_PORT; k = k + 1) + begin + cfg_reg[8 * (((y * 4) + ((k * 4) * N_REGION_MAX)) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)] <= init_START_ADDR_i[((y * N_MASTER_PORT) + k) * C_S_AXI_DATA_WIDTH+:C_S_AXI_DATA_WIDTH]; + cfg_reg[8 * ((((y * 4) + ((k * 4) * N_REGION_MAX)) + 1) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)] <= init_END_ADDR_i[((y * N_MASTER_PORT) + k) * C_S_AXI_DATA_WIDTH+:C_S_AXI_DATA_WIDTH]; + cfg_reg[8 * ((((y * 4) + ((k * 4) * N_REGION_MAX)) + 2) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)] <= {{C_S_AXI_DATA_WIDTH - 1 {1'b0}}, init_valid_rule_i[(y * N_MASTER_PORT) + k]}; + cfg_reg[8 * ((((y * 4) + ((k * 4) * N_REGION_MAX)) + 3) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)] <= 32'hdeadbeef; + end + for (y = 0; y < N_SLAVE_PORT; y = y + 1) + cfg_reg[8 * ((((N_MASTER_PORT * 4) * N_REGION_MAX) + y) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)] <= init_connectivity_map_s[y * C_S_AXI_DATA_WIDTH+:C_S_AXI_DATA_WIDTH]; + end + else if (write_en) + for (byte_index = 0; byte_index <= ((C_S_AXI_DATA_WIDTH / 8) - 1); byte_index = byte_index + 1) + if (wstrb_reg[byte_index] == 1) + cfg_reg[((waddr_reg[7:0] * (C_S_AXI_DATA_WIDTH / 8)) + byte_index) * 8+:8] <= wdata_reg[byte_index * 8+:8]; + generate + for (i = 0; i < N_REGION_MAX; i = i + 1) begin : genblk2 + for (j = 0; j < N_MASTER_PORT; j = j + 1) begin : genblk1 + assign START_ADDR_o[((i * N_MASTER_PORT) + j) * C_S_AXI_DATA_WIDTH+:C_S_AXI_DATA_WIDTH] = cfg_reg[8 * (((i * 4) + ((j * 4) * N_REGION_MAX)) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)]; + assign END_ADDR_o[((i * N_MASTER_PORT) + j) * C_S_AXI_DATA_WIDTH+:C_S_AXI_DATA_WIDTH] = cfg_reg[8 * ((((i * 4) + ((j * 4) * N_REGION_MAX)) + 1) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)]; + assign valid_rule_o[(i * N_MASTER_PORT) + j] = cfg_reg[((((i * 4) + ((j * 4) * N_REGION_MAX)) + 2) * (C_S_AXI_DATA_WIDTH / 8)) * 8]; + end + end + for (i = 0; i < N_SLAVE_PORT; i = i + 1) begin : genblk3 + assign temp_reg[i * C_S_AXI_DATA_WIDTH+:C_S_AXI_DATA_WIDTH] = cfg_reg[8 * ((((N_MASTER_PORT * 4) * N_REGION_MAX) + i) * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)]; + assign connectivity_map_o[i * N_MASTER_PORT+:N_MASTER_PORT] = temp_reg[(i * C_S_AXI_DATA_WIDTH) + (N_MASTER_PORT - 1)-:N_MASTER_PORT]; + end + endgenerate + always @(*) data_out_reg = cfg_reg[8 * (raddr_reg[7:0] * (C_S_AXI_DATA_WIDTH / 8))+:8 * (C_S_AXI_DATA_WIDTH / 8)]; + assign s_axi_awready = awready; + assign s_axi_wready = wready; + assign s_axi_bresp = 2'b00; + assign s_axi_bvalid = bvalid; + assign s_axi_arready = arready; + assign s_axi_rresp = 2'b00; + assign s_axi_rvalid = rvalid; + assign s_axi_rdata = data_out_reg; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_request_block.v b/verilog/rtl/ips/axi/axi_node/axi_request_block.v new file mode 100644 index 0000000..e7db76f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_request_block.v
@@ -0,0 +1,304 @@ +module axi_request_block +#( + parameter AXI_ADDRESS_W = 32, + parameter AXI_DATA_W = 64, + parameter AXI_NUMBYTES = AXI_DATA_W/8, + parameter AXI_USER_W = 6, + + parameter N_INIT_PORT = 5, + parameter N_TARG_PORT = 8, + parameter FIFO_DW_DEPTH = 8, + + parameter AXI_ID_IN = 16, + + parameter LOG_N_TARG = $clog2(N_TARG_PORT), + parameter AXI_ID_OUT = AXI_ID_IN + LOG_N_TARG +) +( + clk, + rst_n, + test_en_i, + awid_i, + awaddr_i, + awlen_i, + awsize_i, + awburst_i, + awlock_i, + awcache_i, + awprot_i, + awregion_i, + awuser_i, + awqos_i, + awvalid_i, + awready_o, + wdata_i, + wstrb_i, + wlast_i, + wuser_i, + wvalid_i, + wready_o, + arid_i, + araddr_i, + arlen_i, + arsize_i, + arburst_i, + arlock_i, + arcache_i, + arprot_i, + arregion_i, + aruser_i, + arqos_i, + arvalid_i, + arready_o, + bid_i, + bvalid_i, + bready_o, + bvalid_o, + bready_i, + rid_i, + rvalid_i, + rready_o, + rvalid_o, + rready_i, + awid_o, + awaddr_o, + awlen_o, + awsize_o, + awburst_o, + awlock_o, + awcache_o, + awprot_o, + awregion_o, + awuser_o, + awqos_o, + awvalid_o, + awready_i, + wdata_o, + wstrb_o, + wlast_o, + wuser_o, + wvalid_o, + wready_i, + arid_o, + araddr_o, + arlen_o, + arsize_o, + arburst_o, + arlock_o, + arcache_o, + arprot_o, + arregion_o, + aruser_o, + arqos_o, + arvalid_o, + arready_i +); + //parameter AXI_ADDRESS_W = 32; + //parameter AXI_DATA_W = 64; + //parameter AXI_NUMBYTES = AXI_DATA_W / 8; + //parameter AXI_USER_W = 6; + //parameter N_INIT_PORT = 5; + //parameter N_TARG_PORT = 8; + //parameter FIFO_DW_DEPTH = 8; + //parameter AXI_ID_IN = 16; + //parameter LOG_N_TARG = $clog2(N_TARG_PORT); + //parameter AXI_ID_OUT = AXI_ID_IN + LOG_N_TARG; + input wire clk; + input wire rst_n; + input wire test_en_i; + input wire [(N_TARG_PORT * AXI_ID_IN) - 1:0] awid_i; + input wire [(N_TARG_PORT * AXI_ADDRESS_W) - 1:0] awaddr_i; + input wire [(N_TARG_PORT * 8) - 1:0] awlen_i; + input wire [(N_TARG_PORT * 3) - 1:0] awsize_i; + input wire [(N_TARG_PORT * 2) - 1:0] awburst_i; + input wire [N_TARG_PORT - 1:0] awlock_i; + input wire [(N_TARG_PORT * 4) - 1:0] awcache_i; + input wire [(N_TARG_PORT * 3) - 1:0] awprot_i; + input wire [(N_TARG_PORT * 4) - 1:0] awregion_i; + input wire [(N_TARG_PORT * AXI_USER_W) - 1:0] awuser_i; + input wire [(N_TARG_PORT * 4) - 1:0] awqos_i; + input wire [N_TARG_PORT - 1:0] awvalid_i; + output wire [N_TARG_PORT - 1:0] awready_o; + input wire [(N_TARG_PORT * AXI_DATA_W) - 1:0] wdata_i; + input wire [(N_TARG_PORT * AXI_NUMBYTES) - 1:0] wstrb_i; + input wire [N_TARG_PORT - 1:0] wlast_i; + input wire [(N_TARG_PORT * AXI_USER_W) - 1:0] wuser_i; + input wire [N_TARG_PORT - 1:0] wvalid_i; + output wire [N_TARG_PORT - 1:0] wready_o; + input wire [(N_TARG_PORT * AXI_ID_IN) - 1:0] arid_i; + input wire [(N_TARG_PORT * AXI_ADDRESS_W) - 1:0] araddr_i; + input wire [(N_TARG_PORT * 8) - 1:0] arlen_i; + input wire [(N_TARG_PORT * 3) - 1:0] arsize_i; + input wire [(N_TARG_PORT * 2) - 1:0] arburst_i; + input wire [N_TARG_PORT - 1:0] arlock_i; + input wire [(N_TARG_PORT * 4) - 1:0] arcache_i; + input wire [(N_TARG_PORT * 3) - 1:0] arprot_i; + input wire [(N_TARG_PORT * 4) - 1:0] arregion_i; + input wire [(N_TARG_PORT * AXI_USER_W) - 1:0] aruser_i; + input wire [(N_TARG_PORT * 4) - 1:0] arqos_i; + input wire [N_TARG_PORT - 1:0] arvalid_i; + output wire [N_TARG_PORT - 1:0] arready_o; + input wire [AXI_ID_OUT - 1:0] bid_i; + input wire bvalid_i; + output wire bready_o; + output wire [N_TARG_PORT - 1:0] bvalid_o; + input wire [N_TARG_PORT - 1:0] bready_i; + input wire [AXI_ID_OUT - 1:0] rid_i; + input wire rvalid_i; + output wire rready_o; + output wire [N_TARG_PORT - 1:0] rvalid_o; + input wire [N_TARG_PORT - 1:0] rready_i; + output wire [AXI_ID_OUT - 1:0] awid_o; + output wire [AXI_ADDRESS_W - 1:0] awaddr_o; + output wire [7:0] awlen_o; + output wire [2:0] awsize_o; + output wire [1:0] awburst_o; + output wire awlock_o; + output wire [3:0] awcache_o; + output wire [2:0] awprot_o; + output wire [3:0] awregion_o; + output wire [AXI_USER_W - 1:0] awuser_o; + output wire [3:0] awqos_o; + output wire awvalid_o; + input wire awready_i; + output wire [AXI_DATA_W - 1:0] wdata_o; + output wire [AXI_NUMBYTES - 1:0] wstrb_o; + output wire wlast_o; + output wire [AXI_USER_W - 1:0] wuser_o; + output wire wvalid_o; + input wire wready_i; + output wire [AXI_ID_OUT - 1:0] arid_o; + output wire [AXI_ADDRESS_W - 1:0] araddr_o; + output wire [7:0] arlen_o; + output wire [2:0] arsize_o; + output wire [1:0] arburst_o; + output wire arlock_o; + output wire [3:0] arcache_o; + output wire [2:0] arprot_o; + output wire [3:0] arregion_o; + output wire [AXI_USER_W - 1:0] aruser_o; + output wire [3:0] arqos_o; + output wire arvalid_o; + input wire arready_i; + wire push_ID; + wire [(LOG_N_TARG + N_TARG_PORT) - 1:0] ID; + wire grant_FIFO_ID; + axi_AR_allocator #( + .AXI_ADDRESS_W(AXI_ADDRESS_W), + .AXI_USER_W(AXI_USER_W), + .N_TARG_PORT(N_TARG_PORT), + .AXI_ID_IN(AXI_ID_IN) + ) AR_ALLOCATOR( + .clk(clk), + .rst_n(rst_n), + .arid_i(arid_i), + .araddr_i(araddr_i), + .arlen_i(arlen_i), + .arsize_i(arsize_i), + .arburst_i(arburst_i), + .arlock_i(arlock_i), + .arcache_i(arcache_i), + .arprot_i(arprot_i), + .arregion_i(arregion_i), + .aruser_i(aruser_i), + .arqos_i(arqos_i), + .arvalid_i(arvalid_i), + .arready_o(arready_o), + .arid_o(arid_o), + .araddr_o(araddr_o), + .arlen_o(arlen_o), + .arsize_o(arsize_o), + .arburst_o(arburst_o), + .arlock_o(arlock_o), + .arcache_o(arcache_o), + .arprot_o(arprot_o), + .arregion_o(arregion_o), + .aruser_o(aruser_o), + .arqos_o(arqos_o), + .arvalid_o(arvalid_o), + .arready_i(arready_i) + ); + axi_AW_allocator #( + .AXI_ADDRESS_W(AXI_ADDRESS_W), + .AXI_USER_W(AXI_USER_W), + .N_TARG_PORT(N_TARG_PORT), + .AXI_ID_IN(AXI_ID_IN) + ) AW_ALLOCATOR( + .clk(clk), + .rst_n(rst_n), + .awid_i(awid_i), + .awaddr_i(awaddr_i), + .awlen_i(awlen_i), + .awsize_i(awsize_i), + .awburst_i(awburst_i), + .awlock_i(awlock_i), + .awcache_i(awcache_i), + .awprot_i(awprot_i), + .awregion_i(awregion_i), + .awuser_i(awuser_i), + .awqos_i(awqos_i), + .awvalid_i(awvalid_i), + .awready_o(awready_o), + .awid_o(awid_o), + .awaddr_o(awaddr_o), + .awlen_o(awlen_o), + .awsize_o(awsize_o), + .awburst_o(awburst_o), + .awlock_o(awlock_o), + .awcache_o(awcache_o), + .awprot_o(awprot_o), + .awregion_o(awregion_o), + .awuser_o(awuser_o), + .awqos_o(awqos_o), + .awvalid_o(awvalid_o), + .awready_i(awready_i), + .push_ID_o(push_ID), + .ID_o(ID), + .grant_FIFO_ID_i(grant_FIFO_ID) + ); + axi_DW_allocator #( + .AXI_USER_W(AXI_USER_W), + .N_TARG_PORT(N_TARG_PORT), + .FIFO_DEPTH(FIFO_DW_DEPTH), + .AXI_DATA_W(AXI_DATA_W) + ) DW_ALLOC( + .clk(clk), + .rst_n(rst_n), + .test_en_i(test_en_i), + .wdata_i(wdata_i), + .wstrb_i(wstrb_i), + .wlast_i(wlast_i), + .wuser_i(wuser_i), + .wvalid_i(wvalid_i), + .wready_o(wready_o), + .wdata_o(wdata_o), + .wstrb_o(wstrb_o), + .wlast_o(wlast_o), + .wuser_o(wuser_o), + .wvalid_o(wvalid_o), + .wready_i(wready_i), + .push_ID_i(push_ID), + .ID_i(ID), + .grant_FIFO_ID_o(grant_FIFO_ID) + ); + axi_address_decoder_BW #( + .N_TARG_PORT(N_TARG_PORT), + .AXI_ID_IN(AXI_ID_IN) + ) BW_DECODER( + .bid_i(bid_i), + .bvalid_i(bvalid_i), + .bready_o(bready_o), + .bvalid_o(bvalid_o), + .bready_i(bready_i) + ); + axi_address_decoder_BR #( + .N_TARG_PORT(N_TARG_PORT), + .AXI_ID_IN(AXI_ID_IN) + ) BR_DECODER( + .rid_i(rid_i), + .rvalid_i(rvalid_i), + .rready_o(rready_o), + .rvalid_o(rvalid_o), + .rready_i(rready_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/axi_response_block.v b/verilog/rtl/ips/axi/axi_node/axi_response_block.v new file mode 100644 index 0000000..404dd34 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/axi_response_block.v
@@ -0,0 +1,275 @@ +module axi_response_block +#( + parameter AXI_ADDRESS_W = 32, + parameter AXI_DATA_W = 64, + parameter AXI_USER_W = 6, + + parameter N_INIT_PORT = 4, + parameter N_TARG_PORT = 8, + parameter FIFO_DEPTH_DW = 8, + + parameter AXI_ID_IN = 16, + parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT), + parameter N_REGION = 2 +) +( + clk, + rst_n, + test_en_i, + rid_i, + rdata_i, + rresp_i, + rlast_i, + ruser_i, + rvalid_i, + rready_o, + bid_i, + bresp_i, + buser_i, + bvalid_i, + bready_o, + rid_o, + rdata_o, + rresp_o, + rlast_o, + ruser_o, + rvalid_o, + rready_i, + bid_o, + bresp_o, + buser_o, + bvalid_o, + bready_i, + arvalid_i, + araddr_i, + arready_o, + arid_i, + arlen_i, + aruser_i, + arvalid_o, + arready_i, + awvalid_i, + awaddr_i, + awready_o, + awid_i, + awuser_i, + awvalid_o, + awready_i, + wvalid_i, + wlast_i, + wready_o, + wvalid_o, + wready_i, + START_ADDR_i, + END_ADDR_i, + enable_region_i, + connectivity_map_i +); + //parameter AXI_ADDRESS_W = 32; + //parameter AXI_DATA_W = 64; + //parameter AXI_USER_W = 6; + //parameter N_INIT_PORT = 4; + //parameter N_TARG_PORT = 8; + //parameter FIFO_DEPTH_DW = 8; + //parameter AXI_ID_IN = 16; + //parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT); + //parameter N_REGION = 2; + input wire clk; + input wire rst_n; + input wire test_en_i; + input wire [(N_INIT_PORT * AXI_ID_OUT) - 1:0] rid_i; + input wire [(N_INIT_PORT * AXI_DATA_W) - 1:0] rdata_i; + input wire [(N_INIT_PORT * 2) - 1:0] rresp_i; + input wire [N_INIT_PORT - 1:0] rlast_i; + input wire [(N_INIT_PORT * AXI_USER_W) - 1:0] ruser_i; + input wire [N_INIT_PORT - 1:0] rvalid_i; + output wire [N_INIT_PORT - 1:0] rready_o; + input wire [(N_INIT_PORT * AXI_ID_OUT) - 1:0] bid_i; + input wire [(N_INIT_PORT * 2) - 1:0] bresp_i; + input wire [(N_INIT_PORT * AXI_USER_W) - 1:0] buser_i; + input wire [N_INIT_PORT - 1:0] bvalid_i; + output wire [N_INIT_PORT - 1:0] bready_o; + output wire [AXI_ID_IN - 1:0] rid_o; + output wire [AXI_DATA_W - 1:0] rdata_o; + output wire [1:0] rresp_o; + output wire rlast_o; + output wire [AXI_USER_W - 1:0] ruser_o; + output wire rvalid_o; + input wire rready_i; + output wire [AXI_ID_IN - 1:0] bid_o; + output wire [1:0] bresp_o; + output wire [AXI_USER_W - 1:0] buser_o; + output wire bvalid_o; + input wire bready_i; + input wire arvalid_i; + input wire [AXI_ADDRESS_W - 1:0] araddr_i; + output wire arready_o; + input wire [AXI_ID_IN - 1:0] arid_i; + input wire [7:0] arlen_i; + input wire [AXI_USER_W - 1:0] aruser_i; + output wire [N_INIT_PORT - 1:0] arvalid_o; + input wire [N_INIT_PORT - 1:0] arready_i; + input wire awvalid_i; + input wire [AXI_ADDRESS_W - 1:0] awaddr_i; + output wire awready_o; + input wire [AXI_ID_IN - 1:0] awid_i; + input wire [AXI_USER_W - 1:0] awuser_i; + output wire [N_INIT_PORT - 1:0] awvalid_o; + input wire [N_INIT_PORT - 1:0] awready_i; + input wire wvalid_i; + input wire wlast_i; + output wire wready_o; + output wire [N_INIT_PORT - 1:0] wvalid_o; + input wire [N_INIT_PORT - 1:0] wready_i; + input wire [((N_REGION * N_INIT_PORT) * AXI_ADDRESS_W) - 1:0] START_ADDR_i; + input wire [((N_REGION * N_INIT_PORT) * AXI_ADDRESS_W) - 1:0] END_ADDR_i; + input wire [(N_REGION * N_INIT_PORT) - 1:0] enable_region_i; + input wire [N_INIT_PORT - 1:0] connectivity_map_i; + wire push_DEST_DW; + wire grant_FIFO_DEST_DW; + wire [N_INIT_PORT - 1:0] DEST_DW; + wire incr_ar_req; + wire full_counter_ar; + wire outstanding_trans_ar; + wire error_ar_req; + wire error_ar_gnt; + wire incr_aw_req; + wire full_counter_aw; + wire outstanding_trans_aw; + wire handle_error_aw; + wire wdata_error_completed; + wire sample_awdata_info; + wire sample_ardata_info; + wire error_aw_req; + wire error_aw_gnt; + axi_BW_allocator #( + .AXI_USER_W(AXI_USER_W), + .N_INIT_PORT(N_INIT_PORT), + .N_TARG_PORT(N_TARG_PORT), + .AXI_DATA_W(AXI_DATA_W), + .AXI_ID_IN(AXI_ID_IN) + ) BW_ALLOC( + .clk(clk), + .rst_n(rst_n), + .bid_i(bid_i), + .bresp_i(bresp_i), + .buser_i(buser_i), + .bvalid_i(bvalid_i), + .bready_o(bready_o), + .bid_o(bid_o), + .bresp_o(bresp_o), + .buser_o(buser_o), + .bvalid_o(bvalid_o), + .bready_i(bready_i), + .incr_req_i(incr_aw_req), + .full_counter_o(full_counter_aw), + .outstanding_trans_o(outstanding_trans_aw), + .sample_awdata_info_i(sample_awdata_info), + .error_req_i(error_aw_req), + .error_gnt_o(error_aw_gnt), + .error_user_i(awuser_i), + .error_id_i(awid_i) + ); + axi_BR_allocator #( + .AXI_USER_W(AXI_USER_W), + .N_INIT_PORT(N_INIT_PORT), + .N_TARG_PORT(N_TARG_PORT), + .AXI_DATA_W(AXI_DATA_W), + .AXI_ID_IN(AXI_ID_IN) + ) BR_ALLOC( + .clk(clk), + .rst_n(rst_n), + .rid_i(rid_i), + .rdata_i(rdata_i), + .rresp_i(rresp_i), + .rlast_i(rlast_i), + .ruser_i(ruser_i), + .rvalid_i(rvalid_i), + .rready_o(rready_o), + .rid_o(rid_o), + .rdata_o(rdata_o), + .rresp_o(rresp_o), + .rlast_o(rlast_o), + .ruser_o(ruser_o), + .rvalid_o(rvalid_o), + .rready_i(rready_i), + .incr_req_i(incr_ar_req), + .full_counter_o(full_counter_ar), + .outstanding_trans_o(outstanding_trans_ar), + .error_req_i(error_ar_req), + .error_gnt_o(error_ar_gnt), + .error_len_i(arlen_i), + .error_user_i(aruser_i), + .error_id_i(arid_i), + .sample_ardata_info_i(sample_ardata_info) + ); + axi_address_decoder_AR #( + .ADDR_WIDTH(AXI_ADDRESS_W), + .N_INIT_PORT(N_INIT_PORT), + .N_REGION(N_REGION) + ) AR_ADDR_DEC( + .clk(clk), + .rst_n(rst_n), + .arvalid_i(arvalid_i), + .araddr_i(araddr_i), + .arready_o(arready_o), + .arvalid_o(arvalid_o), + .arready_i(arready_i), + .START_ADDR_i(START_ADDR_i), + .END_ADDR_i(END_ADDR_i), + .enable_region_i(enable_region_i), + .connectivity_map_i(connectivity_map_i), + .incr_req_o(incr_ar_req), + .full_counter_i(full_counter_ar), + .outstanding_trans_i(outstanding_trans_ar), + .error_req_o(error_ar_req), + .error_gnt_i(error_ar_gnt), + .sample_ardata_info_o(sample_ardata_info) + ); + axi_address_decoder_AW #( + .ADDR_WIDTH(AXI_ADDRESS_W), + .N_INIT_PORT(N_INIT_PORT), + .N_REGION(N_REGION) + ) AW_ADDR_DEC( + .clk(clk), + .rst_n(rst_n), + .awvalid_i(awvalid_i), + .awaddr_i(awaddr_i), + .awready_o(awready_o), + .awvalid_o(awvalid_o), + .awready_i(awready_i), + .grant_FIFO_DEST_i(grant_FIFO_DEST_DW), + .DEST_o(DEST_DW), + .push_DEST_o(push_DEST_DW), + .START_ADDR_i(START_ADDR_i), + .END_ADDR_i(END_ADDR_i), + .enable_region_i(enable_region_i), + .connectivity_map_i(connectivity_map_i), + .incr_req_o(incr_aw_req), + .full_counter_i(full_counter_aw), + .outstanding_trans_i(outstanding_trans_aw), + .error_req_o(error_aw_req), + .error_gnt_i(error_aw_gnt), + .handle_error_o(handle_error_aw), + .wdata_error_completed_i(wdata_error_completed), + .sample_awdata_info_o(sample_awdata_info) + ); + axi_address_decoder_DW #( + .N_INIT_PORT(N_INIT_PORT), + .FIFO_DEPTH(FIFO_DEPTH_DW) + ) DW_ADDR_DEC( + .clk(clk), + .rst_n(rst_n), + .test_en_i(test_en_i), + .wvalid_i(wvalid_i), + .wlast_i(wlast_i), + .wready_o(wready_o), + .wvalid_o(wvalid_o), + .wready_i(wready_i), + .grant_FIFO_DEST_o(grant_FIFO_DEST_DW), + .DEST_i(DEST_DW), + .push_DEST_i(push_DEST_DW), + .handle_error_i(handle_error_aw), + .wdata_error_completed_o(wdata_error_completed) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_node/defines.v b/verilog/rtl/ips/axi/axi_node/defines.v new file mode 100644 index 0000000..9c38d7f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_node/defines.v
@@ -0,0 +1,51 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// ============================================================================= // +// Company: Multitherman Laboratory @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 18/11/2014 // +// Design Name: AXI 4 INTERCONNECT // +// Module Name: none // +// Project Name: PULP // +// Language: SystemVerilog // +// // +// Description: axi_node defines and macros // +// // +// // +// Revision: // +// Revision v0.1 - 18/11/2014 : File Created // +// // +// // +// // +// // +// // +// // +// ============================================================================= // + + +`define OKAY 2'b00 +`define EXOKAY 2'b01 +`define SLVERR 2'b10 +`define DECERR 2'b11 + +//`define USE_CFG_BLOCK +//`define USE_APB + +
diff --git a/verilog/rtl/ips/axi/axi_slice/axi_ar_buffer.v b/verilog/rtl/ips/axi/axi_slice/axi_ar_buffer.v new file mode 100644 index 0000000..62bf6f5 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice/axi_ar_buffer.v
@@ -0,0 +1,90 @@ +module axi_ar_buffer +#( + parameter ID_WIDTH = 4, + parameter ADDR_WIDTH = 32, + parameter USER_WIDTH = 6, + parameter BUFFER_DEPTH = 2 +) +( + clk_i, + rst_ni, + test_en_i, + slave_valid_i, + slave_addr_i, + slave_prot_i, + slave_region_i, + slave_len_i, + slave_size_i, + slave_burst_i, + slave_lock_i, + slave_cache_i, + slave_qos_i, + slave_id_i, + slave_user_i, + slave_ready_o, + master_valid_o, + master_addr_o, + master_prot_o, + master_region_o, + master_len_o, + master_size_o, + master_burst_o, + master_lock_o, + master_cache_o, + master_qos_o, + master_id_o, + master_user_o, + master_ready_i +); + //parameter ID_WIDTH = 4; + //parameter ADDR_WIDTH = 32; + //parameter USER_WIDTH = 6; + //parameter BUFFER_DEPTH = 2; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire slave_valid_i; + input wire [ADDR_WIDTH - 1:0] slave_addr_i; + input wire [2:0] slave_prot_i; + input wire [3:0] slave_region_i; + input wire [7:0] slave_len_i; + input wire [2:0] slave_size_i; + input wire [1:0] slave_burst_i; + input wire slave_lock_i; + input wire [3:0] slave_cache_i; + input wire [3:0] slave_qos_i; + input wire [ID_WIDTH - 1:0] slave_id_i; + input wire [USER_WIDTH - 1:0] slave_user_i; + output wire slave_ready_o; + output wire master_valid_o; + output wire [ADDR_WIDTH - 1:0] master_addr_o; + output wire [2:0] master_prot_o; + output wire [3:0] master_region_o; + output wire [7:0] master_len_o; + output wire [2:0] master_size_o; + output wire [1:0] master_burst_o; + output wire master_lock_o; + output wire [3:0] master_cache_o; + output wire [3:0] master_qos_o; + output wire [ID_WIDTH - 1:0] master_id_o; + output wire [USER_WIDTH - 1:0] master_user_o; + input wire master_ready_i; + wire [(((29 + ADDR_WIDTH) + USER_WIDTH) + ID_WIDTH) - 1:0] s_data_in; + wire [(((29 + ADDR_WIDTH) + USER_WIDTH) + ID_WIDTH) - 1:0] s_data_out; + assign s_data_in = {slave_cache_i, slave_prot_i, slave_lock_i, slave_burst_i, slave_size_i, slave_len_i, slave_qos_i, slave_region_i, slave_addr_i, slave_user_i, slave_id_i}; + assign {master_cache_o, master_prot_o, master_lock_o, master_burst_o, master_size_o, master_len_o, master_qos_o, master_region_o, master_addr_o, master_user_o, master_id_o} = s_data_out; + generic_fifo #( + .DATA_WIDTH(((29 + ADDR_WIDTH) + USER_WIDTH) + ID_WIDTH), + .DATA_DEPTH(BUFFER_DEPTH) + ) buffer_i( + .clk(clk_i), + .rst_n(rst_ni), + .data_i(s_data_in), + .valid_i(slave_valid_i), + .grant_o(slave_ready_o), + .data_o(s_data_out), + .valid_o(master_valid_o), + .grant_i(master_ready_i), + .test_mode_i(test_en_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice/axi_aw_buffer.v b/verilog/rtl/ips/axi/axi_slice/axi_aw_buffer.v new file mode 100644 index 0000000..a15b3ba --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice/axi_aw_buffer.v
@@ -0,0 +1,90 @@ +module axi_aw_buffer +#( + parameter ID_WIDTH = 4, + parameter ADDR_WIDTH = 32, + parameter USER_WIDTH = 6, + parameter BUFFER_DEPTH = 2 +) +( + clk_i, + rst_ni, + test_en_i, + slave_valid_i, + slave_addr_i, + slave_prot_i, + slave_region_i, + slave_len_i, + slave_size_i, + slave_burst_i, + slave_lock_i, + slave_cache_i, + slave_qos_i, + slave_id_i, + slave_user_i, + slave_ready_o, + master_valid_o, + master_addr_o, + master_prot_o, + master_region_o, + master_len_o, + master_size_o, + master_burst_o, + master_lock_o, + master_cache_o, + master_qos_o, + master_id_o, + master_user_o, + master_ready_i +); + //parameter ID_WIDTH = 4; + //parameter ADDR_WIDTH = 32; + //parameter USER_WIDTH = 6; + //parameter BUFFER_DEPTH = 2; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire slave_valid_i; + input wire [ADDR_WIDTH - 1:0] slave_addr_i; + input wire [2:0] slave_prot_i; + input wire [3:0] slave_region_i; + input wire [7:0] slave_len_i; + input wire [2:0] slave_size_i; + input wire [1:0] slave_burst_i; + input wire slave_lock_i; + input wire [3:0] slave_cache_i; + input wire [3:0] slave_qos_i; + input wire [ID_WIDTH - 1:0] slave_id_i; + input wire [USER_WIDTH - 1:0] slave_user_i; + output wire slave_ready_o; + output wire master_valid_o; + output wire [ADDR_WIDTH - 1:0] master_addr_o; + output wire [2:0] master_prot_o; + output wire [3:0] master_region_o; + output wire [7:0] master_len_o; + output wire [2:0] master_size_o; + output wire [1:0] master_burst_o; + output wire master_lock_o; + output wire [3:0] master_cache_o; + output wire [3:0] master_qos_o; + output wire [ID_WIDTH - 1:0] master_id_o; + output wire [USER_WIDTH - 1:0] master_user_o; + input wire master_ready_i; + wire [(((29 + ADDR_WIDTH) + USER_WIDTH) + ID_WIDTH) - 1:0] s_data_in; + wire [(((29 + ADDR_WIDTH) + USER_WIDTH) + ID_WIDTH) - 1:0] s_data_out; + assign s_data_in = {slave_cache_i, slave_prot_i, slave_lock_i, slave_burst_i, slave_size_i, slave_len_i, slave_qos_i, slave_region_i, slave_addr_i, slave_user_i, slave_id_i}; + assign {master_cache_o, master_prot_o, master_lock_o, master_burst_o, master_size_o, master_len_o, master_qos_o, master_region_o, master_addr_o, master_user_o, master_id_o} = s_data_out; + generic_fifo #( + .DATA_WIDTH(((29 + ADDR_WIDTH) + USER_WIDTH) + ID_WIDTH), + .DATA_DEPTH(BUFFER_DEPTH) + ) buffer_i( + .clk(clk_i), + .rst_n(rst_ni), + .data_i(s_data_in), + .valid_i(slave_valid_i), + .grant_o(slave_ready_o), + .data_o(s_data_out), + .valid_o(master_valid_o), + .grant_i(master_ready_i), + .test_mode_i(test_en_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice/axi_b_buffer.v b/verilog/rtl/ips/axi/axi_slice/axi_b_buffer.v new file mode 100644 index 0000000..398045f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice/axi_b_buffer.v
@@ -0,0 +1,56 @@ +module axi_b_buffer +#( + parameter ID_WIDTH = 4, + parameter USER_WIDTH = 6, + parameter BUFFER_DEPTH = 8 +) +( + clk_i, + rst_ni, + test_en_i, + slave_valid_i, + slave_resp_i, + slave_id_i, + slave_user_i, + slave_ready_o, + master_valid_o, + master_resp_o, + master_id_o, + master_user_o, + master_ready_i +); + //parameter ID_WIDTH = 4; + //parameter USER_WIDTH = 6; + //parameter BUFFER_DEPTH = 8; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire slave_valid_i; + input wire [1:0] slave_resp_i; + input wire [ID_WIDTH - 1:0] slave_id_i; + input wire [USER_WIDTH - 1:0] slave_user_i; + output wire slave_ready_o; + output wire master_valid_o; + output wire [1:0] master_resp_o; + output wire [ID_WIDTH - 1:0] master_id_o; + output wire [USER_WIDTH - 1:0] master_user_o; + input wire master_ready_i; + wire [((2 + USER_WIDTH) + ID_WIDTH) - 1:0] s_data_in; + wire [((2 + USER_WIDTH) + ID_WIDTH) - 1:0] s_data_out; + assign s_data_in = {slave_id_i, slave_user_i, slave_resp_i}; + assign {master_id_o, master_user_o, master_resp_o} = s_data_out; + generic_fifo #( + .DATA_WIDTH((2 + USER_WIDTH) + ID_WIDTH), + .DATA_DEPTH(BUFFER_DEPTH) + ) buffer_i( + .clk(clk_i), + .rst_n(rst_ni), + .data_i(s_data_in), + .valid_i(slave_valid_i), + .grant_o(slave_ready_o), + .data_o(s_data_out), + .valid_o(master_valid_o), + .grant_i(master_ready_i), + .test_mode_i(test_en_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice/axi_buffer.v b/verilog/rtl/ips/axi/axi_slice/axi_buffer.v new file mode 100644 index 0000000..cd8bd73 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice/axi_buffer.v
@@ -0,0 +1,72 @@ +module axi_buffer +#( + parameter DATA_WIDTH = 32, + parameter BUFFER_DEPTH = 2, + parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH) +) +( + clk_i, + rst_ni, + data_o, + valid_o, + ready_i, + valid_i, + data_i, + ready_o +); + //parameter DATA_WIDTH = 32; + //parameter BUFFER_DEPTH = 2; + //parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH); + input wire clk_i; + input wire rst_ni; + output wire [DATA_WIDTH - 1:0] data_o; + output wire valid_o; + input wire ready_i; + input wire valid_i; + input wire [DATA_WIDTH - 1:0] data_i; + output wire ready_o; + reg [LOG_BUFFER_DEPTH - 1:0] pointer_in; + reg [LOG_BUFFER_DEPTH - 1:0] pointer_out; + reg [LOG_BUFFER_DEPTH:0] elements; + reg [DATA_WIDTH - 1:0] buffer [BUFFER_DEPTH - 1:0]; + wire full; + reg [31:0] loop1; + assign full = elements == BUFFER_DEPTH; + always @(posedge clk_i or negedge rst_ni) begin : elements_sequential + if (rst_ni == 1'b0) + elements <= 0; + else if ((ready_i && valid_o) && (!valid_i || full)) + elements <= elements - 1; + else if (((!valid_o || !ready_i) && valid_i) && !full) + elements <= elements + 1; + end + always @(posedge clk_i or negedge rst_ni) begin : buffers_sequential + if (rst_ni == 1'b0) begin + for (loop1 = 0; loop1 < BUFFER_DEPTH; loop1 = loop1 + 1) + buffer[loop1] <= 0; + end + else if (valid_i && !full) + buffer[pointer_in] <= data_i; + end + always @(posedge clk_i or negedge rst_ni) begin : sequential + if (rst_ni == 1'b0) begin + pointer_out <= 0; + pointer_in <= 0; + end + else begin + if (valid_i && !full) + if (pointer_in == $unsigned(BUFFER_DEPTH - 1)) + pointer_in <= 0; + else + pointer_in <= pointer_in + 1; + if (ready_i && valid_o) + if (pointer_out == $unsigned(BUFFER_DEPTH - 1)) + pointer_out <= 0; + else + pointer_out <= pointer_out + 1; + end + end + assign data_o = buffer[pointer_out]; + assign valid_o = elements != 0; + assign ready_o = ~full; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice/axi_r_buffer.v b/verilog/rtl/ips/axi/axi_slice/axi_r_buffer.v new file mode 100644 index 0000000..5224a8b --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice/axi_r_buffer.v
@@ -0,0 +1,68 @@ +module axi_r_buffer +#( + parameter ID_WIDTH = 4, + parameter DATA_WIDTH = 64, + parameter USER_WIDTH = 6, + parameter BUFFER_DEPTH = 8, + parameter STRB_WIDTH = DATA_WIDTH/8 // DO NOT OVERRIDE +) +( + clk_i, + rst_ni, + test_en_i, + slave_valid_i, + slave_data_i, + slave_resp_i, + slave_user_i, + slave_id_i, + slave_last_i, + slave_ready_o, + master_valid_o, + master_data_o, + master_resp_o, + master_user_o, + master_id_o, + master_last_o, + master_ready_i +); + //parameter ID_WIDTH = 4; + //parameter DATA_WIDTH = 64; + //parameter USER_WIDTH = 6; + //parameter BUFFER_DEPTH = 8; + //parameter STRB_WIDTH = DATA_WIDTH / 8; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire slave_valid_i; + input wire [DATA_WIDTH - 1:0] slave_data_i; + input wire [1:0] slave_resp_i; + input wire [USER_WIDTH - 1:0] slave_user_i; + input wire [ID_WIDTH - 1:0] slave_id_i; + input wire slave_last_i; + output wire slave_ready_o; + output wire master_valid_o; + output wire [DATA_WIDTH - 1:0] master_data_o; + output wire [1:0] master_resp_o; + output wire [USER_WIDTH - 1:0] master_user_o; + output wire [ID_WIDTH - 1:0] master_id_o; + output wire master_last_o; + input wire master_ready_i; + wire [((2 + DATA_WIDTH) + USER_WIDTH) + ID_WIDTH:0] s_data_in; + wire [((2 + DATA_WIDTH) + USER_WIDTH) + ID_WIDTH:0] s_data_out; + assign s_data_in = {slave_id_i, slave_user_i, slave_data_i, slave_resp_i, slave_last_i}; + assign {master_id_o, master_user_o, master_data_o, master_resp_o, master_last_o} = s_data_out; + generic_fifo #( + .DATA_WIDTH(((3 + DATA_WIDTH) + USER_WIDTH) + ID_WIDTH), + .DATA_DEPTH(BUFFER_DEPTH) + ) buffer_i( + .clk(clk_i), + .rst_n(rst_ni), + .data_i(s_data_in), + .valid_i(slave_valid_i), + .grant_o(slave_ready_o), + .data_o(s_data_out), + .valid_o(master_valid_o), + .grant_i(master_ready_i), + .test_mode_i(test_en_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice/axi_slice.v b/verilog/rtl/ips/axi/axi_slice/axi_slice.v new file mode 100644 index 0000000..3672c97 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice/axi_slice.v
@@ -0,0 +1,336 @@ +module axi_slice +#( + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3, + parameter SLICE_DEPTH = 2, + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 +) +( + clk_i, + rst_ni, + test_en_i, + axi_slave_aw_valid_i, + axi_slave_aw_addr_i, + axi_slave_aw_prot_i, + axi_slave_aw_region_i, + axi_slave_aw_len_i, + axi_slave_aw_size_i, + axi_slave_aw_burst_i, + axi_slave_aw_lock_i, + axi_slave_aw_cache_i, + axi_slave_aw_qos_i, + axi_slave_aw_id_i, + axi_slave_aw_user_i, + axi_slave_aw_ready_o, + axi_slave_ar_valid_i, + axi_slave_ar_addr_i, + axi_slave_ar_prot_i, + axi_slave_ar_region_i, + axi_slave_ar_len_i, + axi_slave_ar_size_i, + axi_slave_ar_burst_i, + axi_slave_ar_lock_i, + axi_slave_ar_cache_i, + axi_slave_ar_qos_i, + axi_slave_ar_id_i, + axi_slave_ar_user_i, + axi_slave_ar_ready_o, + axi_slave_w_valid_i, + axi_slave_w_data_i, + axi_slave_w_strb_i, + axi_slave_w_user_i, + axi_slave_w_last_i, + axi_slave_w_ready_o, + axi_slave_r_valid_o, + axi_slave_r_data_o, + axi_slave_r_resp_o, + axi_slave_r_last_o, + axi_slave_r_id_o, + axi_slave_r_user_o, + axi_slave_r_ready_i, + axi_slave_b_valid_o, + axi_slave_b_resp_o, + axi_slave_b_id_o, + axi_slave_b_user_o, + axi_slave_b_ready_i, + axi_master_aw_valid_o, + axi_master_aw_addr_o, + axi_master_aw_prot_o, + axi_master_aw_region_o, + axi_master_aw_len_o, + axi_master_aw_size_o, + axi_master_aw_burst_o, + axi_master_aw_lock_o, + axi_master_aw_cache_o, + axi_master_aw_qos_o, + axi_master_aw_id_o, + axi_master_aw_user_o, + axi_master_aw_ready_i, + axi_master_ar_valid_o, + axi_master_ar_addr_o, + axi_master_ar_prot_o, + axi_master_ar_region_o, + axi_master_ar_len_o, + axi_master_ar_size_o, + axi_master_ar_burst_o, + axi_master_ar_lock_o, + axi_master_ar_cache_o, + axi_master_ar_qos_o, + axi_master_ar_id_o, + axi_master_ar_user_o, + axi_master_ar_ready_i, + axi_master_w_valid_o, + axi_master_w_data_o, + axi_master_w_strb_o, + axi_master_w_user_o, + axi_master_w_last_o, + axi_master_w_ready_i, + axi_master_r_valid_i, + axi_master_r_data_i, + axi_master_r_resp_i, + axi_master_r_last_i, + axi_master_r_id_i, + axi_master_r_user_i, + axi_master_r_ready_o, + axi_master_b_valid_i, + axi_master_b_resp_i, + axi_master_b_id_i, + axi_master_b_user_i, + axi_master_b_ready_o +); + //parameter AXI_ADDR_WIDTH = 32; + //parameter AXI_DATA_WIDTH = 64; + //parameter AXI_USER_WIDTH = 6; + //parameter AXI_ID_WIDTH = 3; + //parameter SLICE_DEPTH = 2; + //parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire axi_slave_aw_valid_i; + input wire [AXI_ADDR_WIDTH - 1:0] axi_slave_aw_addr_i; + input wire [2:0] axi_slave_aw_prot_i; + input wire [3:0] axi_slave_aw_region_i; + input wire [7:0] axi_slave_aw_len_i; + input wire [2:0] axi_slave_aw_size_i; + input wire [1:0] axi_slave_aw_burst_i; + input wire axi_slave_aw_lock_i; + input wire [3:0] axi_slave_aw_cache_i; + input wire [3:0] axi_slave_aw_qos_i; + input wire [AXI_ID_WIDTH - 1:0] axi_slave_aw_id_i; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_aw_user_i; + output wire axi_slave_aw_ready_o; + input wire axi_slave_ar_valid_i; + input wire [AXI_ADDR_WIDTH - 1:0] axi_slave_ar_addr_i; + input wire [2:0] axi_slave_ar_prot_i; + input wire [3:0] axi_slave_ar_region_i; + input wire [7:0] axi_slave_ar_len_i; + input wire [2:0] axi_slave_ar_size_i; + input wire [1:0] axi_slave_ar_burst_i; + input wire axi_slave_ar_lock_i; + input wire [3:0] axi_slave_ar_cache_i; + input wire [3:0] axi_slave_ar_qos_i; + input wire [AXI_ID_WIDTH - 1:0] axi_slave_ar_id_i; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_ar_user_i; + output wire axi_slave_ar_ready_o; + input wire axi_slave_w_valid_i; + input wire [AXI_DATA_WIDTH - 1:0] axi_slave_w_data_i; + input wire [AXI_STRB_WIDTH - 1:0] axi_slave_w_strb_i; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_w_user_i; + input wire axi_slave_w_last_i; + output wire axi_slave_w_ready_o; + output wire axi_slave_r_valid_o; + output wire [AXI_DATA_WIDTH - 1:0] axi_slave_r_data_o; + output wire [1:0] axi_slave_r_resp_o; + output wire axi_slave_r_last_o; + output wire [AXI_ID_WIDTH - 1:0] axi_slave_r_id_o; + output wire [AXI_USER_WIDTH - 1:0] axi_slave_r_user_o; + input wire axi_slave_r_ready_i; + output wire axi_slave_b_valid_o; + output wire [1:0] axi_slave_b_resp_o; + output wire [AXI_ID_WIDTH - 1:0] axi_slave_b_id_o; + output wire [AXI_USER_WIDTH - 1:0] axi_slave_b_user_o; + input wire axi_slave_b_ready_i; + output wire axi_master_aw_valid_o; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_aw_addr_o; + output wire [2:0] axi_master_aw_prot_o; + output wire [3:0] axi_master_aw_region_o; + output wire [7:0] axi_master_aw_len_o; + output wire [2:0] axi_master_aw_size_o; + output wire [1:0] axi_master_aw_burst_o; + output wire axi_master_aw_lock_o; + output wire [3:0] axi_master_aw_cache_o; + output wire [3:0] axi_master_aw_qos_o; + output wire [AXI_ID_WIDTH - 1:0] axi_master_aw_id_o; + output wire [AXI_USER_WIDTH - 1:0] axi_master_aw_user_o; + input wire axi_master_aw_ready_i; + output wire axi_master_ar_valid_o; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_ar_addr_o; + output wire [2:0] axi_master_ar_prot_o; + output wire [3:0] axi_master_ar_region_o; + output wire [7:0] axi_master_ar_len_o; + output wire [2:0] axi_master_ar_size_o; + output wire [1:0] axi_master_ar_burst_o; + output wire axi_master_ar_lock_o; + output wire [3:0] axi_master_ar_cache_o; + output wire [3:0] axi_master_ar_qos_o; + output wire [AXI_ID_WIDTH - 1:0] axi_master_ar_id_o; + output wire [AXI_USER_WIDTH - 1:0] axi_master_ar_user_o; + input wire axi_master_ar_ready_i; + output wire axi_master_w_valid_o; + output wire [AXI_DATA_WIDTH - 1:0] axi_master_w_data_o; + output wire [AXI_STRB_WIDTH - 1:0] axi_master_w_strb_o; + output wire [AXI_USER_WIDTH - 1:0] axi_master_w_user_o; + output wire axi_master_w_last_o; + input wire axi_master_w_ready_i; + input wire axi_master_r_valid_i; + input wire [AXI_DATA_WIDTH - 1:0] axi_master_r_data_i; + input wire [1:0] axi_master_r_resp_i; + input wire axi_master_r_last_i; + input wire [AXI_ID_WIDTH - 1:0] axi_master_r_id_i; + input wire [AXI_USER_WIDTH - 1:0] axi_master_r_user_i; + output wire axi_master_r_ready_o; + input wire axi_master_b_valid_i; + input wire [1:0] axi_master_b_resp_i; + input wire [AXI_ID_WIDTH - 1:0] axi_master_b_id_i; + input wire [AXI_USER_WIDTH - 1:0] axi_master_b_user_i; + output wire axi_master_b_ready_o; + axi_aw_buffer #( + .ID_WIDTH(AXI_ID_WIDTH), + .ADDR_WIDTH(AXI_ADDR_WIDTH), + .USER_WIDTH(AXI_USER_WIDTH), + .BUFFER_DEPTH(SLICE_DEPTH) + ) aw_buffer_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .slave_valid_i(axi_slave_aw_valid_i), + .slave_addr_i(axi_slave_aw_addr_i), + .slave_prot_i(axi_slave_aw_prot_i), + .slave_region_i(axi_slave_aw_region_i), + .slave_len_i(axi_slave_aw_len_i), + .slave_size_i(axi_slave_aw_size_i), + .slave_burst_i(axi_slave_aw_burst_i), + .slave_lock_i(axi_slave_aw_lock_i), + .slave_cache_i(axi_slave_aw_cache_i), + .slave_qos_i(axi_slave_aw_qos_i), + .slave_id_i(axi_slave_aw_id_i), + .slave_user_i(axi_slave_aw_user_i), + .slave_ready_o(axi_slave_aw_ready_o), + .master_valid_o(axi_master_aw_valid_o), + .master_addr_o(axi_master_aw_addr_o), + .master_prot_o(axi_master_aw_prot_o), + .master_region_o(axi_master_aw_region_o), + .master_len_o(axi_master_aw_len_o), + .master_size_o(axi_master_aw_size_o), + .master_burst_o(axi_master_aw_burst_o), + .master_lock_o(axi_master_aw_lock_o), + .master_cache_o(axi_master_aw_cache_o), + .master_qos_o(axi_master_aw_qos_o), + .master_id_o(axi_master_aw_id_o), + .master_user_o(axi_master_aw_user_o), + .master_ready_i(axi_master_aw_ready_i) + ); + axi_ar_buffer #( + .ID_WIDTH(AXI_ID_WIDTH), + .ADDR_WIDTH(AXI_ADDR_WIDTH), + .USER_WIDTH(AXI_USER_WIDTH), + .BUFFER_DEPTH(SLICE_DEPTH) + ) ar_buffer_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .slave_valid_i(axi_slave_ar_valid_i), + .slave_addr_i(axi_slave_ar_addr_i), + .slave_prot_i(axi_slave_ar_prot_i), + .slave_region_i(axi_slave_ar_region_i), + .slave_len_i(axi_slave_ar_len_i), + .slave_size_i(axi_slave_ar_size_i), + .slave_burst_i(axi_slave_ar_burst_i), + .slave_lock_i(axi_slave_ar_lock_i), + .slave_cache_i(axi_slave_ar_cache_i), + .slave_qos_i(axi_slave_ar_qos_i), + .slave_id_i(axi_slave_ar_id_i), + .slave_user_i(axi_slave_ar_user_i), + .slave_ready_o(axi_slave_ar_ready_o), + .master_valid_o(axi_master_ar_valid_o), + .master_addr_o(axi_master_ar_addr_o), + .master_prot_o(axi_master_ar_prot_o), + .master_region_o(axi_master_ar_region_o), + .master_len_o(axi_master_ar_len_o), + .master_size_o(axi_master_ar_size_o), + .master_burst_o(axi_master_ar_burst_o), + .master_lock_o(axi_master_ar_lock_o), + .master_cache_o(axi_master_ar_cache_o), + .master_qos_o(axi_master_ar_qos_o), + .master_id_o(axi_master_ar_id_o), + .master_user_o(axi_master_ar_user_o), + .master_ready_i(axi_master_ar_ready_i) + ); + axi_w_buffer #( + .DATA_WIDTH(AXI_DATA_WIDTH), + .USER_WIDTH(AXI_USER_WIDTH), + .BUFFER_DEPTH(SLICE_DEPTH) + ) w_buffer_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .slave_valid_i(axi_slave_w_valid_i), + .slave_data_i(axi_slave_w_data_i), + .slave_strb_i(axi_slave_w_strb_i), + .slave_user_i(axi_slave_w_user_i), + .slave_last_i(axi_slave_w_last_i), + .slave_ready_o(axi_slave_w_ready_o), + .master_valid_o(axi_master_w_valid_o), + .master_data_o(axi_master_w_data_o), + .master_strb_o(axi_master_w_strb_o), + .master_user_o(axi_master_w_user_o), + .master_last_o(axi_master_w_last_o), + .master_ready_i(axi_master_w_ready_i) + ); + axi_r_buffer #( + .ID_WIDTH(AXI_ID_WIDTH), + .DATA_WIDTH(AXI_DATA_WIDTH), + .USER_WIDTH(AXI_USER_WIDTH), + .BUFFER_DEPTH(SLICE_DEPTH) + ) r_buffer_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .slave_valid_i(axi_master_r_valid_i), + .slave_data_i(axi_master_r_data_i), + .slave_resp_i(axi_master_r_resp_i), + .slave_user_i(axi_master_r_user_i), + .slave_id_i(axi_master_r_id_i), + .slave_last_i(axi_master_r_last_i), + .slave_ready_o(axi_master_r_ready_o), + .master_valid_o(axi_slave_r_valid_o), + .master_data_o(axi_slave_r_data_o), + .master_resp_o(axi_slave_r_resp_o), + .master_user_o(axi_slave_r_user_o), + .master_id_o(axi_slave_r_id_o), + .master_last_o(axi_slave_r_last_o), + .master_ready_i(axi_slave_r_ready_i) + ); + axi_b_buffer #( + .ID_WIDTH(AXI_ID_WIDTH), + .USER_WIDTH(AXI_USER_WIDTH), + .BUFFER_DEPTH(SLICE_DEPTH) + ) b_buffer_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .slave_valid_i(axi_master_b_valid_i), + .slave_resp_i(axi_master_b_resp_i), + .slave_id_i(axi_master_b_id_i), + .slave_user_i(axi_master_b_user_i), + .slave_ready_o(axi_master_b_ready_o), + .master_valid_o(axi_slave_b_valid_o), + .master_resp_o(axi_slave_b_resp_o), + .master_id_o(axi_slave_b_id_o), + .master_user_o(axi_slave_b_user_o), + .master_ready_i(axi_slave_b_ready_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice/axi_w_buffer.v b/verilog/rtl/ips/axi/axi_slice/axi_w_buffer.v new file mode 100644 index 0000000..9be4400 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice/axi_w_buffer.v
@@ -0,0 +1,62 @@ +module axi_w_buffer +#( + parameter DATA_WIDTH = 64, + parameter USER_WIDTH = 6, + parameter BUFFER_DEPTH = 2, + parameter STRB_WIDTH = DATA_WIDTH/8 // DO NOT OVERRIDE +) +( + clk_i, + rst_ni, + test_en_i, + slave_valid_i, + slave_data_i, + slave_strb_i, + slave_user_i, + slave_last_i, + slave_ready_o, + master_valid_o, + master_data_o, + master_strb_o, + master_user_o, + master_last_o, + master_ready_i +); + //parameter DATA_WIDTH = 64; + //parameter USER_WIDTH = 6; + //parameter BUFFER_DEPTH = 2; + //parameter STRB_WIDTH = DATA_WIDTH / 8; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire slave_valid_i; + input wire [DATA_WIDTH - 1:0] slave_data_i; + input wire [STRB_WIDTH - 1:0] slave_strb_i; + input wire [USER_WIDTH - 1:0] slave_user_i; + input wire slave_last_i; + output wire slave_ready_o; + output wire master_valid_o; + output wire [DATA_WIDTH - 1:0] master_data_o; + output wire [STRB_WIDTH - 1:0] master_strb_o; + output wire [USER_WIDTH - 1:0] master_user_o; + output wire master_last_o; + input wire master_ready_i; + wire [(DATA_WIDTH + STRB_WIDTH) + USER_WIDTH:0] s_data_in; + wire [(DATA_WIDTH + STRB_WIDTH) + USER_WIDTH:0] s_data_out; + assign s_data_in = {slave_user_i, slave_strb_i, slave_data_i, slave_last_i}; + assign {master_user_o, master_strb_o, master_data_o, master_last_o} = s_data_out; + generic_fifo #( + .DATA_WIDTH(((1 + DATA_WIDTH) + STRB_WIDTH) + USER_WIDTH), + .DATA_DEPTH(BUFFER_DEPTH) + ) buffer_i( + .clk(clk_i), + .rst_n(rst_ni), + .data_i(s_data_in), + .valid_i(slave_valid_i), + .grant_o(slave_ready_o), + .data_o(s_data_out), + .valid_o(master_valid_o), + .grant_i(master_ready_i), + .test_mode_i(test_en_i) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/axi_slice_dc_master.v b/verilog/rtl/ips/axi/axi_slice_dc/axi_slice_dc_master.v new file mode 100644 index 0000000..c939e61 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/axi_slice_dc_master.v
@@ -0,0 +1,351 @@ +module axi_slice_dc_master +#( + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 6, + parameter BUFFER_WIDTH = 8 +) +( + clk_i, + rst_ni, + axi_slave_aw_addr, + axi_slave_aw_prot, + axi_slave_aw_region, + axi_slave_aw_len, + axi_slave_aw_size, + axi_slave_aw_burst, + axi_slave_aw_lock, + axi_slave_aw_cache, + axi_slave_aw_qos, + axi_slave_aw_id, + axi_slave_aw_user, + axi_slave_aw_writetoken, + axi_slave_aw_readpointer, + axi_slave_ar_addr, + axi_slave_ar_prot, + axi_slave_ar_region, + axi_slave_ar_len, + axi_slave_ar_size, + axi_slave_ar_burst, + axi_slave_ar_lock, + axi_slave_ar_cache, + axi_slave_ar_qos, + axi_slave_ar_id, + axi_slave_ar_user, + axi_slave_ar_writetoken, + axi_slave_ar_readpointer, + axi_slave_w_data, + axi_slave_w_strb, + axi_slave_w_user, + axi_slave_w_last, + axi_slave_w_writetoken, + axi_slave_w_readpointer, + axi_slave_r_data, + axi_slave_r_resp, + axi_slave_r_last, + axi_slave_r_id, + axi_slave_r_user, + axi_slave_r_writetoken, + axi_slave_r_readpointer, + axi_slave_b_resp, + axi_slave_b_id, + axi_slave_b_user, + axi_slave_b_writetoken, + axi_slave_b_readpointer, + axi_master_aw_valid, + axi_master_aw_addr, + axi_master_aw_prot, + axi_master_aw_region, + axi_master_aw_len, + axi_master_aw_size, + axi_master_aw_burst, + axi_master_aw_lock, + axi_master_aw_cache, + axi_master_aw_qos, + axi_master_aw_id, + axi_master_aw_user, + axi_master_aw_ready, + axi_master_ar_valid, + axi_master_ar_addr, + axi_master_ar_prot, + axi_master_ar_region, + axi_master_ar_len, + axi_master_ar_size, + axi_master_ar_burst, + axi_master_ar_lock, + axi_master_ar_cache, + axi_master_ar_qos, + axi_master_ar_id, + axi_master_ar_user, + axi_master_ar_ready, + axi_master_w_valid, + axi_master_w_data, + axi_master_w_strb, + axi_master_w_user, + axi_master_w_last, + axi_master_w_ready, + axi_master_r_valid, + axi_master_r_data, + axi_master_r_resp, + axi_master_r_last, + axi_master_r_id, + axi_master_r_user, + axi_master_r_ready, + axi_master_b_valid, + axi_master_b_resp, + axi_master_b_id, + axi_master_b_user, + axi_master_b_ready +); + //parameter AXI_ADDR_WIDTH = 32; + //parameter AXI_DATA_WIDTH = 64; + //parameter AXI_USER_WIDTH = 6; + //parameter AXI_ID_WIDTH = 6; + //parameter BUFFER_WIDTH = 8; + input wire clk_i; + input wire rst_ni; + input wire [AXI_ADDR_WIDTH - 1:0] axi_slave_aw_addr; + input wire [2:0] axi_slave_aw_prot; + input wire [3:0] axi_slave_aw_region; + input wire [7:0] axi_slave_aw_len; + input wire [2:0] axi_slave_aw_size; + input wire [1:0] axi_slave_aw_burst; + input wire axi_slave_aw_lock; + input wire [3:0] axi_slave_aw_cache; + input wire [3:0] axi_slave_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] axi_slave_aw_id; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_aw_user; + input wire [BUFFER_WIDTH - 1:0] axi_slave_aw_writetoken; + output wire [BUFFER_WIDTH - 1:0] axi_slave_aw_readpointer; + input wire [AXI_ADDR_WIDTH - 1:0] axi_slave_ar_addr; + input wire [2:0] axi_slave_ar_prot; + input wire [3:0] axi_slave_ar_region; + input wire [7:0] axi_slave_ar_len; + input wire [2:0] axi_slave_ar_size; + input wire [1:0] axi_slave_ar_burst; + input wire axi_slave_ar_lock; + input wire [3:0] axi_slave_ar_cache; + input wire [3:0] axi_slave_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] axi_slave_ar_id; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_ar_user; + input wire [BUFFER_WIDTH - 1:0] axi_slave_ar_writetoken; + output wire [BUFFER_WIDTH - 1:0] axi_slave_ar_readpointer; + input wire [AXI_DATA_WIDTH - 1:0] axi_slave_w_data; + input wire [(AXI_DATA_WIDTH / 8) - 1:0] axi_slave_w_strb; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_w_user; + input wire axi_slave_w_last; + input wire [BUFFER_WIDTH - 1:0] axi_slave_w_writetoken; + output wire [BUFFER_WIDTH - 1:0] axi_slave_w_readpointer; + output wire [AXI_DATA_WIDTH - 1:0] axi_slave_r_data; + output wire [1:0] axi_slave_r_resp; + output wire axi_slave_r_last; + output wire [AXI_ID_WIDTH - 1:0] axi_slave_r_id; + output wire [AXI_USER_WIDTH - 1:0] axi_slave_r_user; + output wire [BUFFER_WIDTH - 1:0] axi_slave_r_writetoken; + input wire [BUFFER_WIDTH - 1:0] axi_slave_r_readpointer; + output wire [1:0] axi_slave_b_resp; + output wire [AXI_ID_WIDTH - 1:0] axi_slave_b_id; + output wire [AXI_USER_WIDTH - 1:0] axi_slave_b_user; + output wire [BUFFER_WIDTH - 1:0] axi_slave_b_writetoken; + input wire [BUFFER_WIDTH - 1:0] axi_slave_b_readpointer; + output wire axi_master_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_aw_addr; + output wire [2:0] axi_master_aw_prot; + output wire [3:0] axi_master_aw_region; + output wire [7:0] axi_master_aw_len; + output wire [2:0] axi_master_aw_size; + output wire [1:0] axi_master_aw_burst; + output wire axi_master_aw_lock; + output wire [3:0] axi_master_aw_cache; + output wire [3:0] axi_master_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_aw_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_aw_user; + input wire axi_master_aw_ready; + output wire axi_master_ar_valid; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_ar_addr; + output wire [2:0] axi_master_ar_prot; + output wire [3:0] axi_master_ar_region; + output wire [7:0] axi_master_ar_len; + output wire [2:0] axi_master_ar_size; + output wire [1:0] axi_master_ar_burst; + output wire axi_master_ar_lock; + output wire [3:0] axi_master_ar_cache; + output wire [3:0] axi_master_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_ar_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_ar_user; + input wire axi_master_ar_ready; + output wire axi_master_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] axi_master_w_data; + output wire [(AXI_DATA_WIDTH / 8) - 1:0] axi_master_w_strb; + output wire [AXI_USER_WIDTH - 1:0] axi_master_w_user; + output wire axi_master_w_last; + input wire axi_master_w_ready; + input wire axi_master_r_valid; + input wire [AXI_DATA_WIDTH - 1:0] axi_master_r_data; + input wire [1:0] axi_master_r_resp; + input wire axi_master_r_last; + input wire [AXI_ID_WIDTH - 1:0] axi_master_r_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_r_user; + output wire axi_master_r_ready; + input wire axi_master_b_valid; + input wire [1:0] axi_master_b_resp; + input wire [AXI_ID_WIDTH - 1:0] axi_master_b_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_b_user; + output wire axi_master_b_ready; + localparam DATA_STRB_WIDTH = AXI_DATA_WIDTH + (AXI_DATA_WIDTH / 8); + localparam DATA_USER_STRB_WIDTH = (AXI_DATA_WIDTH + (AXI_DATA_WIDTH / 8)) + AXI_ID_WIDTH; + localparam DATA_ID_WIDTH = AXI_DATA_WIDTH + AXI_USER_WIDTH; + localparam DATA_USER_ID_WIDTH = (AXI_DATA_WIDTH + AXI_USER_WIDTH) + AXI_ID_WIDTH; + localparam ADDR_ID_WIDTH = AXI_ADDR_WIDTH + AXI_ID_WIDTH; + localparam ADDR_USER_ID_WIDTH = (AXI_ADDR_WIDTH + AXI_USER_WIDTH) + AXI_ID_WIDTH; + localparam USER_ID_WIDTH = AXI_USER_WIDTH + AXI_ID_WIDTH; + localparam WIDTH_FIFO_AW = 30 + ADDR_USER_ID_WIDTH; + localparam WIDTH_FIFO_AR = 30 + ADDR_USER_ID_WIDTH; + localparam WIDTH_FIFO_W = 1 + DATA_USER_STRB_WIDTH; + localparam WIDTH_FIFO_R = 3 + DATA_USER_ID_WIDTH; + localparam WIDTH_FIFO_B = 2 + USER_ID_WIDTH; + wire [WIDTH_FIFO_AW - 1:0] data_aw; + wire [WIDTH_FIFO_AW - 1:0] data_async_aw; + wire [WIDTH_FIFO_AR - 1:0] data_ar; + wire [WIDTH_FIFO_AR - 1:0] data_async_ar; + wire [WIDTH_FIFO_W - 1:0] data_w; + wire [WIDTH_FIFO_W - 1:0] data_async_w; + wire [WIDTH_FIFO_R - 1:0] data_r; + wire [WIDTH_FIFO_R - 1:0] data_async_r; + wire [WIDTH_FIFO_B - 1:0] data_b; + wire [WIDTH_FIFO_B - 1:0] data_async_b; + assign data_async_aw[3:0] = axi_slave_aw_cache; + assign data_async_aw[6:4] = axi_slave_aw_prot; + assign data_async_aw[8:7] = axi_slave_aw_lock; + assign data_async_aw[10:9] = axi_slave_aw_burst; + assign data_async_aw[13:11] = axi_slave_aw_size; + assign data_async_aw[21:14] = axi_slave_aw_len; + assign data_async_aw[25:22] = axi_slave_aw_region; + assign data_async_aw[29:26] = axi_slave_aw_qos; + assign data_async_aw[29 + AXI_ADDR_WIDTH:30] = axi_slave_aw_addr; + assign data_async_aw[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH] = axi_slave_aw_id; + assign data_async_aw[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH] = axi_slave_aw_user; + assign axi_master_aw_cache = data_aw[3:0]; + assign axi_master_aw_prot = data_aw[6:4]; + assign axi_master_aw_lock = data_aw[8:7]; + assign axi_master_aw_burst = data_aw[10:9]; + assign axi_master_aw_size = data_aw[13:11]; + assign axi_master_aw_len = data_aw[21:14]; + assign axi_master_aw_region = data_aw[25:22]; + assign axi_master_aw_qos = data_aw[29:26]; + assign axi_master_aw_addr = data_aw[29 + AXI_ADDR_WIDTH:30]; + assign axi_master_aw_id = data_aw[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH]; + assign axi_master_aw_user = data_aw[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH]; + assign data_async_ar[3:0] = axi_slave_ar_cache; + assign data_async_ar[6:4] = axi_slave_ar_prot; + assign data_async_ar[8:7] = axi_slave_ar_lock; + assign data_async_ar[10:9] = axi_slave_ar_burst; + assign data_async_ar[13:11] = axi_slave_ar_size; + assign data_async_ar[21:14] = axi_slave_ar_len; + assign data_async_ar[25:22] = axi_slave_ar_region; + assign data_async_ar[29:26] = axi_slave_ar_qos; + assign data_async_ar[29 + AXI_ADDR_WIDTH:30] = axi_slave_ar_addr; + assign data_async_ar[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH] = axi_slave_ar_id; + assign data_async_ar[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH] = axi_slave_ar_user; + assign axi_master_ar_cache = data_ar[3:0]; + assign axi_master_ar_prot = data_ar[6:4]; + assign axi_master_ar_lock = data_ar[8:7]; + assign axi_master_ar_burst = data_ar[10:9]; + assign axi_master_ar_size = data_ar[13:11]; + assign axi_master_ar_len = data_ar[21:14]; + assign axi_master_ar_region = data_ar[25:22]; + assign axi_master_ar_qos = data_ar[29:26]; + assign axi_master_ar_addr = data_ar[29 + AXI_ADDR_WIDTH:30]; + assign axi_master_ar_id = data_ar[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH]; + assign axi_master_ar_user = data_ar[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH]; + assign data_r[0] = axi_master_r_last; + assign data_r[2:1] = axi_master_r_resp; + assign data_r[2 + AXI_DATA_WIDTH:3] = axi_master_r_data; + assign data_r[2 + DATA_ID_WIDTH:3 + AXI_DATA_WIDTH] = axi_master_r_id; + assign data_r[2 + DATA_USER_ID_WIDTH:3 + DATA_ID_WIDTH] = axi_master_r_user; + assign axi_slave_r_last = data_async_r[0]; + assign axi_slave_r_resp = data_async_r[2:1]; + assign axi_slave_r_data = data_async_r[2 + AXI_DATA_WIDTH:3]; + assign axi_slave_r_id = data_async_r[2 + DATA_ID_WIDTH:3 + AXI_DATA_WIDTH]; + assign axi_slave_r_user = data_async_r[2 + DATA_USER_ID_WIDTH:3 + DATA_ID_WIDTH]; + assign data_async_w[0] = axi_slave_w_last; + assign data_async_w[AXI_DATA_WIDTH:1] = axi_slave_w_data; + assign data_async_w[DATA_STRB_WIDTH:1 + AXI_DATA_WIDTH] = axi_slave_w_strb; + assign data_async_w[DATA_USER_STRB_WIDTH:1 + DATA_STRB_WIDTH] = axi_slave_w_user; + assign axi_master_w_last = data_w[0]; + assign axi_master_w_data = data_w[AXI_DATA_WIDTH:1]; + assign axi_master_w_strb = data_w[DATA_STRB_WIDTH:1 + AXI_DATA_WIDTH]; + assign axi_master_w_user = data_w[DATA_USER_STRB_WIDTH:1 + DATA_STRB_WIDTH]; + assign data_b[1:0] = axi_master_b_resp; + assign data_b[1 + AXI_ID_WIDTH:2] = axi_master_b_id; + assign data_b[1 + USER_ID_WIDTH:2 + AXI_ID_WIDTH] = axi_master_b_user; + assign axi_slave_b_resp = data_async_b[1:0]; + assign axi_slave_b_id = data_async_b[1 + AXI_ID_WIDTH:2]; + assign axi_slave_b_user = data_async_b[1 + USER_ID_WIDTH:2 + AXI_ID_WIDTH]; + dc_token_ring_fifo_dout #( + WIDTH_FIFO_AW, + BUFFER_WIDTH + ) dc_awchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_aw), + .valid(axi_master_aw_valid), + .ready(axi_master_aw_ready), + .write_token(axi_slave_aw_writetoken), + .read_pointer(axi_slave_aw_readpointer), + .data_async(data_async_aw) + ); + dc_token_ring_fifo_dout #( + WIDTH_FIFO_AR, + BUFFER_WIDTH + ) dc_archan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_ar), + .valid(axi_master_ar_valid), + .ready(axi_master_ar_ready), + .write_token(axi_slave_ar_writetoken), + .read_pointer(axi_slave_ar_readpointer), + .data_async(data_async_ar) + ); + dc_token_ring_fifo_dout #( + WIDTH_FIFO_W, + BUFFER_WIDTH + ) dc_wchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_w), + .valid(axi_master_w_valid), + .ready(axi_master_w_ready), + .write_token(axi_slave_w_writetoken), + .read_pointer(axi_slave_w_readpointer), + .data_async(data_async_w) + ); + dc_token_ring_fifo_din #( + WIDTH_FIFO_R, + BUFFER_WIDTH + ) dc_rchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_r), + .valid(axi_master_r_valid), + .ready(axi_master_r_ready), + .write_token(axi_slave_r_writetoken), + .read_pointer(axi_slave_r_readpointer), + .data_async(data_async_r) + ); + dc_token_ring_fifo_din #( + WIDTH_FIFO_B, + BUFFER_WIDTH + ) dc_bchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_b), + .valid(axi_master_b_valid), + .ready(axi_master_b_ready), + .write_token(axi_slave_b_writetoken), + .read_pointer(axi_slave_b_readpointer), + .data_async(data_async_b) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/axi_slice_dc_slave.v b/verilog/rtl/ips/axi/axi_slice_dc/axi_slice_dc_slave.v new file mode 100644 index 0000000..53c18d9 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/axi_slice_dc_slave.v
@@ -0,0 +1,351 @@ +module axi_slice_dc_slave +#( + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 6, + parameter BUFFER_WIDTH = 8 +) +( + clk_i, + rst_ni, + axi_slave_aw_valid, + axi_slave_aw_addr, + axi_slave_aw_prot, + axi_slave_aw_region, + axi_slave_aw_len, + axi_slave_aw_size, + axi_slave_aw_burst, + axi_slave_aw_lock, + axi_slave_aw_cache, + axi_slave_aw_qos, + axi_slave_aw_id, + axi_slave_aw_user, + axi_slave_aw_ready, + axi_slave_ar_valid, + axi_slave_ar_addr, + axi_slave_ar_prot, + axi_slave_ar_region, + axi_slave_ar_len, + axi_slave_ar_size, + axi_slave_ar_burst, + axi_slave_ar_lock, + axi_slave_ar_cache, + axi_slave_ar_qos, + axi_slave_ar_id, + axi_slave_ar_user, + axi_slave_ar_ready, + axi_slave_w_valid, + axi_slave_w_data, + axi_slave_w_strb, + axi_slave_w_user, + axi_slave_w_last, + axi_slave_w_ready, + axi_slave_r_valid, + axi_slave_r_data, + axi_slave_r_resp, + axi_slave_r_last, + axi_slave_r_id, + axi_slave_r_user, + axi_slave_r_ready, + axi_slave_b_valid, + axi_slave_b_resp, + axi_slave_b_id, + axi_slave_b_user, + axi_slave_b_ready, + axi_master_aw_addr, + axi_master_aw_prot, + axi_master_aw_region, + axi_master_aw_len, + axi_master_aw_size, + axi_master_aw_burst, + axi_master_aw_lock, + axi_master_aw_cache, + axi_master_aw_qos, + axi_master_aw_id, + axi_master_aw_user, + axi_master_aw_writetoken, + axi_master_aw_readpointer, + axi_master_ar_addr, + axi_master_ar_prot, + axi_master_ar_region, + axi_master_ar_len, + axi_master_ar_size, + axi_master_ar_burst, + axi_master_ar_lock, + axi_master_ar_cache, + axi_master_ar_qos, + axi_master_ar_id, + axi_master_ar_user, + axi_master_ar_writetoken, + axi_master_ar_readpointer, + axi_master_w_data, + axi_master_w_strb, + axi_master_w_user, + axi_master_w_last, + axi_master_w_writetoken, + axi_master_w_readpointer, + axi_master_r_data, + axi_master_r_resp, + axi_master_r_last, + axi_master_r_id, + axi_master_r_user, + axi_master_r_writetoken, + axi_master_r_readpointer, + axi_master_b_resp, + axi_master_b_id, + axi_master_b_user, + axi_master_b_writetoken, + axi_master_b_readpointer +); + //parameter AXI_ADDR_WIDTH = 32; + //parameter AXI_DATA_WIDTH = 64; + //parameter AXI_USER_WIDTH = 6; + //parameter AXI_ID_WIDTH = 6; + //parameter BUFFER_WIDTH = 8; + input wire clk_i; + input wire rst_ni; + input wire axi_slave_aw_valid; + input wire [AXI_ADDR_WIDTH - 1:0] axi_slave_aw_addr; + input wire [2:0] axi_slave_aw_prot; + input wire [3:0] axi_slave_aw_region; + input wire [7:0] axi_slave_aw_len; + input wire [2:0] axi_slave_aw_size; + input wire [1:0] axi_slave_aw_burst; + input wire axi_slave_aw_lock; + input wire [3:0] axi_slave_aw_cache; + input wire [3:0] axi_slave_aw_qos; + input wire [AXI_ID_WIDTH - 1:0] axi_slave_aw_id; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_aw_user; + output wire axi_slave_aw_ready; + input wire axi_slave_ar_valid; + input wire [AXI_ADDR_WIDTH - 1:0] axi_slave_ar_addr; + input wire [2:0] axi_slave_ar_prot; + input wire [3:0] axi_slave_ar_region; + input wire [7:0] axi_slave_ar_len; + input wire [2:0] axi_slave_ar_size; + input wire [1:0] axi_slave_ar_burst; + input wire axi_slave_ar_lock; + input wire [3:0] axi_slave_ar_cache; + input wire [3:0] axi_slave_ar_qos; + input wire [AXI_ID_WIDTH - 1:0] axi_slave_ar_id; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_ar_user; + output wire axi_slave_ar_ready; + input wire axi_slave_w_valid; + input wire [AXI_DATA_WIDTH - 1:0] axi_slave_w_data; + input wire [(AXI_DATA_WIDTH / 8) - 1:0] axi_slave_w_strb; + input wire [AXI_USER_WIDTH - 1:0] axi_slave_w_user; + input wire axi_slave_w_last; + output wire axi_slave_w_ready; + output wire axi_slave_r_valid; + output wire [AXI_DATA_WIDTH - 1:0] axi_slave_r_data; + output wire [1:0] axi_slave_r_resp; + output wire axi_slave_r_last; + output wire [AXI_ID_WIDTH - 1:0] axi_slave_r_id; + output wire [AXI_USER_WIDTH - 1:0] axi_slave_r_user; + input wire axi_slave_r_ready; + output wire axi_slave_b_valid; + output wire [1:0] axi_slave_b_resp; + output wire [AXI_ID_WIDTH - 1:0] axi_slave_b_id; + output wire [AXI_USER_WIDTH - 1:0] axi_slave_b_user; + input wire axi_slave_b_ready; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_aw_addr; + output wire [2:0] axi_master_aw_prot; + output wire [3:0] axi_master_aw_region; + output wire [7:0] axi_master_aw_len; + output wire [2:0] axi_master_aw_size; + output wire [1:0] axi_master_aw_burst; + output wire axi_master_aw_lock; + output wire [3:0] axi_master_aw_cache; + output wire [3:0] axi_master_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_aw_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_aw_user; + output wire [BUFFER_WIDTH - 1:0] axi_master_aw_writetoken; + input wire [BUFFER_WIDTH - 1:0] axi_master_aw_readpointer; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_ar_addr; + output wire [2:0] axi_master_ar_prot; + output wire [3:0] axi_master_ar_region; + output wire [7:0] axi_master_ar_len; + output wire [2:0] axi_master_ar_size; + output wire [1:0] axi_master_ar_burst; + output wire axi_master_ar_lock; + output wire [3:0] axi_master_ar_cache; + output wire [3:0] axi_master_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_ar_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_ar_user; + output wire [BUFFER_WIDTH - 1:0] axi_master_ar_writetoken; + input wire [BUFFER_WIDTH - 1:0] axi_master_ar_readpointer; + output wire [AXI_DATA_WIDTH - 1:0] axi_master_w_data; + output wire [(AXI_DATA_WIDTH / 8) - 1:0] axi_master_w_strb; + output wire [AXI_USER_WIDTH - 1:0] axi_master_w_user; + output wire axi_master_w_last; + output wire [BUFFER_WIDTH - 1:0] axi_master_w_writetoken; + input wire [BUFFER_WIDTH - 1:0] axi_master_w_readpointer; + input wire [AXI_DATA_WIDTH - 1:0] axi_master_r_data; + input wire [1:0] axi_master_r_resp; + input wire axi_master_r_last; + input wire [AXI_ID_WIDTH - 1:0] axi_master_r_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_r_user; + input wire [BUFFER_WIDTH - 1:0] axi_master_r_writetoken; + output wire [BUFFER_WIDTH - 1:0] axi_master_r_readpointer; + input wire [1:0] axi_master_b_resp; + input wire [AXI_ID_WIDTH - 1:0] axi_master_b_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_b_user; + input wire [BUFFER_WIDTH - 1:0] axi_master_b_writetoken; + output wire [BUFFER_WIDTH - 1:0] axi_master_b_readpointer; + localparam DATA_STRB_WIDTH = AXI_DATA_WIDTH + (AXI_DATA_WIDTH / 8); + localparam DATA_USER_STRB_WIDTH = (AXI_DATA_WIDTH + (AXI_DATA_WIDTH / 8)) + AXI_ID_WIDTH; + localparam DATA_ID_WIDTH = AXI_DATA_WIDTH + AXI_ID_WIDTH; + localparam DATA_USER_ID_WIDTH = (AXI_DATA_WIDTH + AXI_ID_WIDTH) + AXI_USER_WIDTH; + localparam ADDR_ID_WIDTH = AXI_ADDR_WIDTH + AXI_ID_WIDTH; + localparam ADDR_USER_ID_WIDTH = (AXI_ADDR_WIDTH + AXI_ID_WIDTH) + AXI_USER_WIDTH; + localparam USER_ID_WIDTH = AXI_USER_WIDTH + AXI_ID_WIDTH; + localparam WIDTH_FIFO_AW = 30 + ADDR_USER_ID_WIDTH; + localparam WIDTH_FIFO_AR = 30 + ADDR_USER_ID_WIDTH; + localparam WIDTH_FIFO_W = 1 + DATA_USER_STRB_WIDTH; + localparam WIDTH_FIFO_R = 3 + DATA_USER_ID_WIDTH; + localparam WIDTH_FIFO_B = 2 + USER_ID_WIDTH; + wire [WIDTH_FIFO_AW - 1:0] data_aw; + wire [WIDTH_FIFO_AW - 1:0] data_async_aw; + wire [WIDTH_FIFO_AR - 1:0] data_ar; + wire [WIDTH_FIFO_AR - 1:0] data_async_ar; + wire [WIDTH_FIFO_W - 1:0] data_w; + wire [WIDTH_FIFO_W - 1:0] data_async_w; + wire [WIDTH_FIFO_R - 1:0] data_r; + wire [WIDTH_FIFO_R - 1:0] data_async_r; + wire [WIDTH_FIFO_B - 1:0] data_b; + wire [WIDTH_FIFO_B - 1:0] data_async_b; + assign data_aw[3:0] = axi_slave_aw_cache; + assign data_aw[6:4] = axi_slave_aw_prot; + assign data_aw[8:7] = axi_slave_aw_lock; + assign data_aw[10:9] = axi_slave_aw_burst; + assign data_aw[13:11] = axi_slave_aw_size; + assign data_aw[21:14] = axi_slave_aw_len; + assign data_aw[25:22] = axi_slave_aw_region; + assign data_aw[29:26] = axi_slave_aw_qos; + assign data_aw[29 + AXI_ADDR_WIDTH:30] = axi_slave_aw_addr; + assign data_aw[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH] = axi_slave_aw_id; + assign data_aw[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH] = axi_slave_aw_user; + assign axi_master_aw_cache = data_async_aw[3:0]; + assign axi_master_aw_prot = data_async_aw[6:4]; + assign axi_master_aw_lock = data_async_aw[8:7]; + assign axi_master_aw_burst = data_async_aw[10:9]; + assign axi_master_aw_size = data_async_aw[13:11]; + assign axi_master_aw_len = data_async_aw[21:14]; + assign axi_master_aw_region = data_async_aw[25:22]; + assign axi_master_aw_qos = data_async_aw[29:26]; + assign axi_master_aw_addr = data_async_aw[29 + AXI_ADDR_WIDTH:30]; + assign axi_master_aw_id = data_async_aw[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH]; + assign axi_master_aw_user = data_async_aw[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH]; + assign data_ar[3:0] = axi_slave_ar_cache; + assign data_ar[6:4] = axi_slave_ar_prot; + assign data_ar[8:7] = axi_slave_ar_lock; + assign data_ar[10:9] = axi_slave_ar_burst; + assign data_ar[13:11] = axi_slave_ar_size; + assign data_ar[21:14] = axi_slave_ar_len; + assign data_ar[25:22] = axi_slave_ar_region; + assign data_ar[29:26] = axi_slave_ar_qos; + assign data_ar[29 + AXI_ADDR_WIDTH:30] = axi_slave_ar_addr; + assign data_ar[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH] = axi_slave_ar_id; + assign data_ar[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH] = axi_slave_ar_user; + assign axi_master_ar_cache = data_async_ar[3:0]; + assign axi_master_ar_prot = data_async_ar[6:4]; + assign axi_master_ar_lock = data_async_ar[8:7]; + assign axi_master_ar_burst = data_async_ar[10:9]; + assign axi_master_ar_size = data_async_ar[13:11]; + assign axi_master_ar_len = data_async_ar[21:14]; + assign axi_master_ar_region = data_async_ar[25:22]; + assign axi_master_ar_qos = data_async_ar[29:26]; + assign axi_master_ar_addr = data_async_ar[29 + AXI_ADDR_WIDTH:30]; + assign axi_master_ar_id = data_async_ar[29 + ADDR_ID_WIDTH:30 + AXI_ADDR_WIDTH]; + assign axi_master_ar_user = data_async_ar[29 + ADDR_USER_ID_WIDTH:30 + ADDR_ID_WIDTH]; + assign data_async_r[0] = axi_master_r_last; + assign data_async_r[2:1] = axi_master_r_resp; + assign data_async_r[2 + AXI_DATA_WIDTH:3] = axi_master_r_data; + assign data_async_r[2 + DATA_ID_WIDTH:3 + AXI_DATA_WIDTH] = axi_master_r_id; + assign data_async_r[2 + DATA_USER_ID_WIDTH:3 + DATA_ID_WIDTH] = axi_master_r_user; + assign axi_slave_r_last = data_r[0]; + assign axi_slave_r_resp = data_r[2:1]; + assign axi_slave_r_data = data_r[2 + AXI_DATA_WIDTH:3]; + assign axi_slave_r_id = data_r[2 + DATA_ID_WIDTH:3 + AXI_DATA_WIDTH]; + assign axi_slave_r_user = data_r[2 + DATA_USER_ID_WIDTH:3 + DATA_ID_WIDTH]; + assign data_w[0] = axi_slave_w_last; + assign data_w[AXI_DATA_WIDTH:1] = axi_slave_w_data; + assign data_w[DATA_STRB_WIDTH:1 + AXI_DATA_WIDTH] = axi_slave_w_strb; + assign data_w[DATA_USER_STRB_WIDTH:1 + DATA_STRB_WIDTH] = axi_slave_w_user; + assign axi_master_w_last = data_async_w[0]; + assign axi_master_w_data = data_async_w[AXI_DATA_WIDTH:1]; + assign axi_master_w_strb = data_async_w[DATA_STRB_WIDTH:1 + AXI_DATA_WIDTH]; + assign axi_master_w_user = data_async_w[DATA_USER_STRB_WIDTH:1 + DATA_STRB_WIDTH]; + assign data_async_b[1:0] = axi_master_b_resp; + assign data_async_b[1 + AXI_ID_WIDTH:2] = axi_master_b_id; + assign data_async_b[1 + USER_ID_WIDTH:2 + AXI_ID_WIDTH] = axi_master_b_user; + assign axi_slave_b_resp = data_b[1:0]; + assign axi_slave_b_id = data_b[1 + AXI_ID_WIDTH:2]; + assign axi_slave_b_user = data_b[1 + USER_ID_WIDTH:2 + AXI_ID_WIDTH]; + dc_token_ring_fifo_din #( + WIDTH_FIFO_AW, + BUFFER_WIDTH + ) dc_awchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_aw), + .valid(axi_slave_aw_valid), + .ready(axi_slave_aw_ready), + .write_token(axi_master_aw_writetoken), + .read_pointer(axi_master_aw_readpointer), + .data_async(data_async_aw) + ); + dc_token_ring_fifo_din #( + WIDTH_FIFO_AR, + BUFFER_WIDTH + ) dc_archan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_ar), + .valid(axi_slave_ar_valid), + .ready(axi_slave_ar_ready), + .write_token(axi_master_ar_writetoken), + .read_pointer(axi_master_ar_readpointer), + .data_async(data_async_ar) + ); + dc_token_ring_fifo_din #( + WIDTH_FIFO_W, + BUFFER_WIDTH + ) dc_wchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_w), + .valid(axi_slave_w_valid), + .ready(axi_slave_w_ready), + .write_token(axi_master_w_writetoken), + .read_pointer(axi_master_w_readpointer), + .data_async(data_async_w) + ); + dc_token_ring_fifo_dout #( + WIDTH_FIFO_R, + BUFFER_WIDTH + ) dc_rchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_r), + .valid(axi_slave_r_valid), + .ready(axi_slave_r_ready), + .write_token(axi_master_r_writetoken), + .read_pointer(axi_master_r_readpointer), + .data_async(data_async_r) + ); + dc_token_ring_fifo_dout #( + WIDTH_FIFO_B, + BUFFER_WIDTH + ) dc_bchan( + .clk(clk_i), + .rstn(rst_ni), + .data(data_b), + .valid(axi_slave_b_valid), + .ready(axi_slave_b_ready), + .write_token(axi_master_b_writetoken), + .read_pointer(axi_master_b_readpointer), + .data_async(data_async_b) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v b/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v new file mode 100644 index 0000000..cd6f6a0 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v
@@ -0,0 +1,52 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_data_buffer(clk, rstn, write_pointer, write_data, read_pointer, read_data); + + parameter DATA_WIDTH = 32; + parameter BUFFER_DEPTH = 8; + +// `ifndef PULP_FPGA_EMUL +// function integer log2(input integer value); +// begin +// value = value - 1; +// for (log2 = 0; value > 0; log2 = log2 + 1) +// value = value >> 1; +// end +// endfunction +// `define log2(N) log2(N) +// `else + `define log2(N) ((N)<=(1) ? 0 : (N)<=(2) ? 1 : (N)<=(4) ? 2 : (N)<=(8) ? 3 : (N)<=(16) ? 4 : (N)<=(32) ? 5 : (N)<=(64) ? 6 : (N)<=(128) ? 7 : (N)<=(256) ? 8 : (N)<=(512) ? 9 : (N)<=(1024) ? 10 : -1) +// `endif + + input clk; + input rstn; + + input [BUFFER_DEPTH - 1 : 0] write_pointer; + input [DATA_WIDTH - 1 : 0] write_data; + input [BUFFER_DEPTH - 1 : 0] read_pointer; + output [DATA_WIDTH - 1 : 0] read_data; + + reg [DATA_WIDTH - 1 : 0] data[BUFFER_DEPTH - 1 : 0]; + + integer loop; + + always @(posedge clk or negedge rstn) + begin: read_write_data + if (rstn == 1'b0) + for (loop = 0; loop < BUFFER_DEPTH; loop = loop + 1) + data[loop] <= 'h0; + else + data[`log2(write_pointer)] <= write_data; + end + + assign read_data = data[`log2(read_pointer)]; + +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/dc_full_detector.v b/verilog/rtl/ips/axi/axi_slice_dc/dc_full_detector.v new file mode 100644 index 0000000..3061a9f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/dc_full_detector.v
@@ -0,0 +1,57 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_full_detector(clk, rstn, read_pointer, write_pointer, valid, full); + + parameter BUFFER_DEPTH = 8; + + input clk; + input rstn; + input [BUFFER_DEPTH - 1 : 0] read_pointer; + input [BUFFER_DEPTH - 1 : 0] write_pointer; + input valid; + output full; + + wire fifo_full; + wire fifo_1_free; + wire fifo_2_free; + wire full_dn; + wire full_up; + reg latched_full_s; + + assign fifo_full = |(read_pointer & {write_pointer[BUFFER_DEPTH - 2 : 0], write_pointer[BUFFER_DEPTH - 1]}); + assign fifo_1_free = |(read_pointer & {write_pointer[BUFFER_DEPTH - 3 : 0], write_pointer[BUFFER_DEPTH - 1 : BUFFER_DEPTH - 2]}); + assign fifo_2_free = |(read_pointer & {write_pointer[BUFFER_DEPTH - 4 : 0], write_pointer[BUFFER_DEPTH - 1 : BUFFER_DEPTH - 3]}); + assign full_dn = (fifo_full | fifo_1_free | fifo_2_free); + + dc_synchronizer + #( + .WIDTH(1), + .RESET_VALUE(1'b0) + ) + full_synch + ( + .clk ( clk ), + .rstn ( rstn ), + .d_in ( full_dn ), + .d_out ( full_up ) + ); + + always @(posedge clk or negedge rstn) + begin: full_evaluator + if (rstn == 1'b0) + latched_full_s <= 1'b0; + else + latched_full_s <= full_up | valid; + end + + assign full = latched_full_s & full_up; + +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/dc_synchronizer.v b/verilog/rtl/ips/axi/axi_slice_dc/dc_synchronizer.v new file mode 100644 index 0000000..9d329bc --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/dc_synchronizer.v
@@ -0,0 +1,38 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_synchronizer (clk, rstn, d_in, d_out); + + parameter WIDTH = 1; + parameter RESET_VALUE = 'h0; + + input clk; + input rstn; + input [WIDTH - 1 : 0] d_in; + output [WIDTH - 1 : 0] d_out; + + reg [WIDTH - 1 : 0] d_middle; + reg [WIDTH - 1 : 0] d_out; + + always @(posedge clk or negedge rstn) + begin: update_state + if (rstn == 1'b0) + begin + d_middle <= RESET_VALUE; + d_out <= RESET_VALUE; + end + else + begin + d_middle <= d_in; + d_out <= d_middle; + end + end + +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring.v b/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring.v new file mode 100644 index 0000000..c6f722b --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring.v
@@ -0,0 +1,40 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_token_ring(clk, rstn, enable, state); + + parameter BUFFER_DEPTH = 8; + parameter RESET_VALUE = 'h3; + + input clk; + input rstn; + input enable; + output [BUFFER_DEPTH - 1 : 0] state; + + reg [BUFFER_DEPTH - 1 : 0] state; + reg [BUFFER_DEPTH - 1 : 0] next_state; + + always @(posedge clk or negedge rstn) + begin: update_state + if (rstn == 1'b0) + state <= RESET_VALUE; + else + state <= next_state; + end + + always @(enable, state) + begin + if (enable) + next_state = {state[BUFFER_DEPTH - 2 : 0], state[BUFFER_DEPTH - 1]}; + else + next_state = state; + end + +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring_fifo_din.v b/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring_fifo_din.v new file mode 100644 index 0000000..f4a0f70 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring_fifo_din.v
@@ -0,0 +1,84 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_token_ring_fifo_din(clk, rstn, data, valid, ready, write_token, read_pointer, data_async); + + parameter DATA_WIDTH = 10; + parameter BUFFER_DEPTH = 8; + + input clk; + input rstn; + input [DATA_WIDTH - 1 : 0] data; + input valid; + output ready; + + output [BUFFER_DEPTH - 1 : 0] write_token; + input [BUFFER_DEPTH - 1 : 0] read_pointer; + + output [DATA_WIDTH - 1 : 0] data_async; + + wire stall; + wire write_enable; + wire [BUFFER_DEPTH - 1 : 0] write_pointer; + + assign ready = ~stall; + + // FIFO read/write enable + assign write_enable = (valid & ready); + + // Actual FIFO + dc_data_buffer + #( + .DATA_WIDTH ( DATA_WIDTH ), + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) + buffer + ( + .clk ( clk ), + .rstn ( rstn ), + .write_pointer ( write_pointer ), + .write_data ( data ), + .read_pointer ( read_pointer ), + .read_data ( data_async ) + ); + + // Logic to compute the read, write pointers + dc_token_ring + #( + .BUFFER_DEPTH ( BUFFER_DEPTH ), + .RESET_VALUE ( 'hc ) + ) + write_tr + ( + .clk ( clk ), + .rstn ( rstn ), + .enable ( write_enable ), + .state ( write_token ) + ); + + // Pointers to the write, read addresses (semi-accurate, leveraging the two-hot encoding for extra robustness) + assign write_pointer = {write_token[BUFFER_DEPTH - 2 : 0], write_token[BUFFER_DEPTH - 1]} & write_token; + + // Full detector + dc_full_detector + #( + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) + full + ( + .clk ( clk ), + .rstn ( rstn ), + .read_pointer ( read_pointer ), + .write_pointer ( write_pointer ), + .valid ( valid ), + .full ( stall ) + ); + +endmodule
diff --git a/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring_fifo_dout.v b/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring_fifo_dout.v new file mode 100644 index 0000000..48c2758 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_slice_dc/dc_token_ring_fifo_dout.v
@@ -0,0 +1,77 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_token_ring_fifo_dout(clk, rstn, data_async, write_token, read_pointer, data, valid, ready); + + parameter DATA_WIDTH = 10; + parameter BUFFER_DEPTH = 8; + + input [DATA_WIDTH - 1 : 0] data_async; + + input clk; + input rstn; + output [DATA_WIDTH - 1 : 0] data; + output valid; + input ready; + + input [BUFFER_DEPTH - 1 : 0] write_token; + output [BUFFER_DEPTH - 1 : 0] read_pointer; + + wire read_enable; + wire stall; + // Pointers to the write, read addresses (two-hot encoding) + wire [BUFFER_DEPTH - 1 : 0] read_token; + + wire [BUFFER_DEPTH - 1 : 0] write_token_dn; + wire [BUFFER_DEPTH - 1 : 0] empty; + + assign data = data_async; + + assign stall = ~ready; + + // FIFO read/write enable + assign read_enable = (valid & ~stall); + + // Logic to compute the read, write pointers + dc_token_ring + #( + .BUFFER_DEPTH ( BUFFER_DEPTH ), + .RESET_VALUE ( 'h3 ) + ) + read_tr + ( + .clk ( clk ), + .rstn ( rstn ), + .enable ( read_enable ), + .state ( read_token ) + ); + + // Pointers to the write, read addresses (semi-accurate, leveraging the two-hot encoding for extra robustness) + assign read_pointer = {read_token[BUFFER_DEPTH - 3 : 0], read_token[BUFFER_DEPTH - 1 : BUFFER_DEPTH - 2]} & + {read_token[BUFFER_DEPTH - 4 : 0], read_token[BUFFER_DEPTH - 1 : BUFFER_DEPTH - 3]}; + + // Empty detector; if any of the bits is 1, the synchronizer is empty + dc_synchronizer + #( + .WIDTH ( BUFFER_DEPTH ), + .RESET_VALUE ( 'hc ) + ) + empty_synch + ( + .clk ( clk ), + .rstn ( rstn ), + .d_in ( write_token ), + .d_out ( write_token_dn ) + ); + + assign empty = ~write_token_dn & {write_token_dn[0], write_token_dn[BUFFER_DEPTH - 1 : 1]} & {read_pointer[1 : 0], read_pointer[BUFFER_DEPTH - 1 : 2]}; + assign valid = ~(|empty); + +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_master/axi_spi_master.v b/verilog/rtl/ips/axi/axi_spi_master/axi_spi_master.v new file mode 100644 index 0000000..1b0c2b5 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_master/axi_spi_master.v
@@ -0,0 +1,295 @@ +`define log2(VALUE) ((VALUE) < ( 1 ) ? 0 : (VALUE) < ( 2 ) ? 1 : (VALUE) < ( 4 ) ? 2 : (VALUE) < ( 8 ) ? 3 : (VALUE) < ( 16 ) ? 4 : (VALUE) < ( 32 ) ? 5 : (VALUE) < ( 64 ) ? 6 : (VALUE) < ( 128 ) ? 7 : (VALUE) < ( 256 ) ? 8 : (VALUE) < ( 512 ) ? 9 : (VALUE) < ( 1024 ) ? 10 : (VALUE) < ( 2048 ) ? 11 : (VALUE) < ( 4096 ) ? 12 : (VALUE) < ( 8192 ) ? 13 : (VALUE) < ( 16384 ) ? 14 : (VALUE) < ( 32768 ) ? 15 : (VALUE) < ( 65536 ) ? 16 : (VALUE) < ( 131072 ) ? 17 : (VALUE) < ( 262144 ) ? 18 : (VALUE) < ( 524288 ) ? 19 : (VALUE) < ( 1048576 ) ? 20 : (VALUE) < ( 1048576 * 2 ) ? 21 : (VALUE) < ( 1048576 * 4 ) ? 22 : (VALUE) < ( 1048576 * 8 ) ? 23 : (VALUE) < ( 1048576 * 16 ) ? 24 : 25) + +module axi_spi_master +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 32, + parameter AXI4_WDATA_WIDTH = 32, + parameter AXI4_USER_WIDTH = 4, + parameter AXI4_ID_WIDTH = 16, + parameter BUFFER_DEPTH = 8 +) +( + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awid, + s_axi_awlen, + s_axi_awaddr, + s_axi_awuser, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wready, + s_axi_bvalid, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bready, + s_axi_arvalid, + s_axi_arid, + s_axi_arlen, + s_axi_araddr, + s_axi_aruser, + s_axi_arready, + s_axi_rvalid, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rready, + events_o, + spi_clk, + spi_csn0, + spi_csn1, + spi_csn2, + spi_csn3, + spi_mode, + spi_sdo0, + spi_sdo1, + spi_sdo2, + spi_sdo3, + spi_sdi0, + spi_sdi1, + spi_sdi2, + spi_sdi3 +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 32; + //parameter AXI4_WDATA_WIDTH = 32; + //parameter AXI4_USER_WIDTH = 4; + //parameter AXI4_ID_WIDTH = 16; + //parameter BUFFER_DEPTH = 8; + input wire s_axi_aclk; + input wire s_axi_aresetn; + input wire s_axi_awvalid; + input wire [AXI4_ID_WIDTH - 1:0] s_axi_awid; + input wire [7:0] s_axi_awlen; + input wire [AXI4_ADDRESS_WIDTH - 1:0] s_axi_awaddr; + input wire [AXI4_USER_WIDTH - 1:0] s_axi_awuser; + output wire s_axi_awready; + input wire s_axi_wvalid; + input wire [AXI4_WDATA_WIDTH - 1:0] s_axi_wdata; + input wire [(AXI4_WDATA_WIDTH / 8) - 1:0] s_axi_wstrb; + input wire s_axi_wlast; + input wire [AXI4_USER_WIDTH - 1:0] s_axi_wuser; + output wire s_axi_wready; + output wire s_axi_bvalid; + output wire [AXI4_ID_WIDTH - 1:0] s_axi_bid; + output wire [1:0] s_axi_bresp; + output wire [AXI4_USER_WIDTH - 1:0] s_axi_buser; + input wire s_axi_bready; + input wire s_axi_arvalid; + input wire [AXI4_ID_WIDTH - 1:0] s_axi_arid; + input wire [7:0] s_axi_arlen; + input wire [AXI4_ADDRESS_WIDTH - 1:0] s_axi_araddr; + input wire [AXI4_USER_WIDTH - 1:0] s_axi_aruser; + output wire s_axi_arready; + output wire s_axi_rvalid; + output wire [AXI4_ID_WIDTH - 1:0] s_axi_rid; + output wire [AXI4_RDATA_WIDTH - 1:0] s_axi_rdata; + output wire [1:0] s_axi_rresp; + output wire s_axi_rlast; + output wire [AXI4_USER_WIDTH - 1:0] s_axi_ruser; + input wire s_axi_rready; + output wire [1:0] events_o; + output wire spi_clk; + output wire spi_csn0; + output wire spi_csn1; + output wire spi_csn2; + output wire spi_csn3; + output wire [1:0] spi_mode; + output wire spi_sdo0; + output wire spi_sdo1; + output wire spi_sdo2; + output wire spi_sdo3; + input wire spi_sdi0; + input wire spi_sdi1; + input wire spi_sdi2; + input wire spi_sdi3; + localparam LOG_BUFFER_DEPTH = (BUFFER_DEPTH < 1 ? 0 : (BUFFER_DEPTH < 2 ? 1 : (BUFFER_DEPTH < 4 ? 2 : (BUFFER_DEPTH < 8 ? 3 : (BUFFER_DEPTH < 16 ? 4 : (BUFFER_DEPTH < 32 ? 5 : (BUFFER_DEPTH < 64 ? 6 : (BUFFER_DEPTH < 128 ? 7 : (BUFFER_DEPTH < 256 ? 8 : (BUFFER_DEPTH < 512 ? 9 : (BUFFER_DEPTH < 1024 ? 10 : (BUFFER_DEPTH < 2048 ? 11 : (BUFFER_DEPTH < 4096 ? 12 : (BUFFER_DEPTH < 8192 ? 13 : (BUFFER_DEPTH < 16384 ? 14 : (BUFFER_DEPTH < 32768 ? 15 : (BUFFER_DEPTH < 65536 ? 16 : (BUFFER_DEPTH < 131072 ? 17 : (BUFFER_DEPTH < 262144 ? 18 : (BUFFER_DEPTH < 524288 ? 19 : (BUFFER_DEPTH < 1048576 ? 20 : (BUFFER_DEPTH < 2097152 ? 21 : (BUFFER_DEPTH < 4194304 ? 22 : (BUFFER_DEPTH < 8388608 ? 23 : (BUFFER_DEPTH < 16777216 ? 24 : 25))))))))))))))))))))))))); + wire [7:0] spi_clk_div; + wire spi_clk_div_valid; + wire [31:0] spi_status; + wire [31:0] spi_addr; + wire [5:0] spi_addr_len; + wire [31:0] spi_cmd; + wire [5:0] spi_cmd_len; + wire [15:0] spi_data_len; + wire [15:0] spi_dummy_rd; + wire [15:0] spi_dummy_wr; + wire spi_swrst; + wire spi_rd; + wire spi_wr; + wire spi_qrd; + wire spi_qwr; + wire [3:0] spi_csreg; + wire [31:0] spi_data_tx; + wire spi_data_tx_valid; + wire spi_data_tx_ready; + wire [31:0] spi_data_rx; + wire spi_data_rx_valid; + wire spi_data_rx_ready; + wire [6:0] spi_ctrl_status; + wire [31:0] spi_ctrl_data_tx; + wire spi_ctrl_data_tx_valid; + wire spi_ctrl_data_tx_ready; + wire [31:0] spi_ctrl_data_rx; + wire spi_ctrl_data_rx_valid; + wire spi_ctrl_data_rx_ready; + wire s_eot; + wire [LOG_BUFFER_DEPTH:0] elements_tx; + wire [LOG_BUFFER_DEPTH:0] elements_rx; + reg [LOG_BUFFER_DEPTH:0] elements_tx_old; + reg [LOG_BUFFER_DEPTH:0] elements_rx_old; + localparam FILL_BITS = 7 - LOG_BUFFER_DEPTH; + assign spi_status = {{FILL_BITS {1'b0}}, elements_tx, {FILL_BITS {1'b0}}, elements_rx, 9'h000, spi_ctrl_status}; + assign events_o[0] = ((elements_rx == 4'b0100) && (elements_rx_old == 4'b0101)) || ((elements_tx == 4'b0101) && (elements_tx_old == 4'b0100)); + assign events_o[1] = s_eot; + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (s_axi_aresetn == 1'b0) begin + elements_rx_old <= 'h0; + elements_tx_old <= 'h0; + end + else begin + elements_rx_old <= elements_rx; + elements_tx_old <= elements_tx; + end + spi_master_axi_if #( + .AXI4_ADDRESS_WIDTH(AXI4_ADDRESS_WIDTH), + .AXI4_RDATA_WIDTH(AXI4_RDATA_WIDTH), + .AXI4_WDATA_WIDTH(AXI4_WDATA_WIDTH), + .AXI4_USER_WIDTH(AXI4_USER_WIDTH), + .AXI4_ID_WIDTH(AXI4_ID_WIDTH) + ) u_axiregs( + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awuser(s_axi_awuser), + .s_axi_awready(s_axi_awready), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), + .s_axi_wuser(s_axi_wuser), + .s_axi_wready(s_axi_wready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(s_axi_buser), + .s_axi_bready(s_axi_bready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_araddr(s_axi_araddr), + .s_axi_aruser(s_axi_aruser), + .s_axi_arready(s_axi_arready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rid(s_axi_rid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rresp(s_axi_rresp), + .s_axi_rlast(s_axi_rlast), + .s_axi_ruser(s_axi_ruser), + .s_axi_rready(s_axi_rready), + .spi_clk_div(spi_clk_div), + .spi_clk_div_valid(spi_clk_div_valid), + .spi_status(spi_status), + .spi_addr(spi_addr), + .spi_addr_len(spi_addr_len), + .spi_cmd(spi_cmd), + .spi_cmd_len(spi_cmd_len), + .spi_data_len(spi_data_len), + .spi_dummy_rd(spi_dummy_rd), + .spi_dummy_wr(spi_dummy_wr), + .spi_swrst(spi_swrst), + .spi_rd(spi_rd), + .spi_wr(spi_wr), + .spi_qrd(spi_qrd), + .spi_qwr(spi_qwr), + .spi_csreg(spi_csreg), + .spi_data_tx(spi_data_tx), + .spi_data_tx_valid(spi_data_tx_valid), + .spi_data_tx_ready(spi_data_tx_ready), + .spi_data_rx(spi_data_rx), + .spi_data_rx_valid(spi_data_rx_valid), + .spi_data_rx_ready(spi_data_rx_ready) + ); + spi_master_fifo #( + .DATA_WIDTH(32), + .BUFFER_DEPTH(BUFFER_DEPTH) + ) u_txfifo( + .clk_i(s_axi_aclk), + .rst_ni(s_axi_aresetn), + .clr_i(spi_swrst), + .elements_o(elements_tx), + .data_o(spi_ctrl_data_tx), + .valid_o(spi_ctrl_data_tx_valid), + .ready_i(spi_ctrl_data_tx_ready), + .valid_i(spi_data_tx_valid), + .data_i(spi_data_tx), + .ready_o(spi_data_tx_ready) + ); + spi_master_fifo #( + .DATA_WIDTH(32), + .BUFFER_DEPTH(BUFFER_DEPTH) + ) u_rxfifo( + .clk_i(s_axi_aclk), + .rst_ni(s_axi_aresetn), + .clr_i(spi_swrst), + .elements_o(elements_rx), + .data_o(spi_data_rx), + .valid_o(spi_data_rx_valid), + .ready_i(spi_data_rx_ready), + .valid_i(spi_ctrl_data_rx_valid), + .data_i(spi_ctrl_data_rx), + .ready_o(spi_ctrl_data_rx_ready) + ); + spi_master_controller u_spictrl( + .clk(s_axi_aclk), + .rstn(s_axi_aresetn), + .eot(s_eot), + .spi_clk_div(spi_clk_div), + .spi_clk_div_valid(spi_clk_div_valid), + .spi_status(spi_ctrl_status), + .spi_addr(spi_addr), + .spi_addr_len(spi_addr_len), + .spi_cmd(spi_cmd), + .spi_cmd_len(spi_cmd_len), + .spi_data_len(spi_data_len), + .spi_dummy_rd(spi_dummy_rd), + .spi_dummy_wr(spi_dummy_wr), + .spi_swrst(spi_swrst), + .spi_rd(spi_rd), + .spi_wr(spi_wr), + .spi_qrd(spi_qrd), + .spi_qwr(spi_qwr), + .spi_csreg(spi_csreg), + .spi_ctrl_data_tx(spi_ctrl_data_tx), + .spi_ctrl_data_tx_valid(spi_ctrl_data_tx_valid), + .spi_ctrl_data_tx_ready(spi_ctrl_data_tx_ready), + .spi_ctrl_data_rx(spi_ctrl_data_rx), + .spi_ctrl_data_rx_valid(spi_ctrl_data_rx_valid), + .spi_ctrl_data_rx_ready(spi_ctrl_data_rx_ready), + .spi_clk(spi_clk), + .spi_csn0(spi_csn0), + .spi_csn1(spi_csn1), + .spi_csn2(spi_csn2), + .spi_csn3(spi_csn3), + .spi_mode(spi_mode), + .spi_sdo0(spi_sdo0), + .spi_sdo1(spi_sdo1), + .spi_sdo2(spi_sdo2), + .spi_sdo3(spi_sdo3), + .spi_sdi0(spi_sdi0), + .spi_sdi1(spi_sdi1), + .spi_sdi2(spi_sdi2), + .spi_sdi3(spi_sdi3) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_master/spi_master_axi_if.v b/verilog/rtl/ips/axi/axi_spi_master/spi_master_axi_if.v new file mode 100644 index 0000000..45418d4 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_master/spi_master_axi_if.v
@@ -0,0 +1,617 @@ +`define log2(VALUE) ((VALUE) < ( 1 ) ? 0 : (VALUE) < ( 2 ) ? 1 : (VALUE) < ( 4 ) ? 2 : (VALUE) < ( 8 ) ? 3 : (VALUE) < ( 16 ) ? 4 : (VALUE) < ( 32 ) ? 5 : (VALUE) < ( 64 ) ? 6 : (VALUE) < ( 128 ) ? 7 : (VALUE) < ( 256 ) ? 8 : (VALUE) < ( 512 ) ? 9 : (VALUE) < ( 1024 ) ? 10 : (VALUE) < ( 2048 ) ? 11 : (VALUE) < ( 4096 ) ? 12 : (VALUE) < ( 8192 ) ? 13 : (VALUE) < ( 16384 ) ? 14 : (VALUE) < ( 32768 ) ? 15 : (VALUE) < ( 65536 ) ? 16 : (VALUE) < ( 131072 ) ? 17 : (VALUE) < ( 262144 ) ? 18 : (VALUE) < ( 524288 ) ? 19 : (VALUE) < ( 1048576 ) ? 20 : (VALUE) < ( 1048576 * 2 ) ? 21 : (VALUE) < ( 1048576 * 4 ) ? 22 : (VALUE) < ( 1048576 * 8 ) ? 23 : (VALUE) < ( 1048576 * 16 ) ? 24 : 25) + +module spi_master_axi_if +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 32, + parameter AXI4_WDATA_WIDTH = 32, + parameter AXI4_USER_WIDTH = 4, + parameter AXI4_ID_WIDTH = 16 + ) +( + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awid, + s_axi_awlen, + s_axi_awaddr, + s_axi_awuser, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wready, + s_axi_bvalid, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bready, + s_axi_arvalid, + s_axi_arid, + s_axi_arlen, + s_axi_araddr, + s_axi_aruser, + s_axi_arready, + s_axi_rvalid, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rready, + spi_clk_div, + spi_clk_div_valid, + spi_status, + spi_addr, + spi_addr_len, + spi_cmd, + spi_cmd_len, + spi_csreg, + spi_data_len, + spi_dummy_rd, + spi_dummy_wr, + spi_swrst, + spi_rd, + spi_wr, + spi_qrd, + spi_qwr, + spi_data_tx, + spi_data_tx_valid, + spi_data_tx_ready, + spi_data_rx, + spi_data_rx_valid, + spi_data_rx_ready +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 32; + //parameter AXI4_WDATA_WIDTH = 32; + //parameter AXI4_USER_WIDTH = 4; + //parameter AXI4_ID_WIDTH = 16; + input wire s_axi_aclk; + input wire s_axi_aresetn; + input wire s_axi_awvalid; + input wire [AXI4_ID_WIDTH - 1:0] s_axi_awid; + input wire [7:0] s_axi_awlen; + input wire [AXI4_ADDRESS_WIDTH - 1:0] s_axi_awaddr; + input wire [AXI4_USER_WIDTH - 1:0] s_axi_awuser; + output reg s_axi_awready; + input wire s_axi_wvalid; + input wire [AXI4_WDATA_WIDTH - 1:0] s_axi_wdata; + input wire [(AXI4_WDATA_WIDTH / 8) - 1:0] s_axi_wstrb; + input wire s_axi_wlast; + input wire [AXI4_USER_WIDTH - 1:0] s_axi_wuser; + output reg s_axi_wready; + output reg s_axi_bvalid; + output reg [AXI4_ID_WIDTH - 1:0] s_axi_bid; + output reg [1:0] s_axi_bresp; + output reg [AXI4_USER_WIDTH - 1:0] s_axi_buser; + input wire s_axi_bready; + input wire s_axi_arvalid; + input wire [AXI4_ID_WIDTH - 1:0] s_axi_arid; + input wire [7:0] s_axi_arlen; + input wire [AXI4_ADDRESS_WIDTH - 1:0] s_axi_araddr; + input wire [AXI4_USER_WIDTH - 1:0] s_axi_aruser; + output reg s_axi_arready; + output reg s_axi_rvalid; + output reg [AXI4_ID_WIDTH - 1:0] s_axi_rid; + output reg [AXI4_RDATA_WIDTH - 1:0] s_axi_rdata; + output reg [1:0] s_axi_rresp; + output reg s_axi_rlast; + output reg [AXI4_USER_WIDTH - 1:0] s_axi_ruser; + input wire s_axi_rready; + output reg [7:0] spi_clk_div; + output reg spi_clk_div_valid; + input wire [31:0] spi_status; + output reg [31:0] spi_addr; + output reg [5:0] spi_addr_len; + output reg [31:0] spi_cmd; + output reg [5:0] spi_cmd_len; + output reg [3:0] spi_csreg; + output reg [15:0] spi_data_len; + output reg [15:0] spi_dummy_rd; + output reg [15:0] spi_dummy_wr; + output reg spi_swrst; + output reg spi_rd; + output reg spi_wr; + output reg spi_qrd; + output reg spi_qwr; + output wire [31:0] spi_data_tx; + output wire spi_data_tx_valid; + input wire spi_data_tx_ready; + input wire [31:0] spi_data_rx; + input wire spi_data_rx_valid; + output reg spi_data_rx_ready; + localparam WR_ADDR_CMP = ((AXI4_WDATA_WIDTH / 8) < 1 ? 0 : ((AXI4_WDATA_WIDTH / 8) < 2 ? 1 : ((AXI4_WDATA_WIDTH / 8) < 4 ? 2 : ((AXI4_WDATA_WIDTH / 8) < 8 ? 3 : ((AXI4_WDATA_WIDTH / 8) < 16 ? 4 : ((AXI4_WDATA_WIDTH / 8) < 32 ? 5 : ((AXI4_WDATA_WIDTH / 8) < 64 ? 6 : ((AXI4_WDATA_WIDTH / 8) < 128 ? 7 : ((AXI4_WDATA_WIDTH / 8) < 256 ? 8 : ((AXI4_WDATA_WIDTH / 8) < 512 ? 9 : ((AXI4_WDATA_WIDTH / 8) < 1024 ? 10 : ((AXI4_WDATA_WIDTH / 8) < 2048 ? 11 : ((AXI4_WDATA_WIDTH / 8) < 4096 ? 12 : ((AXI4_WDATA_WIDTH / 8) < 8192 ? 13 : ((AXI4_WDATA_WIDTH / 8) < 16384 ? 14 : ((AXI4_WDATA_WIDTH / 8) < 32768 ? 15 : ((AXI4_WDATA_WIDTH / 8) < 65536 ? 16 : ((AXI4_WDATA_WIDTH / 8) < 131072 ? 17 : ((AXI4_WDATA_WIDTH / 8) < 262144 ? 18 : ((AXI4_WDATA_WIDTH / 8) < 524288 ? 19 : ((AXI4_WDATA_WIDTH / 8) < 1048576 ? 20 : ((AXI4_WDATA_WIDTH / 8) < 2097152 ? 21 : ((AXI4_WDATA_WIDTH / 8) < 4194304 ? 22 : ((AXI4_WDATA_WIDTH / 8) < 8388608 ? 23 : ((AXI4_WDATA_WIDTH / 8) < 16777216 ? 24 : 25))))))))))))))))))))))))) - 1; + localparam RD_ADDR_CMP = ((AXI4_RDATA_WIDTH / 8) < 1 ? 0 : ((AXI4_RDATA_WIDTH / 8) < 2 ? 1 : ((AXI4_RDATA_WIDTH / 8) < 4 ? 2 : ((AXI4_RDATA_WIDTH / 8) < 8 ? 3 : ((AXI4_RDATA_WIDTH / 8) < 16 ? 4 : ((AXI4_RDATA_WIDTH / 8) < 32 ? 5 : ((AXI4_RDATA_WIDTH / 8) < 64 ? 6 : ((AXI4_RDATA_WIDTH / 8) < 128 ? 7 : ((AXI4_RDATA_WIDTH / 8) < 256 ? 8 : ((AXI4_RDATA_WIDTH / 8) < 512 ? 9 : ((AXI4_RDATA_WIDTH / 8) < 1024 ? 10 : ((AXI4_RDATA_WIDTH / 8) < 2048 ? 11 : ((AXI4_RDATA_WIDTH / 8) < 4096 ? 12 : ((AXI4_RDATA_WIDTH / 8) < 8192 ? 13 : ((AXI4_RDATA_WIDTH / 8) < 16384 ? 14 : ((AXI4_RDATA_WIDTH / 8) < 32768 ? 15 : ((AXI4_RDATA_WIDTH / 8) < 65536 ? 16 : ((AXI4_RDATA_WIDTH / 8) < 131072 ? 17 : ((AXI4_RDATA_WIDTH / 8) < 262144 ? 18 : ((AXI4_RDATA_WIDTH / 8) < 524288 ? 19 : ((AXI4_RDATA_WIDTH / 8) < 1048576 ? 20 : ((AXI4_RDATA_WIDTH / 8) < 2097152 ? 21 : ((AXI4_RDATA_WIDTH / 8) < 4194304 ? 22 : ((AXI4_RDATA_WIDTH / 8) < 8388608 ? 23 : ((AXI4_RDATA_WIDTH / 8) < 16777216 ? 24 : 25))))))))))))))))))))))))) - 1; + localparam OFFSET_BIT = ((AXI4_WDATA_WIDTH - 1) < 1 ? 0 : ((AXI4_WDATA_WIDTH - 1) < 2 ? 1 : ((AXI4_WDATA_WIDTH - 1) < 4 ? 2 : ((AXI4_WDATA_WIDTH - 1) < 8 ? 3 : ((AXI4_WDATA_WIDTH - 1) < 16 ? 4 : ((AXI4_WDATA_WIDTH - 1) < 32 ? 5 : ((AXI4_WDATA_WIDTH - 1) < 64 ? 6 : ((AXI4_WDATA_WIDTH - 1) < 128 ? 7 : ((AXI4_WDATA_WIDTH - 1) < 256 ? 8 : ((AXI4_WDATA_WIDTH - 1) < 512 ? 9 : ((AXI4_WDATA_WIDTH - 1) < 1024 ? 10 : ((AXI4_WDATA_WIDTH - 1) < 2048 ? 11 : ((AXI4_WDATA_WIDTH - 1) < 4096 ? 12 : ((AXI4_WDATA_WIDTH - 1) < 8192 ? 13 : ((AXI4_WDATA_WIDTH - 1) < 16384 ? 14 : ((AXI4_WDATA_WIDTH - 1) < 32768 ? 15 : ((AXI4_WDATA_WIDTH - 1) < 65536 ? 16 : ((AXI4_WDATA_WIDTH - 1) < 131072 ? 17 : ((AXI4_WDATA_WIDTH - 1) < 262144 ? 18 : ((AXI4_WDATA_WIDTH - 1) < 524288 ? 19 : ((AXI4_WDATA_WIDTH - 1) < 1048576 ? 20 : ((AXI4_WDATA_WIDTH - 1) < 2097152 ? 21 : ((AXI4_WDATA_WIDTH - 1) < 4194304 ? 22 : ((AXI4_WDATA_WIDTH - 1) < 8388608 ? 23 : ((AXI4_WDATA_WIDTH - 1) < 16777216 ? 24 : 25))))))))))))))))))))))))) - 3; + wire [4:0] wr_addr; + wire [4:0] rd_addr; + wire is_tx_fifo_sel; + wire is_rx_fifo_sel; + reg is_tx_fifo_sel_q; + reg is_rx_fifo_sel_q; + reg read_req; + reg [4:0] read_address; + reg sample_AR; + reg [4:0] ARADDR_Q; + reg [7:0] ARLEN_Q; + reg decr_ARLEN; + reg [7:0] CountBurstCS; + reg [7:0] CountBurstNS; + reg [AXI4_ID_WIDTH - 1:0] ARID_Q; + reg [AXI4_USER_WIDTH - 1:0] ARUSER_Q; + reg write_req; + reg [4:0] write_address; + reg sample_AW; + reg [4:0] AWADDR_Q; + reg [7:0] AWLEN_Q; + reg decr_AWLEN; + reg [7:0] CountBurst_AW_CS; + reg [7:0] CountBurst_AW_NS; + reg [AXI4_ID_WIDTH - 1:0] AWID_Q; + reg [AXI4_USER_WIDTH - 1:0] AWUSER_Q; + reg [2:0] AR_CS; + reg [2:0] AR_NS; + reg [2:0] AW_CS; + reg [2:0] AW_NS; + assign wr_addr = s_axi_awaddr[WR_ADDR_CMP + 4:WR_ADDR_CMP]; + assign rd_addr = s_axi_araddr[RD_ADDR_CMP + 4:RD_ADDR_CMP]; + assign is_tx_fifo_sel = wr_addr[3] == 1'b1; + assign is_rx_fifo_sel = rd_addr[4] == 1'b1; + assign spi_data_tx = s_axi_wdata[31:0]; + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (s_axi_aresetn == 1'b0) begin + AR_CS <= 3'd0; + ARADDR_Q <= 1'sb0; + CountBurstCS <= 1'sb0; + ARID_Q <= 1'sb0; + ARUSER_Q <= 1'sb0; + is_tx_fifo_sel_q <= 1'sb0; + is_rx_fifo_sel_q <= 1'sb0; + end + else begin + AR_CS <= AR_NS; + CountBurstCS <= CountBurstNS; + is_tx_fifo_sel_q <= is_tx_fifo_sel; + is_rx_fifo_sel_q <= is_rx_fifo_sel; + if (sample_AR) + ARLEN_Q <= s_axi_arlen; + else if (decr_ARLEN) + ARLEN_Q <= ARLEN_Q - 1'b1; + if (sample_AR) begin + ARID_Q <= s_axi_arid; + ARADDR_Q <= read_address; + ARUSER_Q <= s_axi_aruser; + end + end + always @(*) begin + s_axi_arready = 1'b0; + read_address = 1'sb0; + read_req = 1'b0; + sample_AR = 1'b0; + decr_ARLEN = 1'b0; + CountBurstNS = CountBurstCS; + spi_data_rx_ready = 1'b0; + s_axi_rvalid = 1'b0; + s_axi_rresp = 2'b00; + s_axi_ruser = 1'sb0; + s_axi_rlast = 1'b0; + s_axi_rid = 1'sb0; + AR_NS = AR_CS; + case (AR_CS) + 3'd0: begin + s_axi_arready = 1'b1; + if (s_axi_arvalid) begin + sample_AR = 1'b1; + read_req = 1'b1; + read_address = rd_addr; + if (s_axi_arlen == 0) begin + AR_NS = 3'd1; + CountBurstNS = 1'sb0; + end + else begin + AR_NS = 3'd2; + CountBurstNS = CountBurstCS + 1'b1; + end + end + else begin + AR_NS = 3'd0; + CountBurstNS = 1'sb0; + end + end + 3'd1: begin + s_axi_rresp = 2'b00; + s_axi_rid = ARID_Q; + s_axi_ruser = ARUSER_Q; + s_axi_rlast = 1'b1; + read_address = ARADDR_Q; + if (is_rx_fifo_sel_q) + s_axi_rvalid = spi_data_rx_valid; + else + s_axi_rvalid = 1'b1; + if ((s_axi_rready && !is_rx_fifo_sel_q) | ((s_axi_rready && is_rx_fifo_sel_q) && spi_data_rx_valid)) begin + if (is_rx_fifo_sel_q) + spi_data_rx_ready = 1'b1; + s_axi_arready = 1'b1; + if (s_axi_arvalid) begin + sample_AR = 1'b1; + read_req = 1'b1; + read_address = rd_addr; + if (s_axi_arlen == 0) begin + AR_NS = 3'd1; + CountBurstNS = 1'sb0; + end + else begin + AR_NS = 3'd2; + CountBurstNS = CountBurstCS + 1'b1; + end + end + else begin + AR_NS = 3'd0; + CountBurstNS = 1'sb0; + end + end + else begin + AR_NS = 3'd1; + read_req = 1'b1; + read_address = ARADDR_Q; + CountBurstNS = 1'sb0; + end + end + 3'd2: begin + s_axi_rresp = 2'b00; + s_axi_rid = ARID_Q; + s_axi_ruser = ARUSER_Q; + read_address = ARADDR_Q; + if (is_rx_fifo_sel_q) + s_axi_rvalid = spi_data_rx_valid; + else + s_axi_rvalid = 1'b1; + if ((s_axi_rready && !is_rx_fifo_sel_q) | ((s_axi_rready && is_rx_fifo_sel_q) && spi_data_rx_valid)) begin + if (is_rx_fifo_sel_q) + spi_data_rx_ready = 1'b1; + if (ARLEN_Q > 0) begin + AR_NS = 3'd2; + read_req = 1'b1; + decr_ARLEN = 1'b1; + read_address = ARADDR_Q + CountBurstCS; + s_axi_rlast = 1'b0; + s_axi_arready = 1'b0; + end + else begin + s_axi_rlast = 1'b1; + s_axi_arready = 1'b1; + if (s_axi_arvalid) begin + sample_AR = 1'b1; + read_req = 1'b1; + read_address = rd_addr; + if (s_axi_arlen == 0) begin + AR_NS = 3'd1; + CountBurstNS = 0; + end + else begin + AR_NS = 3'd2; + CountBurstNS = 1; + end + end + else begin + AR_NS = 3'd0; + CountBurstNS = 0; + end + end + end + else begin + AR_NS = 3'd2; + read_req = 1'b1; + decr_ARLEN = 1'b0; + read_address = ARADDR_Q + CountBurstCS; + s_axi_arready = 1'b0; + end + end + default: + ; + endcase + end + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (s_axi_aresetn == 1'b0) begin + AW_CS <= 3'd0; + AWADDR_Q <= 1'sb0; + CountBurst_AW_CS <= 1'sb0; + AWID_Q <= 1'sb0; + AWUSER_Q <= 1'sb0; + end + else begin + AW_CS <= AW_NS; + CountBurst_AW_CS <= CountBurst_AW_NS; + if (sample_AW) begin + AWLEN_Q <= s_axi_awlen; + AWADDR_Q <= wr_addr; + AWID_Q <= s_axi_awid; + AWUSER_Q <= s_axi_awuser; + end + else if (decr_AWLEN) + AWLEN_Q <= AWLEN_Q - 1'b1; + end + always @(*) begin + s_axi_awready = 1'b0; + s_axi_wready = 1'b0; + write_address = 1'sb0; + write_req = 1'b0; + sample_AW = 1'b0; + decr_AWLEN = 1'b0; + CountBurst_AW_NS = CountBurst_AW_CS; + s_axi_bid = 1'sb0; + s_axi_bresp = 2'b00; + s_axi_buser = 1'sb0; + s_axi_bvalid = 1'b0; + AW_NS = AW_CS; + case (AW_CS) + 3'd0: begin + s_axi_awready = 1'b1; + if (s_axi_awvalid) begin + sample_AW = 1'b1; + if (s_axi_wvalid) begin + s_axi_wready = 1'b1; + write_req = 1'b1; + write_address = wr_addr; + if (s_axi_awlen == 0) begin + AW_NS = 3'd1; + CountBurst_AW_NS = 0; + end + else begin + AW_NS = 3'd2; + CountBurst_AW_NS = 1; + end + end + else begin + s_axi_wready = 1'b1; + write_req = 1'b0; + write_address = 1'sb0; + if (s_axi_awlen == 0) begin + AW_NS = 3'd4; + CountBurst_AW_NS = 0; + end + else begin + AW_NS = 3'd3; + CountBurst_AW_NS = 0; + end + end + end + else begin + s_axi_wready = 1'b1; + AW_NS = 3'd0; + CountBurst_AW_NS = 1'sb0; + end + end + 3'd3: begin + s_axi_awready = 1'b0; + if (s_axi_wvalid) begin + s_axi_wready = 1'b1; + write_req = 1'b1; + write_address = AWADDR_Q; + AW_NS = 3'd2; + CountBurst_AW_NS = 1; + decr_AWLEN = 1'b1; + end + else begin + s_axi_wready = 1'b1; + write_req = 1'b0; + AW_NS = 3'd3; + CountBurst_AW_NS = 1'sb0; + end + end + 3'd4: begin + s_axi_awready = 1'b0; + CountBurst_AW_NS = 1'sb0; + if (s_axi_wvalid) begin + s_axi_wready = 1'b1; + write_req = 1'b1; + write_address = AWADDR_Q; + AW_NS = 3'd1; + end + else begin + s_axi_wready = 1'b1; + write_req = 1'b0; + AW_NS = 3'd4; + end + end + 3'd1: begin + s_axi_bid = AWID_Q; + s_axi_bresp = 2'b00; + s_axi_buser = AWUSER_Q; + s_axi_bvalid = 1'b1; + if (s_axi_bready) begin + s_axi_awready = 1'b1; + if (s_axi_awvalid) begin + sample_AW = 1'b1; + write_req = 1'b1; + write_address = wr_addr; + if (s_axi_awlen == 0) begin + AW_NS = 3'd1; + CountBurst_AW_NS = 1'sb0; + end + else begin + AW_NS = 3'd2; + CountBurst_AW_NS = CountBurst_AW_CS + 1'b1; + end + end + else begin + AW_NS = 3'd0; + CountBurst_AW_NS = 1'sb0; + end + end + else begin + AW_NS = 3'd1; + CountBurst_AW_NS = 1'sb0; + s_axi_awready = 1'b0; + end + end + 3'd2: begin + CountBurst_AW_NS = CountBurst_AW_CS; + s_axi_awready = 1'b0; + write_address = AWADDR_Q; + if (s_axi_wvalid) begin + s_axi_wready = 1'b1; + write_req = 1'b1; + decr_AWLEN = 1'b1; + CountBurst_AW_NS = CountBurst_AW_CS + 1'b1; + end + else begin + s_axi_wready = 1'b1; + write_req = 1'b0; + decr_AWLEN = 1'b0; + end + if (AWLEN_Q > 0) + AW_NS = 3'd2; + else + AW_NS = 3'd5; + end + 3'd5: begin + s_axi_bvalid = 1'b1; + s_axi_bid = AWID_Q; + s_axi_bresp = 2'b00; + s_axi_buser = AWUSER_Q; + if (s_axi_bready) begin + s_axi_awready = 1'b1; + if (s_axi_awvalid) begin + sample_AW = 1'b1; + if (s_axi_wvalid) begin + s_axi_wready = 1'b1; + write_req = 1'b1; + write_address = wr_addr; + if (s_axi_awlen == 0) begin + AW_NS = 3'd1; + CountBurst_AW_NS = 0; + end + else begin + AW_NS = 3'd2; + CountBurst_AW_NS = 1; + end + end + else begin + s_axi_wready = 1'b1; + write_req = 1'b0; + write_address = 1'sb0; + if (s_axi_awlen == 0) begin + AW_NS = 3'd4; + CountBurst_AW_NS = 0; + end + else begin + AW_NS = 3'd3; + CountBurst_AW_NS = 0; + end + end + end + else begin + s_axi_wready = 1'b1; + AW_NS = 3'd0; + CountBurst_AW_NS = 1'sb0; + end + end + else begin + AW_NS = 3'd5; + s_axi_awready = 1'b0; + s_axi_wready = 1'b0; + end + end + endcase + end + always @(posedge s_axi_aclk or negedge s_axi_aresetn) + if (s_axi_aresetn == 1'b0) begin + spi_swrst = 1'b0; + spi_rd = 1'b0; + spi_wr = 1'b0; + spi_qrd = 1'b0; + spi_qwr = 1'b0; + spi_clk_div_valid = 1'b0; + spi_clk_div = 'h0; + spi_cmd = 'h0; + spi_addr = 'h0; + spi_cmd_len = 'h0; + spi_addr_len = 'h0; + spi_data_len = 'h0; + spi_dummy_rd = 'h0; + spi_dummy_wr = 'h0; + spi_csreg = 'h0; + end + else if (write_req) begin + spi_swrst = 1'b0; + spi_rd = 1'b0; + spi_wr = 1'b0; + spi_qrd = 1'b0; + spi_qwr = 1'b0; + spi_clk_div_valid = 1'b0; + case (write_address) + 3'b000: begin + if (s_axi_wstrb[0] == 1) begin + spi_rd = s_axi_wdata[0]; + spi_wr = s_axi_wdata[1]; + spi_qrd = s_axi_wdata[2]; + spi_qwr = s_axi_wdata[3]; + spi_swrst = s_axi_wdata[4]; + end + if (s_axi_wstrb[1] == 1) + spi_csreg = s_axi_wdata[11:8]; + end + 3'b001: + if (s_axi_wstrb[0] == 1) begin + spi_clk_div = s_axi_wdata[7:0]; + spi_clk_div_valid = 1'b1; + end + 3'b010: begin : sv2v_autoblock_1 + reg signed [31:0] byte_index; + for (byte_index = 0; byte_index < 4; byte_index = byte_index + 1) + if (s_axi_wstrb[byte_index] == 1) + spi_cmd[byte_index * 8+:8] = s_axi_wdata[byte_index * 8+:8]; + end + 3'b011: begin : sv2v_autoblock_2 + reg signed [31:0] byte_index; + for (byte_index = 0; byte_index < 4; byte_index = byte_index + 1) + if (s_axi_wstrb[byte_index] == 1) + spi_addr[byte_index * 8+:8] = s_axi_wdata[byte_index * 8+:8]; + end + 3'b100: begin + if (s_axi_wstrb[0] == 1) + spi_cmd_len = s_axi_wdata[7:0]; + if (s_axi_wstrb[1] == 1) + spi_addr_len = s_axi_wdata[15:8]; + if (s_axi_wstrb[2] == 1) + spi_data_len[7:0] = s_axi_wdata[23:16]; + if (s_axi_wstrb[3] == 1) + spi_data_len[15:8] = s_axi_wdata[31:24]; + end + 3'b101: begin + if (s_axi_wstrb[0] == 1) + spi_dummy_rd[7:0] = s_axi_wdata[7:0]; + if (s_axi_wstrb[1] == 1) + spi_dummy_rd[15:8] = s_axi_wdata[15:8]; + if (s_axi_wstrb[2] == 1) + spi_dummy_wr[7:0] = s_axi_wdata[23:16]; + if (s_axi_wstrb[3] == 1) + spi_dummy_wr[15:8] = s_axi_wdata[31:24]; + end + endcase + end + else begin + spi_swrst = 1'b0; + spi_rd = 1'b0; + spi_wr = 1'b0; + spi_qrd = 1'b0; + spi_qwr = 1'b0; + spi_clk_div_valid = 1'b0; + end + always @(*) begin + s_axi_rdata = {32'h00000000, spi_data_rx}; + case (read_address) + 3'b000: s_axi_rdata[31:0] = spi_status; + 3'b001: s_axi_rdata[31:0] = {24'h000000, spi_clk_div}; + 3'b010: s_axi_rdata[31:0] = spi_cmd; + 3'b011: s_axi_rdata[31:0] = spi_addr; + 3'b100: s_axi_rdata[31:0] = {spi_data_len, 2'b00, spi_addr_len, 2'b00, spi_cmd_len}; + 3'b101: s_axi_rdata[31:0] = {spi_dummy_wr, spi_dummy_rd}; + endcase + end + assign spi_data_tx_valid = write_req & (write_address[3] == 1'b1); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_master/spi_master_clkgen.v b/verilog/rtl/ips/axi/axi_spi_master/spi_master_clkgen.v new file mode 100644 index 0000000..787aa57 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_master/spi_master_clkgen.v
@@ -0,0 +1,62 @@ +module spi_master_clkgen ( + clk, + rstn, + en, + clk_div, + clk_div_valid, + spi_clk, + spi_fall, + spi_rise +); + input wire clk; + input wire rstn; + input wire en; + input wire [7:0] clk_div; + input wire clk_div_valid; + output reg spi_clk; + output reg spi_fall; + output reg spi_rise; + reg [7:0] counter_trgt; + reg [7:0] counter_trgt_next; + reg [7:0] counter; + reg [7:0] counter_next; + reg spi_clk_next; + reg running; + always @(*) begin + spi_rise = 1'b0; + spi_fall = 1'b0; + if (clk_div_valid) + counter_trgt_next = clk_div; + else + counter_trgt_next = counter_trgt; + if (counter == counter_trgt) begin + counter_next = 0; + spi_clk_next = ~spi_clk; + if (spi_clk == 1'b0) + spi_rise = running; + else + spi_fall = running; + end + else begin + counter_next = counter + 1; + spi_clk_next = spi_clk; + end + end + always @(posedge clk or negedge rstn) + if (rstn == 1'b0) begin + counter_trgt <= 'h0; + counter <= 'h0; + spi_clk <= 1'b0; + running <= 1'b0; + end + else begin + counter_trgt <= counter_trgt_next; + if (!((spi_clk == 1'b0) && ~en)) begin + running <= 1'b1; + spi_clk <= spi_clk_next; + counter <= counter_next; + end + else + running <= 1'b0; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_master/spi_master_controller.v b/verilog/rtl/ips/axi/axi_spi_master/spi_master_controller.v new file mode 100644 index 0000000..d128d16 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_master/spi_master_controller.v
@@ -0,0 +1,484 @@ +module spi_master_controller ( + clk, + rstn, + eot, + spi_clk_div, + spi_clk_div_valid, + spi_status, + spi_addr, + spi_addr_len, + spi_cmd, + spi_cmd_len, + spi_data_len, + spi_dummy_rd, + spi_dummy_wr, + spi_csreg, + spi_swrst, + spi_rd, + spi_wr, + spi_qrd, + spi_qwr, + spi_ctrl_data_tx, + spi_ctrl_data_tx_valid, + spi_ctrl_data_tx_ready, + spi_ctrl_data_rx, + spi_ctrl_data_rx_valid, + spi_ctrl_data_rx_ready, + spi_clk, + spi_csn0, + spi_csn1, + spi_csn2, + spi_csn3, + spi_mode, + spi_sdo0, + spi_sdo1, + spi_sdo2, + spi_sdo3, + spi_sdi0, + spi_sdi1, + spi_sdi2, + spi_sdi3 +); + input wire clk; + input wire rstn; + output reg eot; + input wire [7:0] spi_clk_div; + input wire spi_clk_div_valid; + output reg [6:0] spi_status; + input wire [31:0] spi_addr; + input wire [5:0] spi_addr_len; + input wire [31:0] spi_cmd; + input wire [5:0] spi_cmd_len; + input wire [15:0] spi_data_len; + input wire [15:0] spi_dummy_rd; + input wire [15:0] spi_dummy_wr; + input wire [3:0] spi_csreg; + input wire spi_swrst; + input wire spi_rd; + input wire spi_wr; + input wire spi_qrd; + input wire spi_qwr; + input wire [31:0] spi_ctrl_data_tx; + input wire spi_ctrl_data_tx_valid; + output reg spi_ctrl_data_tx_ready; + output wire [31:0] spi_ctrl_data_rx; + output wire spi_ctrl_data_rx_valid; + input wire spi_ctrl_data_rx_ready; + output wire spi_clk; + output wire spi_csn0; + output wire spi_csn1; + output wire spi_csn2; + output wire spi_csn3; + output reg [1:0] spi_mode; + output wire spi_sdo0; + output wire spi_sdo1; + output wire spi_sdo2; + output wire spi_sdo3; + input wire spi_sdi0; + input wire spi_sdi1; + input wire spi_sdi2; + input wire spi_sdi3; + wire spi_rise; + wire spi_fall; + reg spi_clock_en; + reg spi_en_tx; + reg spi_en_rx; + reg [15:0] counter_tx; + reg counter_tx_valid; + reg [15:0] counter_rx; + reg counter_rx_valid; + reg [31:0] data_to_tx; + reg data_to_tx_valid; + wire data_to_tx_ready; + wire en_quad; + reg en_quad_int; + reg do_tx; + reg do_rx; + wire tx_done; + wire rx_done; + reg [1:0] s_spi_mode; + reg ctrl_data_valid; + reg spi_cs; + wire tx_clk_en; + wire rx_clk_en; + reg [2:0] ctrl_data_mux; + reg [4:0] state; + reg [4:0] state_next; + assign en_quad = (spi_qrd | spi_qwr) | en_quad_int; + spi_master_clkgen u_clkgen( + .clk(clk), + .rstn(rstn), + .en(spi_clock_en), + .clk_div(spi_clk_div), + .clk_div_valid(spi_clk_div_valid), + .spi_clk(spi_clk), + .spi_fall(spi_fall), + .spi_rise(spi_rise) + ); + spi_master_tx u_txreg( + .clk(clk), + .rstn(rstn), + .en(spi_en_tx), + .tx_edge(spi_fall), + .tx_done(tx_done), + .sdo0(spi_sdo0), + .sdo1(spi_sdo1), + .sdo2(spi_sdo2), + .sdo3(spi_sdo3), + .en_quad_in(en_quad), + .counter_in(counter_tx), + .counter_in_upd(counter_tx_valid), + .data(data_to_tx), + .data_valid(data_to_tx_valid), + .data_ready(data_to_tx_ready), + .clk_en_o(tx_clk_en) + ); + spi_master_rx u_rxreg( + .clk(clk), + .rstn(rstn), + .en(spi_en_rx), + .rx_edge(spi_rise), + .rx_done(rx_done), + .sdi0(spi_sdi0), + .sdi1(spi_sdi1), + .sdi2(spi_sdi2), + .sdi3(spi_sdi3), + .en_quad_in(en_quad), + .counter_in(counter_rx), + .counter_in_upd(counter_rx_valid), + .data(spi_ctrl_data_rx), + .data_valid(spi_ctrl_data_rx_valid), + .data_ready(spi_ctrl_data_rx_ready), + .clk_en_o(rx_clk_en) + ); + always @(*) begin + data_to_tx = 'h0; + data_to_tx_valid = 1'b0; + spi_ctrl_data_tx_ready = 1'b0; + case (ctrl_data_mux) + 3'd0: begin + data_to_tx = 1'sb0; + data_to_tx_valid = 1'b0; + spi_ctrl_data_tx_ready = 1'b0; + end + 3'd1: begin + data_to_tx = 1'sb0; + data_to_tx_valid = 1'b1; + end + 3'd2: begin + data_to_tx = spi_cmd; + data_to_tx_valid = ctrl_data_valid; + spi_ctrl_data_tx_ready = 1'b0; + end + 3'd3: begin + data_to_tx = spi_addr; + data_to_tx_valid = ctrl_data_valid; + spi_ctrl_data_tx_ready = 1'b0; + end + 3'd4: begin + data_to_tx = spi_ctrl_data_tx; + data_to_tx_valid = spi_ctrl_data_tx_valid; + spi_ctrl_data_tx_ready = data_to_tx_ready; + end + endcase + end + always @(*) begin + spi_cs = 1'b1; + spi_clock_en = 1'b0; + counter_tx = 1'sb0; + counter_tx_valid = 1'b0; + counter_rx = 1'sb0; + counter_rx_valid = 1'b0; + state_next = state; + ctrl_data_mux = 3'd0; + ctrl_data_valid = 1'b0; + spi_en_rx = 1'b0; + spi_en_tx = 1'b0; + spi_status = 1'sb0; + s_spi_mode = 2'b10; + eot = 1'b0; + case (state) + 5'd0: begin + spi_status[0] = 1'b1; + s_spi_mode = 2'b10; + if (((spi_rd || spi_wr) || spi_qrd) || spi_qwr) begin + spi_cs = 1'b0; + spi_clock_en = 1'b1; + if (spi_cmd_len != 0) begin + s_spi_mode = (spi_qrd | spi_qwr ? 2'b01 : 2'b00); + counter_tx = {8'h00, spi_cmd_len}; + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd2; + ctrl_data_valid = 1'b1; + spi_en_tx = 1'b1; + state_next = 5'd1; + end + else if (spi_addr_len != 0) begin + s_spi_mode = (spi_qrd | spi_qwr ? 2'b01 : 2'b00); + counter_tx = {8'h00, spi_addr_len}; + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd3; + ctrl_data_valid = 1'b1; + spi_en_tx = 1'b1; + state_next = 5'd2; + end + else if (spi_data_len != 0) + if (spi_rd || spi_qrd) begin + s_spi_mode = (spi_qrd ? 2'b10 : 2'b00); + if (spi_dummy_rd != 0) begin + counter_tx = (en_quad ? {spi_dummy_rd[13:0], 2'b00} : spi_dummy_rd); + counter_tx_valid = 1'b1; + spi_en_tx = 1'b1; + ctrl_data_mux = 3'd1; + state_next = 5'd4; + end + else begin + counter_rx = spi_data_len; + counter_rx_valid = 1'b1; + spi_en_rx = 1'b1; + state_next = 5'd6; + end + end + else begin + s_spi_mode = (spi_qwr ? 2'b01 : 2'b00); + if (spi_dummy_wr != 0) begin + counter_tx = (en_quad ? {spi_dummy_wr[13:0], 2'b00} : spi_dummy_wr); + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd1; + spi_en_tx = 1'b1; + state_next = 5'd4; + end + else begin + counter_tx = spi_data_len; + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd4; + ctrl_data_valid = 1'b0; + spi_en_tx = 1'b1; + state_next = 5'd5; + end + end + end + else begin + spi_cs = 1'b1; + state_next = 5'd0; + end + end + 5'd1: begin + spi_status[1] = 1'b1; + spi_cs = 1'b0; + spi_clock_en = 1'b1; + s_spi_mode = (en_quad ? 2'b01 : 2'b00); + if (tx_done) begin + if (spi_addr_len != 0) begin + s_spi_mode = (en_quad ? 2'b01 : 2'b00); + counter_tx = {8'h00, spi_addr_len}; + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd3; + ctrl_data_valid = 1'b1; + spi_en_tx = 1'b1; + state_next = 5'd2; + end + else if (spi_data_len != 0) begin + if (do_rx) begin + s_spi_mode = (en_quad ? 2'b10 : 2'b00); + if (spi_dummy_rd != 0) begin + counter_tx = (en_quad ? {spi_dummy_rd[13:0], 2'b00} : spi_dummy_rd); + counter_tx_valid = 1'b1; + spi_en_tx = 1'b1; + ctrl_data_mux = 3'd1; + state_next = 5'd4; + end + else begin + counter_rx = spi_data_len; + counter_rx_valid = 1'b1; + spi_en_rx = 1'b1; + state_next = 5'd6; + end + end + else begin + s_spi_mode = (en_quad ? 2'b01 : 2'b00); + if (spi_dummy_wr != 0) begin + counter_tx = (en_quad ? {spi_dummy_wr[13:0], 2'b00} : spi_dummy_wr); + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd1; + spi_en_tx = 1'b1; + state_next = 5'd4; + end + else begin + counter_tx = spi_data_len; + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd4; + ctrl_data_valid = 1'b1; + spi_en_tx = 1'b1; + state_next = 5'd5; + end + end + end + else + state_next = 5'd0; + end + else begin + spi_en_tx = 1'b1; + state_next = 5'd1; + end + end + 5'd2: begin + spi_en_tx = 1'b1; + spi_status[2] = 1'b1; + spi_cs = 1'b0; + spi_clock_en = 1'b1; + s_spi_mode = (en_quad ? 2'b01 : 2'b00); + if (tx_done) + if (spi_data_len != 0) begin + if (do_rx) begin + s_spi_mode = (en_quad ? 2'b10 : 2'b00); + if (spi_dummy_rd != 0) begin + counter_tx = (en_quad ? {spi_dummy_rd[13:0], 2'b00} : spi_dummy_rd); + counter_tx_valid = 1'b1; + spi_en_tx = 1'b1; + ctrl_data_mux = 3'd1; + state_next = 5'd4; + end + else begin + counter_rx = spi_data_len; + counter_rx_valid = 1'b1; + spi_en_rx = 1'b1; + state_next = 5'd6; + end + end + else begin + s_spi_mode = (en_quad ? 2'b01 : 2'b00); + spi_en_tx = 1'b1; + if (spi_dummy_wr != 0) begin + counter_tx = (en_quad ? {spi_dummy_wr[13:0], 2'b00} : spi_dummy_wr); + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd1; + state_next = 5'd4; + end + else begin + counter_tx = spi_data_len; + counter_tx_valid = 1'b1; + ctrl_data_mux = 3'd4; + ctrl_data_valid = 1'b1; + state_next = 5'd5; + end + end + end + else + state_next = 5'd0; + end + 5'd3: begin + spi_status[3] = 1'b1; + spi_cs = 1'b0; + spi_clock_en = 1'b1; + spi_en_tx = 1'b1; + end + 5'd4: begin + spi_en_tx = 1'b1; + spi_status[4] = 1'b1; + spi_cs = 1'b0; + spi_clock_en = 1'b1; + s_spi_mode = (en_quad ? 2'b10 : 2'b00); + if (tx_done) begin + if (spi_data_len != 0) begin + if (do_rx) begin + counter_rx = spi_data_len; + counter_rx_valid = 1'b1; + spi_en_rx = 1'b1; + state_next = 5'd6; + end + else begin + counter_tx = spi_data_len; + counter_tx_valid = 1'b1; + s_spi_mode = (en_quad ? 2'b01 : 2'b00); + spi_clock_en = tx_clk_en; + spi_en_tx = 1'b1; + state_next = 5'd5; + end + end + else begin + eot = 1'b1; + state_next = 5'd0; + end + end + else begin + ctrl_data_mux = 3'd1; + spi_en_tx = 1'b1; + state_next = 5'd4; + end + end + 5'd5: begin + spi_status[5] = 1'b1; + spi_cs = 1'b0; + spi_clock_en = tx_clk_en; + ctrl_data_mux = 3'd4; + ctrl_data_valid = 1'b1; + spi_en_tx = 1'b1; + s_spi_mode = (en_quad ? 2'b01 : 2'b00); + if (tx_done) begin + eot = 1'b1; + state_next = 5'd0; + spi_clock_en = 1'b0; + end + else + state_next = 5'd5; + end + 5'd6: begin + spi_status[6] = 1'b1; + spi_cs = 1'b0; + spi_clock_en = rx_clk_en; + s_spi_mode = (en_quad ? 2'b10 : 2'b00); + if (rx_done) + state_next = 5'd7; + else begin + spi_en_rx = 1'b1; + state_next = 5'd6; + end + end + 5'd7: begin + spi_status[6] = 1'b1; + spi_cs = 1'b0; + spi_clock_en = 1'b0; + s_spi_mode = (en_quad ? 2'b10 : 2'b00); + if (spi_fall) begin + eot = 1'b1; + state_next = 5'd0; + end + else + state_next = 5'd7; + end + endcase + end + always @(posedge clk or negedge rstn) + if (rstn == 1'b0) begin + state <= 5'd0; + en_quad_int <= 1'b0; + do_rx <= 1'b0; + do_tx <= 1'b0; + spi_mode <= 2'b10; + end + else begin + state <= state_next; + spi_mode <= s_spi_mode; + if (spi_qrd || spi_qwr) + en_quad_int <= 1'b1; + else if (state_next == 5'd0) + en_quad_int <= 1'b0; + if (spi_rd || spi_qrd) begin + do_rx <= 1'b1; + do_tx <= 1'b0; + end + else if (spi_wr || spi_qwr) begin + do_rx <= 1'b0; + do_tx <= 1'b1; + end + else if (state_next == 5'd0) begin + do_rx <= 1'b0; + do_tx <= 1'b0; + end + end + assign spi_csn0 = ~spi_csreg[0] | spi_cs; + assign spi_csn1 = ~spi_csreg[1] | spi_cs; + assign spi_csn2 = ~spi_csreg[2] | spi_cs; + assign spi_csn3 = ~spi_csreg[3] | spi_cs; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_master/spi_master_fifo.v b/verilog/rtl/ips/axi/axi_spi_master/spi_master_fifo.v new file mode 100644 index 0000000..08e20a1 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_master/spi_master_fifo.v
@@ -0,0 +1,85 @@ +`define log2(VALUE) ((VALUE) < ( 1 ) ? 0 : (VALUE) < ( 2 ) ? 1 : (VALUE) < ( 4 ) ? 2 : (VALUE) < ( 8 ) ? 3 : (VALUE) < ( 16 ) ? 4 : (VALUE) < ( 32 ) ? 5 : (VALUE) < ( 64 ) ? 6 : (VALUE) < ( 128 ) ? 7 : (VALUE) < ( 256 ) ? 8 : (VALUE) < ( 512 ) ? 9 : (VALUE) < ( 1024 ) ? 10 : (VALUE) < ( 2048 ) ? 11 : (VALUE) < ( 4096 ) ? 12 : (VALUE) < ( 8192 ) ? 13 : (VALUE) < ( 16384 ) ? 14 : (VALUE) < ( 32768 ) ? 15 : (VALUE) < ( 65536 ) ? 16 : (VALUE) < ( 131072 ) ? 17 : (VALUE) < ( 262144 ) ? 18 : (VALUE) < ( 524288 ) ? 19 : (VALUE) < ( 1048576 ) ? 20 : (VALUE) < ( 1048576 * 2 ) ? 21 : (VALUE) < ( 1048576 * 4 ) ? 22 : (VALUE) < ( 1048576 * 8 ) ? 23 : (VALUE) < ( 1048576 * 16 ) ? 24 : 25) + +module spi_master_fifo +#( + parameter DATA_WIDTH = 32, + parameter BUFFER_DEPTH = 2, + parameter LOG_BUFFER_DEPTH = `log2(BUFFER_DEPTH) +) +( + clk_i, + rst_ni, + clr_i, + elements_o, + data_o, + valid_o, + ready_i, + valid_i, + data_i, + ready_o +); + //parameter DATA_WIDTH = 32; + //parameter BUFFER_DEPTH = 2; + //parameter LOG_BUFFER_DEPTH = (BUFFER_DEPTH < 1 ? 0 : (BUFFER_DEPTH < 2 ? 1 : (BUFFER_DEPTH < 4 ? 2 : (BUFFER_DEPTH < 8 ? 3 : (BUFFER_DEPTH < 16 ? 4 : (BUFFER_DEPTH < 32 ? 5 : (BUFFER_DEPTH < 64 ? 6 : (BUFFER_DEPTH < 128 ? 7 : (BUFFER_DEPTH < 256 ? 8 : (BUFFER_DEPTH < 512 ? 9 : (BUFFER_DEPTH < 1024 ? 10 : (BUFFER_DEPTH < 2048 ? 11 : (BUFFER_DEPTH < 4096 ? 12 : (BUFFER_DEPTH < 8192 ? 13 : (BUFFER_DEPTH < 16384 ? 14 : (BUFFER_DEPTH < 32768 ? 15 : (BUFFER_DEPTH < 65536 ? 16 : (BUFFER_DEPTH < 131072 ? 17 : (BUFFER_DEPTH < 262144 ? 18 : (BUFFER_DEPTH < 524288 ? 19 : (BUFFER_DEPTH < 1048576 ? 20 : (BUFFER_DEPTH < 2097152 ? 21 : (BUFFER_DEPTH < 4194304 ? 22 : (BUFFER_DEPTH < 8388608 ? 23 : (BUFFER_DEPTH < 16777216 ? 24 : 25))))))))))))))))))))))))); + input wire clk_i; + input wire rst_ni; + input wire clr_i; + output wire [LOG_BUFFER_DEPTH:0] elements_o; + output wire [DATA_WIDTH - 1:0] data_o; + output wire valid_o; + input wire ready_i; + input wire valid_i; + input wire [DATA_WIDTH - 1:0] data_i; + output wire ready_o; + reg [LOG_BUFFER_DEPTH - 1:0] pointer_in; + reg [LOG_BUFFER_DEPTH - 1:0] pointer_out; + reg [LOG_BUFFER_DEPTH:0] elements; + reg [DATA_WIDTH - 1:0] buffer [BUFFER_DEPTH - 1:0]; + wire full; + integer loop1; + assign full = elements == BUFFER_DEPTH; + assign elements_o = elements; + always @(posedge clk_i or negedge rst_ni) begin : elements_sequential + if (rst_ni == 1'b0) + elements <= 0; + else if (clr_i) + elements <= 0; + else if ((ready_i && valid_o) && (!valid_i || full)) + elements <= elements - 1; + else if (((!valid_o || !ready_i) && valid_i) && !full) + elements <= elements + 1; + end + always @(posedge clk_i or negedge rst_ni) begin : buffers_sequential + if (rst_ni == 1'b0) begin + for (loop1 = 0; loop1 < BUFFER_DEPTH; loop1 = loop1 + 1) + buffer[loop1] <= 0; + end + else if (valid_i && !full) + buffer[pointer_in] <= data_i; + end + always @(posedge clk_i or negedge rst_ni) begin : sequential + if (rst_ni == 1'b0) begin + pointer_out <= 0; + pointer_in <= 0; + end + else if (clr_i) begin + pointer_out <= 0; + pointer_in <= 0; + end + else begin + if (valid_i && !full) + if (pointer_in == $unsigned(BUFFER_DEPTH - 1)) + pointer_in <= 0; + else + pointer_in <= pointer_in + 1; + if (ready_i && valid_o) + if (pointer_out == $unsigned(BUFFER_DEPTH - 1)) + pointer_out <= 0; + else + pointer_out <= pointer_out + 1; + end + end + assign data_o = buffer[pointer_out]; + assign valid_o = elements != 0; + assign ready_o = ~full; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_master/spi_master_rx.v b/verilog/rtl/ips/axi/axi_spi_master/spi_master_rx.v new file mode 100644 index 0000000..8885afc --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_master/spi_master_rx.v
@@ -0,0 +1,116 @@ +module spi_master_rx ( + clk, + rstn, + en, + rx_edge, + rx_done, + sdi0, + sdi1, + sdi2, + sdi3, + en_quad_in, + counter_in, + counter_in_upd, + data, + data_ready, + data_valid, + clk_en_o +); + input wire clk; + input wire rstn; + input wire en; + input wire rx_edge; + output wire rx_done; + input wire sdi0; + input wire sdi1; + input wire sdi2; + input wire sdi3; + input wire en_quad_in; + input wire [15:0] counter_in; + input wire counter_in_upd; + output wire [31:0] data; + input wire data_ready; + output reg data_valid; + output reg clk_en_o; + reg [31:0] data_int; + reg [31:0] data_int_next; + reg [15:0] counter; + reg [15:0] counter_trgt; + reg [15:0] counter_next; + reg [15:0] counter_trgt_next; + wire done; + wire reg_done; + reg [1:0] rx_CS; + reg [1:0] rx_NS; + assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111)); + assign data = data_int_next; + assign rx_done = done; + always @(*) + if (counter_in_upd) + counter_trgt_next = (en_quad_in ? {2'b00, counter_in[15:2]} : counter_in); + else + counter_trgt_next = counter_trgt; + assign done = (counter == (counter_trgt - 1)) && rx_edge; + always @(*) begin + rx_NS = rx_CS; + clk_en_o = 1'b0; + data_int_next = data_int; + data_valid = 1'b0; + counter_next = counter; + case (rx_CS) + 2'd0: begin + clk_en_o = 1'b0; + if (en) + rx_NS = 2'd1; + end + 2'd1: begin + clk_en_o = 1'b1; + if (rx_edge) begin + counter_next = counter + 1; + if (en_quad_in) + data_int_next = {data_int[27:0], sdi3, sdi2, sdi1, sdi0}; + else + data_int_next = {data_int[30:0], sdi0}; + if (rx_done) begin + counter_next = 0; + data_valid = 1'b1; + if (data_ready) + rx_NS = 2'd0; + else + rx_NS = 2'd3; + end + else if (reg_done) begin + data_valid = 1'b1; + if (~data_ready) begin + clk_en_o = 1'b0; + rx_NS = 2'd2; + end + end + end + end + 2'd3: begin + data_valid = 1'b1; + if (data_ready) + rx_NS = 2'd0; + end + 2'd2: begin + data_valid = 1'b1; + if (data_ready) + rx_NS = 2'd1; + end + endcase + end + always @(posedge clk or negedge rstn) + if (rstn == 0) begin + counter <= 0; + counter_trgt <= 'h8; + data_int <= 1'sb0; + rx_CS <= 2'd0; + end + else begin + counter <= counter_next; + counter_trgt <= counter_trgt_next; + data_int <= data_int_next; + rx_CS <= rx_NS; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_master/spi_master_tx.v b/verilog/rtl/ips/axi/axi_spi_master/spi_master_tx.v new file mode 100644 index 0000000..ede9996 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_master/spi_master_tx.v
@@ -0,0 +1,115 @@ +module spi_master_tx ( + clk, + rstn, + en, + tx_edge, + tx_done, + sdo0, + sdo1, + sdo2, + sdo3, + en_quad_in, + counter_in, + counter_in_upd, + data, + data_valid, + data_ready, + clk_en_o +); + input wire clk; + input wire rstn; + input wire en; + input wire tx_edge; + output wire tx_done; + output wire sdo0; + output wire sdo1; + output wire sdo2; + output wire sdo3; + input wire en_quad_in; + input wire [15:0] counter_in; + input wire counter_in_upd; + input wire [31:0] data; + input wire data_valid; + output reg data_ready; + output reg clk_en_o; + reg [31:0] data_int; + reg [31:0] data_int_next; + reg [15:0] counter; + reg [15:0] counter_trgt; + reg [15:0] counter_next; + reg [15:0] counter_trgt_next; + wire done; + wire reg_done; + reg [0:0] tx_CS; + reg [0:0] tx_NS; + assign sdo0 = (en_quad_in ? data_int[28] : data_int[31]); + assign sdo1 = data_int[29]; + assign sdo2 = data_int[30]; + assign sdo3 = data_int[31]; + assign tx_done = done; + assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111)); + always @(*) + if (counter_in_upd) + counter_trgt_next = (en_quad_in ? {2'b00, counter_in[15:2]} : counter_in); + else + counter_trgt_next = counter_trgt; + assign done = (counter == (counter_trgt - 1)) && tx_edge; + always @(*) begin + tx_NS = tx_CS; + clk_en_o = 1'b0; + data_int_next = data_int; + data_ready = 1'b0; + counter_next = counter; + case (tx_CS) + 1'd0: begin + clk_en_o = 1'b0; + if (en && data_valid) begin + data_int_next = data; + data_ready = 1'b1; + tx_NS = 1'd1; + end + end + 1'd1: begin + clk_en_o = 1'b1; + if (tx_edge) begin + counter_next = counter + 1; + data_int_next = (en_quad_in ? {data_int[27:0], 4'b0000} : {data_int[30:0], 1'b0}); + if (tx_done) begin + counter_next = 0; + if (en && data_valid) begin + data_int_next = data; + data_ready = 1'b1; + tx_NS = 1'd1; + end + else begin + clk_en_o = 1'b0; + tx_NS = 1'd0; + end + end + else if (reg_done) + if (data_valid) begin + data_int_next = data; + data_ready = 1'b1; + end + else begin + clk_en_o = 1'b0; + tx_NS = 1'd0; + end + end + end + endcase + end + always @(posedge clk or negedge rstn) + if (~rstn) begin + counter <= 0; + counter_trgt <= 'h8; + data_int <= 'h0; + tx_CS <= 1'd0; + end + else begin + counter <= counter_next; + counter_trgt <= counter_trgt_next; + data_int <= data_int_next; + tx_CS <= tx_NS; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/axi_spi_slave.v b/verilog/rtl/ips/axi/axi_spi_slave/axi_spi_slave.v new file mode 100644 index 0000000..ad33361 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/axi_spi_slave.v
@@ -0,0 +1,322 @@ +module axi_spi_slave +#( + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3, + parameter DUMMY_CYCLES = 32 +) +( + test_mode, + spi_sclk, + spi_cs, + spi_mode, + spi_sdi0, + spi_sdi1, + spi_sdi2, + spi_sdi3, + spi_sdo0, + spi_sdo1, + spi_sdo2, + spi_sdo3, + axi_aclk, + axi_aresetn, + axi_master_aw_valid, + axi_master_aw_addr, + axi_master_aw_prot, + axi_master_aw_region, + axi_master_aw_len, + axi_master_aw_size, + axi_master_aw_burst, + axi_master_aw_lock, + axi_master_aw_cache, + axi_master_aw_qos, + axi_master_aw_id, + axi_master_aw_user, + axi_master_aw_ready, + axi_master_ar_valid, + axi_master_ar_addr, + axi_master_ar_prot, + axi_master_ar_region, + axi_master_ar_len, + axi_master_ar_size, + axi_master_ar_burst, + axi_master_ar_lock, + axi_master_ar_cache, + axi_master_ar_qos, + axi_master_ar_id, + axi_master_ar_user, + axi_master_ar_ready, + axi_master_w_valid, + axi_master_w_data, + axi_master_w_strb, + axi_master_w_user, + axi_master_w_last, + axi_master_w_ready, + axi_master_r_valid, + axi_master_r_data, + axi_master_r_resp, + axi_master_r_last, + axi_master_r_id, + axi_master_r_user, + axi_master_r_ready, + axi_master_b_valid, + axi_master_b_resp, + axi_master_b_id, + axi_master_b_user, + axi_master_b_ready +); + //parameter AXI_ADDR_WIDTH = 32; + //parameter AXI_DATA_WIDTH = 64; + //parameter AXI_USER_WIDTH = 6; + //parameter AXI_ID_WIDTH = 3; + //parameter DUMMY_CYCLES = 32; + input wire test_mode; + input wire spi_sclk; + input wire spi_cs; + output wire [1:0] spi_mode; + input wire spi_sdi0; + input wire spi_sdi1; + input wire spi_sdi2; + input wire spi_sdi3; + output wire spi_sdo0; + output wire spi_sdo1; + output wire spi_sdo2; + output wire spi_sdo3; + input wire axi_aclk; + input wire axi_aresetn; + output wire axi_master_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_aw_addr; + output wire [2:0] axi_master_aw_prot; + output wire [3:0] axi_master_aw_region; + output wire [7:0] axi_master_aw_len; + output wire [2:0] axi_master_aw_size; + output wire [1:0] axi_master_aw_burst; + output wire axi_master_aw_lock; + output wire [3:0] axi_master_aw_cache; + output wire [3:0] axi_master_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_aw_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_aw_user; + input wire axi_master_aw_ready; + output wire axi_master_ar_valid; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_ar_addr; + output wire [2:0] axi_master_ar_prot; + output wire [3:0] axi_master_ar_region; + output wire [7:0] axi_master_ar_len; + output wire [2:0] axi_master_ar_size; + output wire [1:0] axi_master_ar_burst; + output wire axi_master_ar_lock; + output wire [3:0] axi_master_ar_cache; + output wire [3:0] axi_master_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_ar_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_ar_user; + input wire axi_master_ar_ready; + output wire axi_master_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] axi_master_w_data; + output wire [(AXI_DATA_WIDTH / 8) - 1:0] axi_master_w_strb; + output wire [AXI_USER_WIDTH - 1:0] axi_master_w_user; + output wire axi_master_w_last; + input wire axi_master_w_ready; + input wire axi_master_r_valid; + input wire [AXI_DATA_WIDTH - 1:0] axi_master_r_data; + input wire [1:0] axi_master_r_resp; + input wire axi_master_r_last; + input wire [AXI_ID_WIDTH - 1:0] axi_master_r_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_r_user; + output wire axi_master_r_ready; + input wire axi_master_b_valid; + input wire [1:0] axi_master_b_resp; + input wire [AXI_ID_WIDTH - 1:0] axi_master_b_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_b_user; + output wire axi_master_b_ready; + wire en_quad; + wire [7:0] rx_counter; + wire rx_counter_upd; + wire [31:0] rx_data; + wire rx_data_valid; + wire [7:0] tx_counter; + wire tx_counter_upd; + wire [31:0] tx_data; + wire tx_data_valid; + wire ctrl_rd_wr; + wire [31:0] ctrl_addr; + wire ctrl_addr_valid; + wire [31:0] ctrl_data_rx; + wire ctrl_data_rx_valid; + wire ctrl_data_rx_ready; + wire [31:0] ctrl_data_tx; + wire ctrl_data_tx_valid; + wire ctrl_data_tx_ready; + wire [31:0] fifo_data_rx; + wire fifo_data_rx_valid; + wire fifo_data_rx_ready; + wire [31:0] fifo_data_tx; + wire fifo_data_tx_valid; + wire fifo_data_tx_ready; + wire [AXI_ADDR_WIDTH - 1:0] addr_sync; + wire addr_valid_sync; + wire cs_sync; + wire tx_done; + wire rd_wr_sync; + wire [15:0] wrap_length; + spi_slave_rx u_rxreg( + .sclk(spi_sclk), + .cs(spi_cs), + .sdi0(spi_sdi0), + .sdi1(spi_sdi1), + .sdi2(spi_sdi2), + .sdi3(spi_sdi3), + .en_quad_in(en_quad), + .counter_in(rx_counter), + .counter_in_upd(rx_counter_upd), + .data(rx_data), + .data_ready(rx_data_valid) + ); + spi_slave_tx u_txreg( + .test_mode(test_mode), + .sclk(spi_sclk), + .cs(spi_cs), + .sdo0(spi_sdo0), + .sdo1(spi_sdo1), + .sdo2(spi_sdo2), + .sdo3(spi_sdo3), + .en_quad_in(en_quad), + .counter_in(tx_counter), + .counter_in_upd(tx_counter_upd), + .data(tx_data), + .data_valid(tx_data_valid), + .done(tx_done) + ); + spi_slave_controller #(.DUMMY_CYCLES(DUMMY_CYCLES)) u_slave_sm( + .sclk(spi_sclk), + .sys_rstn(axi_aresetn), + .cs(spi_cs), + .en_quad(en_quad), + .pad_mode(spi_mode), + .rx_counter(rx_counter), + .rx_counter_upd(rx_counter_upd), + .rx_data(rx_data), + .rx_data_valid(rx_data_valid), + .tx_counter(tx_counter), + .tx_counter_upd(tx_counter_upd), + .tx_data(tx_data), + .tx_data_valid(tx_data_valid), + .tx_done(tx_done), + .ctrl_rd_wr(ctrl_rd_wr), + .ctrl_addr(ctrl_addr), + .ctrl_addr_valid(ctrl_addr_valid), + .ctrl_data_rx(ctrl_data_rx), + .ctrl_data_rx_valid(ctrl_data_rx_valid), + .ctrl_data_rx_ready(ctrl_data_rx_ready), + .ctrl_data_tx(ctrl_data_tx), + .ctrl_data_tx_valid(ctrl_data_tx_valid), + .ctrl_data_tx_ready(ctrl_data_tx_ready), + .wrap_length(wrap_length) + ); + spi_slave_dc_fifo #( + .DATA_WIDTH(32), + .BUFFER_DEPTH(8) + ) u_dcfifo_rx( + .clk_a(spi_sclk), + .rstn_a(axi_aresetn), + .data_a(ctrl_data_rx), + .valid_a(ctrl_data_rx_valid), + .ready_a(ctrl_data_rx_ready), + .clk_b(axi_aclk), + .rstn_b(axi_aresetn), + .data_b(fifo_data_rx), + .valid_b(fifo_data_rx_valid), + .ready_b(fifo_data_rx_ready) + ); + spi_slave_dc_fifo #( + .DATA_WIDTH(32), + .BUFFER_DEPTH(8) + ) u_dcfifo_tx( + .clk_a(axi_aclk), + .rstn_a(axi_aresetn), + .data_a(fifo_data_tx), + .valid_a(fifo_data_tx_valid), + .ready_a(fifo_data_tx_ready), + .clk_b(spi_sclk), + .rstn_b(axi_aresetn), + .data_b(ctrl_data_tx), + .valid_b(ctrl_data_tx_valid), + .ready_b(ctrl_data_tx_ready) + ); + spi_slave_axi_plug #( + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_USER_WIDTH(AXI_USER_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH) + ) u_axiplug( + .axi_aclk(axi_aclk), + .axi_aresetn(axi_aresetn), + .axi_master_aw_valid(axi_master_aw_valid), + .axi_master_aw_addr(axi_master_aw_addr), + .axi_master_aw_prot(axi_master_aw_prot), + .axi_master_aw_region(axi_master_aw_region), + .axi_master_aw_len(axi_master_aw_len), + .axi_master_aw_size(axi_master_aw_size), + .axi_master_aw_burst(axi_master_aw_burst), + .axi_master_aw_lock(axi_master_aw_lock), + .axi_master_aw_cache(axi_master_aw_cache), + .axi_master_aw_qos(axi_master_aw_qos), + .axi_master_aw_id(axi_master_aw_id), + .axi_master_aw_user(axi_master_aw_user), + .axi_master_aw_ready(axi_master_aw_ready), + .axi_master_ar_valid(axi_master_ar_valid), + .axi_master_ar_addr(axi_master_ar_addr), + .axi_master_ar_prot(axi_master_ar_prot), + .axi_master_ar_region(axi_master_ar_region), + .axi_master_ar_len(axi_master_ar_len), + .axi_master_ar_size(axi_master_ar_size), + .axi_master_ar_burst(axi_master_ar_burst), + .axi_master_ar_lock(axi_master_ar_lock), + .axi_master_ar_cache(axi_master_ar_cache), + .axi_master_ar_qos(axi_master_ar_qos), + .axi_master_ar_id(axi_master_ar_id), + .axi_master_ar_user(axi_master_ar_user), + .axi_master_ar_ready(axi_master_ar_ready), + .axi_master_w_valid(axi_master_w_valid), + .axi_master_w_data(axi_master_w_data), + .axi_master_w_strb(axi_master_w_strb), + .axi_master_w_user(axi_master_w_user), + .axi_master_w_last(axi_master_w_last), + .axi_master_w_ready(axi_master_w_ready), + .axi_master_r_valid(axi_master_r_valid), + .axi_master_r_data(axi_master_r_data), + .axi_master_r_resp(axi_master_r_resp), + .axi_master_r_last(axi_master_r_last), + .axi_master_r_id(axi_master_r_id), + .axi_master_r_user(axi_master_r_user), + .axi_master_r_ready(axi_master_r_ready), + .axi_master_b_valid(axi_master_b_valid), + .axi_master_b_resp(axi_master_b_resp), + .axi_master_b_id(axi_master_b_id), + .axi_master_b_user(axi_master_b_user), + .axi_master_b_ready(axi_master_b_ready), + .rxtx_addr(addr_sync), + .rxtx_addr_valid(addr_valid_sync), + .start_tx(rd_wr_sync & addr_valid_sync), + .cs(cs_sync), + .tx_data(fifo_data_tx), + .tx_valid(fifo_data_tx_valid), + .tx_ready(fifo_data_tx_ready), + .rx_data(fifo_data_rx), + .rx_valid(fifo_data_rx_valid), + .rx_ready(fifo_data_rx_ready), + .wrap_length(wrap_length) + ); + spi_slave_syncro #(.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH)) u_syncro( + .sys_clk(axi_aclk), + .rstn(axi_aresetn), + .cs(spi_cs), + .address(ctrl_addr), + .address_valid(ctrl_addr_valid), + .rd_wr(ctrl_rd_wr), + .cs_sync(cs_sync), + .address_sync(addr_sync), + .address_valid_sync(addr_valid_sync), + .rd_wr_sync(rd_wr_sync) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_axi_plug.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_axi_plug.v new file mode 100644 index 0000000..900ba26 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_axi_plug.v
@@ -0,0 +1,305 @@ +module spi_slave_axi_plug +#( + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3 +) +( + axi_aclk, + axi_aresetn, + axi_master_aw_valid, + axi_master_aw_addr, + axi_master_aw_prot, + axi_master_aw_region, + axi_master_aw_len, + axi_master_aw_size, + axi_master_aw_burst, + axi_master_aw_lock, + axi_master_aw_cache, + axi_master_aw_qos, + axi_master_aw_id, + axi_master_aw_user, + axi_master_aw_ready, + axi_master_ar_valid, + axi_master_ar_addr, + axi_master_ar_prot, + axi_master_ar_region, + axi_master_ar_len, + axi_master_ar_size, + axi_master_ar_burst, + axi_master_ar_lock, + axi_master_ar_cache, + axi_master_ar_qos, + axi_master_ar_id, + axi_master_ar_user, + axi_master_ar_ready, + axi_master_w_valid, + axi_master_w_data, + axi_master_w_strb, + axi_master_w_user, + axi_master_w_last, + axi_master_w_ready, + axi_master_r_valid, + axi_master_r_data, + axi_master_r_resp, + axi_master_r_last, + axi_master_r_id, + axi_master_r_user, + axi_master_r_ready, + axi_master_b_valid, + axi_master_b_resp, + axi_master_b_id, + axi_master_b_user, + axi_master_b_ready, + rxtx_addr, + rxtx_addr_valid, + start_tx, + cs, + tx_data, + tx_valid, + tx_ready, + rx_data, + rx_valid, + rx_ready, + wrap_length +); + //parameter AXI_ADDR_WIDTH = 32; + //parameter AXI_DATA_WIDTH = 64; + //parameter AXI_USER_WIDTH = 6; + //parameter AXI_ID_WIDTH = 3; + input wire axi_aclk; + input wire axi_aresetn; + output reg axi_master_aw_valid; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_aw_addr; + output wire [2:0] axi_master_aw_prot; + output wire [3:0] axi_master_aw_region; + output wire [7:0] axi_master_aw_len; + output wire [2:0] axi_master_aw_size; + output wire [1:0] axi_master_aw_burst; + output wire axi_master_aw_lock; + output wire [3:0] axi_master_aw_cache; + output wire [3:0] axi_master_aw_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_aw_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_aw_user; + input wire axi_master_aw_ready; + output reg axi_master_ar_valid; + output wire [AXI_ADDR_WIDTH - 1:0] axi_master_ar_addr; + output wire [2:0] axi_master_ar_prot; + output wire [3:0] axi_master_ar_region; + output wire [7:0] axi_master_ar_len; + output wire [2:0] axi_master_ar_size; + output wire [1:0] axi_master_ar_burst; + output wire axi_master_ar_lock; + output wire [3:0] axi_master_ar_cache; + output wire [3:0] axi_master_ar_qos; + output wire [AXI_ID_WIDTH - 1:0] axi_master_ar_id; + output wire [AXI_USER_WIDTH - 1:0] axi_master_ar_user; + input wire axi_master_ar_ready; + output reg axi_master_w_valid; + output wire [AXI_DATA_WIDTH - 1:0] axi_master_w_data; + output wire [(AXI_DATA_WIDTH / 8) - 1:0] axi_master_w_strb; + output wire [AXI_USER_WIDTH - 1:0] axi_master_w_user; + output wire axi_master_w_last; + input wire axi_master_w_ready; + input wire axi_master_r_valid; + input wire [AXI_DATA_WIDTH - 1:0] axi_master_r_data; + input wire [1:0] axi_master_r_resp; + input wire axi_master_r_last; + input wire [AXI_ID_WIDTH - 1:0] axi_master_r_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_r_user; + output reg axi_master_r_ready; + input wire axi_master_b_valid; + input wire [1:0] axi_master_b_resp; + input wire [AXI_ID_WIDTH - 1:0] axi_master_b_id; + input wire [AXI_USER_WIDTH - 1:0] axi_master_b_user; + output reg axi_master_b_ready; + input wire [AXI_ADDR_WIDTH - 1:0] rxtx_addr; + input wire rxtx_addr_valid; + input wire start_tx; + input wire cs; + output wire [31:0] tx_data; + output reg tx_valid; + input wire tx_ready; + input wire [31:0] rx_data; + input wire rx_valid; + output reg rx_ready; + input wire [15:0] wrap_length; + reg [AXI_ADDR_WIDTH - 1:0] curr_addr; + reg [AXI_ADDR_WIDTH - 1:0] next_addr; + reg [31:0] curr_data_rx; + reg [AXI_DATA_WIDTH - 1:0] curr_data_tx; + reg incr_addr_w; + reg incr_addr_r; + reg sample_fifo; + reg sample_axidata; + reg [15:0] tx_counter; + reg [2:0] AR_CS; + reg [2:0] AR_NS; + reg [2:0] AW_CS; + reg [2:0] AW_NS; + always @(posedge axi_aclk or negedge axi_aresetn) + if (axi_aresetn == 0) begin + AW_CS <= 3'd0; + AR_CS <= 3'd0; + curr_data_rx <= 'h0; + curr_data_tx <= 'h0; + curr_addr <= 'h0; + end + else begin + AW_CS <= AW_NS; + AR_CS <= AR_NS; + if (sample_fifo) + curr_data_rx <= rx_data; + if (sample_axidata) + curr_data_tx <= axi_master_r_data; + if (rxtx_addr_valid) + curr_addr <= rxtx_addr; + else if (incr_addr_w | incr_addr_r) + curr_addr <= next_addr; + end + always @(posedge axi_aclk or negedge axi_aresetn) + if (axi_aresetn == 1'b0) + tx_counter <= 16'h0000; + else if (start_tx) + tx_counter <= 16'h0000; + else if (incr_addr_w | incr_addr_r) + if (tx_counter == (wrap_length - 1)) + tx_counter <= 16'h0000; + else + tx_counter <= tx_counter + 16'h0001; + always @(*) begin + next_addr = 32'b00000000000000000000000000000000; + if (rxtx_addr_valid) + next_addr = rxtx_addr; + else if (tx_counter == (wrap_length - 1)) + next_addr = rxtx_addr; + else + next_addr = curr_addr + 32'h00000004; + end + always @(*) begin + AW_NS = 3'd0; + sample_fifo = 1'b0; + rx_ready = 1'b0; + axi_master_aw_valid = 1'b0; + axi_master_w_valid = 1'b0; + axi_master_b_ready = 1'b0; + incr_addr_w = 1'b0; + case (AW_CS) + 3'd0: + if (rx_valid) begin + sample_fifo = 1'b1; + rx_ready = 1'b1; + AW_NS = 3'd2; + end + else + AW_NS = 3'd0; + 3'd2: begin + axi_master_aw_valid = 1'b1; + if (axi_master_aw_ready) + AW_NS = 3'd3; + else + AW_NS = 3'd2; + end + 3'd3: begin + axi_master_w_valid = 1'b1; + if (axi_master_w_ready) begin + incr_addr_w = 1'b1; + AW_NS = 3'd4; + end + else + AW_NS = 3'd3; + end + 3'd4: begin + axi_master_b_ready = 1'b1; + if (axi_master_b_valid) + AW_NS = 3'd0; + else + AW_NS = 3'd4; + end + endcase + end + always @(*) begin + AR_NS = 3'd0; + tx_valid = 1'b0; + axi_master_ar_valid = 1'b0; + axi_master_r_ready = 1'b0; + incr_addr_r = 1'b0; + sample_axidata = 1'b0; + case (AR_CS) + 3'd0: + if (start_tx && !cs) + AR_NS = 3'd2; + else + AR_NS = 3'd0; + 3'd1: begin + tx_valid = 1'b1; + if (cs) + AR_NS = 3'd0; + else if (tx_ready) begin + incr_addr_r = 1'b1; + AR_NS = 3'd2; + end + else + AR_NS = 3'd1; + end + 3'd2: begin + axi_master_ar_valid = 1'b1; + if (axi_master_ar_ready) + AR_NS = 3'd4; + else + AR_NS = 3'd2; + end + 3'd4: begin + axi_master_r_ready = 1'b1; + if (axi_master_r_valid) begin + sample_axidata = 1'b1; + AR_NS = 3'd1; + end + else + AR_NS = 3'd4; + end + endcase + end + generate + if (AXI_DATA_WIDTH == 32) begin : genblk1 + assign tx_data = curr_data_tx[31:0]; + end + else begin : genblk1 + assign tx_data = (curr_addr[2] ? curr_data_tx[63:32] : curr_data_tx[31:0]); + end + endgenerate + assign axi_master_aw_addr = curr_addr; + assign axi_master_aw_prot = 'h0; + assign axi_master_aw_region = 'h0; + assign axi_master_aw_len = 'h0; + assign axi_master_aw_size = 3'b010; + assign axi_master_aw_burst = 'h0; + assign axi_master_aw_lock = 'h0; + assign axi_master_aw_cache = 'h0; + assign axi_master_aw_qos = 'h0; + assign axi_master_aw_id = 'h1; + assign axi_master_aw_user = 'h0; + assign axi_master_w_data = {AXI_DATA_WIDTH / 32 {curr_data_rx}}; + generate + if (AXI_DATA_WIDTH == 32) begin : genblk2 + assign axi_master_w_strb = 4'hf; + end + else begin : genblk2 + assign axi_master_w_strb = (curr_addr[2] ? 8'hf0 : 8'h0f); + end + endgenerate + assign axi_master_w_user = 'h0; + assign axi_master_w_last = 1'b1; + assign axi_master_ar_addr = curr_addr; + assign axi_master_ar_prot = 'h0; + assign axi_master_ar_region = 'h0; + assign axi_master_ar_len = 'h0; + assign axi_master_ar_size = 3'b010; + assign axi_master_ar_burst = 'h0; + assign axi_master_ar_lock = 'h0; + assign axi_master_ar_cache = 'h0; + assign axi_master_ar_qos = 'h0; + assign axi_master_ar_id = 'h1; + assign axi_master_ar_user = 'h0; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_cmd_parser.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_cmd_parser.v new file mode 100644 index 0000000..68f465c --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_cmd_parser.v
@@ -0,0 +1,146 @@ +module spi_slave_cmd_parser ( + cmd, + get_addr, + get_mode, + get_data, + send_data, + enable_cont, + enable_regs, + wait_dummy, + error, + reg_sel +); + input wire [7:0] cmd; + output reg get_addr; + output reg get_mode; + output reg get_data; + output reg send_data; + output reg enable_cont; + output reg enable_regs; + output reg wait_dummy; + output reg error; + output reg [1:0] reg_sel; + always @(*) begin + get_addr = 0; + get_mode = 0; + get_data = 0; + send_data = 0; + enable_cont = 0; + enable_regs = 1'b0; + wait_dummy = 0; + reg_sel = 2'b00; + error = 1'b1; + case (cmd) + 8'h01: begin + get_addr = 0; + get_mode = 0; + get_data = 1; + send_data = 0; + enable_cont = 0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 0; + reg_sel = 2'b00; + end + 8'h02: begin + get_addr = 1; + get_mode = 0; + get_data = 1; + send_data = 0; + enable_cont = 1'b1; + enable_regs = 1'b0; + error = 1'b0; + wait_dummy = 0; + reg_sel = 2'b00; + end + 8'h05: begin + get_addr = 0; + get_mode = 0; + get_data = 0; + send_data = 1; + enable_cont = 0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 0; + reg_sel = 2'b00; + end + 8'h07: begin + get_addr = 0; + get_mode = 0; + get_data = 0; + send_data = 1; + enable_cont = 0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 0; + reg_sel = 2'b01; + end + 8'h0b: begin + get_addr = 1; + get_mode = 0; + get_data = 0; + send_data = 1; + enable_cont = 1'b1; + enable_regs = 1'b0; + error = 1'b0; + wait_dummy = 1; + reg_sel = 2'b00; + end + 8'h11: begin + get_addr = 1'b0; + get_mode = 1'b0; + get_data = 1'b1; + send_data = 1'b0; + enable_cont = 1'b0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 1'b0; + reg_sel = 2'b01; + end + 8'h20: begin + get_addr = 1'b0; + get_mode = 1'b0; + get_data = 1'b1; + send_data = 1'b0; + enable_cont = 1'b0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 1'b0; + reg_sel = 2'b10; + end + 8'h21: begin + get_addr = 1'b0; + get_mode = 1'b0; + get_data = 1'b0; + send_data = 1'b1; + enable_cont = 1'b0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 1'b0; + reg_sel = 2'b10; + end + 8'h30: begin + get_addr = 1'b0; + get_mode = 1'b0; + get_data = 1'b1; + send_data = 1'b0; + enable_cont = 1'b0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 1'b0; + reg_sel = 2'b11; + end + 8'h31: begin + get_addr = 1'b0; + get_mode = 1'b0; + get_data = 1'b0; + send_data = 1'b1; + enable_cont = 1'b0; + enable_regs = 1'b1; + error = 1'b0; + wait_dummy = 1'b0; + reg_sel = 2'b11; + end + endcase + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_controller.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_controller.v new file mode 100644 index 0000000..69f255f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_controller.v
@@ -0,0 +1,312 @@ +module spi_slave_controller +#( + parameter DUMMY_CYCLES = 32 + ) +( + sclk, + sys_rstn, + cs, + en_quad, + pad_mode, + rx_counter, + rx_counter_upd, + rx_data, + rx_data_valid, + tx_counter, + tx_counter_upd, + tx_data, + tx_data_valid, + tx_done, + ctrl_rd_wr, + ctrl_addr, + ctrl_addr_valid, + ctrl_data_rx, + ctrl_data_rx_valid, + ctrl_data_rx_ready, + ctrl_data_tx, + ctrl_data_tx_valid, + ctrl_data_tx_ready, + wrap_length +); + //parameter DUMMY_CYCLES = 32; + input wire sclk; + input wire sys_rstn; + input wire cs; + output wire en_quad; + output reg [1:0] pad_mode; + output reg [7:0] rx_counter; + output reg rx_counter_upd; + input wire [31:0] rx_data; + input wire rx_data_valid; + output reg [7:0] tx_counter; + output reg tx_counter_upd; + output reg [31:0] tx_data; + output reg tx_data_valid; + input wire tx_done; + output wire ctrl_rd_wr; + output wire [31:0] ctrl_addr; + output reg ctrl_addr_valid; + output wire [31:0] ctrl_data_rx; + output reg ctrl_data_rx_valid; + input wire ctrl_data_rx_ready; + input wire [31:0] ctrl_data_tx; + input wire ctrl_data_tx_valid; + output reg ctrl_data_tx_ready; + output wire [15:0] wrap_length; + localparam REG_SIZE = 8; + reg [2:0] state; + reg [2:0] state_next; + wire [7:0] command; + reg decode_cmd_comb; + reg [31:0] addr_reg; + reg [7:0] cmd_reg; + reg [7:0] mode_reg; + reg [31:0] data_reg; + reg sample_ADDR; + reg sample_MODE; + reg sample_CMD; + reg sample_DATA; + wire get_addr; + wire wait_dummy; + wire get_mode; + wire get_data; + wire send_data; + wire enable_cont; + wire enable_regs; + wire cmd_error; + wire [1:0] reg_sel; + wire [7:0] reg_data; + reg reg_valid; + reg ctrl_data_tx_ready_next; + reg [7:0] tx_counter_next; + reg tx_counter_upd_next; + reg tx_data_valid_next; + reg tx_done_reg; + reg [1:0] pad_mode_next; + wire [7:0] s_dummy_cycles; + assign command = (decode_cmd_comb ? rx_data[7:0] : cmd_reg); + spi_slave_cmd_parser u_cmd_parser( + .cmd(command), + .get_addr(get_addr), + .get_mode(get_mode), + .get_data(get_data), + .send_data(send_data), + .wait_dummy(wait_dummy), + .enable_cont(enable_cont), + .enable_regs(enable_regs), + .error(cmd_error), + .reg_sel(reg_sel) + ); + spi_slave_regs #(.REG_SIZE(REG_SIZE)) u_spiregs( + .sclk(sclk), + .rstn(sys_rstn), + .wr_data(rx_data[7:0]), + .wr_addr(reg_sel), + .wr_data_valid(reg_valid), + .rd_data(reg_data), + .rd_addr(reg_sel), + .dummy_cycles(s_dummy_cycles), + .en_qpi(en_quad), + .wrap_length(wrap_length) + ); + always @(*) begin + pad_mode = (en_quad ? 2'b11 : 2'b01); + rx_counter = 8'h1f; + rx_counter_upd = 0; + tx_counter_next = 8'h1f; + tx_counter_upd_next = 0; + decode_cmd_comb = 1'b0; + sample_ADDR = 1'b0; + sample_MODE = 1'b0; + sample_CMD = 1'b0; + sample_DATA = 1'b0; + ctrl_data_rx_valid = 1'b0; + ctrl_data_tx_ready_next = 1'b0; + reg_valid = 1'b0; + tx_data_valid_next = 1'b0; + state_next = state; + case (state) + 3'd0: begin + pad_mode = (en_quad ? 2'b11 : 2'b01); + decode_cmd_comb = 1'b1; + ctrl_data_tx_ready_next = 1'b1; + if (rx_data_valid) begin + sample_CMD = 1'b1; + if (get_addr) begin + state_next = 3'd1; + rx_counter_upd = 1; + rx_counter = (en_quad ? 8'h07 : 8'h1f); + end + else if (get_data) begin + state_next = 3'd4; + rx_counter_upd = 1; + if (enable_regs) + rx_counter = (en_quad ? 8'h01 : 8'h07); + end + else begin + state_next = 3'd3; + tx_counter_upd_next = 1; + tx_data_valid_next = 1'b1; + tx_counter_next = (en_quad ? 8'h07 : 8'h1f); + if (~enable_regs) + ctrl_data_tx_ready_next = 1'b1; + end + end + else + state_next = 3'd0; + end + 3'd1: begin + pad_mode = (en_quad ? 2'b11 : 2'b01); + ctrl_data_tx_ready_next = 1'b1; + if (rx_data_valid) begin + sample_ADDR = 1'b1; + if (wait_dummy) begin + state_next = 3'd5; + rx_counter = s_dummy_cycles; + rx_counter_upd = 1; + end + else if (send_data) begin + state_next = 3'd3; + tx_counter_upd_next = 1; + tx_counter_next = (en_quad ? 8'h07 : 8'h1f); + end + else if (get_data) begin + state_next = 3'd4; + rx_counter_upd = 1; + rx_counter = (en_quad ? 8'h07 : 8'h1f); + end + end + else + state_next = 3'd1; + end + 3'd2: begin + pad_mode = (en_quad ? 2'b11 : 2'b01); + if (rx_data_valid) begin + if (wait_dummy) begin + state_next = 3'd5; + rx_counter = DUMMY_CYCLES; + rx_counter_upd = 1; + end + else if (get_data) begin + state_next = 3'd4; + rx_counter = (en_quad ? 8'h07 : 8'h1f); + rx_counter_upd = 1; + end + else if (send_data) begin + state_next = 3'd3; + tx_counter_next = (en_quad ? 8'h07 : 8'h1f); + tx_counter_upd_next = 1; + tx_data_valid_next = 1'b1; + if (~enable_regs) + ctrl_data_tx_ready_next = 1'b1; + end + end + else + state_next = 3'd2; + end + 3'd5: begin + pad_mode = (en_quad ? 2'b11 : 2'b01); + if (rx_data_valid) begin + if (get_data) begin + state_next = 3'd4; + rx_counter = (en_quad ? 8'h07 : 8'h1f); + rx_counter_upd = 1; + end + else begin + if (en_quad) + pad_mode_next = 2'b10; + state_next = 3'd3; + tx_counter_next = (en_quad ? 8'h07 : 8'h1f); + tx_counter_upd_next = 1; + tx_data_valid_next = 1'b1; + if (~enable_regs) + ctrl_data_tx_ready_next = 1'b1; + end + end + else + state_next = 3'd5; + end + 3'd4: begin + pad_mode = (en_quad ? 2'b11 : 2'b01); + if (rx_data_valid) begin + if (enable_regs) + reg_valid = 1'b1; + else + ctrl_data_rx_valid = 1'b1; + if (enable_cont) begin + state_next = 3'd4; + rx_counter = (en_quad ? 8'h07 : 8'h1f); + rx_counter_upd = 1; + end + else begin + state_next = 3'd0; + rx_counter = (en_quad ? 8'h01 : 8'h07); + rx_counter_upd = 1; + end + end + else + state_next = 3'd4; + end + 3'd3: begin + pad_mode = (en_quad ? 2'b10 : 2'b00); + if (tx_done_reg) begin + if (enable_cont) begin + state_next = 3'd3; + tx_counter_next = (en_quad ? 8'h07 : 8'h1f); + tx_counter_upd_next = 1; + tx_data_valid_next = 1'b1; + if (~enable_regs) + ctrl_data_tx_ready_next = 1'b1; + end + else begin + state_next = 3'd0; + rx_counter = (en_quad ? 8'h01 : 8'h07); + rx_counter_upd = 1; + end + end + else + state_next = 3'd3; + end + 3'd6: state_next = 3'd6; + endcase + end + always @(posedge sclk or posedge cs) + if (cs == 1'b1) + state <= 3'd0; + else + state <= state_next; + always @(posedge sclk or posedge cs) + if (cs == 1'b1) begin + addr_reg <= 'h0; + mode_reg <= 'h0; + data_reg <= 'h0; + cmd_reg <= 'h0; + tx_done_reg <= 1'b0; + ctrl_addr_valid <= 1'b0; + tx_counter_upd <= 1'b0; + tx_data_valid <= 1'b0; + ctrl_data_tx_ready <= 1'b0; + tx_counter <= 'h0; + tx_data <= 'h0; + end + else begin + if (sample_ADDR) + addr_reg <= rx_data; + if (sample_MODE) + mode_reg <= rx_data[7:0]; + if (sample_CMD) + cmd_reg <= rx_data[7:0]; + if (sample_DATA) + data_reg <= rx_data; + ctrl_addr_valid <= sample_ADDR; + tx_counter_upd <= tx_counter_upd_next; + tx_counter <= tx_counter_next; + tx_data_valid <= tx_data_valid_next; + tx_done_reg <= tx_done; + ctrl_data_tx_ready <= ctrl_data_tx_ready_next; + tx_data <= (enable_regs ? reg_data : ctrl_data_tx); + end + assign ctrl_data_rx = rx_data; + assign ctrl_addr = addr_reg; + assign ctrl_rd_wr = send_data; +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_dc_fifo.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_dc_fifo.v new file mode 100644 index 0000000..f5c883f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_dc_fifo.v
@@ -0,0 +1,59 @@ +module spi_slave_dc_fifo +#( + parameter DATA_WIDTH = 32, + parameter BUFFER_DEPTH = 8 + ) +( + clk_a, + rstn_a, + data_a, + valid_a, + ready_a, + clk_b, + rstn_b, + data_b, + valid_b, + ready_b +); + //parameter DATA_WIDTH = 32; + //parameter BUFFER_DEPTH = 8; + input wire clk_a; + input wire rstn_a; + input wire [DATA_WIDTH - 1:0] data_a; + input wire valid_a; + output wire ready_a; + input wire clk_b; + input wire rstn_b; + output wire [DATA_WIDTH - 1:0] data_b; + output wire valid_b; + input wire ready_b; + wire [DATA_WIDTH - 1:0] data_async; + wire [BUFFER_DEPTH - 1:0] write_token; + wire [BUFFER_DEPTH - 1:0] read_pointer; + dc_token_ring_fifo_din #( + .DATA_WIDTH(DATA_WIDTH), + .BUFFER_DEPTH(BUFFER_DEPTH) + ) u_din( + .clk(clk_a), + .rstn(rstn_a), + .data(data_a), + .valid(valid_a), + .ready(ready_a), + .write_token(write_token), + .read_pointer(read_pointer), + .data_async(data_async) + ); + dc_token_ring_fifo_dout #( + .DATA_WIDTH(DATA_WIDTH), + .BUFFER_DEPTH(BUFFER_DEPTH) + ) u_dout( + .clk(clk_b), + .rstn(rstn_b), + .data(data_b), + .valid(valid_b), + .ready(ready_b), + .write_token(write_token), + .read_pointer(read_pointer), + .data_async(data_async) + ); +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_regs.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_regs.v new file mode 100644 index 0000000..56aa4d7 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_regs.v
@@ -0,0 +1,56 @@ +module spi_slave_regs +#( + parameter REG_SIZE = 8 +) +( + sclk, + rstn, + wr_data, + wr_addr, + wr_data_valid, + rd_data, + rd_addr, + dummy_cycles, + en_qpi, + wrap_length +); + //parameter REG_SIZE = 8; + input wire sclk; + input wire rstn; + input wire [REG_SIZE - 1:0] wr_data; + input wire [1:0] wr_addr; + input wire wr_data_valid; + output reg [REG_SIZE - 1:0] rd_data; + input wire [1:0] rd_addr; + output wire [7:0] dummy_cycles; + output wire en_qpi; + output wire [15:0] wrap_length; + reg [REG_SIZE - 1:0] reg0; + reg [REG_SIZE - 1:0] reg1; + reg [REG_SIZE - 1:0] reg2; + reg [REG_SIZE - 1:0] reg3; + assign en_qpi = reg0[0]; + assign dummy_cycles = reg1; + assign wrap_length = {reg3, reg2}; + always @(*) + case (rd_addr) + 2'b00: rd_data = reg0; + 2'b01: rd_data = reg1; + 2'b10: rd_data = reg2; + 2'b11: rd_data = reg3; + endcase + always @(posedge sclk or negedge rstn) + if (rstn == 0) begin + reg0 <= 'h0; + reg1 <= 'd32; + reg2 <= 'h0; + reg3 <= 'h0; + end + else if (wr_data_valid) + case (wr_addr) + 2'b00: reg0 <= wr_data; + 2'b01: reg1 <= wr_data; + 2'b10: reg2 <= wr_data; + 2'b11: reg3 <= wr_data; + endcase +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_rx.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_rx.v new file mode 100644 index 0000000..92b9161 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_rx.v
@@ -0,0 +1,80 @@ +module spi_slave_rx ( + sclk, + cs, + sdi0, + sdi1, + sdi2, + sdi3, + en_quad_in, + counter_in, + counter_in_upd, + data, + data_ready +); + input wire sclk; + input wire cs; + input wire sdi0; + input wire sdi1; + input wire sdi2; + input wire sdi3; + input wire en_quad_in; + input wire [7:0] counter_in; + input wire counter_in_upd; + output wire [31:0] data; + output reg data_ready; + reg [31:0] data_int; + reg [31:0] data_int_next; + reg [7:0] counter; + reg [7:0] counter_trgt; + reg [7:0] counter_next; + reg [7:0] counter_trgt_next; + reg running; + reg running_next; + assign data = data_int_next; + always @(*) begin + if (counter_in_upd) + counter_trgt_next = counter_in; + else if ((counter_trgt == 8'h01) && !en_quad_in) + counter_trgt_next = 8'h07; + else + counter_trgt_next = counter_trgt; + if (counter_in_upd) + running_next = 1'b1; + else if (counter == counter_trgt) + running_next = 1'b0; + else + running_next = running; + if (running) begin + if (counter == counter_trgt) begin + counter_next = 'h0; + data_ready = 1'b1; + end + else begin + counter_next = counter + 1; + data_ready = 1'b0; + end + if (en_quad_in) + data_int_next = {data_int[27:0], sdi3, sdi2, sdi1, sdi0}; + else + data_int_next = {data_int[30:0], sdi0}; + end + else begin + counter_next = counter; + data_ready = 1'b0; + data_int_next = data_int; + end + end + always @(posedge sclk or posedge cs) + if (cs == 1'b1) begin + counter <= 0; + counter_trgt <= 'h1; + data_int <= 'h0; + running <= 'h1; + end + else begin + counter <= counter_next; + counter_trgt <= counter_trgt_next; + data_int <= data_int_next; + running <= running_next; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_syncro.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_syncro.v new file mode 100644 index 0000000..538279f --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_syncro.v
@@ -0,0 +1,46 @@ +module spi_slave_syncro +#( + parameter AXI_ADDR_WIDTH = 32 + ) +( + sys_clk, + rstn, + cs, + address, + address_valid, + rd_wr, + cs_sync, + address_sync, + address_valid_sync, + rd_wr_sync +); + //parameter AXI_ADDR_WIDTH = 32; + input wire sys_clk; + input wire rstn; + input wire cs; + input wire [AXI_ADDR_WIDTH - 1:0] address; + input wire address_valid; + input wire rd_wr; + output wire cs_sync; + output wire [AXI_ADDR_WIDTH - 1:0] address_sync; + output wire address_valid_sync; + output wire rd_wr_sync; + reg [1:0] cs_reg; + reg [2:0] valid_reg; + reg [1:0] rdwr_reg; + assign cs_sync = cs_reg[1]; + assign address_valid_sync = ~valid_reg[2] & valid_reg[1]; + assign address_sync = address; + assign rd_wr_sync = rdwr_reg[1]; + always @(posedge sys_clk or negedge rstn) + if (rstn == 1'b0) begin + cs_reg <= 2'b11; + valid_reg <= 3'b000; + rdwr_reg <= 2'b00; + end + else begin + cs_reg <= {cs_reg[0], cs}; + valid_reg <= {valid_reg[1:0], address_valid}; + rdwr_reg <= {rdwr_reg[0], rd_wr}; + end +endmodule
diff --git a/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_tx.v b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_tx.v new file mode 100644 index 0000000..0288466 --- /dev/null +++ b/verilog/rtl/ips/axi/axi_spi_slave/spi_slave_tx.v
@@ -0,0 +1,97 @@ +module spi_slave_tx ( + test_mode, + sclk, + cs, + sdo0, + sdo1, + sdo2, + sdo3, + en_quad_in, + counter_in, + counter_in_upd, + data, + data_valid, + done +); + input wire test_mode; + input wire sclk; + input wire cs; + output wire sdo0; + output wire sdo1; + output wire sdo2; + output wire sdo3; + input wire en_quad_in; + input wire [7:0] counter_in; + input wire counter_in_upd; + input wire [31:0] data; + input wire data_valid; + output reg done; + reg [31:0] data_int; + reg [31:0] data_int_next; + reg [7:0] counter; + reg [7:0] counter_trgt; + reg [7:0] counter_next; + reg [7:0] counter_trgt_next; + reg running; + reg running_next; + wire sclk_inv; + wire sclk_test; + assign sdo0 = (en_quad_in ? data_int[28] : data_int[31]); + assign sdo1 = (en_quad_in ? data_int[29] : 1'b0); + assign sdo2 = (en_quad_in ? data_int[30] : 1'b0); + assign sdo3 = (en_quad_in ? data_int[31] : 1'b0); + always @(*) begin + done = 1'b0; + if (counter_in_upd) + counter_trgt_next = counter_in; + else + counter_trgt_next = counter_trgt; + if (counter_in_upd) + running_next = 1'b1; + else if (counter == counter_trgt) + running_next = 1'b0; + else + running_next = running; + if (running || counter_in_upd) begin + if (counter == counter_trgt) begin + done = 1'b1; + counter_next = 0; + end + else + counter_next = counter + 1; + if (data_valid) + data_int_next = data; + else if (en_quad_in) + data_int_next = {data_int[27:0], 4'b0000}; + else + data_int_next = {data_int[30:0], 1'b0}; + end + else begin + counter_next = counter; + data_int_next = data_int; + end + end + pulp_clock_inverter clk_inv_i( + .clk_i(sclk), + .clk_o(sclk_inv) + ); + pulp_clock_mux2 clk_mux_i( + .clk0_i(sclk_inv), + .clk1_i(sclk), + .clk_sel_i(test_mode), + .clk_o(sclk_test) + ); + always @(posedge sclk_test or posedge cs) + if (cs == 1'b1) begin + counter <= 'h0; + counter_trgt <= 'h7; + data_int <= 'h0; + running <= 1'b0; + end + else begin + counter <= counter_next; + counter_trgt <= counter_trgt_next; + data_int <= data_int_next; + running <= running_next; + end +endmodule
diff --git a/verilog/rtl/ips/axi/core2axi/core2axi.v b/verilog/rtl/ips/axi/core2axi/core2axi.v new file mode 100644 index 0000000..dac1c55 --- /dev/null +++ b/verilog/rtl/ips/axi/core2axi/core2axi.v
@@ -0,0 +1,286 @@ +module core2axi +#( + parameter AXI4_ADDRESS_WIDTH = 32, + parameter AXI4_RDATA_WIDTH = 32, + parameter AXI4_WDATA_WIDTH = 32, + parameter AXI4_ID_WIDTH = 16, + parameter AXI4_USER_WIDTH = 10, + parameter REGISTERED_GRANT = "FALSE" // "TRUE"|"FALSE" +) +( + clk_i, + rst_ni, + data_req_i, + data_gnt_o, + data_rvalid_o, + data_addr_i, + data_we_i, + data_be_i, + data_rdata_o, + data_wdata_i, + aw_id_o, + aw_addr_o, + aw_len_o, + aw_size_o, + aw_burst_o, + aw_lock_o, + aw_cache_o, + aw_prot_o, + aw_region_o, + aw_user_o, + aw_qos_o, + aw_valid_o, + aw_ready_i, + w_data_o, + w_strb_o, + w_last_o, + w_user_o, + w_valid_o, + w_ready_i, + b_id_i, + b_resp_i, + b_valid_i, + b_user_i, + b_ready_o, + ar_id_o, + ar_addr_o, + ar_len_o, + ar_size_o, + ar_burst_o, + ar_lock_o, + ar_cache_o, + ar_prot_o, + ar_region_o, + ar_user_o, + ar_qos_o, + ar_valid_o, + ar_ready_i, + r_id_i, + r_data_i, + r_resp_i, + r_last_i, + r_user_i, + r_valid_i, + r_ready_o +); + //parameter AXI4_ADDRESS_WIDTH = 32; + //parameter AXI4_RDATA_WIDTH = 32; + //parameter AXI4_WDATA_WIDTH = 32; + //parameter AXI4_ID_WIDTH = 16; + //parameter AXI4_USER_WIDTH = 10; + //parameter REGISTERED_GRANT = "FALSE"; + input wire clk_i; + input wire rst_ni; + input wire data_req_i; + output wire data_gnt_o; + output wire data_rvalid_o; + input wire [AXI4_ADDRESS_WIDTH - 1:0] data_addr_i; + input wire data_we_i; + input wire [3:0] data_be_i; + output wire [31:0] data_rdata_o; + input wire [31:0] data_wdata_i; + output wire [AXI4_ID_WIDTH - 1:0] aw_id_o; + output wire [AXI4_ADDRESS_WIDTH - 1:0] aw_addr_o; + output wire [7:0] aw_len_o; + output wire [2:0] aw_size_o; + output wire [1:0] aw_burst_o; + output wire aw_lock_o; + output wire [3:0] aw_cache_o; + output wire [2:0] aw_prot_o; + output wire [3:0] aw_region_o; + output wire [AXI4_USER_WIDTH - 1:0] aw_user_o; + output wire [3:0] aw_qos_o; + output reg aw_valid_o; + input wire aw_ready_i; + output wire [AXI4_WDATA_WIDTH - 1:0] w_data_o; + output wire [(AXI4_WDATA_WIDTH / 8) - 1:0] w_strb_o; + output wire w_last_o; + output wire [AXI4_USER_WIDTH - 1:0] w_user_o; + output reg w_valid_o; + input wire w_ready_i; + input wire [AXI4_ID_WIDTH - 1:0] b_id_i; + input wire [1:0] b_resp_i; + input wire b_valid_i; + input wire [AXI4_USER_WIDTH - 1:0] b_user_i; + output reg b_ready_o; + output wire [AXI4_ID_WIDTH - 1:0] ar_id_o; + output wire [AXI4_ADDRESS_WIDTH - 1:0] ar_addr_o; + output wire [7:0] ar_len_o; + output wire [2:0] ar_size_o; + output wire [1:0] ar_burst_o; + output wire ar_lock_o; + output wire [3:0] ar_cache_o; + output wire [2:0] ar_prot_o; + output wire [3:0] ar_region_o; + output wire [AXI4_USER_WIDTH - 1:0] ar_user_o; + output wire [3:0] ar_qos_o; + output reg ar_valid_o; + input wire ar_ready_i; + input wire [AXI4_ID_WIDTH - 1:0] r_id_i; + input wire [AXI4_RDATA_WIDTH - 1:0] r_data_i; + input wire [1:0] r_resp_i; + input wire r_last_i; + input wire [AXI4_USER_WIDTH - 1:0] r_user_i; + input wire r_valid_i; + output reg r_ready_o; + reg [2:0] CS; + reg [2:0] NS; + wire [31:0] rdata; + reg valid; + reg granted; + always @(*) begin + NS = CS; + granted = 1'b0; + valid = 1'b0; + aw_valid_o = 1'b0; + ar_valid_o = 1'b0; + r_ready_o = 1'b0; + w_valid_o = 1'b0; + b_ready_o = 1'b0; + case (CS) + 3'd0: + if (data_req_i) begin + if (data_we_i) begin + aw_valid_o = 1'b1; + w_valid_o = 1'b1; + if (aw_ready_i) begin + if (w_ready_i) begin + granted = 1'b1; + NS = 3'd4; + end + else + NS = 3'd2; + end + else if (w_ready_i) + NS = 3'd3; + else + NS = 3'd0; + end + else begin + ar_valid_o = 1'b1; + if (ar_ready_i) begin + granted = 1'b1; + NS = 3'd1; + end + else + NS = 3'd0; + end + end + else + NS = 3'd0; + 3'd2: begin + w_valid_o = 1'b1; + if (w_ready_i) begin + granted = 1'b1; + NS = 3'd4; + end + end + 3'd3: begin + aw_valid_o = 1'b1; + if (aw_ready_i) begin + granted = 1'b1; + NS = 3'd4; + end + end + 3'd4: begin + b_ready_o = 1'b1; + if (b_valid_i) begin + valid = 1'b1; + NS = 3'd0; + end + end + 3'd1: + if (r_valid_i) begin + valid = 1'b1; + r_ready_o = 1'b1; + NS = 3'd0; + end + default: NS = 3'd0; + endcase + end + always @(posedge clk_i or negedge rst_ni) + if (~rst_ni) + CS <= 3'd0; + else + CS <= NS; + generate + if (AXI4_RDATA_WIDTH == 32) begin : genblk1 + assign rdata = r_data_i[31:0]; + end + else if (AXI4_RDATA_WIDTH == 64) begin : genblk1 + reg [0:0] addr_q; + always @(posedge clk_i or negedge rst_ni) + if (~rst_ni) + addr_q <= 1'sb0; + else if (data_gnt_o) + addr_q <= data_addr_i[2:2]; + assign rdata = (addr_q[0] ? r_data_i[63:32] : r_data_i[31:0]); + end + else begin : genblk1 + initial $error("AXI4_WDATA_WIDTH has an invalid value"); + end + endgenerate + genvar w; + generate + for (w = 0; w < (AXI4_WDATA_WIDTH / 32); w = w + 1) begin : genblk2 + assign w_data_o[(w * 32) + 31:w * 32] = data_wdata_i; + end + if (AXI4_WDATA_WIDTH == 32) begin : genblk3 + assign w_strb_o = data_be_i; + end + else if (AXI4_WDATA_WIDTH == 64) begin : genblk3 + assign w_strb_o = (data_addr_i[2] ? {data_be_i, 4'b0000} : {4'b0000, data_be_i}); + end + else begin : genblk3 + initial $error("AXI4_WDATA_WIDTH has an invalid value"); + end + endgenerate + assign aw_id_o = 1'sb0; + assign aw_addr_o = data_addr_i; + assign aw_size_o = 3'b010; + assign aw_len_o = 1'sb0; + assign aw_burst_o = 1'sb0; + assign aw_lock_o = 1'sb0; + assign aw_cache_o = 1'sb0; + assign aw_prot_o = 1'sb0; + assign aw_region_o = 1'sb0; + assign aw_user_o = 1'sb0; + assign aw_qos_o = 1'sb0; + assign ar_id_o = 1'sb0; + assign ar_addr_o = data_addr_i; + assign ar_size_o = 3'b010; + assign ar_len_o = 1'sb0; + assign ar_burst_o = 1'sb0; + assign ar_prot_o = 1'sb0; + assign ar_region_o = 1'sb0; + assign ar_lock_o = 1'sb0; + assign ar_cache_o = 1'sb0; + assign ar_qos_o = 1'sb0; + assign ar_user_o = 1'sb0; + assign w_last_o = 1'b1; + assign w_user_o = 1'sb0; + generate + if (REGISTERED_GRANT == "TRUE") begin : genblk4 + reg valid_q; + reg [31:0] rdata_q; + always @(posedge clk_i or negedge rst_ni) + if (~rst_ni) begin + valid_q <= 1'b0; + rdata_q <= 1'sb0; + end + else begin + valid_q <= valid; + if (valid) + rdata_q <= rdata; + end + assign data_rdata_o = rdata_q; + assign data_rvalid_o = valid_q; + assign data_gnt_o = valid; + end + else begin : genblk4 + assign data_rdata_o = rdata; + assign data_rvalid_o = valid; + assign data_gnt_o = granted; + end + endgenerate +endmodule