commit b8c990e72e2e299836cb9d9ba8fd4c53a22b9fb8
author mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 01:00:50 2022 +0300
committer mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 01:00:50 2022 +0300
tree 0fe6f5c3ae4480aedb5424a71df6f6a5ddb3730b
parent 991806812a9677a8ead390aeb0066eeaa5fbb772

Update README.md

README.md

diff --git a/README.md b/README.md
index 31aef5d..85ea344 100644
--- a/README.md
+++ b/README.md
@@ -28,10 +28,19 @@
 Original SystemVerilog implementation of Yonga-MCU is verified through modelsim environment provided with pulpino repo. We converted SV files to Verilog through sv2v and reverified the MCU.
 
 ## GDSII Images
+
+axi_node_intf_wrap macro
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/axi_node_intf_wrap.PNG "axi_node_intf_wrap")
 
+mba_core_region macro
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/mba_core_region.PNG "mba_core_region")
 
+peripherals macro
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/peripherals.PNG "peripherals")
 
+user_project_wrapper - top module
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/user_project_wrapper.PNG "user_project_wrapper")
\ No newline at end of file