diff --git a/README.md b/README.md
index 31aef5d..85ea344 100644
--- a/README.md
+++ b/README.md
@@ -28,10 +28,19 @@
 Original SystemVerilog implementation of Yonga-MCU is verified through modelsim environment provided with pulpino repo. We converted SV files to Verilog through sv2v and reverified the MCU.
 
 ## GDSII Images
+
+axi_node_intf_wrap macro
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/axi_node_intf_wrap.PNG "axi_node_intf_wrap")
 
+mba_core_region macro
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/mba_core_region.PNG "mba_core_region")
 
+peripherals macro
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/peripherals.PNG "peripherals")
 
+user_project_wrapper - top module
+
 ![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/user_project_wrapper.PNG "user_project_wrapper")
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