update macro wrappers and config.tcl
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index f47761b..4588029 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -39,7 +39,7 @@ ## Clock configurations set ::env(CLOCK_PORT) "user_clock2" -set ::env(CLOCK_NET) "mprj.clk" +set ::env(CLOCK_NET) "user_clock2" set ::env(CLOCK_PERIOD) "200" @@ -50,15 +50,17 @@ #set ::env(VDD_NETS) [list {vccd1}] #set ::env(GND_NETS) [list {vssd1}] +#set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} +#set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2} #set ::env(VDD_NET) {vccd1} #set ::env(VDD_PIN) {vccd1} #set ::env(GND_NET) {vssd1} #set ::env(GND_PIN) {vssd1} -#set ::env(FP_PDN_ENABLE_MACROS_GRID) "1" +set ::env(FP_PDN_ENABLE_MACROS_GRID) "1" #set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1" ### Macro Placement set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg -#set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" +set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" #set ::env(SYNTH_DEFINES) "USE_POWER_PINS" # other configurations @@ -101,7 +103,7 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ + $script_dir/../../verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v \ $script_dir/../../verilog/rtl/rtl/mba_core_region.v \ $script_dir/../../verilog/rtl/rtl/clk_rst_gen.v \ $script_dir/../../verilog/rtl/rtl/peripherals.v \ @@ -123,7 +125,7 @@ # set ::env(GLB_RT_MAXLAYER) 5 -set ::env(RT_MAX_LAYER) {met5} +set ::env(RT_MAX_LAYER) {met4} # disable pdn check nodes becuase it hangs with multiple power domains. # any issue with pdn connections will be flagged with LVS so it is not a critical check.
diff --git a/verilog/rtl/rtl/axi_node_intf_wrap.v b/verilog/rtl/rtl/axi_node_intf_wrap.v index c6ecb6f..6c40638 100644 --- a/verilog/rtl/rtl/axi_node_intf_wrap.v +++ b/verilog/rtl/rtl/axi_node_intf_wrap.v
@@ -1,4 +1,4 @@ -`define USE_POWER_PINS +//`define USE_POWER_PINS module axi_node_intf_wrap #( @@ -280,9 +280,9 @@ m02_b_id, m02_b_user, m02_b_ready, - m02_b_valid, - start_addr_i, - end_addr_i + m02_b_valid +// start_addr_i, +// end_addr_i ); //parameter NB_MASTER = 3; //parameter NB_SLAVE = 3; @@ -564,8 +564,8 @@ input wire [AXI_USER_WIDTH - 1:0] m02_b_user; output wire m02_b_ready; input wire m02_b_valid; - input wire [(NB_MASTER * AXI_ADDR_WIDTH) - 1:0] start_addr_i; - input wire [(NB_MASTER * AXI_ADDR_WIDTH) - 1:0] end_addr_i; +// input wire [(NB_MASTER * AXI_ADDR_WIDTH) - 1:0] start_addr_i; +// input wire [(NB_MASTER * AXI_ADDR_WIDTH) - 1:0] end_addr_i; localparam NB_REGION = 1; wire [(NB_MASTER * AXI_ID_WIDTH_INIT) - 1:0] s_master_aw_id; @@ -704,8 +704,8 @@ assign s_master_r_user[0+:AXI_USER_WIDTH] = m00_r_user; assign s_master_r_valid[0] = m00_r_valid; assign m00_r_ready = s_master_r_ready[0]; - assign s_start_addr[0+:AXI_ADDR_WIDTH] = start_addr_i[0+:AXI_ADDR_WIDTH]; - assign s_end_addr[0+:AXI_ADDR_WIDTH] = end_addr_i[0+:AXI_ADDR_WIDTH]; +// assign s_start_addr[0+:AXI_ADDR_WIDTH] = start_addr_i[0+:AXI_ADDR_WIDTH]; +// assign s_end_addr[0+:AXI_ADDR_WIDTH] = end_addr_i[0+:AXI_ADDR_WIDTH]; assign m01_aw_id[AXI_ID_WIDTH_INIT - 1:0] = s_master_aw_id[AXI_ID_WIDTH_INIT+:AXI_ID_WIDTH_INIT]; assign m01_aw_addr = s_master_aw_addr[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; assign m01_aw_len = s_master_aw_len[8+:8]; @@ -750,8 +750,8 @@ assign s_master_r_user[AXI_USER_WIDTH+:AXI_USER_WIDTH] = m01_r_user; assign s_master_r_valid[1] = m01_r_valid; assign m01_r_ready = s_master_r_ready[1]; - assign s_start_addr[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = start_addr_i[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; - assign s_end_addr[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = end_addr_i[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; +// assign s_start_addr[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = start_addr_i[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; +// assign s_end_addr[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = end_addr_i[AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; assign m02_aw_id[AXI_ID_WIDTH_INIT - 1:0] = s_master_aw_id[2 * AXI_ID_WIDTH_INIT+:AXI_ID_WIDTH_INIT]; assign m02_aw_addr = s_master_aw_addr[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; assign m02_aw_len = s_master_aw_len[16+:8]; @@ -796,8 +796,8 @@ assign s_master_r_user[2 * AXI_USER_WIDTH+:AXI_USER_WIDTH] = m02_r_user; assign s_master_r_valid[2] = m02_r_valid; assign m02_r_ready = s_master_r_ready[2]; - assign s_start_addr[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = start_addr_i[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; - assign s_end_addr[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = end_addr_i[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; +// assign s_start_addr[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = start_addr_i[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; +// assign s_end_addr[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH] = end_addr_i[2 * AXI_ADDR_WIDTH+:AXI_ADDR_WIDTH]; assign s_slave_aw_id[0+:AXI_ID_WIDTH_TARG] = s00_aw_id[AXI_ID_WIDTH_TARG - 1:0]; assign s_slave_aw_addr[0+:AXI_ADDR_WIDTH] = s00_aw_addr; assign s_slave_aw_len[0+:8] = s00_aw_len; @@ -1035,6 +1035,8 @@ .cfg_valid_rule_i(s_valid_rule), .cfg_connectivity_map_i(s_connectivity_map) ); +assign s_start_addr = 96'h1a1000000010000000000000; +assign s_end_addr = 96'h1a11ffff001fffff000fffff; assign s_valid_rule = 1'sb1; assign s_connectivity_map = 1'sb1; endmodule
diff --git a/verilog/rtl/rtl/clk_rst_gen.v b/verilog/rtl/rtl/clk_rst_gen.v index 4c86e2d..c19e804 100644 --- a/verilog/rtl/rtl/clk_rst_gen.v +++ b/verilog/rtl/rtl/clk_rst_gen.v
@@ -1,4 +1,4 @@ -`define USE_POWER_PINS +//`define USE_POWER_PINS module clk_rst_gen ( `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v index c4a3e62..b6bb3a1 100644 --- a/verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v +++ b/verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -2,7 +2,7 @@ // Words: 512 // Word size: 32 // Write size: 8 -`define USE_POWER_PINS +//`define USE_POWER_PINS module sky130_sram_2kbyte_1rw1r_32x512_8( `ifdef USE_POWER_PINS vccd1,
diff --git a/verilog/rtl/rtl/mba_core_region.v b/verilog/rtl/rtl/mba_core_region.v index d6d955f..4e08520 100644 --- a/verilog/rtl/rtl/mba_core_region.v +++ b/verilog/rtl/rtl/mba_core_region.v
@@ -1,4 +1,4 @@ -`define USE_POWER_PINS +//`define USE_POWER_PINS module mba_core_region #( parameter AXI_ADDR_WIDTH = 32,
diff --git a/verilog/rtl/rtl/peripherals.v b/verilog/rtl/rtl/peripherals.v index 0658e17..0fd7055 100644 --- a/verilog/rtl/rtl/peripherals.v +++ b/verilog/rtl/rtl/peripherals.v
@@ -1,4 +1,4 @@ -`define USE_POWER_PINS +//`define USE_POWER_PINS module peripherals #(
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index a6f406a..ed4a355 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -460,12 +460,19 @@ ////////////////////////////////////////// // MBA END - assign io_oeb[37:27] = 11'b00000000000; - assign io_out[26:0] = 27'b111111111111111111111111111; // does not have effect due to io_oeb - assign io_oeb[26:0] = 27'b111111111111111111111111111; - assign wbs_ack_o = 1'b0; - assign wbs_dat_o = 32'b00000000000000000000000000000000; - assign la_data_out[63:0] = 64'b0000000000000000000000000000000000000000000000000000000000000000; +// assign io_oeb[37:27] = 11'b00000000000; +// assign io_out[26:0] = 27'b111111111111111111111111111; // does not have effect due to io_oeb +// assign io_oeb[26:0] = 27'b111111111111111111111111111; +// assign wbs_ack_o = 1'b0; +// assign wbs_dat_o = 32'b00000000000000000000000000000000; +// assign la_data_out[63:0] = 64'b0000000000000000000000000000000000000000000000000000000000000000; + + assign io_oeb[37:27] = {11{wb_rst_i}}; + assign io_out[26:0] = {27{wb_rst_i}}; // does not have effect due to io_oeb + assign io_oeb[26:0] = {27{wb_rst_i}}; + assign wbs_ack_o = wb_rst_i; + assign wbs_dat_o = {32{wb_rst_i}}; + assign la_data_out[63:0] = {64{wb_rst_i}}; /*--------------------------------------*/ @@ -481,7 +488,8 @@ .clk_sel_i(la_data_in[0]), .clk_standalone_i(la_data_in[1]), .testmode_i(la_data_in[2]), - .scan_i(1'b0), +// .scan_i(1'b0), +.scan_i(wb_dat_i[0]), .scan_o(), .scan_en_i(la_data_in[3]), .fll_req_i(cfgreq_fll_int), @@ -745,7 +753,7 @@ .addr0(mba_instr_mem_addr0_o[10:2]), .din0(mba_instr_mem_din0_o), .dout0(mba_instr_mem_dout0_i), - .clk1(1'b0), + .clk1(wb_dat_i[0]), .csb1(mba_instr_mem_csb1_o), .addr1(mba_instr_mem_addr1_o[10:2]), .dout1() @@ -764,7 +772,7 @@ .addr0(mba_data_mem_addr0_o[10:2]), .din0(mba_data_mem_din0_o), .dout0(mba_data_mem_dout0_i), - .clk1(1'b0), + .clk1(wb_dat_i[0]), .csb1(mba_data_mem_csb1_o), .addr1(mba_data_mem_addr1_o[10:2]), .dout1() @@ -845,9 +853,9 @@ .spi_sdo2_o(), .spi_sdo3_o(), .spi_sdi0_i(io_in[19]), - .spi_sdi1_i(1'b0), - .spi_sdi2_i(1'b0), - .spi_sdi3_i(1'b0), + .spi_sdi1_i(wb_dat_i[0]), + .spi_sdi2_i(wb_dat_i[0]), + .spi_sdi3_i(wb_dat_i[0]), .slave_aw_addr(slaves_02_aw_addr), .slave_aw_prot(slaves_02_aw_prot), .slave_aw_region(slaves_02_aw_region), @@ -909,9 +917,9 @@ .spi_master_sdo2(), .spi_master_sdo3(), .spi_master_sdi0(io_in[21]), - .spi_master_sdi1(1'b0), - .spi_master_sdi2(1'b0), - .spi_master_sdi3(1'b0), + .spi_master_sdi1(wb_dat_i[0]), + .spi_master_sdi2(wb_dat_i[0]), + .spi_master_sdi3(wb_dat_i[0]), .scl_pad_i(io_in[22]), .scl_pad_o(io_out[28]), .scl_padoen_o(), @@ -1214,9 +1222,9 @@ .s02_b_id(masters_02_b_id), .s02_b_user(masters_02_b_user), .s02_b_ready(masters_02_b_ready), - .s02_b_valid(masters_02_b_valid), - .start_addr_i(96'h1a1000000010000000000000), - .end_addr_i(96'h1a11ffff001fffff000fffff) + .s02_b_valid(masters_02_b_valid) +// .start_addr_i(96'h1a1000000010000000000000), +// .end_addr_i(96'h1a11ffff001fffff000fffff) );