| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY | |
| /home/mbaykenar/Desktop/workspace/mpw7_yonga_soc/openlane/peripherals_2,peripherals,22_09_07_17_47,flow completed,0h38m42s0ms,0h13m26s0ms,-3.3333333333333335,1.54,-1,17.31,5075.41,-1,0,0,0,0,0,0,0,0,0,-1,-1,3357132,210359,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,2806842043.0,0.0,31.17,75.91,14.23,75.53,-1,18233,38085,1766,21547,0,0,0,22190,766,683,673,618,4546,669,138,2332,4739,4705,28,1600,21253,0,22853,1500720.2304,0.000114,0.000112,0.00019,0.000144,0.000144,2.59e-07,0.000163,0.000171,3.54e-07,1.8999999999999986,201.0,4.975124378109452,200,AREA 0,5,30,1,153.6,153.18,0.30,0.3,sky130_fd_sc_hd,4,3 |