Modfiy user_project_wrapper and config

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 02eb54d..f47761b 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -48,14 +48,18 @@
 
 ## Internal Macros
 
-set ::env(VDD_NETS) [list {vccd1}]
-set ::env(GND_NETS) [list {vssd1}]
-set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
+#set ::env(VDD_NETS) [list {vccd1}]
+#set ::env(GND_NETS) [list {vssd1}]
+#set ::env(VDD_NET) {vccd1}
+#set ::env(VDD_PIN) {vccd1}
+#set ::env(GND_NET) {vssd1}
+#set ::env(GND_PIN) {vssd1}
+#set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
 #set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
 ### Macro Placement
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
-set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
-set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
+#set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+#set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
 
 # other configurations
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 40

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index e8e90c6..a6f406a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -34,7 +34,7 @@
 `define AXI_ID_MASTER_WIDTH     2
 `define AXI_ID_SLAVE_WIDTH      4
 `define AXI_USER_WIDTH          1
-`define USE_POWER_PINS          1
+//`define USE_POWER_PINS          1