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/root/yonga-mcu/verilog/rtl/rtl/pulpino_top_wrapper.v
/root/yonga-mcu/verilog/rtl/rtl/ram_mux.v
/root/yonga-mcu/verilog/rtl/rtl/sp_ram_wrap.v
/root/yonga-mcu/verilog/rtl/rtl/components/cluster_clock_gating.v
/root/yonga-mcu/verilog/rtl/rtl/components/cluster_clock_inverter.v
/root/yonga-mcu/verilog/rtl/rtl/components/cluster_clock_mux2.v
/root/yonga-mcu/verilog/rtl/rtl/components/dp_ram.v
/root/yonga-mcu/verilog/rtl/rtl/components/generic_fifo.v
/root/yonga-mcu/verilog/rtl/rtl/components/pulp_clock_gating.v
/root/yonga-mcu/verilog/rtl/rtl/components/pulp_clock_inverter.v
/root/yonga-mcu/verilog/rtl/rtl/components/pulp_clock_mux2.v
/root/yonga-mcu/verilog/rtl/rtl/components/rstgen.v
/root/yonga-mcu/verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v
/root/yonga-mcu/verilog/rtl/rtl/components/sp_ram.v
/root/yonga-mcu/verilog/rtl/rtl/includes/apb_bus.sv
/root/yonga-mcu/verilog/rtl/rtl/includes/apu_defines.sv
/root/yonga-mcu/verilog/rtl/rtl/includes/axi_bus.sv
/root/yonga-mcu/verilog/rtl/rtl/includes/config.sv
/root/yonga-mcu/verilog/rtl/rtl/includes/debug_bus.sv