sdc/clk_rst_gen.sdc

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# Created by write_sdc
# Wed Sep  7 12:09:55 2022
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current_design clk_rst_gen
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# Timing Constraints
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create_clock -name clk_i -period 200.0000 [get_ports {clk_i}]
set_clock_transition 0.1500 [get_clocks {clk_i}]
set_clock_uncertainty 0.2500 clk_i
set_propagated_clock [get_clocks {clk_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {clk_sel_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {clk_standalone_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_add_i[0]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_add_i[1]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[0]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[10]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[11]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[12]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[13]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[14]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[15]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[16]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[17]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[18]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[19]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[1]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[20]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[21]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[22]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[23]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[24]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[25]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[26]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[27]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[28]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[29]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[2]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[30]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[31]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[3]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[4]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[5]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[6]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[7]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[8]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_data_i[9]}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_req_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_wrn_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rstn_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {scan_en_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {scan_i}]
set_input_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {testmode_i}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {clk_o}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_ack_o}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_lock_o}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[0]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[10]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[11]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[12]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[13]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[14]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[15]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[16]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[17]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[18]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[19]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[1]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[20]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[21]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[22]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[23]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[24]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[25]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[26]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[27]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[28]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[29]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[2]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[30]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[31]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[3]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[4]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[5]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[6]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[7]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[8]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {fll_r_data_o[9]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[0]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[10]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[11]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[12]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[13]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[14]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[15]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[16]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[17]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[18]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[19]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[1]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[20]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[21]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[22]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[23]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[24]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[25]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[26]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[27]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[28]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[29]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[2]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[30]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[31]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[32]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[33]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[34]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[35]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[36]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[37]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[3]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[4]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[5]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[6]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[7]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[8]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_oeb[9]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[0]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[10]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[11]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[12]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[13]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[14]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[15]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[16]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[17]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[18]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[19]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[1]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[20]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[21]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[22]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[23]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[24]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[25]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[2]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[3]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[4]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[5]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[6]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[7]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[8]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {io_out[9]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[0]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[10]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[11]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[12]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[13]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[14]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[15]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[16]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[17]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[18]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[19]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[1]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[20]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[21]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[22]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[23]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[24]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[25]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[26]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[27]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[28]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[29]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[2]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[30]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[31]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[32]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[33]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[34]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[35]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[36]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[37]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[38]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[39]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[3]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[40]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[41]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[42]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[43]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[44]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[45]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[46]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[47]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[48]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[49]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[4]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[50]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[51]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[52]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[53]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[54]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[55]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[56]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[57]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[58]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[59]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[5]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[60]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[61]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[62]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[63]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[6]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[7]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[8]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {la_data_out[9]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rstn_o}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {scan_o}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {user_irq[0]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {user_irq[1]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {user_irq[2]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_ack_o}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
set_output_delay 40.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {clk_o}]
set_load -pin_load 0.0334 [get_ports {fll_ack_o}]
set_load -pin_load 0.0334 [get_ports {fll_lock_o}]
set_load -pin_load 0.0334 [get_ports {rstn_o}]
set_load -pin_load 0.0334 [get_ports {scan_o}]
set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[31]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[30]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[29]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[28]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[27]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[26]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[25]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[24]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[23]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[22]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[21]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[20]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[19]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[18]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[17]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[16]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[15]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[14]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[13]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[12]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[11]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[10]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[9]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[8]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[7]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[6]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[5]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[4]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[3]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[2]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[1]}]
set_load -pin_load 0.0334 [get_ports {fll_r_data_o[0]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
set_load -pin_load 0.0334 [get_ports {io_out[25]}]
set_load -pin_load 0.0334 [get_ports {io_out[24]}]
set_load -pin_load 0.0334 [get_ports {io_out[23]}]
set_load -pin_load 0.0334 [get_ports {io_out[22]}]
set_load -pin_load 0.0334 [get_ports {io_out[21]}]
set_load -pin_load 0.0334 [get_ports {io_out[20]}]
set_load -pin_load 0.0334 [get_ports {io_out[19]}]
set_load -pin_load 0.0334 [get_ports {io_out[18]}]
set_load -pin_load 0.0334 [get_ports {io_out[17]}]
set_load -pin_load 0.0334 [get_ports {io_out[16]}]
set_load -pin_load 0.0334 [get_ports {io_out[15]}]
set_load -pin_load 0.0334 [get_ports {io_out[14]}]
set_load -pin_load 0.0334 [get_ports {io_out[13]}]
set_load -pin_load 0.0334 [get_ports {io_out[12]}]
set_load -pin_load 0.0334 [get_ports {io_out[11]}]
set_load -pin_load 0.0334 [get_ports {io_out[10]}]
set_load -pin_load 0.0334 [get_ports {io_out[9]}]
set_load -pin_load 0.0334 [get_ports {io_out[8]}]
set_load -pin_load 0.0334 [get_ports {io_out[7]}]
set_load -pin_load 0.0334 [get_ports {io_out[6]}]
set_load -pin_load 0.0334 [get_ports {io_out[5]}]
set_load -pin_load 0.0334 [get_ports {io_out[4]}]
set_load -pin_load 0.0334 [get_ports {io_out[3]}]
set_load -pin_load 0.0334 [get_ports {io_out[2]}]
set_load -pin_load 0.0334 [get_ports {io_out[1]}]
set_load -pin_load 0.0334 [get_ports {io_out[0]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_sel_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_standalone_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_req_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_wrn_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rstn_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_en_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {testmode_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_add_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_add_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fll_data_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]