verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/rtl/sha1_top.v
-v $(USER_PROJECT_VERILOG)/rtl/sha1.v
-v $(USER_PROJECT_VERILOG)/rtl/sha1_core.v
-v $(USER_PROJECT_VERILOG)/rtl/sha1_w_mem.v