opencore hasher
diff --git a/verilog/rtl/opencore_hasher/fuse.xmsgs b/verilog/rtl/opencore_hasher/fuse.xmsgs new file mode 100755 index 0000000..c42b14a --- /dev/null +++ b/verilog/rtl/opencore_hasher/fuse.xmsgs
@@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +</messages> +
diff --git a/verilog/rtl/opencore_hasher/fuseRelaunch.cmd b/verilog/rtl/opencore_hasher/fuseRelaunch.cmd new file mode 100755 index 0000000..2f5e58d --- /dev/null +++ b/verilog/rtl/opencore_hasher/fuseRelaunch.cmd
@@ -0,0 +1 @@ +-intstyle "ise" -incremental -lib "secureip" -o "Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/testbench_isim_beh.exe" -prj "Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/testbench_beh.prj" "work.testbench"
diff --git a/verilog/rtl/opencore_hasher/gv_sha256.vhd b/verilog/rtl/opencore_hasher/gv_sha256.vhd new file mode 100755 index 0000000..4213ede --- /dev/null +++ b/verilog/rtl/opencore_hasher/gv_sha256.vhd
@@ -0,0 +1,334 @@ +---------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 01:21:32 05/05/2016 +-- Design Name: gv_sha256 +-- Module Name: GV_SHA256 toplevel +-- Project Name: GV_SHA256 engine +-- Target Devices: Spartan-6 LX45 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- This is the gv_sha256 engine top level. +-- The gv_sha256 is a stream hash engine, i.e., the data words are hashed as a stream of words read from an input bus, with +-- control inputs for BEGIN/END of the message data stream. The input bus is a 32bit word bus, with a byte lane selector to signalize +-- how many bytes are valid in the last word. +-- +-- The core is a structural integration of the logic blocks for the SHA256 engine, with the internal datapath and controlpath wires. +-- +-- Written in synthesizable VHDL, the hash engine is a low resource, area-efficient implementation of the FIPS-180-4 SHA256 hash algorithm. +-- Designed around the core registers and combinational hash functions as a 768bit-wide engine, the engine takes 64+1 clocks to +-- compute a hash block. +-- +-- It is designed for stand-alone ASIC functions and 32-bit bus interfaces for generic processor integration. +-- +-- The data input port is organized as a 32bit word write register, with flow control and begin/end signals. +-- The 256bit result register is organized as 8 x 32bit registers that can be read simultaneously. +-- +-- This implementation is a conservative implementation of the approved FIPS-180-4 algorithm, with a fair compromise of resources, +-- comprising of only 32 registers of 32bit words for the hash engine, with a single-cycle combinational logic for each algorithm step. +-- The combinational logic depth of the engine is 10 logic layers. For a process with 650ps of average (Tpd + Tsu), this core can +-- be synthesized to 75MHz system clock. +-- +-- The GV_SHA256 is a basic cryptographic block, used by almost all encryption and digital signature schemes. +-- +-- Applications include low-cost CyberPhysical Systems and also fast backend crypto functions for realtime hashing of packet data. +-- It is used in the GridVortex CyberSec IP, as a base for the fused HMAC-SHA256, HKDF, HMAC-SHA256-DRBG, and the SP-800 TRNG Entropy Source. +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed. +-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed. +-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed. +-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block, added lookahead register feedback. +-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'. +-- +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity gv_sha256 is + port ( + -- clock and core enable + clk_i : in std_logic := 'U'; -- system clock + ce_i : in std_logic := 'U'; -- core clock enable + -- input data + di_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- big endian input message words + bytes_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- valid bytes in input word + -- start/end commands + start_i : in std_logic := 'U'; -- reset the engine and start a new hash + end_i : in std_logic := 'U'; -- marks end of last block data input + -- handshake + di_req_o : out std_logic; -- requests data input for next word + di_wr_i : in std_logic := 'U'; -- high for di_i valid, low for hold + error_o : out std_logic; -- signalizes error. output data is invalid + do_valid_o : out std_logic; -- when high, the output is valid + -- 256bit output registers + H0_o : out std_logic_vector (31 downto 0); + H1_o : out std_logic_vector (31 downto 0); + H2_o : out std_logic_vector (31 downto 0); + H3_o : out std_logic_vector (31 downto 0); + H4_o : out std_logic_vector (31 downto 0); + H5_o : out std_logic_vector (31 downto 0); + H6_o : out std_logic_vector (31 downto 0); + H7_o : out std_logic_vector (31 downto 0) + ); +end gv_sha256; + +architecture rtl of gv_sha256 is + -- internal register data values + signal R0_data : std_logic_vector (31 downto 0); + signal R1_data : std_logic_vector (31 downto 0); + signal R2_data : std_logic_vector (31 downto 0); + signal R3_data : std_logic_vector (31 downto 0); + signal R4_data : std_logic_vector (31 downto 0); + signal R5_data : std_logic_vector (31 downto 0); + signal R6_data : std_logic_vector (31 downto 0); + signal R7_data : std_logic_vector (31 downto 0); + -- initial hash data values + signal K0_data : std_logic_vector (31 downto 0); + signal K1_data : std_logic_vector (31 downto 0); + signal K2_data : std_logic_vector (31 downto 0); + signal K3_data : std_logic_vector (31 downto 0); + signal K4_data : std_logic_vector (31 downto 0); + signal K5_data : std_logic_vector (31 downto 0); + signal K6_data : std_logic_vector (31 downto 0); + signal K7_data : std_logic_vector (31 downto 0); + -- hash result lookahead port + signal N0_data : std_logic_vector (31 downto 0); + signal N1_data : std_logic_vector (31 downto 0); + signal N2_data : std_logic_vector (31 downto 0); + signal N3_data : std_logic_vector (31 downto 0); + signal N4_data : std_logic_vector (31 downto 0); + signal N5_data : std_logic_vector (31 downto 0); + signal N6_data : std_logic_vector (31 downto 0); + signal N7_data : std_logic_vector (31 downto 0); + -- hash result data + signal H0_data : std_logic_vector (31 downto 0); + signal H1_data : std_logic_vector (31 downto 0); + signal H2_data : std_logic_vector (31 downto 0); + signal H3_data : std_logic_vector (31 downto 0); + signal H4_data : std_logic_vector (31 downto 0); + signal H5_data : std_logic_vector (31 downto 0); + signal H6_data : std_logic_vector (31 downto 0); + signal H7_data : std_logic_vector (31 downto 0); + -- message schedule word datapath + signal Mi_data : std_logic_vector (31 downto 0); + signal Wt_data : std_logic_vector (31 downto 0); + -- coefficients ROMs + signal Kt_data : std_logic_vector (31 downto 0); + signal Kt_addr : std_logic_vector (5 downto 0); + -- padding control + signal words_sel : std_logic_vector (1 downto 0); + signal bytes_ena : std_logic_vector (3 downto 0); + signal one_insert : std_logic; + signal msg_bitlen : std_logic_vector (63 downto 0); + signal pad_data : std_logic_vector (31 downto 0); + -- block mux selectors + signal sch_ld : std_logic; + signal core_ld : std_logic; + signal oregs_ld : std_logic; + -- block clock enables + signal sch_ce : std_logic; + signal core_ce : std_logic; + signal oregs_ce : std_logic; + -- output data valid / error + signal data_valid : std_logic; + signal error_pad : std_logic; + signal error_ctrl : std_logic; +begin + --============================================================================================= + -- INTERNAL COMPONENT INSTANTIATIONS AND CONNECTIONS + --============================================================================================= + + -- control path core logic + Inst_sha256_control: entity work.sha256_control(rtl) + port map( + -- inputs + clk_i => clk_i, + ce_i => ce_i, + bytes_i => bytes_i, + wr_i => di_wr_i, + start_i => start_i, + end_i => end_i, + error_i => error_pad, + -- output control signals + bitlen_o => msg_bitlen, + words_sel_o => words_sel, + Kt_addr_o => Kt_addr, + sch_ld_o => sch_ld, + core_ld_o => core_ld, + oregs_ld_o => oregs_ld, + sch_ce_o => sch_ce, + core_ce_o => core_ce, + oregs_ce_o => oregs_ce, + one_insert_o => one_insert, + bytes_ena_o => bytes_ena, + di_req_o => di_req_o, + data_valid_o => data_valid, + error_o => error_ctrl + ); + + -- datapath: sha256 byte padding + Inst_sha256_padding: entity work.sha256_padding(rtl) + port map( + words_sel_i => words_sel, + one_insert_i => one_insert, + bytes_ena_i => bytes_ena, + bitlen_i => msg_bitlen, + di_i => di_i, + do_o => Mi_data, + error_o => error_pad + ); + + -- datapath: sha256 message schedule + Inst_sha256_msg_sch: entity work.sha256_msg_sch(rtl) + port map( + clk_i => clk_i, + ce_i => sch_ce, + ld_i => sch_ld, + M_i => Mi_data, + Wt_o => Wt_data + ); + + -- datapath: sha256 core logic + Inst_sha256_hash_core: entity work.sha256_hash_core(rtl) + port map( + clk_i => clk_i, + ce_i => core_ce, + ld_i => core_ld, + -- initial hash data values + A_i => N0_data, + B_i => N1_data, + C_i => N2_data, + D_i => N3_data, + E_i => N4_data, + F_i => N5_data, + G_i => N6_data, + H_i => N7_data, + -- block hash values + A_o => R0_data, + B_o => R1_data, + C_o => R2_data, + D_o => R3_data, + E_o => R4_data, + F_o => R5_data, + G_o => R6_data, + H_o => R7_data, + -- key coefficients + Kt_i => Kt_data, + -- message schedule word input + Wt_i => Wt_data + ); + + -- datapath: sha256 output registers + Inst_sha256_regs: entity work.sha256_regs(rtl) + port map( + clk_i => clk_i, + ce_i => oregs_ce, + ld_i => oregs_ld, + -- register data from the core logic + A_i => R0_data, + B_i => R1_data, + C_i => R2_data, + D_i => R3_data, + E_i => R4_data, + F_i => R5_data, + G_i => R6_data, + H_i => R7_data, + -- initial hash values + K0_i => K0_data, + K1_i => K1_data, + K2_i => K2_data, + K3_i => K3_data, + K4_i => K4_data, + K5_i => K5_data, + K6_i => K6_data, + K7_i => K7_data, + -- lookahead output hash values, one pipeline advanced + N0_o => N0_data, + N1_o => N1_data, + N2_o => N2_data, + N3_o => N3_data, + N4_o => N4_data, + N5_o => N5_data, + N6_o => N6_data, + N7_o => N7_data, + -- output hash values + H0_o => H0_data, + H1_o => H1_data, + H2_o => H2_data, + H3_o => H3_data, + H4_o => H4_data, + H5_o => H5_data, + H6_o => H6_data, + H7_o => H7_data + ); + + -- coefficients ROM: modelled as an asynchronously addressable ROM + Inst_sha256_kt_rom: entity work.sha256_kt_rom(behavioral) + port map( + addr_i => Kt_addr, + dout_o => Kt_data + ); + + -- init output data ROM: modelled as a statically defined constant + Inst_sha256_ki_rom: entity work.sha256_ki_rom(behavioral) + port map( + K0_o => K0_data, + K1_o => K1_data, + K2_o => K2_data, + K3_o => K3_data, + K4_o => K4_data, + K5_o => K5_data, + K6_o => K6_data, + K7_o => K7_data + ); + + --============================================================================================= + -- OUTPUTS LOGIC + --============================================================================================= + + error_o_proc: error_o <= error_ctrl; + do_valid_o_proc: do_valid_o <= data_valid; + H0_o_proc: H0_o <= H0_data; + H1_o_proc: H1_o <= H1_data; + H2_o_proc: H2_o <= H2_data; + H3_o_proc: H3_o <= H3_data; + H4_o_proc: H4_o <= H4_data; + H5_o_proc: H5_o <= H5_data; + H6_o_proc: H6_o <= H6_data; + H7_o_proc: H7_o <= H7_data; + +end rtl; +
diff --git a/verilog/rtl/opencore_hasher/iseconfig/gv_sha256.xreport b/verilog/rtl/opencore_hasher/iseconfig/gv_sha256.xreport new file mode 100755 index 0000000..3ea9877 --- /dev/null +++ b/verilog/rtl/opencore_hasher/iseconfig/gv_sha256.xreport
@@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2016-10-02T16:50:09</DateModified> + <ModuleName>gv_sha256</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport</SavedFilePath> + <ImplementationReportsDirectory>Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256\</ImplementationReportsDirectory> + <DateInitialized>2016-05-24T02:29:42</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="gv_sha256_summary.html" label="Summary" ExpandClockNets="true" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="gv_sha256_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="gv_sha256_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="gv_sha256_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="gv_sha256_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="gv_sha256.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="gv_sha256_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="gv_sha256_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="gv_sha256.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="gv_sha256_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="gv_sha256_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="gv_sha256.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="gv_sha256.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> + <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> + <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> + <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> + <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> + <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> + <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> + <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> + <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> + </view> + <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="gv_sha256.srr" label="Synplify Report" /> + <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="gv_sha256.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="gv_sha256.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="gv_sha256_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + 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target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="gv_sha256.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="gv_sha256.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="gv_sha256.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="gv_sha256.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="gv_sha256.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="gv_sha256.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/gv_sha256_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/gv_sha256_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="gv_sha256_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="gv_sha256_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="gv_sha256_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/gv_sha256_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="gv_sha256_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="gv_sha256_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="gv_sha256.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="gv_sha256_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="gv_sha256.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="gv_sha256.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="gv_sha256.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="gv_sha256.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="gv_sha256_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/gv_sha256_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="gv_sha256_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" 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diff --git a/verilog/rtl/opencore_hasher/iseconfig/sha256.projectmgr b/verilog/rtl/opencore_hasher/iseconfig/sha256.projectmgr new file mode 100755 index 0000000..e87e5e2 --- /dev/null +++ b/verilog/rtl/opencore_hasher/iseconfig/sha256.projectmgr
@@ -0,0 +1,117 @@ +<?xml version='1.0' encoding='utf-8'?> +<!--This is an ISE project configuration file.--> +<!--It holds project specific layout data for the projectmgr plugin.--> +<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> +<Project version="2" owner="projectmgr" name="sha256" > + <!--This is an ISE project configuration file.--> + <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/sha256_hash - rtl Z:|Dropbox|develop|fpga|sha_256|trunk|syn|sha256|gv_sha256.vhd</ClosedNode> + <ClosedNode>/spi_master_atlys_top - rtl Z:|Dropbox|develop|fpga|sha_256|trunk|syn|sha256|sha256_hash.vhd</ClosedNode> + <ClosedNode>/spi_master_atlys_top - rtl Z:|Dropbox|develop|fpga|sha_256|trunk|syn|sha256|spi_master_atlys_top.vhd</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>gv_sha256 - rtl (Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/gv_sha256.vhd)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000381000000020000000000000000000000000200000064ffffffff000000810000000300000002000003810000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>gv_sha256 - rtl (Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/gv_sha256.vhd)</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Design Utilities</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002e4000000010000000100000000000000000000000064ffffffff000000810000000000000001000002e40000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Design Utilities</CurrentItem> + </ItemView> + <ItemView guiview="File" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000039d000000040101000100000000000000000000000064ffffffff000000810000000000000004000001ad00000001000000000000009d0000000100000000000000660000000100000000000000ed0000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView guiview="Library" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000099000000010001000100000000000000000000000064ffffffff000000810000000000000001000000990000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>work</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Configure Target Device</ClosedNode> + <ClosedNode>Implement Design</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>View RTL Schematic</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000064000000010000000100000000000000000000000064ffffffff000000810000000000000001000000640000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>View RTL Schematic</CurrentItem> + </ItemView> + <SourceProcessView>000000ff0000000000000002000000d4000000dc01000000050100000002</SourceProcessView> + <CurrentView>Behavioral Simulation</CurrentView> + <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/gv_sha256 - rtl Z:|Dropbox|develop|fpga|sha_256|trunk|syn|sha256|gv_sha256.vhd</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>testbench - behavior (Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/sha256_test.vhd)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000395000000020000000000000000000000000200000064ffffffff000000810000000300000002000003950000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>testbench - behavior (Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/sha256_test.vhd)</CurrentItem> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem/> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ad000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ad0000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem/> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000003af000000010000000100000000000000000000000064ffffffff000000810000000000000001000003af0000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> +</Project>
diff --git a/verilog/rtl/opencore_hasher/iseconfig/spi_master_atlys.projectmgr b/verilog/rtl/opencore_hasher/iseconfig/spi_master_atlys.projectmgr new file mode 100755 index 0000000..b8bbe0e --- /dev/null +++ b/verilog/rtl/opencore_hasher/iseconfig/spi_master_atlys.projectmgr
@@ -0,0 +1,131 @@ +<?xml version='1.0' encoding='utf-8'?> +<!--This is an ISE project configuration file.--> +<!--It holds project specific layout data for the projectmgr plugin.--> +<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> +<Project version="2" owner="projectmgr" name="spi_master_atlys" > + <!--This is an ISE project configuration file.--> + <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>spi_master_atlys_top - rtl (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_top.vhd)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000031d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000031d0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>spi_master_atlys_top - rtl (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_top.vhd)</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem/> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000018f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000018f0000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem/> + </ItemView> + <ItemView guiview="File" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\gray_counter.vhd</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003c5000000040101000100000000000000000000000064ffffffff0000008100000000000000040000021b00000001000000000000009d0000000100000000000000660000000100000000000000a70000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\gray_counter.vhd</CurrentItem> + </ItemView> + <ItemView guiview="Library" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\spi_master.vhd</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003c5000000010001000100000000000000000000000064ffffffff000000810000000000000001000003c50000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\spi_master.vhd</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>User Constraints</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem/> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000018f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000018f0000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem/> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Back-annotate Pin Locations</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Generate IBIS Model</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>I/O Pin Planning (PlanAhead) - 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diff --git a/verilog/rtl/opencore_hasher/iseconfig/spi_master_atlys_top.xreport b/verilog/rtl/opencore_hasher/iseconfig/spi_master_atlys_top.xreport new file mode 100755 index 0000000..938e2d0 --- /dev/null +++ b/verilog/rtl/opencore_hasher/iseconfig/spi_master_atlys_top.xreport
@@ -0,0 +1,226 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2016-05-24T01:52:42</DateModified> + <ModuleName>sha256_hash</ModuleName> + <SummaryTimeStamp>2014-07-24T11:26:18</SummaryTimeStamp> + <SavedFilePath>Z:/Dropbox/develop/fpga/sha_256/trunk/syn/sha256/iseconfig/spi_master_atlys_top.xreport</SavedFilePath> + <ImplementationReportsDirectory>Z:/Dropbox/develop/fpga/sha_256/trunk/syn/sha256\</ImplementationReportsDirectory> + <DateInitialized>2016-05-24T01:52:41</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="sha256_hash_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> + <table-item 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<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="sha256_hash_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="sha256_hash_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="sha256_hash.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="sha256_hash_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="sha256_hash_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="sha256_hash.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="sha256_hash.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> 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program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="sha256_hash.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="sha256_hash.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="sha256_hash_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> + <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> + <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> + <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> + <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="sha256_hash.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="sha256_hash.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" 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hidden="true" type="Report" file="sha256_hash.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="sha256_hash.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="sha256_hash.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/sha256_hash_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/sha256_hash_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="sha256_hash_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" 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<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/sha256_hash_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sha256_hash_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="sha256_hash_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="sha256_hash.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sha256_hash_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sha256_hash.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sha256_hash.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sha256_hash.clk_rgn" label="Clock Region Report" /> + <view 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file="sha256_hash.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sha256_hash.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sha256_hash.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/sha256_hash_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views>
diff --git a/verilog/rtl/opencore_hasher/makefile b/verilog/rtl/opencore_hasher/makefile new file mode 100755 index 0000000..6302314 --- /dev/null +++ b/verilog/rtl/opencore_hasher/makefile
@@ -0,0 +1,18 @@ +GHDL=ghdl + + +build: + + $(GHDL) -a sha256_hash_core.vhd + $(GHDL) -a sha256_Ki_rom.vhd + $(GHDL) -a sha256_Kt_rom.vhd + $(GHDL) -a sha256_msg_sch.vhd + $(GHDL) -a sha256_padding.vhd + $(GHDL) -a sha256_regs.vhd + $(GHDL) -a gv_sha256.vhd + $(GDHL) -a sha256_test.vh + +sim: + + $(GHDL) -e testbench + $(GHDL) -r testbench --wave=wave.ghw --stop-time=50us --ieee-asserts=disable
diff --git a/verilog/rtl/opencore_hasher/sha256.gise b/verilog/rtl/opencore_hasher/sha256.gise new file mode 100755 index 0000000..de8c954 --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256.gise
@@ -0,0 +1,117 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <!-- --> + + <!-- For tool use only. Do not edit. --> + + <!-- --> + + <!-- ProjectNavigator created generated project file. --> + + <!-- For use in tracking generated file and other information --> + + <!-- allowing preservation of process status. --> + + <!-- --> + + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + + <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version> + + <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sha256.xise"/> + + <files xmlns="http://www.xilinx.com/XMLSchema"> + <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> + <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> + <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> + <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/> + <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="sha256_control_isim_beh.exe"/> + <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sha256_control_stx_beh.prj"/> + <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_beh.prj"/> + <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/> + <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_beh.wdb"/> + <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_beh.prj"/> + <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> + </files> + + <transforms xmlns="http://www.xilinx.com/XMLSchema"> + <transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1475335110"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + </transform> + <transform xil_pn:end_ts="1475418461" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1475418461"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + <status xil_pn:value="OutOfDateForInputs"/> + <status xil_pn:value="OutOfDateForOutputs"/> + <status xil_pn:value="InputChanged"/> + <status xil_pn:value="OutputChanged"/> + <outfile xil_pn:name="gv_sha256.vhd"/> + <outfile xil_pn:name="sha256_Ki_rom.vhd"/> + <outfile xil_pn:name="sha256_Kt_rom.vhd"/> + <outfile xil_pn:name="sha256_control.vhd"/> + <outfile xil_pn:name="sha256_hash_core.vhd"/> + <outfile xil_pn:name="sha256_msg_sch.vhd"/> + <outfile xil_pn:name="sha256_padding.vhd"/> + <outfile xil_pn:name="sha256_regs.vhd"/> + <outfile xil_pn:name="sha256_test.vhd"/> + </transform> + <transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="4434870115928851094" xil_pn:start_ts="1475335110"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + </transform> + <transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1902104842233773292" xil_pn:start_ts="1475335110"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + </transform> + <transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1109748418894572325" xil_pn:start_ts="1475335110"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + </transform> + <transform xil_pn:end_ts="1475418464" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1475418464"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + <status xil_pn:value="OutOfDateForInputs"/> + <status xil_pn:value="OutOfDateForPredecessor"/> + <status xil_pn:value="OutOfDateForOutputs"/> + <status xil_pn:value="InputChanged"/> + <status xil_pn:value="OutputChanged"/> + <outfile xil_pn:name="gv_sha256.vhd"/> + <outfile xil_pn:name="sha256_Ki_rom.vhd"/> + <outfile xil_pn:name="sha256_Kt_rom.vhd"/> + <outfile xil_pn:name="sha256_control.vhd"/> + <outfile xil_pn:name="sha256_hash_core.vhd"/> + <outfile xil_pn:name="sha256_msg_sch.vhd"/> + <outfile xil_pn:name="sha256_padding.vhd"/> + <outfile xil_pn:name="sha256_regs.vhd"/> + <outfile xil_pn:name="sha256_test.vhd"/> + </transform> + <transform xil_pn:end_ts="1475418472" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="1459423336703152140" xil_pn:start_ts="1475418464"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + <status xil_pn:value="OutOfDateForInputs"/> + <status xil_pn:value="OutOfDateForPredecessor"/> + <status xil_pn:value="OutOfDateForOutputs"/> + <status xil_pn:value="InputChanged"/> + <status xil_pn:value="OutputChanged"/> + <outfile xil_pn:name="fuse.log"/> + <outfile xil_pn:name="isim"/> + <outfile xil_pn:name="isim.log"/> + <outfile xil_pn:name="testbench_beh.prj"/> + <outfile xil_pn:name="testbench_isim_beh.exe"/> + <outfile xil_pn:name="xilinxsim.ini"/> + </transform> + <transform xil_pn:end_ts="1475418473" xil_pn:in_ck="-5570483995328803433" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5414671575160791934" xil_pn:start_ts="1475418472"> + <status xil_pn:value="SuccessfullyRun"/> + <status xil_pn:value="ReadyToRun"/> + <status xil_pn:value="OutOfDateForPredecessor"/> + <status xil_pn:value="OutOfDateForOutputs"/> + <status xil_pn:value="OutputChanged"/> + <outfile xil_pn:name="isim.cmd"/> + <outfile xil_pn:name="isim.log"/> + <outfile xil_pn:name="testbench_isim_beh.wdb"/> + </transform> + </transforms> + +</generated_project>
diff --git a/verilog/rtl/opencore_hasher/sha256.wcfg b/verilog/rtl/opencore_hasher/sha256.wcfg new file mode 100755 index 0000000..454b6ad --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256.wcfg
@@ -0,0 +1,179 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/testbench_isim_beh.wdb" id="1" type="auto"> + <top_modules> + <top_module name="numeric_std" /> + <top_module name="std_logic_1164" /> + <top_module name="testbench" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="41" /> + <wvobject fp_name="/testbench/test_case" type="other" db_ref_id="1"> + <obj_property name="ElementShortName">test_case</obj_property> + <obj_property name="ObjectShortName">test_case</obj_property> + </wvobject> + <wvobject fp_name="/testbench/pclk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">pclk</obj_property> + <obj_property name="ObjectShortName">pclk</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/hash_control_st_reg" type="other" db_ref_id="1"> + <obj_property name="ElementShortName">hash_control_st_reg</obj_property> + <obj_property name="ObjectShortName">hash_control_st_reg</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/hash_control_st_next" type="other" db_ref_id="1"> + <obj_property name="ElementShortName">hash_control_st_next</obj_property> + <obj_property name="ObjectShortName">hash_control_st_next</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_ce" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">dut_ce</obj_property> + <obj_property name="ObjectShortName">dut_ce</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_start" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">dut_start</obj_property> + <obj_property name="ObjectShortName">dut_start</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_end" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">dut_end</obj_property> + <obj_property name="ObjectShortName">dut_end</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/di_wr_window" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">di_wr_window</obj_property> + <obj_property name="ObjectShortName">di_wr_window</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_di_req" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">dut_di_req</obj_property> + <obj_property name="ObjectShortName">dut_di_req</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_di_wr" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">dut_di_wr</obj_property> + <obj_property name="ObjectShortName">dut_di_wr</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_error" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">dut_error</obj_property> + <obj_property name="ObjectShortName">dut_error</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_do_valid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">dut_do_valid</obj_property> + <obj_property name="ObjectShortName">dut_do_valid</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/error_i" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">error_i</obj_property> + <obj_property name="ObjectShortName">error_i</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/core_error" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">core_error</obj_property> + <obj_property name="ObjectShortName">core_error</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_di" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_di[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_di[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_bytes" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_bytes[1:0]</obj_property> + <obj_property name="ObjectShortName">dut_bytes[1:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/st_cnt_reg" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">st_cnt_reg[6:0]</obj_property> + <obj_property name="ObjectShortName">st_cnt_reg[6:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/bitlen_o" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">bitlen_o[63:0]</obj_property> + <obj_property name="ObjectShortName">bitlen_o[63:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/sha_reset" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">sha_reset</obj_property> + <obj_property name="ObjectShortName">sha_reset</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/sha_init" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">sha_init</obj_property> + <obj_property name="ObjectShortName">sha_init</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/sch_ld_o" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">sch_ld_o</obj_property> + <obj_property name="ObjectShortName">sch_ld_o</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/core_ld_o" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">core_ld_o</obj_property> + <obj_property name="ObjectShortName">core_ld_o</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/oregs_ld_o" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">oregs_ld_o</obj_property> + <obj_property name="ObjectShortName">oregs_ld_o</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/core_ce_o" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">core_ce_o</obj_property> + <obj_property name="ObjectShortName">core_ce_o</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/sch_ce_o" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">sch_ce_o</obj_property> + <obj_property name="ObjectShortName">sch_ce_o</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/oregs_ce_o" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">oregs_ce_o</obj_property> + <obj_property name="ObjectShortName">oregs_ce_o</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/one_insert_o" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">one_insert_o</obj_property> + <obj_property name="ObjectShortName">one_insert_o</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/sha_last_blk_reg" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">sha_last_blk_reg</obj_property> + <obj_property name="ObjectShortName">sha_last_blk_reg</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/sha_last_blk_next" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">sha_last_blk_next</obj_property> + <obj_property name="ObjectShortName">sha_last_blk_next</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_hash_core/kt_i" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">kt_i[31:0]</obj_property> + <obj_property name="ObjectShortName">kt_i[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_msg_sch/wt_o" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">wt_o[31:0]</obj_property> + <obj_property name="ObjectShortName">wt_o[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_hash_core/wt_i" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">wt_i[31:0]</obj_property> + <obj_property name="ObjectShortName">wt_i[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_hash_core/a_o" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">a_o[31:0]</obj_property> + <obj_property name="ObjectShortName">a_o[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h0" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h0[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h0[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h1[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h1[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h2" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h2[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h2[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h3" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h3[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h3[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h4" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h4[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h4[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h5" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h5[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h5[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h6" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h6[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h6[31:0]</obj_property> + </wvobject> + <wvobject fp_name="/testbench/dut_h7" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">dut_h7[31:0]</obj_property> + <obj_property name="ObjectShortName">dut_h7[31:0]</obj_property> + </wvobject> +</wave_config>
diff --git a/verilog/rtl/opencore_hasher/sha256.xise b/verilog/rtl/opencore_hasher/sha256.xise new file mode 100755 index 0000000..6ad5807 --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256.xise
@@ -0,0 +1,397 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="sha256_msg_sch.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + </file> + <file xil_pn:name="sha256_hash_core.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="6"/> + </file> + <file xil_pn:name="sha256_Ki_rom.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + </file> + <file xil_pn:name="sha256_Kt_rom.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + </file> + <file xil_pn:name="gv_sha256.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> + <association xil_pn:name="Implementation" xil_pn:seqID="8"/> + </file> + <file xil_pn:name="sha256_padding.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="sha256_control.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="Implementation" xil_pn:seqID="7"/> + </file> + <file xil_pn:name="sha256_regs.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="sha256_test.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="11"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="11"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="11"/> + </file> + </files> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + + <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> + <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" 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xil_pn:valueState="default"/> + <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> + <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Place And Route Mode" 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Translate Simulation Model Name" xil_pn:value="sha256_hash_translate.vhd" xil_pn:valueState="non-default"/> + <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> + <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="RAM Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="ROM Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> + <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Register Duplication Xst" xil_pn:value="false" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Register Ordering spartan6" xil_pn:value="Off" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="sha256_hash" xil_pn:valueState="non-default"/> + <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="10" xil_pn:valueState="non-default"/> + <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="10" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="10" xil_pn:valueState="non-default"/> + <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Retain Hierarchy" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Retry Configuration if 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xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="30000 ns" xil_pn:valueState="non-default"/> + <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Par" xil_pn:value="12000 ns" xil_pn:valueState="non-default"/> + <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="12 us" xil_pn:valueState="non-default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.testbench" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> + <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default" xil_pn:x_locked="true"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/mapruntimect3.xds" xil_pn:valueState="non-default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="true" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="spi_master_atlys" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-07T09:55:20" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C5BE631B69F48AB8C2F24035AF7A13B" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + +</project>
diff --git a/verilog/rtl/opencore_hasher/sha256_Ki_rom.vhd b/verilog/rtl/opencore_hasher/sha256_Ki_rom.vhd new file mode 100755 index 0000000..c984c12 --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_Ki_rom.vhd
@@ -0,0 +1,84 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/06/2016 +-- Module Name: sha256_Ki_rom +-- Project Name: sha256 processor +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- Initial values for the hash result registers. +-- This module is modelled as a fixed value function. +-- It can be implemented as a local constant fixed value. +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors passed. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sha256_ki_rom is + port ( + K0_o : out std_logic_vector (31 downto 0) := (others => 'U'); + K1_o : out std_logic_vector (31 downto 0) := (others => 'U'); + K2_o : out std_logic_vector (31 downto 0) := (others => 'U'); + K3_o : out std_logic_vector (31 downto 0) := (others => 'U'); + K4_o : out std_logic_vector (31 downto 0) := (others => 'U'); + K5_o : out std_logic_vector (31 downto 0) := (others => 'U'); + K6_o : out std_logic_vector (31 downto 0) := (others => 'U'); + K7_o : out std_logic_vector (31 downto 0) := (others => 'U') + ); +end sha256_ki_rom; + +architecture behavioral of sha256_ki_rom is +begin + --============================================================================================= + -- CONSTANTS FOR Ki VALUES + --============================================================================================= + K0_o_proc: K0_o <= x"6A09E667"; + K1_o_proc: K1_o <= x"BB67AE85"; + K2_o_proc: K2_o <= x"3C6EF372"; + K3_o_proc: K3_o <= x"A54FF53A"; + K4_o_proc: K4_o <= x"510E527F"; + K5_o_proc: K5_o <= x"9B05688C"; + K6_o_proc: K6_o <= x"1F83D9AB"; + K7_o_proc: K7_o <= x"5BE0CD19"; + +end behavioral; +
diff --git a/verilog/rtl/opencore_hasher/sha256_Kt_rom.vhd b/verilog/rtl/opencore_hasher/sha256_Kt_rom.vhd new file mode 100755 index 0000000..985650e --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_Kt_rom.vhd
@@ -0,0 +1,152 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/06/2016 +-- Module Name: sha256_kt_rom - RTL +-- Project Name: sha256 processor +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- This is the 64 words coefficients rom for the block hash core. +-- It is modelled as an asynchronous addressable ROM memory. +-- Depending on the fabrication process and technology, this memory can be implemented +-- as a OTP, a MUX, a fixed LUT or a combinational function. +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors passed. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +-- +----------------------------------------------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sha256_kt_rom is + port ( + addr_i : in std_logic_vector(5 downto 0) := (others => '0'); -- address of the Kt constant + dout_o : out std_logic_vector(31 downto 0) -- output delayed one clock + ); +end sha256_kt_rom; + +architecture behavioral of sha256_kt_rom is + signal addr : integer range 0 to 63; + signal next_rout : std_logic_vector (31 downto 0); +begin + --============================================================================================= + -- COEFFICIENTS ROM + --============================================================================================= + -- The coefficients for the block hash are synthesized as an unregistered 64x32bit ROM. + + addr <= to_integer(unsigned(addr_i)); + + -- The ROM is a 5-bit select MUX + next_rout <= x"428a2f98" when addr = 0 else + x"71374491" when addr = 1 else + x"b5c0fbcf" when addr = 2 else + x"e9b5dba5" when addr = 3 else + x"3956c25b" when addr = 4 else + x"59f111f1" when addr = 5 else + x"923f82a4" when addr = 6 else + x"ab1c5ed5" when addr = 7 else + x"d807aa98" when addr = 8 else + x"12835b01" when addr = 9 else + x"243185be" when addr = 10 else + x"550c7dc3" when addr = 11 else + x"72be5d74" when addr = 12 else + x"80deb1fe" when addr = 13 else + x"9bdc06a7" when addr = 14 else + x"c19bf174" when addr = 15 else + x"e49b69c1" when addr = 16 else + x"efbe4786" when addr = 17 else + x"0fc19dc6" when addr = 18 else + x"240ca1cc" when addr = 19 else + x"2de92c6f" when addr = 20 else + x"4a7484aa" when addr = 21 else + x"5cb0a9dc" when addr = 22 else + x"76f988da" when addr = 23 else + x"983e5152" when addr = 24 else + x"a831c66d" when addr = 25 else + x"b00327c8" when addr = 26 else + x"bf597fc7" when addr = 27 else + x"c6e00bf3" when addr = 28 else + x"d5a79147" when addr = 29 else + x"06ca6351" when addr = 30 else + x"14292967" when addr = 31 else + x"27b70a85" when addr = 32 else + x"2e1b2138" when addr = 33 else + x"4d2c6dfc" when addr = 34 else + x"53380d13" when addr = 35 else + x"650a7354" when addr = 36 else + x"766a0abb" when addr = 37 else + x"81c2c92e" when addr = 38 else + x"92722c85" when addr = 39 else + x"a2bfe8a1" when addr = 40 else + x"a81a664b" when addr = 41 else + x"c24b8b70" when addr = 42 else + x"c76c51a3" when addr = 43 else + x"d192e819" when addr = 44 else + x"d6990624" when addr = 45 else + x"f40e3585" when addr = 46 else + x"106aa070" when addr = 47 else + x"19a4c116" when addr = 48 else + x"1e376c08" when addr = 49 else + x"2748774c" when addr = 50 else + x"34b0bcb5" when addr = 51 else + x"391c0cb3" when addr = 52 else + x"4ed8aa4a" when addr = 53 else + x"5b9cca4f" when addr = 54 else + x"682e6ff3" when addr = 55 else + x"748f82ee" when addr = 56 else + x"78a5636f" when addr = 57 else + x"84c87814" when addr = 58 else + x"8cc70208" when addr = 59 else + x"90befffa" when addr = 60 else + x"a4506ceb" when addr = 61 else + x"bef9a3f7" when addr = 62 else + x"c67178f2"; + + --============================================================================================= + -- OUTPUT LOGIC + --============================================================================================= + -- connect output port + + dout_o_proc: dout_o <= next_rout; + +end behavioral; + +
diff --git a/verilog/rtl/opencore_hasher/sha256_control.vhd b/verilog/rtl/opencore_hasher/sha256_control.vhd new file mode 100755 index 0000000..ffdc428 --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_control.vhd
@@ -0,0 +1,651 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/06/2016 +-- Module Name: sha256_control - RTL +-- Project Name: sha256 hash engine +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- This is the control path logic for the GV_SHA256 fast engine. +-- +-- It is a fully synchronous design, with all signals synchronous to the rising edge of the system clock. +-- The sequencer state machine controls the hash datapath modules, generating addresses for the coefficients ROM, load/enable signals for the +-- message schedule, hash core and output registers circuit blocks, and control signals for the input padding logic. +-- +-- The SHA256 hash core follows the FIPS-180-4 logic description for the SHA-256 algorithm, optimized as a single-cycle per iteration engine. +-- +-- This implementation follows the implementation guidelines of the NIST Cryptographic Toolkit, and the NIST Approved Algorithms notes. +-- +-- RELEVANT NIST PUBLICATIONS +-- Link to Document | Description +-- ------------------------------------------------------------------------------ | --------------------------------------------------------- +-- http://csrc.nist.gov/publications/fips/fips140-2/fips1402.pdf | SECURITY REQUIREMENTS FOR CRYPTOGRAPHIC MODULES +-- http://csrc.nist.gov/groups/ST/toolkit/index.html | NIST CRYPTOGRAPHIC TOOLKIT +-- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf | Secure Hash Standard (SHS) SHA-256 +-- http://csrc.nist.gov/publications/fips/fips198-1/FIPS-198-1_final.pdf | The Keyed-Hash Message Authentication Code (HMAC) +-- http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA256.pdf | SHA-256 verification test vectors +-- http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA2_Additional.pdf | Additional SHA-256 corner case verification test vectors +-- +-- RELEVANT RFCs +-- Link to PDF document | Description +-- ------------------------------------------ | --------------------------------------------------------- +-- https://tools.ietf.org/pdf/rfc2104.pdf | RFC2104 - HMAC: Keyed-Hashing for Message Authentication +-- https://tools.ietf.org/pdf/rfc4231.pdf | RFC4231 - Identifiers and Test Vectors for HMAC-SHA-256 +-- https://tools.ietf.org/pdf/rfc4868.pdf | RFC4868 - Using HMAC-SHA-256, HMAC-SHA-384, and HMAC-SHA-512 with IPsec +--------------------------------------------------------------------------------------------------------------------------------------------------------------- +-- SHA256 ENGINE +-- ============= +-- +-- The setup of all circuit blocks is performed in a single extra clock cycle, besides the 64 steps needed to compute a hash block operation, +-- resulting in a 65-cycle per block hash computation processor. Heavy pipelining is implemented to suppress control path operations logic steps. +-- The engine is internally implemented as a 256-bit machine, with all combinational operations performed as a single-cycle operation on each +-- 64 steps of the hash algorithm. Wide transfers of 256-bit data are also performed as single-cycle operations. +-- +-- The data input accepts 16 consecutive 32bit words for a total of 64 bytes per block, one word per clock cycle. The input signal 'wr_i' can be +-- used as a flow control input to hold the processor to wait for slower data. +-- +-- A hash computation starts with a 'start_i' pulse that resets the processor. A pulse of the 'end_i' signal marks the last input data word. The +-- core will pad the last block according to the SHA256 rules, and present the results of the hash computation at the output registers, raising the +-- 'data_valid' signal to mark the end of the computation. The hash results are available at the 256-bit output port. +-- +-- The following waveforms describe the detailed operation for message start, update and end, with internal signals and FSM states. +-- +-- BEGIN BLOCK (1st block) - showing lookahead Wt and Kt +-- ====================== +-- +-- The hash operation starts with a 'start' sync pulse, which causes the RESET of the processor. The processor comes out of RESET only after 'start' is +-- released. +-- The DATA_INPUT state is signalled by the data request signal 'di_req' going HIGH. The processor will latch 16 words from the 'di' port, at every +-- rising edge of the system clock. At the end of the block input, the 'di_req' signal goes LOW. +-- The input data can be held by bringing the 'ack' input LOW. When the 'ack' input is held LOW, it includes a wait state in the whole processor, to +-- cope with slow inputs or to allow periodic fetches of input data from multiple data sources. +-- +-- STATE |reset| data |wait | | process +-- __ |__ |__ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ |__ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock +-- _____ +-- start_i ______/ \_\_______________________________________________________________________________________________________________________... -- 'start_i' resets the processor and starts a new hash +-- +-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input +-- __ _ _ _ _____________________________________________________________________________________________________ +-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input +-- ___________________________________________ _________________________________________________________ +-- wr_i __________/____/ \_____/ \_____________... -- 'wr_i' can hold the core for slow data +-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________... +-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge +-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... +-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value +-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... +-- Wt_i@core __________\___\__W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_________________... -- msg scheduler lookahead output for Wt_i at core +-- ______________ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... +-- Kt_i@core ______________/__K0_/__K1_/__K2_/__K3_/__K4_/__K5_/__K6_______/__K7_/__K8_/__K9_/_K10_/_K11_/_K12_/_K13_/_K14_/_K15_________________... -- Kt rom synchronous with scheduler for Kt_i at core +-- __ _ _ _ +-- error_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' clears any error condition +-- __ _ _ _ +-- do_valid_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' invalidates any previous results +-- +-- +-- UPDATE BLOCK (preload) +-- ===================== +-- +-- At the start of each block, the 'di_req' signal is raised to request new data. +-- +-- STATE ... process |next | data |wait | | process +-- __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock +-- +-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input +-- _____________________________________________________________________________________________________ +-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input +-- ___________________________________________________ _________________________________________________________ +-- wr_i ________/__________/ \_____/ \_... -- 'wr_i' can hold the core for slow data +-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____... +-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge +-- +-- +-- UPDATE BLOCK (delayed start) +-- =========================== +-- +-- The data for the new block can be delayed, by keeping the 'ack' signal low until the data is present at the data input port. +-- +-- STATE ..|next | data |wait | | process +-- __ __ __ __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock +-- +-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input +-- _______ _ _ ___________________________________________________________________________________________________________ +-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input +-- __________________________________________________ _____________________________________________ +-- wr_i ________________ _ _ ______/ \_____/ \_... -- 'wr_i' valid on rising edge of 'clk_i' +-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____... +-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\\\\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge +-- +-- +-- END BLOCK (success) +-- ================== +-- +-- At the end of the last block the signal 'end' must be raised for at least one clock cycle. +-- The 'bytes' input marks the number of valid bytes in the last word. +-- A PADDING state completes the last data block and a BLK_PROCESS finishes the hash computation. +-- The 'do_valid' remains HIGH until the next RESET. +-- +-- STATE ..|next | data | padding | process |next | valid |reset| data +-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock +-- ______ +-- start_i ____________________________________________________________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash +-- ______ +-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input +-- ___________________________________ __________ +-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input +-- ______________________________________ _________ +-- wr_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'wr_i' can hold the core for slow data +-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____... +-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored +-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____ +-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value +-- _____ _____ _____ _____ _____ _____ _____ ____ +-- bytes_i --------<__0__\__0__\__0__\__0__\__0__\__3__>-----------------------------------------------------------------------<__0__\__0_... -- bytes_i mark number of valid bytes in each word +-- +-- error_o _______________________________________________________ _ _ ___________________ _ _ ___________________________________________... -- 'error_o' goes high on an invalid computation +-- ___________ +-- do_valid_o _______________________________________________________ _ _ ___________________ _ _ ______________/ \________________... -- 'do_valid_o' goes high at the end of a computation +-- ___________ +-- H0_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H0______\________________... -- H0 holds the bytes 0..3 of the output +-- ___________ +-- H1_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H1______\________________... -- H1 holds the bytes 4..7 of the output +-- ___________ +-- H2_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H2______\________________... -- H2 holds the bytes 8..11 of the output +-- ___________ +-- H3_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H3______\________________... -- H3 holds the bytes 12..15 of the output +-- ___________ +-- H4_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H4______\________________... -- H4 holds the bytes 16..19 of the output +-- ___________ +-- H5_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H5______\________________... -- H5 holds the bytes 20..23 of the output +-- ___________ +-- H6_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H6______\________________... -- H6 holds the bytes 24..27 of the output +-- ___________ +-- H7_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H7______\________________... -- H7 holds the bytes 28..31 of the output +-- +-- +-- END BLOCK (full last block) +-- ================== +-- +-- If the last block has exactly 16 full words, the controller starts the block processing in the PADDING cycle, processes the input block, +-- and inserts a last PADDING block followed by a last BLK_PROCESS block. +-- +-- STATE ... data |pad | process |next | pad | process |next | valid |reset| data +-- __ __ __ |__ |__ |__ |__ __ __ |__ |__ |__ __ |__ |__ __ +-- clk_i \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock +-- ______ +-- start_i ____________________________ _ _ ____________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash +-- _____ +-- end_i ____________/ \_________ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input +-- _________________ __________ +-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i' +-- ____________________ _________ +-- wr_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'wr_i' valid on rising edge of 'clk_i' +-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____... +-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored +-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____ +-- st_cnt_reg _13__/_14__/_15__/_16__/_17_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value +-- _____ _____ _____ _____ ____ +-- bytes_i __0__/__0__/__0__>-----------------------------------------------------------------------------------<__0__/__0_... -- bytes_i mark number of valid bytes in each word +-- ___________ +-- do_valid_o ____________________________ _ _ ___________________ _ _ __________________________/ \________________... -- 'do_valid_o' goes high at the end of a computation +-- +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed. +-- 2016/06/07 v0.01.0101 [JD] failed 2-block test for "abcdbcdecd..." vector. Fixed padding control logic. +-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed. +-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed. +-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block. +-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input. +-- 2016/07/06 v0.01.0210 [JD] optimized suspend logic on 'sch_ld' to supress possible glitch in 'pad_one_next'. +-- 2016/09/25 v0.01.0220 [JD] changed 'ack_i' name to 'wr_i', and changed semantics to 'data write'. +-- 2016/10/01 v0.01.0250 [JD] optimized the last null-padding state, making the algorithm isochronous for full last data blocks. +-- 2016/10/01 v0.01.0260 [JD] eliminated bytes error register, streamlined error logic. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sha256_control is + port ( + -- inputs + clk_i : in std_logic := 'U'; -- system clock + ce_i : in std_logic := 'U'; -- core clock enable + start_i : in std_logic := 'U'; -- reset the processor and start a new hash + end_i : in std_logic := 'U'; -- marks end of last block data input + wr_i : in std_logic := 'U'; -- input word write/hold control + bytes_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- valid bytes in input word + error_i : in std_logic := 'U'; -- datapath error input from other modules + -- output control signals + bitlen_o : out std_logic_vector (63 downto 0); -- message bit length + words_sel_o : out std_logic_vector (1 downto 0); -- bitlen insertion control + Kt_addr_o : out std_logic_vector (5 downto 0); -- address for the Kt coefficients ROM + sch_ld_o : out std_logic; -- load/recirculate words for message scheduler + core_ld_o : out std_logic; -- load all registers for hash core + oregs_ld_o : out std_logic; -- load output registers + sch_ce_o : out std_logic; -- clock enable for message scheduler logic block + core_ce_o : out std_logic; -- clock enable for hash core logic block + oregs_ce_o : out std_logic; -- clock enable for output regs logic block + bytes_ena_o : out std_logic_vector (3 downto 0); -- byte lane selectors for padding logic block + one_insert_o : out std_logic; -- insert leading '1' in the padding + di_req_o : out std_logic; -- external data request by the 'di_i' port + data_valid_o : out std_logic; -- operation finished. output data is valid + error_o : out std_logic -- operation aborted. output data is not valid + ); +end sha256_control; + +architecture rtl of sha256_control is + --============================================================================================= + -- Type definitions + --============================================================================================= + -- controller states + type hash_toplevel_control is + ( st_reset, -- core reset, initial state + st_sha_data_input, -- sha data input + st_sha_blk_process, -- sha block process + st_sha_blk_nxt, -- sha block next + st_sha_padding, -- sha padding + st_sha_data_valid, -- sha data valid + st_error -- fsm locks on error, exit only by reset + ); + + --============================================================================================= + -- Signals for state machine control + --============================================================================================= + signal hash_control_st_reg : hash_toplevel_control := st_reset; + signal hash_control_st_next : hash_toplevel_control := st_reset; + + --============================================================================================= + -- Signals for internal operation + --============================================================================================= + -- combinational flags: message data input / padding control / block internal process selection + signal reset : std_logic; + signal sha_reset : std_logic; + signal sha_init : std_logic; + signal wait_run_ce : std_logic; + -- registered flags: last block, padding control + signal sha_last_blk_reg : std_logic; + signal sha_last_blk_next : std_logic; + signal padding_reg : std_logic; + signal padding_next : std_logic; + signal pad_one_reg : std_logic; + signal pad_one_next : std_logic; + -- 64 bit message bit counter + signal msg_bit_cnt_reg : unsigned (63 downto 0); + signal msg_bit_cnt_next : unsigned (63 downto 0); + signal bits_to_add : unsigned (5 downto 0); + signal msg_bit_cnt_ce : std_logic; + -- sequencer state counter + signal st_cnt_reg : unsigned (6 downto 0); + signal st_cnt_next : unsigned (6 downto 0); + signal st_cnt_ce : std_logic; + signal st_cnt_clr : std_logic; + + --============================================================================================= + -- Output Control Signals + --============================================================================================= + -- unregistered control signals + signal words_sel : std_logic_vector (1 downto 0); -- bitlen insertion control + signal sch_ld : std_logic; -- input data load into message scheduler control + signal core_ld : std_logic; -- hash core load data registers control + signal oregs_ld : std_logic; -- load initial value into output regs control + signal sch_ce : std_logic; -- clock enable for message scheduler logic block + signal core_ce : std_logic; -- clock enable for hash core logic block + signal oregs_ce : std_logic; -- clock enable for output regs logic block + signal bytes_ena : std_logic_vector (3 downto 0); -- byte lane selectors for padding logic block + signal one_insert : std_logic; -- insert leading one in the padding + signal di_req : std_logic; -- data request + signal di_wr_window : std_logic; -- valid data write window + signal data_valid : std_logic; -- operation finished. output data is valid + signal data_input_error : std_logic; -- data write outside write valid window + signal bytes_error : std_logic; -- bytes selection error + signal error_lock : std_logic; -- error state lock + signal core_error : std_logic; -- operation aborted. output data is not valid + +begin + --============================================================================================= + -- REGISTER TRANSFER PROCESSES + --============================================================================================= + -- control fsm register transfer logic + control_fsm_proc: process (clk_i) is + begin + -- FSM state register: sync RESET on 'reset', and sync PRESET on error_i + if clk_i'event and clk_i = '1' then + if reset = '1' then + -- all registered values are reset on master clear + hash_control_st_reg <= st_reset; + elsif core_error = '1' then + -- error latch: lock on the error state + hash_control_st_reg <= st_error; + elsif ce_i = '1' then + -- all registered values are held on master clock enable + hash_control_st_reg <= hash_control_st_next; + end if; + end if; + -- SHA256 registers, RESET on 'sha_init' + if clk_i'event and clk_i = '1' then + if sha_init = '1' then + -- all SHA256 registered values are reset on SHA master clear + sha_last_blk_reg <= '0'; + padding_reg <= '0'; + elsif ce_i = '1' then + -- all registered values are held on master clock enable + sha_last_blk_reg <= sha_last_blk_next; + padding_reg <= padding_next; + end if; + end if; + end process control_fsm_proc; + + -- bit counter register transfer logic + bit_counter_proc: process (clk_i) is + begin + -- bit counter + if clk_i'event and clk_i = '1' then + if sha_init = '1' then + msg_bit_cnt_reg <= (others => '0'); + elsif ce_i = '1' and msg_bit_cnt_ce = '1' then + msg_bit_cnt_reg <= msg_bit_cnt_next; + end if; + end if; + end process bit_counter_proc; + + -- state counter register transfer process + state_counter_proc: process (clk_i) is + begin + -- core state counter + if clk_i'event and clk_i = '1' then + if (sha_init = '1') or (st_cnt_clr = '1') then + st_cnt_reg <= (others => '0'); + elsif (ce_i = '1') and (st_cnt_ce = '1') then + st_cnt_reg <= st_cnt_next; + end if; + end if; + end process state_counter_proc; + + -- one-padding register transfer logic + pad_one_fsm_proc: process (clk_i) is + begin + if clk_i'event and clk_i = '1' then + if sha_init = '1' then + -- all registered values are reset on master clear + pad_one_reg <= '1'; + elsif (ce_i = '1') and (sch_ce = '1') then + -- one-padding register is clocked synchronous with the message schedule + pad_one_reg <= pad_one_next; + end if; + end if; + end process pad_one_fsm_proc; + + --============================================================================================= + -- COMBINATIONAL NEXT-STATE LOGIC + --============================================================================================= + -- State and control path combinational logic + -- The hash_control_st_reg state register controls the SHA256 algorithm. + control_combi_proc : process ( hash_control_st_reg, sha_last_blk_reg, padding_reg, wait_run_ce, + end_i, st_cnt_reg, sha_last_blk_next, one_insert, sha_reset ) is + begin + -- default logic that applies to all states at each fsm clock -- + + -- assign default values to all unchanging combinational outputs (avoid latches) + hash_control_st_next <= hash_control_st_reg; + sha_last_blk_next <= sha_last_blk_reg; + padding_next <= padding_reg; + -- handshaking + sha_init <= '0'; + error_lock <= '0'; + di_wr_window <= '0'; + words_sel <= b"00"; + data_valid <= '0'; + di_req <= '0'; -- data request only during data input + -- state counter + st_cnt_clr <= '0'; -- only clear the state counter at the beginning of each block + st_cnt_ce <= '0'; + -- message scheduler + sch_ld <= '1'; -- enable pass-thru input through message schedule + sch_ce <= '0'; -- stop message schedule clock + -- hash core + core_ld <= '0'; -- enable internal hash core logic + core_ce <= '0'; -- core computation enabled only for data input and processing + -- output registers + oregs_ld <= '0'; -- defaults for accumulate blk hash + oregs_ce <= '0'; -- only register init values and end of computation + case hash_control_st_reg is + + when st_reset => -- master reset: starts a new hash/hmac processing + -- moore outputs + sha_init <= '1'; -- reset SHA256 engine + oregs_ld <= '1'; -- load initial hash values + oregs_ce <= '1'; -- latch initial hash values into output registers + core_ld <= '1'; -- load initial value into core registers + core_ce <= '1'; -- latch initial value into core registers + st_cnt_clr <= '1'; -- reset state counter + di_wr_window <= '1'; -- enable data write window + -- next state + hash_control_st_next <= st_sha_data_input; + + when st_sha_data_input => -- message data words are clocked into the processor + -- moore outputs + di_req <= '1'; -- request message data + di_wr_window <= '1'; -- enable data write window + sch_ce <= wait_run_ce; -- hold the message scheduler with data hold + st_cnt_ce <= wait_run_ce; -- hold state count with data hold + core_ce <= wait_run_ce; -- hold processing clock with data hold + -- next state + if wait_run_ce = '1' then + if end_i = '1' then + hash_control_st_next <= st_sha_padding; -- pad incomplete blocks + elsif st_cnt_reg = 15 then + hash_control_st_next <= st_sha_blk_process; -- process one more block + end if; + end if; + + when st_sha_blk_process => -- internal block hash processing + -- moore outputs + st_cnt_ce <= '1'; -- enable state counter + sch_ld <= '0'; -- recirculate scheduler data + sch_ce <= '1'; -- enable message scheduler clock + core_ce <= '1'; -- enable processing clock + -- next state + if st_cnt_reg = 63 then + hash_control_st_next <= st_sha_blk_nxt; + end if; + + when st_sha_blk_nxt => -- prepare for next block + -- moore outputs + st_cnt_clr <= '1'; -- reset state counter at the beginning of each block + sch_ce <= '0'; -- stop the message schedule + core_ld <= '1'; -- load result value into core registers + core_ce <= '1'; -- latch result value into core registers + oregs_ce <= '1'; -- latch core result into regs accumulator + -- next state + if sha_last_blk_reg = '1' then + hash_control_st_next <= st_sha_data_valid; -- no hmac operation: publish data valid + elsif padding_reg = '1' then + hash_control_st_next <= st_sha_padding; -- additional padding block + else + hash_control_st_next <= st_sha_data_input; -- continue requesting input data + end if; + + when st_sha_padding => -- padding of bits on the last message block + -- moore outputs + padding_next <= '1'; + if st_cnt_reg = 16 then -- if word 16, data block was full: proceed to process this block + -- process state #16 in this cycle and proceed to process the rest of the block + st_cnt_ce <= '1'; -- enable state counter + sch_ld <= '0'; -- recirculate scheduler data + sch_ce <= '1'; -- enable message scheduler clock + core_ce <= '1'; -- enable processing clock + -- next state + hash_control_st_next <= st_sha_blk_process; + else -- incomplete block: pad words until data block completes + sch_ld <= '1'; -- load padded data into scheduler + sch_ce <= '1'; -- enable message scheduler clock + core_ce <= '1'; -- enable processing clock + st_cnt_ce <= '1'; -- enable state counter + if st_cnt_reg = 15 then -- pad up to word 15 + if sha_last_blk_next = '1' then + words_sel <= b"10"; -- insert bitlen lo + end if; + -- next state + hash_control_st_next <= st_sha_blk_process; + elsif (one_insert = '0') and (st_cnt_reg = 14) then + words_sel <= b"01"; -- insert bitlen hi + sha_last_blk_next <= '1'; -- mark this as the last block + elsif st_cnt_reg = 13 then + sha_last_blk_next <= '1'; -- mark this as the last block + end if; + end if; + + when st_sha_data_valid => -- process is finished, waiting for begin command + -- moore outputs + data_valid <= '1'; -- output results are valid + -- wait for core reset with 'start' + + when st_error => -- processing or input error: reset with 'reset' = 1 + -- moore outputs + error_lock <= '1'; -- lock error state + st_cnt_clr <= '1'; -- clear state counter + -- wait for core reset with 'start' + + when others => -- internal state machine error + -- next state + hash_control_st_next <= st_error; + + end case; + end process control_combi_proc; + + --============================================================================================= + -- COMBINATIONAL CONTROL LOGIC + --============================================================================================= + + -- controller RESET signal logic + sha_reset_combi_proc: sha_reset <= '1' when start_i = '1' else '0'; + reset_combi_proc: reset <= '1' when sha_reset = '1' else '0'; + + -- pad-one flag register + pad_one_next_combi_proc: process (bytes_ena, sch_ld, pad_one_reg) is + begin + -- after one-insertion, clear the pad-one flag register + if (bytes_ena /= b"1111") and (sch_ld = '1') then + pad_one_next <= '0'; + else + pad_one_next <= pad_one_reg; + end if; + end process pad_one_next_combi_proc; + + -- padding byte lane selectors + bytes_ena_combi_proc: process (bytes_i, padding_next, di_req, one_insert, end_i) is + begin + if di_req = '1' and end_i /= '1' then + -- accept only full words before last word + bytes_ena <= b"1111"; + elsif di_req = '1' and end_i = '1' then + -- user data: bytes controlled by 'bytes_i' + case bytes_i is + when b"01" => bytes_ena <= b"0001"; + when b"10" => bytes_ena <= b"0011"; + when b"11" => bytes_ena <= b"0111"; + when others => bytes_ena <= b"1111"; + end case; + else + -- no data input: force zero bits valid + bytes_ena <= b"0000"; + end if; + end process bytes_ena_combi_proc; + + -- bit counter next logic + msg_bit_cnt_next_combi_proc: process (bytes_ena, msg_bit_cnt_reg, bits_to_add) is + begin + case bytes_ena is + when b"0001" => bits_to_add <= to_unsigned( 8, 6); + when b"0011" => bits_to_add <= to_unsigned(16, 6); + when b"0111" => bits_to_add <= to_unsigned(24, 6); + when b"1111" => bits_to_add <= to_unsigned(32, 6); + when others => bits_to_add <= to_unsigned( 0, 6); + end case; + msg_bit_cnt_next <= msg_bit_cnt_reg + bits_to_add; + end process msg_bit_cnt_next_combi_proc; + + -- data input wait/run: insert wait states during data input for 'wr_i' = '0' + wait_run_ce_proc: wait_run_ce <= '1' when di_req = '1' and wr_i = '1' else '0'; + + -- padding one-insertion control + one_insert_proc: one_insert <= '1' when pad_one_reg = '1' else '0'; + + -- bit counter clock enable + msg_bit_cnt_ce_proc : msg_bit_cnt_ce <= '1' when wait_run_ce = '1' else '0'; + + -- state counter next logic + st_cnt_next_proc: st_cnt_next <= st_cnt_reg + 1; + + -- bytes_i error logic + bytes_error_proc: bytes_error <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and wr_i = '1' else '0'; + + -- data input error logic + data_input_error_proc: data_input_error <= '1' when wr_i = '1' and di_wr_window /= '1' else '0'; + + -- error detection logic + core_error_combi_proc: core_error <= '1' when error_i = '1' or error_lock = '1' or bytes_error = '1' or data_input_error = '1' else '0'; + + --============================================================================================= + -- OUTPUT LOGIC PROCESSES + --============================================================================================= + + bitlen_o_proc : bitlen_o <= std_logic_vector(msg_bit_cnt_reg); + bytes_ena_o_proc : bytes_ena_o <= bytes_ena; + one_insert_o_proc : one_insert_o <= one_insert; + words_sel_o_proc : words_sel_o <= words_sel; + sch_ce_o_proc : sch_ce_o <= sch_ce; + sch_ld_o_proc : sch_ld_o <= sch_ld; + core_ce_o_proc : core_ce_o <= core_ce; + core_ld_o_proc : core_ld_o <= core_ld; + oregs_ce_o_proc : oregs_ce_o <= oregs_ce; + oregs_ld_o_proc : oregs_ld_o <= oregs_ld; + Kt_addr_o_proc : Kt_addr_o <= std_logic_vector(st_cnt_reg(5 downto 0)); + di_req_o_proc : di_req_o <= di_req; + data_valid_o_proc : data_valid_o <= data_valid; + error_o_proc : error_o <= core_error; + +end rtl; +
diff --git a/verilog/rtl/opencore_hasher/sha256_hash_core.vhd b/verilog/rtl/opencore_hasher/sha256_hash_core.vhd new file mode 100755 index 0000000..ab52949 --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_hash_core.vhd
@@ -0,0 +1,190 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/06/2016 +-- Module Name: sha256_hash_core - RTL +-- Project Name: sha256 processor +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- This is the 256bit single-cycle hash core processing logic for each of the 64 block steps. +-- The combinational depth of this block is 8 layers of logic and adders. +-- This module will be the largest limitation of the synthesis top operating frequency. +-- If extra pipelining is needed, the control logic must account for the extra clock delays. +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] failed verification. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] passed first simulation verification against NIST-FIPS-180-4 test vectors. +-- 2016/06/06 v0.01.0100 [JD] passed first simulation verification against NIST-FIPS-180-4 test vectors. +-- 2016/06/07 v0.01.0105 [JD] passed verification against all NIST-FIPS-180-4 test vectors. +-- 2016/06/11 v0.01.0105 [JD] passed verification against NIST-SHA2_Additional test vectors #1 to #10. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity sha256_hash_core is + port ( + clk_i : in std_logic := 'U'; -- system clock + ce_i : in std_logic := 'U'; -- clock enable from control logic + ld_i : in std_logic := 'U'; -- parallel load internal registers with input words + A_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg A + B_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg B + C_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg C + D_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg D + E_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg E + F_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg F + G_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg G + H_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- input for reg H + A_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg A + B_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg B + C_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg C + D_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg D + E_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg E + F_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg F + G_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg G + H_o : out std_logic_vector (31 downto 0) := (others => 'U'); -- output for reg H + Kt_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- coefficients for the 64 steps of the message schedule + Wt_i : in std_logic_vector (31 downto 0) := (others => 'U') -- message schedule words for the 64 steps + ); +end sha256_hash_core; + +architecture rtl of sha256_hash_core is + -- core registers + signal reg_a : unsigned (31 downto 0) := (others => '0'); + signal reg_b : unsigned (31 downto 0) := (others => '0'); + signal reg_c : unsigned (31 downto 0) := (others => '0'); + signal reg_d : unsigned (31 downto 0) := (others => '0'); + signal reg_e : unsigned (31 downto 0) := (others => '0'); + signal reg_f : unsigned (31 downto 0) := (others => '0'); + signal reg_g : unsigned (31 downto 0) := (others => '0'); + signal reg_h : unsigned (31 downto 0) := (others => '0'); + -- combinational inputs + signal next_reg_a : unsigned (31 downto 0); + signal next_reg_b : unsigned (31 downto 0); + signal next_reg_c : unsigned (31 downto 0); + signal next_reg_d : unsigned (31 downto 0); + signal next_reg_e : unsigned (31 downto 0); + signal next_reg_f : unsigned (31 downto 0); + signal next_reg_g : unsigned (31 downto 0); + signal next_reg_h : unsigned (31 downto 0); + -- internal modulo adders + signal sum0 : unsigned (31 downto 0); + signal sum1 : unsigned (31 downto 0); + signal sum2 : unsigned (31 downto 0); + signal sum3 : unsigned (31 downto 0); + signal sum4 : unsigned (31 downto 0); + signal sum5 : unsigned (31 downto 0); + signal sum6 : unsigned (31 downto 0); + -- upper sigma functions + signal SIG0 : unsigned (31 downto 0); + signal SIG1 : unsigned (31 downto 0); + -- Ch and Maj functions + signal Ch : unsigned (31 downto 0); + signal Maj : unsigned (31 downto 0); +begin + --============================================================================================= + -- HASH BLOCK CORE LOGIC + --============================================================================================= + -- The hash core block implements the hash kernel operation that is used in each of the 64 block hash steps. + -- All operations for a kernel step execute in a single clock cycle. + -- The longest combinational path is the 'next_reg_a', with 12 logic layers total, including the upstream + -- datapath from the message scheduler. + + -- core register transfer logic + core_regs_proc: process (clk_i, ce_i) is + begin + if clk_i'event and clk_i = '1' then + if ce_i = '1' then + reg_a <= next_reg_a; + reg_b <= next_reg_b; + reg_c <= next_reg_c; + reg_d <= next_reg_d; + reg_e <= next_reg_e; + reg_f <= next_reg_f; + reg_g <= next_reg_g; + reg_h <= next_reg_h; + end if; + end if; + end process core_regs_proc; + + --============================================================================================= + -- COMBINATIONAL LOGIC + --============================================================================================= + -- word rotation and bit manipulation for each cycle + + -- input muxes and word shifter wires + next_reg_a_proc: next_reg_a <= unsigned(A_i) when ld_i = '1' else sum0; + next_reg_b_proc: next_reg_b <= unsigned(B_i) when ld_i = '1' else reg_a; + next_reg_c_proc: next_reg_c <= unsigned(C_i) when ld_i = '1' else reg_b; + next_reg_d_proc: next_reg_d <= unsigned(D_i) when ld_i = '1' else reg_c; + next_reg_e_proc: next_reg_e <= unsigned(E_i) when ld_i = '1' else sum2; + next_reg_f_proc: next_reg_f <= unsigned(F_i) when ld_i = '1' else reg_e; + next_reg_g_proc: next_reg_g <= unsigned(G_i) when ld_i = '1' else reg_f; + next_reg_h_proc: next_reg_h <= unsigned(H_i) when ld_i = '1' else reg_g; + + -- adders for the ARX functions + sum0_proc: sum0 <= sum1 + sum3; + sum1_proc: sum1 <= SIG0 + Maj; + sum2_proc: sum2 <= sum3 + reg_d; + sum3_proc: sum3 <= sum4 + SIG1; + sum4_proc: sum4 <= sum5 + unsigned(Wt_i); + sum5_proc: sum5 <= sum6 + unsigned(Kt_i); + sum6_proc: sum6 <= reg_h + Ch; + + -- upper sigma functions + SIG0_proc: SIG0 <= (reg_a(1 downto 0) & reg_a(31 downto 2)) xor (reg_a(12 downto 0) & reg_a(31 downto 13)) xor (reg_a(21 downto 0) & reg_a(31 downto 22)); + SIG1_proc: SIG1 <= (reg_e(5 downto 0) & reg_e(31 downto 6)) xor (reg_e(10 downto 0) & reg_e(31 downto 11)) xor (reg_e(24 downto 0) & reg_e(31 downto 25)); + + -- Maj and Ch functions + Maj_proc: Maj <= (reg_a and reg_b) xor (reg_a and reg_c) xor (reg_b and reg_c); + Ch_proc: Ch <= (reg_e and reg_f) xor ((not reg_e) and reg_g); + + --============================================================================================= + -- OUTPUT LOGIC + --============================================================================================= + -- connect output ports + A_o_proc: A_o <= std_logic_vector(reg_a); + B_o_proc: B_o <= std_logic_vector(reg_b); + C_o_proc: C_o <= std_logic_vector(reg_c); + D_o_proc: D_o <= std_logic_vector(reg_d); + E_o_proc: E_o <= std_logic_vector(reg_e); + F_o_proc: F_o <= std_logic_vector(reg_f); + G_o_proc: G_o <= std_logic_vector(reg_g); + H_o_proc: H_o <= std_logic_vector(reg_h); +end rtl; +
diff --git a/verilog/rtl/opencore_hasher/sha256_msg_sch.vhd b/verilog/rtl/opencore_hasher/sha256_msg_sch.vhd new file mode 100755 index 0000000..97eeabd --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_msg_sch.vhd
@@ -0,0 +1,180 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/06/2016 +-- Module Name: sha256_msg_sch - RTL +-- Project Name: sha256 processor +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- This is the message scheduler datapath for the sha256 processor. +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors passed. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity sha256_msg_sch is + port ( + clk_i : in std_logic := 'U'; -- system clock + ce_i : in std_logic := 'U'; -- clock input to word shifter + ld_i : in std_logic := 'U'; -- transparent load input to output + M_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- big endian input message words + Wt_o : out std_logic_vector (31 downto 0) -- message schedule output words + ); +end sha256_msg_sch; + +architecture rtl of sha256_msg_sch is + -- datapath pipeline + signal r0 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r1 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r2 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r3 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r4 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r5 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r6 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r7 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r8 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r9 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r10 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r11 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r12 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r13 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r14 : unsigned (31 downto 0) := (others => '0'); -- internal message register + signal r15 : unsigned (31 downto 0) := (others => '0'); -- internal message register + -- input mux feedback + signal next_M : unsigned (31 downto 0); -- sum feedback + -- word shifter wires + signal next_r0 : unsigned (31 downto 0); + signal next_r1 : unsigned (31 downto 0); + signal next_r2 : unsigned (31 downto 0); + signal next_r3 : unsigned (31 downto 0); + signal next_r4 : unsigned (31 downto 0); + signal next_r5 : unsigned (31 downto 0); + signal next_r6 : unsigned (31 downto 0); + signal next_r7 : unsigned (31 downto 0); + signal next_r8 : unsigned (31 downto 0); + signal next_r9 : unsigned (31 downto 0); + signal next_r10 : unsigned (31 downto 0); + signal next_r11 : unsigned (31 downto 0); + signal next_r12 : unsigned (31 downto 0); + signal next_r13 : unsigned (31 downto 0); + signal next_r14 : unsigned (31 downto 0); + signal next_r15 : unsigned (31 downto 0); + -- internal modulo adders + signal sum0 : unsigned (31 downto 0); -- modulo adder r1 + sum1 + signal sum1 : unsigned (31 downto 0); -- modulo adder s0 + sum2 + signal sum2 : unsigned (31 downto 0); -- modulo adder s1 + r10 + -- lower sigma functions + signal s0 : unsigned (31 downto 0); -- lower sigma0 function + signal s1 : unsigned (31 downto 0); -- lower sigma1 function +begin + --============================================================================================= + -- MESSAGE SCHEDULER LOGIC + --============================================================================================= + -- This logic implements the 256 bytes message schedule as a folded 16 word circular word shifter. + -- The Add-Rotate-Xor functions s0 and s1 are implemented and fed back to the word shifter. + -- To avoid a datapath pipeline delay insertion, the output is taken from the r0 input, rather than + -- the registered r0 output. This lookahead reduces one clock cycle in the overall hash computation, + -- but increases the combinational path from the input to the processor core. + -- The next_r0 combinational function has 5 layers of logic, including 3 carry chains. + + -- word shifter register transfer logic + word_shifter_proc: process (clk_i, ce_i) is + begin + if clk_i'event and clk_i = '1' then + if ce_i = '1' then + r0 <= next_r0; + r1 <= next_r1; + r2 <= next_r2; + r3 <= next_r3; + r4 <= next_r4; + r5 <= next_r5; + r6 <= next_r6; + r7 <= next_r7; + r8 <= next_r8; + r9 <= next_r9; + r10 <= next_r10; + r11 <= next_r11; + r12 <= next_r12; + r13 <= next_r13; + r14 <= next_r14; + r15 <= next_r15; + end if; + end if; + end process word_shifter_proc; + + -- input mux + next_r0_proc: next_r0 <= unsigned(M_i) when ld_i = '1' else next_M; + next_m_proc: next_M <= sum0; + + -- word shifter wires + next_r15_proc: next_r15 <= r0; + next_r14_proc: next_r14 <= r15; + next_r13_proc: next_r13 <= r14; + next_r12_proc: next_r12 <= r13; + next_r11_proc: next_r11 <= r12; + next_r10_proc: next_r10 <= r11; + next_r9_proc: next_r9 <= r10; + next_r8_proc: next_r8 <= r9; + next_r7_proc: next_r7 <= r8; + next_r6_proc: next_r6 <= r7; + next_r5_proc: next_r5 <= r6; + next_r4_proc: next_r4 <= r5; + next_r3_proc: next_r3 <= r4; + next_r2_proc: next_r2 <= r3; + next_r1_proc: next_r1 <= r2; + + -- adders + sum0_proc: sum0 <= sum1 + r1; + sum1_proc: sum1 <= sum2 + s0; + sum2_proc: sum2 <= r10 + s1; + + -- lower sigma functions + s0_proc: s0 <= (B"000" & r2(31 downto 3)) xor (r2(17 downto 0) & r2(31 downto 18)) xor (r2(6 downto 0) & r2(31 downto 7)); + s1_proc: s1 <= (B"0000000000" & r15(31 downto 10)) xor (r15(18 downto 0) & r15(31 downto 19)) xor (r15(16 downto 0) & r15(31 downto 17)); + + --============================================================================================= + -- OUTPUT LOGIC + --============================================================================================= + -- connect output ports + Wt_o_proc: Wt_o <= std_logic_vector(next_r0); -- message scheduler output look ahead +end rtl; +
diff --git a/verilog/rtl/opencore_hasher/sha256_padding.vhd b/verilog/rtl/opencore_hasher/sha256_padding.vhd new file mode 100755 index 0000000..ebeabc6 --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_padding.vhd
@@ -0,0 +1,165 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/04/2016 +-- Module Name: sha256_padding - RTL +-- Project Name: sha256 processor +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- This is the byte padding datapath logic for the sha256 processor. +-- The padding of the last block is controlled by the byte lane selectors and the last words selectors. +-- These control signals are generated at the Control Logic block of the SHA256 processor. +-- A consistency check error signal is generated, to flag illegal control conditions. +-- This block is a fully combinational circuit, with 2 layers of logic. +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors passed. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity sha256_padding is + port ( + words_sel_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- selector for bitcnt insertion at the last block + one_insert_i : in std_logic; -- insert a leading one in the padding + bytes_ena_i : in std_logic_vector (3 downto 0) := (others => 'U'); -- byte lane selector lines + bitlen_i : in std_logic_vector (63 downto 0) := (others => 'U'); -- 64bit message bit length + di_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- big endian input message words + do_o : out std_logic_vector (31 downto 0); -- padded output words + error_o : out std_logic -- '1' if error in the byte_ena selectors + ); +end sha256_padding; + +architecture rtl of sha256_padding is + -- byte lane wires + signal BL0 : std_logic_vector (7 downto 0); -- byte lane 0 (MSB) + signal BL1 : std_logic_vector (7 downto 0); -- byte lane 1 (1SB) + signal BL2 : std_logic_vector (7 downto 0); -- byte lane 2 (2SB) + signal BL3 : std_logic_vector (7 downto 0); -- byte lane 3 (LSB) + -- selectors + signal one_insert : std_logic; -- leading one padding + signal B_ena : std_logic_vector (3 downto 0); -- byte lane selectors + signal W_sel : std_logic_vector (1 downto 0); -- last words selector + -- padded words + signal W_pad : std_logic_vector (31 downto 0); -- padding mux output + signal W_out : std_logic_vector (31 downto 0); -- output word + -- ones insertion muxes + signal BL0_top_bit : std_logic; + signal BL1_top_bit : std_logic; + signal BL2_top_bit : std_logic; + signal BL3_top_bit : std_logic; + -- bit length words + signal bitlen_hi : std_logic_vector (31 downto 0); + signal bitlen_lo : std_logic_vector (31 downto 0); + -- error indication + signal bsel_error : std_logic; + signal wsel_error : std_logic; + signal err : std_logic; +begin + --============================================================================================= + -- INPUT LOGIC + --============================================================================================= + -- copy the input ports into the internal wires + + -- byte lanes are internally spliced from the 32bit input word + BL0 <= di_i(31 downto 24); + BL1 <= di_i(23 downto 16); + BL2 <= di_i(15 downto 8); + BL3 <= di_i(7 downto 0); + + -- bitlen words spliced from the 64bit bitlen input word + bitlen_hi <= bitlen_i(63 downto 32); + bitlen_lo <= bitlen_i(31 downto 0); + + -- byte lane selectors + one_insert <= one_insert_i; + B_ena <= bytes_ena_i; + W_sel <= words_sel_i; + + --============================================================================================= + -- PADDING LOGIC + --============================================================================================= + -- The last block padding logic is implemented as a stream insertion into the input words datapath. + + -- top bit for the padding bytes. one_insert controls whether a leading one will be inserted on the leading pad byte. + BL0_top_bit <= one_insert and (not B_ena(0)); + BL1_top_bit <= one_insert and (B_ena(0) and not B_ena(1)); + BL2_top_bit <= one_insert and (B_ena(1) and not B_ena(2)); + BL3_top_bit <= one_insert and (B_ena(2) and not B_ena(3)); + + -- byte lane padding muxes + W_pad(31 downto 24) <= BL0 when B_ena(0) = '1' else (BL0_top_bit & b"0000000"); + W_pad(23 downto 16) <= BL1 when B_ena(1) = '1' else (BL1_top_bit & b"0000000"); + W_pad(15 downto 8) <= BL2 when B_ena(2) = '1' else (BL2_top_bit & b"0000000"); + W_pad(7 downto 0) <= BL3 when B_ena(3) = '1' else (BL3_top_bit & b"0000000"); + + --============================================================================================= + -- BIT COUNTER INSERTION LOGIC + --============================================================================================= + -- At the end of the last block, the 64bit message length is inserted as the last 2 words. + + W_out <= bitlen_hi when W_sel = b"01" else + bitlen_lo when W_sel = b"10" else + W_pad; + + --============================================================================================= + -- ERROR INDICATION LOGIC + --============================================================================================= + -- Invalid selectors conditions are flagged as errors + + -- byte lane selectors error: priority encoder + bsel_error <= '1' when (B_ena(3) = '1') and ((B_ena(2) = '0') or (B_ena(1) = '0') or (B_ena(0) = '0')) else + '1' when (B_ena(2) = '1') and ((B_ena(1) = '0') or (B_ena(0) = '0')) else + '1' when (B_ena(1) = '1') and (B_ena(0) = '0') else + '0'; + + -- word selector error: invalid code B"11" + wsel_error <= '1' when W_sel = b"11" else '0'; + + err <= bsel_error or wsel_error; + + --============================================================================================= + -- OUTPUT LOGIC + --============================================================================================= + -- connect output ports + do_o_proc: do_o <= W_out; + error_o_proc: error_o <= err; +end rtl; +
diff --git a/verilog/rtl/opencore_hasher/sha256_regs.vhd b/verilog/rtl/opencore_hasher/sha256_regs.vhd new file mode 100755 index 0000000..4d5f6f8 --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_regs.vhd
@@ -0,0 +1,189 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/06/2016 +-- Module Name: sha256_regs - RTL +-- Project Name: sha256 processor +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- The regs block has the output result registers for the SHA256 processor. +-- It is a single-cycle 256bit Accumulator for the block hash results, and can be implemented +-- as a 32bit MUX and a 32bit carry chain for each register. +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors passed. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sha256_regs is + port ( + clk_i : in std_logic := 'U'; -- system clock + ce_i : in std_logic := 'U'; -- clock enable from control logic + ld_i : in std_logic := 'U'; -- internal mux selection from control logic + A_i : in std_logic_vector (31 downto 0) := (others => 'U'); + B_i : in std_logic_vector (31 downto 0) := (others => 'U'); + C_i : in std_logic_vector (31 downto 0) := (others => 'U'); + D_i : in std_logic_vector (31 downto 0) := (others => 'U'); + E_i : in std_logic_vector (31 downto 0) := (others => 'U'); + F_i : in std_logic_vector (31 downto 0) := (others => 'U'); + G_i : in std_logic_vector (31 downto 0) := (others => 'U'); + H_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K0_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K1_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K2_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K3_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K4_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K5_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K6_i : in std_logic_vector (31 downto 0) := (others => 'U'); + K7_i : in std_logic_vector (31 downto 0) := (others => 'U'); + N0_o : out std_logic_vector (31 downto 0) := (others => 'U'); + N1_o : out std_logic_vector (31 downto 0) := (others => 'U'); + N2_o : out std_logic_vector (31 downto 0) := (others => 'U'); + N3_o : out std_logic_vector (31 downto 0) := (others => 'U'); + N4_o : out std_logic_vector (31 downto 0) := (others => 'U'); + N5_o : out std_logic_vector (31 downto 0) := (others => 'U'); + N6_o : out std_logic_vector (31 downto 0) := (others => 'U'); + N7_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H0_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H1_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H2_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H3_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H4_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H5_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H6_o : out std_logic_vector (31 downto 0) := (others => 'U'); + H7_o : out std_logic_vector (31 downto 0) := (others => 'U') + ); +end sha256_regs; + +architecture rtl of sha256_regs is + -- output result registers + signal reg_H0 : unsigned (31 downto 0) := (others => '0'); + signal reg_H1 : unsigned (31 downto 0) := (others => '0'); + signal reg_H2 : unsigned (31 downto 0) := (others => '0'); + signal reg_H3 : unsigned (31 downto 0) := (others => '0'); + signal reg_H4 : unsigned (31 downto 0) := (others => '0'); + signal reg_H5 : unsigned (31 downto 0) := (others => '0'); + signal reg_H6 : unsigned (31 downto 0) := (others => '0'); + signal reg_H7 : unsigned (31 downto 0) := (others => '0'); + -- word shifter wires + signal next_reg_H0 : unsigned (31 downto 0); + signal next_reg_H1 : unsigned (31 downto 0); + signal next_reg_H2 : unsigned (31 downto 0); + signal next_reg_H3 : unsigned (31 downto 0); + signal next_reg_H4 : unsigned (31 downto 0); + signal next_reg_H5 : unsigned (31 downto 0); + signal next_reg_H6 : unsigned (31 downto 0); + signal next_reg_H7 : unsigned (31 downto 0); + -- internal modulo adders + signal sum0 : unsigned (31 downto 0); + signal sum1 : unsigned (31 downto 0); + signal sum2 : unsigned (31 downto 0); + signal sum3 : unsigned (31 downto 0); + signal sum4 : unsigned (31 downto 0); + signal sum5 : unsigned (31 downto 0); + signal sum6 : unsigned (31 downto 0); + signal sum7 : unsigned (31 downto 0); +begin + --============================================================================================= + -- OUTPUT RESULT REGISTERS LOGIC + --============================================================================================= + -- The output result registers hold the intermediate values for the hash update blocks, and also the final 256bit hash value. + -- + + -- output register transfer logic + out_regs_proc: process (clk_i, ce_i) is + begin + if clk_i'event and clk_i = '1' then + if ce_i = '1' then + reg_H0 <= next_reg_H0; + reg_H1 <= next_reg_H1; + reg_H2 <= next_reg_H2; + reg_H3 <= next_reg_H3; + reg_H4 <= next_reg_H4; + reg_H5 <= next_reg_H5; + reg_H6 <= next_reg_H6; + reg_H7 <= next_reg_H7; + end if; + end if; + end process out_regs_proc; + + -- input muxes + next_reg_H0_proc: next_reg_H0 <= unsigned(K0_i) when ld_i = '1' else sum0; + next_reg_H1_proc: next_reg_H1 <= unsigned(K1_i) when ld_i = '1' else sum1; + next_reg_H2_proc: next_reg_H2 <= unsigned(K2_i) when ld_i = '1' else sum2; + next_reg_H3_proc: next_reg_H3 <= unsigned(K3_i) when ld_i = '1' else sum3; + next_reg_H4_proc: next_reg_H4 <= unsigned(K4_i) when ld_i = '1' else sum4; + next_reg_H5_proc: next_reg_H5 <= unsigned(K5_i) when ld_i = '1' else sum5; + next_reg_H6_proc: next_reg_H6 <= unsigned(K6_i) when ld_i = '1' else sum6; + next_reg_H7_proc: next_reg_H7 <= unsigned(K7_i) when ld_i = '1' else sum7; + + -- adders + sum0_proc: sum0 <= reg_H0 + unsigned(A_i); + sum1_proc: sum1 <= reg_H1 + unsigned(B_i); + sum2_proc: sum2 <= reg_H2 + unsigned(C_i); + sum3_proc: sum3 <= reg_H3 + unsigned(D_i); + sum4_proc: sum4 <= reg_H4 + unsigned(E_i); + sum5_proc: sum5 <= reg_H5 + unsigned(F_i); + sum6_proc: sum6 <= reg_H6 + unsigned(G_i); + sum7_proc: sum7 <= reg_H7 + unsigned(H_i); + + --============================================================================================= + -- OUTPUT LOGIC + --============================================================================================= + -- connect output ports + H0_o_proc: H0_o <= std_logic_vector(reg_H0); + H1_o_proc: H1_o <= std_logic_vector(reg_H1); + H2_o_proc: H2_o <= std_logic_vector(reg_H2); + H3_o_proc: H3_o <= std_logic_vector(reg_H3); + H4_o_proc: H4_o <= std_logic_vector(reg_H4); + H5_o_proc: H5_o <= std_logic_vector(reg_H5); + H6_o_proc: H6_o <= std_logic_vector(reg_H6); + H7_o_proc: H7_o <= std_logic_vector(reg_H7); + + N0_o_proc: N0_o <= std_logic_vector(next_reg_H0); + N1_o_proc: N1_o <= std_logic_vector(next_reg_H1); + N2_o_proc: N2_o <= std_logic_vector(next_reg_H2); + N3_o_proc: N3_o <= std_logic_vector(next_reg_H3); + N4_o_proc: N4_o <= std_logic_vector(next_reg_H4); + N5_o_proc: N5_o <= std_logic_vector(next_reg_H5); + N6_o_proc: N6_o <= std_logic_vector(next_reg_H6); + N7_o_proc: N7_o <= std_logic_vector(next_reg_H7); +end rtl; +
diff --git a/verilog/rtl/opencore_hasher/sha256_test.vhd b/verilog/rtl/opencore_hasher/sha256_test.vhd new file mode 100755 index 0000000..16df21d --- /dev/null +++ b/verilog/rtl/opencore_hasher/sha256_test.vhd
@@ -0,0 +1,1190 @@ +----------------------------------------------------------------------------------------------------------------------- +-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com +-- +-- Create Date: 09:56:30 05/22/2016 +-- Module Name: sha256_test.vhd +-- Project Name: sha256 engine +-- Target Devices: Spartan-6 +-- Tool versions: ISE 14.7 +-- Description: +-- +-- Testbench for the GV_SHA256 engine. +-- This is the testbench for the GV_SHA256 engine. It exercises all the input control signals and error generation, +-- and tests the GV_SHA256 engine with the NIST SHA256 test vectors, including the additional NIST test vectors up to the +-- 1 million chars. +-- +-- The logic implements a fast engine, with 65 cycles per 512-bit block. +-- +-- The following waveforms describe the operation of the engine control signals for message start, update and end. +-- +-- BEGIN BLOCK (1st block) +-- ====================== +-- +-- The hash operation starts with a 'begin' sync pulse, which causes the RESET of the processor. The processor comes out of RESET only after 'begin' is +-- released. +-- The DATA_INPUT state is signalled by the data request signal 'di_req' going HIGH. The processor will latch 16 words from the 'di' port, at every +-- rising edge of the system clock. At the end of the block input, the 'di_req' signal goes LOW. +-- The input data can be held by bringing the 'wr_i' input LOW. When the 'wr_i' input is held LOW during data write, it inserts a wait state in the +-- processor, to cope with slow inputs or to allow periodic fetches of input data from multiple data sources. +-- The 'di_req' signal will remain HIGH while data input is requested. When all 16 words are clocked in, 'di_req' goes LOW, and 'wr_i' is not allowed +-- during the internal processing phase. +-- +-- state |reset| data |wait | | process +-- __ |__ |__ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ |__ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock +-- _____ +-- start_i ______/ \_\_______________________________________________________________________________________________________________________... -- 'start_i' resets the processor and starts a new hash +-- +-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input +-- __ _ _ _ _____________________________________________________________________________________________________ +-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input +-- ___________________________________________ _________________________________________________________ +-- wr_i __________/____/ \_____/ \_____________... -- 'wr_i' can hold the core for slow data +-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________... +-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge +-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... +-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value +-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... +-- Wt_i@core __________\___\__W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_________________... -- msg scheduler lookahead output for Wt_i at core +-- ______________ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... +-- Kt_i@core ______________/__K0_/__K1_/__K2_/__K3_/__K4_/__K5_/__K6_______/__K7_/__K8_/__K9_/_K10_/_K11_/_K12_/_K13_/_K14_/_K15_________________... -- Kt rom synchronous with scheduler for Kt_i at core +-- __ _ _ _ +-- error_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' clears any error condition +-- __ _ _ _ +-- do_valid_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' invalidates any previous results +-- +-- +-- UPDATE BLOCK (preload) +-- ===================== +-- +-- At the start of each block, the 'di_req' signal is raised to request new data. +-- +-- state ... process |next | data |wait | | process +-- __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock +-- +-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input +-- _____________________________________________________________________________________________________ +-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input +-- ______________________________________ _________________________________________________________ +-- wr_i _____________________/ \_____/ \_... -- 'wr_i' can hold the core for slow data +-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____... +-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge +-- +-- +-- UPDATE BLOCK (delayed start) +-- =========================== +-- +-- The data for the new block can be delayed, by keeping the 'wr_i' signal low until the data is present at the data input port. +-- +-- state ..|next | wait | data |wait | | process +-- __ __ __ __ __ |__ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock +-- +-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input +-- _______ _ _ ___________________________________________________________________________________________________________ +-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input +-- __________________________________________________ _____________________________________________ +-- wr_i ________________ _ _ ______/ \_____/ \_... -- 'wr_i' valid on rising edge of 'clk_i' +-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____... +-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\_____W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\__Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge +-- +-- +-- END BLOCK (success) +-- ================== +-- +-- At the end of the last block the signal 'end' must be raised for at least one clock cycle. +-- The 'bytes' input marks the number of valid bytes in the last word. +-- A PADDING state completes the last data block and a BLK_PROCESS finishes the hash computation. +-- The 'do_valid' remains HIGH until the next RESET. +-- +-- state ..|next | data | padding | process |next | valid |reset| data +-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ +-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock +-- ______ +-- start_i ____________________________________________________________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash +-- ______ +-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input +-- ___________________________________ __________ +-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input +-- ______________________________________ _________ +-- wr_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'wr_i' can hold the core for slow data +-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____... +-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored +-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____ +-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value +-- _____ _____ _____ _____ _____ _____ _____ ____ +-- bytes_i --------<__0__\__0__\__0__\__0__\__0__\__3__>-----------------------------------------------------------------------<__0__\__0_... -- bytes_i mark number of valid bytes in each word +-- +-- error_o _______________________________________________________ _ _ ___________________ _ _ ___________________________________________... -- 'error_o' goes high on an invalid computation +-- ___________ +-- do_valid_o _______________________________________________________ _ _ ___________________ _ _ ______________/ \________________... -- 'do_valid_o' goes high at the end of a computation +-- ___________ +-- H0_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H0______\________________... -- H0 holds the bytes 0..3 of the output +-- ___________ +-- H1_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H1______\________________... -- H1 holds the bytes 4..7 of the output +-- ___________ +-- H2_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H2______\________________... -- H2 holds the bytes 8..11 of the output +-- ___________ +-- H3_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H3______\________________... -- H3 holds the bytes 12..15 of the output +-- ___________ +-- H4_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H4______\________________... -- H4 holds the bytes 16..19 of the output +-- ___________ +-- H5_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H5______\________________... -- H5 holds the bytes 20..23 of the output +-- ___________ +-- H6_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H6______\________________... -- H6 holds the bytes 24..27 of the output +-- ___________ +-- H7_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H7______\________________... -- H7 holds the bytes 28..31 of the output +-- +-- +-- END BLOCK (full last block) +-- ================== +-- +-- If the last block has exactly 16 full words, the controller starts the block processing in the PADDING cycle, processes the input block, +-- and inserts a last PADDING block followed by a last BLK_PROCESS block. +-- +-- state ... data |pad | process |next | pad | process |next | valid |reset| data +-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ +-- clk_i \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock +-- ______ +-- start_i _____________________________________________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash +-- ______ +-- end_i ______________/ \______ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input +-- _________________ __________ +-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i' +-- ____________________ _________ +-- wr_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'wr_i' valid on rising edge of 'clk_i' +-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____... +-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored +-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____ +-- st_cnt_reg _13__/_14__/_15__/_16__/_17_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value +-- _____ _____ _____ _____ ____ +-- bytes_i __0__/__0__/__0__>-----------------------------------------------------------------------------------<__0__/__0_... -- bytes_i mark number of valid bytes in each word +-- ___________ +-- do_valid_o ____________________________ _ _ ___________________ _ _ __________________________/ \________________... -- 'do_valid_o' goes high at the end of a computation +-- +------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- +------------------------------ REVISION HISTORY ----------------------------------------------------------------------- +-- +-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. +-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification. +-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath. +-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed. +-- 2016/06/07 v0.01.0101 [JD] failed 2-block test for "abcdbcdecd..." vector. Fixed padding control logic. +-- 2016/06/07 v0.01.0105 [JD] sha256 verification against all NIST-FIPS-180-4 test vectors passed. +-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed. +-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block. +-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input. +-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'. +-- 2016/10/01 v0.01.0250 [JD] optimized the last null-padding state, making the algorithm isochronous for full last data blocks. +-- +----------------------------------------------------------------------------------------------------------------------- +-- TODO +-- ==== +-- +-- +----------------------------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testbench is + Generic ( + CLK_PERIOD : time := 10 ns; -- clock period for pclk_i (default 100MHz) + START_DELAY : time := 200 ns -- start delay between each run + ); +end testbench; + +architecture behavior of testbench is + + --============================================================================================= + -- Constants + --============================================================================================= + -- clock period + constant PCLK_PERIOD : time := CLK_PERIOD; -- parallel high-speed clock + + --============================================================================================= + -- Signals for state machine control + --============================================================================================= + + --============================================================================================= + -- Signals for internal operation + --============================================================================================= + --- clock signals --- + signal pclk : std_logic := '1'; -- 100MHz clock + signal dut_ce : std_logic; + -- input data + signal dut_di : std_logic_vector (31 downto 0); -- big endian input message words + signal dut_bytes : std_logic_vector (1 downto 0); -- valid bytes in input word + -- start/end commands + signal dut_start : std_logic; -- reset the processor and start a new hash + signal dut_end : std_logic; -- marks end of last block data input + -- handshake + signal dut_di_req : std_logic; -- requests data input for next word + signal dut_di_wr : std_logic; -- high for di_i write, low for hold + signal dut_error : std_logic; -- signalizes error. output data is invalid + signal dut_do_valid : std_logic; -- when high, the output is valid + -- 256bit output registers + signal dut_H0 : std_logic_vector (31 downto 0); + signal dut_H1 : std_logic_vector (31 downto 0); + signal dut_H2 : std_logic_vector (31 downto 0); + signal dut_H3 : std_logic_vector (31 downto 0); + signal dut_H4 : std_logic_vector (31 downto 0); + signal dut_H5 : std_logic_vector (31 downto 0); + signal dut_H6 : std_logic_vector (31 downto 0); + signal dut_H7 : std_logic_vector (31 downto 0); + + -- testbench control signals + signal words : natural; + signal blocks : natural; + signal test_case : natural; +begin + + --============================================================================================= + -- INSTANTIATION FOR THE DEVICE UNDER TEST + --============================================================================================= + Inst_sha_256_dut: entity work.gv_sha256(rtl) + port map( + -- clock and core enable + clk_i => pclk, + ce_i => dut_ce, + -- input data + di_i => dut_di, + bytes_i => dut_bytes, + -- start/end commands + start_i => dut_start, + end_i => dut_end, + -- handshake + di_req_o => dut_di_req, + di_wr_i => dut_di_wr, + error_o => dut_error, + do_valid_o => dut_do_valid, + -- 256bit output registers + H0_o => dut_H0, + H1_o => dut_H1, + H2_o => dut_H2, + H3_o => dut_H3, + H4_o => dut_H4, + H5_o => dut_H5, + H6_o => dut_H6, + H7_o => dut_H7 + ); + + --============================================================================================= + -- CLOCK GENERATION + --============================================================================================= + pclk_proc: process is + begin + loop + pclk <= not pclk; + wait for PCLK_PERIOD / 2; + end loop; + end process pclk_proc; + --============================================================================================= + -- TEST BENCH STIMULI + --============================================================================================= + -- This testbench exercises the SHA256 toplevel with the NIST-FIPS-180-4 test vectors. + -- + tb1 : process is + variable count_words : natural := 0; + variable count_blocks : natural := 0; + variable temp_di : unsigned (31 downto 0) := (others => '0'); + begin + wait for START_DELAY; -- wait until global set/reset completes + ------------------------------------------------------------------------------------------- + -- test vector 1 + -- src: NIST-FIPS-180-4 + -- msg := "abc" + -- hash:= BA7816BF 8F01CFEA 414140DE 5DAE2223 B00361A3 96177A9C B410FF61 F20015AD + test_case <= 1; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"61626300"; + dut_bytes <= b"11"; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: BA7816BF 8F01CFEA 414140DE 5DAE2223 B00361A3 96177A9C B410FF61 F20015AD + assert dut_H0 = x"BA7816BF" report "test #1 failed on H0" severity error; + assert dut_H1 = x"8F01CFEA" report "test #1 failed on H1" severity error; + assert dut_H2 = x"414140DE" report "test #1 failed on H2" severity error; + assert dut_H3 = x"5DAE2223" report "test #1 failed on H3" severity error; + assert dut_H4 = x"B00361A3" report "test #1 failed on H4" severity error; + assert dut_H5 = x"96177A9C" report "test #1 failed on H5" severity error; + assert dut_H6 = x"B410FF61" report "test #1 failed on H6" severity error; + assert dut_H7 = x"F20015AD" report "test #1 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 2 + -- src: NIST-FIPS-180-4 + -- msg := "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" + -- hash:= 248D6A61 D20638B8 E5C02693 0C3E6039 A33CE459 64FF2167 F6ECEDD4 19DB06C1 + test_case <= 2; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock + wait for 25 ns; -- TEST: stretch 'begin' pulse + dut_start <= '0'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + dut_bytes <= b"00"; + dut_di <= x"61626364"; + wait until pclk'event and pclk = '1'; + dut_di <= x"62636465"; + wait until pclk'event and pclk = '1'; + dut_di <= x"63646566"; + wait until pclk'event and pclk = '1'; + dut_di <= x"64656667"; + wait until pclk'event and pclk = '1'; + dut_di <= x"65666768"; + wait until pclk'event and pclk = '1'; + dut_di <= x"66676869"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6768696A"; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; -- TEST: slow inputs with 'wr_i' handshake + wait until pclk'event and pclk = '1'; + dut_di <= x"68696A6B"; + wait until pclk'event and pclk = '1'; + dut_di <= x"696A6B6C"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6A6B6C6D"; + dut_bytes <= b"01"; -- induce ERROR + wait until pclk'event and pclk = '1'; + dut_di <= x"6B6C6D6E"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6C6D6E6F"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6D6E6F70"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6E6F7071"; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock + dut_bytes <= b"01"; -- TEST: change 'bytes' value after END + wait for 75 ns; -- TEST: stretch 'end' pulse + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + ------------------------------------------------------------------------- + -- restart test #2: force error by stretching the write strobe + dut_ce <= '0'; + test_case <= 0; + wait until pclk'event and pclk = '1'; + test_case <= 2; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock + wait for 25 ns; -- TEST: stretch 'begin' pulse + dut_start <= '0'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + dut_bytes <= b"00"; + dut_di <= x"61626364"; + wait until pclk'event and pclk = '1'; + dut_di <= x"62636465"; + wait until pclk'event and pclk = '1'; + dut_di <= x"63646566"; + wait until pclk'event and pclk = '1'; + dut_di <= x"64656667"; + wait until pclk'event and pclk = '1'; + dut_di <= x"65666768"; + wait until pclk'event and pclk = '1'; + dut_di <= x"66676869"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6768696A"; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; -- TEST: slow inputs with 'wr_i' handshake + wait until pclk'event and pclk = '1'; + dut_di <= x"68696A6B"; + wait until pclk'event and pclk = '1'; + dut_di <= x"696A6B6C"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6A6B6C6D"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6B6C6D6E"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6C6D6E6F"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6D6E6F70"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6E6F7071"; + wait for 75 ns; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + ------------------------------------------------------------------------- + -- restart test #2 + dut_ce <= '0'; + test_case <= 0; + wait until pclk'event and pclk = '1'; + test_case <= 2; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"61626364"; + dut_bytes <= b"00"; + wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + wait until pclk'event and pclk = '1'; + dut_di <= x"62636465"; + wait until pclk'event and pclk = '1'; + dut_di <= x"63646566"; + wait until pclk'event and pclk = '1'; + dut_di <= x"64656667"; + wait until pclk'event and pclk = '1'; + dut_di <= x"65666768"; + wait until pclk'event and pclk = '1'; + dut_di <= x"66676869"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6768696A"; + wait until pclk'event and pclk = '1'; + dut_di <= x"68696A6B"; + wait until pclk'event and pclk = '1'; + dut_di <= x"696A6B6C"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6A6B6C6D"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6B6C6D6E"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6C6D6E6F"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6D6E6F70"; + wait until pclk'event and pclk = '1'; + dut_di <= x"6E6F7071"; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: 248D6A61 D20638B8 E5C02693 0C3E6039 A33CE459 64FF2167 F6ECEDD4 19DB06C1 + assert dut_H0 = x"248D6A61" report "test #2 failed on H0" severity error; + assert dut_H1 = x"D20638B8" report "test #2 failed on H1" severity error; + assert dut_H2 = x"E5C02693" report "test #2 failed on H2" severity error; + assert dut_H3 = x"0C3E6039" report "test #2 failed on H3" severity error; + assert dut_H4 = x"A33CE459" report "test #2 failed on H4" severity error; + assert dut_H5 = x"64FF2167" report "test #2 failed on H5" severity error; + assert dut_H6 = x"F6ECEDD4" report "test #2 failed on H6" severity error; + assert dut_H7 = x"19DB06C1" report "test #2 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 3 + -- src: NIST-ADDITIONAL-SHA256 + -- #1) 1 byte 0xbd + -- msg := x"bd" + -- hash:= 68325720 aabd7c82 f30f554b 313d0570 c95accbb 7dc4b5aa e11204c0 8ffe732b + test_case <= 3; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"bd000000"; + dut_bytes <= b"01"; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: 68325720 aabd7c82 f30f554b 313d0570 c95accbb 7dc4b5aa e11204c0 8ffe732b + assert dut_H0 = x"68325720" report "test #3 failed on H0" severity error; + assert dut_H1 = x"aabd7c82" report "test #3 failed on H1" severity error; + assert dut_H2 = x"f30f554b" report "test #3 failed on H2" severity error; + assert dut_H3 = x"313d0570" report "test #3 failed on H3" severity error; + assert dut_H4 = x"c95accbb" report "test #3 failed on H4" severity error; + assert dut_H5 = x"7dc4b5aa" report "test #3 failed on H5" severity error; + assert dut_H6 = x"e11204c0" report "test #3 failed on H6" severity error; + assert dut_H7 = x"8ffe732b" report "test #3 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 4 + -- src: NIST-ADDITIONAL-SHA256 + -- #2) 4 bytes 0xc98c8e55 + -- msg := x"c98c8e55" + -- hash:= 7abc22c0 ae5af26c e93dbb94 433a0e0b 2e119d01 4f8e7f65 bd56c61c cccd9504 + test_case <= 4; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"c98c8e55"; + dut_bytes <= b"00"; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + dut_di_wr <= '1'; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: 7abc22c0 ae5af26c e93dbb94 433a0e0b 2e119d01 4f8e7f65 bd56c61c cccd9504 + assert dut_H0 = x"7abc22c0" report "test #4 failed on H0" severity error; + assert dut_H1 = x"ae5af26c" report "test #4 failed on H1" severity error; + assert dut_H2 = x"e93dbb94" report "test #4 failed on H2" severity error; + assert dut_H3 = x"433a0e0b" report "test #4 failed on H3" severity error; + assert dut_H4 = x"2e119d01" report "test #4 failed on H4" severity error; + assert dut_H5 = x"4f8e7f65" report "test #4 failed on H5" severity error; + assert dut_H6 = x"bd56c61c" report "test #4 failed on H6" severity error; + assert dut_H7 = x"cccd9504" report "test #4 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 5 + -- src: NIST-ADDITIONAL-SHA256 + -- #3) 55 bytes of zeros + -- msg := 55 x"00" + -- hash:= 02779466 cdec1638 11d07881 5c633f21 90141308 1449002f 24aa3e80 f0b88ef7 + test_case <= 5; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"00000000"; + dut_bytes <= b"00"; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '1'; + dut_bytes <= b"11"; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: 02779466 cdec1638 11d07881 5c633f21 90141308 1449002f 24aa3e80 f0b88ef7 + assert dut_H0 = x"02779466" report "test #5 failed on H0" severity error; + assert dut_H1 = x"cdec1638" report "test #5 failed on H1" severity error; + assert dut_H2 = x"11d07881" report "test #5 failed on H2" severity error; + assert dut_H3 = x"5c633f21" report "test #5 failed on H3" severity error; + assert dut_H4 = x"90141308" report "test #5 failed on H4" severity error; + assert dut_H5 = x"1449002f" report "test #5 failed on H5" severity error; + assert dut_H6 = x"24aa3e80" report "test #5 failed on H6" severity error; + assert dut_H7 = x"f0b88ef7" report "test #5 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 6 + -- src: NIST-ADDITIONAL-SHA256 + -- #4) 56 bytes of zeros + -- msg := 56 x"00" + -- hash:= d4817aa5 497628e7 c77e6b60 6107042b bba31308 88c5f47a 375e6179 be789fbb + test_case <= 6; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"00000000"; + dut_bytes <= b"00"; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: d4817aa5 497628e7 c77e6b60 6107042b bba31308 88c5f47a 375e6179 be789fbb + assert dut_H0 = x"d4817aa5" report "test #6 failed on H0" severity error; + assert dut_H1 = x"497628e7" report "test #6 failed on H1" severity error; + assert dut_H2 = x"c77e6b60" report "test #6 failed on H2" severity error; + assert dut_H3 = x"6107042b" report "test #6 failed on H3" severity error; + assert dut_H4 = x"bba31308" report "test #6 failed on H4" severity error; + assert dut_H5 = x"88c5f47a" report "test #6 failed on H5" severity error; + assert dut_H6 = x"375e6179" report "test #6 failed on H6" severity error; + assert dut_H7 = x"be789fbb" report "test #6 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 7 + -- src: NIST-ADDITIONAL-SHA256 + -- #5) 57 bytes of zeros + -- msg := 57 x"00" + -- hash:= 65a16cb7 861335d5 ace3c607 18b5052e 44660726 da4cd13b b745381b 235a1785 + test_case <= 7; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"00000000"; + dut_bytes <= b"00"; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '1'; + dut_bytes <= b"01"; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: 65a16cb7 861335d5 ace3c607 18b5052e 44660726 da4cd13b b745381b 235a1785 + assert dut_H0 = x"65a16cb7" report "test #7 failed on H0" severity error; + assert dut_H1 = x"861335d5" report "test #7 failed on H1" severity error; + assert dut_H2 = x"ace3c607" report "test #7 failed on H2" severity error; + assert dut_H3 = x"18b5052e" report "test #7 failed on H3" severity error; + assert dut_H4 = x"44660726" report "test #7 failed on H4" severity error; + assert dut_H5 = x"da4cd13b" report "test #7 failed on H5" severity error; + assert dut_H6 = x"b745381b" report "test #7 failed on H6" severity error; + assert dut_H7 = x"235a1785" report "test #7 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 8 + -- src: NIST-ADDITIONAL-SHA256 + -- #6) 64 bytes of zeros + -- msg := 64 x"00" + -- hash:= f5a5fd42 d16a2030 2798ef6e d309979b 43003d23 20d9f0e8 ea9831a9 2759fb4b + test_case <= 8; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + dut_di <= x"00000000"; + dut_bytes <= b"00"; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: f5a5fd42 d16a2030 2798ef6e d309979b 43003d23 20d9f0e8 ea9831a9 2759fb4b + assert dut_H0 = x"f5a5fd42" report "test #8 failed on H0" severity error; + assert dut_H1 = x"d16a2030" report "test #8 failed on H1" severity error; + assert dut_H2 = x"2798ef6e" report "test #8 failed on H2" severity error; + assert dut_H3 = x"d309979b" report "test #8 failed on H3" severity error; + assert dut_H4 = x"43003d23" report "test #8 failed on H4" severity error; + assert dut_H5 = x"20d9f0e8" report "test #8 failed on H5" severity error; + assert dut_H6 = x"ea9831a9" report "test #8 failed on H6" severity error; + assert dut_H7 = x"2759fb4b" report "test #8 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 9 + -- src: NIST-ADDITIONAL-SHA256 + -- #7) 1000 bytes of zeros + -- msg := 1000 x"00" + -- hash:= 541b3e9d aa09b20b f85fa273 e5cbd3e8 0185aa4e c298e765 db87742b 70138a53 + test_case <= 9; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_bytes <= b"00"; + dut_di <= x"00000000"; + count_words := 0; + words <= count_words; + count_blocks := 0; + blocks <= count_blocks; + loop + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 15; + end loop; + dut_di_wr <= '0'; + count_words := 0; + words <= count_words; + count_blocks := count_blocks + 1; + blocks <= count_blocks; + exit when blocks = 14; + end loop; + count_words := 0; + words <= count_words; + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 8; + end loop; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: 541b3e9d aa09b20b f85fa273 e5cbd3e8 0185aa4e c298e765 db87742b 70138a53 + assert dut_H0 = x"541b3e9d" report "test #9 failed on H0" severity error; + assert dut_H1 = x"aa09b20b" report "test #9 failed on H1" severity error; + assert dut_H2 = x"f85fa273" report "test #9 failed on H2" severity error; + assert dut_H3 = x"e5cbd3e8" report "test #9 failed on H3" severity error; + assert dut_H4 = x"0185aa4e" report "test #9 failed on H4" severity error; + assert dut_H5 = x"c298e765" report "test #9 failed on H5" severity error; + assert dut_H6 = x"db87742b" report "test #9 failed on H6" severity error; + assert dut_H7 = x"70138a53" report "test #9 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 10 + -- src: NIST-ADDITIONAL-SHA256 + -- #8) 1000 bytes of 0x41 'A' + -- msg := 1000 x"41" + -- hash:= c2e68682 3489ced2 017f6059 b8b23931 8b6364f6 dcd835d0 a519105a 1eadd6e4 + test_case <= 10; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_bytes <= b"00"; + dut_di <= x"41414141"; + count_words := 0; + words <= count_words; + count_blocks := 0; + blocks <= count_blocks; + loop + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 15; + end loop; + dut_di_wr <= '0'; + count_words := 0; + words <= count_words; + count_blocks := count_blocks + 1; + blocks <= count_blocks; + exit when blocks = 14; + end loop; + count_words := 0; + words <= count_words; + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 8; + end loop; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: c2e68682 3489ced2 017f6059 b8b23931 8b6364f6 dcd835d0 a519105a 1eadd6e4 + assert dut_H0 = x"c2e68682" report "test #10 failed on H0" severity error; + assert dut_H1 = x"3489ced2" report "test #10 failed on H1" severity error; + assert dut_H2 = x"017f6059" report "test #10 failed on H2" severity error; + assert dut_H3 = x"b8b23931" report "test #10 failed on H3" severity error; + assert dut_H4 = x"8b6364f6" report "test #10 failed on H4" severity error; + assert dut_H5 = x"dcd835d0" report "test #10 failed on H5" severity error; + assert dut_H6 = x"a519105a" report "test #10 failed on H6" severity error; + assert dut_H7 = x"1eadd6e4" report "test #10 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 11 + -- src: NIST-ADDITIONAL-SHA256 + -- #9) 1005 bytes of 0x55 'U' + -- msg := 1000 x"55" + -- hash:= f4d62dde c0f3dd90 ea1380fa 16a5ff8d c4c54b21 740650f2 4afc4120 903552b0 + test_case <= 11; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_bytes <= b"00"; + dut_di <= x"55555555"; + count_words := 0; + words <= count_words; + count_blocks := 0; + blocks <= count_blocks; + loop + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 15; + end loop; + dut_di_wr <= '0'; + count_words := 0; + words <= count_words; + count_blocks := count_blocks + 1; + blocks <= count_blocks; + exit when blocks = 14; + end loop; + count_words := 0; + words <= count_words; + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 9; + end loop; + wait until pclk'event and pclk = '1'; + dut_bytes <= b"01"; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: f4d62dde c0f3dd90 ea1380fa 16a5ff8d c4c54b21 740650f2 4afc4120 903552b0 + assert dut_H0 = x"f4d62dde" report "test #11 failed on H0" severity error; + assert dut_H1 = x"c0f3dd90" report "test #11 failed on H1" severity error; + assert dut_H2 = x"ea1380fa" report "test #11 failed on H2" severity error; + assert dut_H3 = x"16a5ff8d" report "test #11 failed on H3" severity error; + assert dut_H4 = x"c4c54b21" report "test #11 failed on H4" severity error; + assert dut_H5 = x"740650f2" report "test #11 failed on H5" severity error; + assert dut_H6 = x"4afc4120" report "test #11 failed on H6" severity error; + assert dut_H7 = x"903552b0" report "test #11 failed on H7" severity error; + + ------------------------------------------------------------------------------------------- + -- test vector 12 + -- src: NIST-ADDITIONAL-SHA256 + -- #10) 1000000 bytes of zeros + -- msg := 1000000 x"00" + -- hash:= d29751f2 649b32ff 572b5e0a 9f541ea6 60a50f94 ff0beedf b0b692b9 24cc8025 + test_case <= 12; + dut_ce <= '0'; + dut_di <= (others => '0'); + dut_bytes <= b"00"; + dut_start <= '0'; + dut_end <= '0'; + dut_di_wr <= '0'; + wait until pclk'event and pclk = '1'; + dut_ce <= '1'; + dut_start <= '1'; + wait until pclk'event and pclk = '1'; + dut_start <= '0'; + dut_bytes <= b"00"; + dut_di <= x"00000000"; + count_words := 0; + words <= count_words; + count_blocks := 0; + blocks <= count_blocks; + loop + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 15; + end loop; + dut_di_wr <= '0'; + count_words := 0; + words <= count_words; + count_blocks := count_blocks + 1; + blocks <= count_blocks; + exit when blocks = 15623; + end loop; + count_words := 0; + words <= count_words; + wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; + loop + wait until pclk'event and pclk = '1'; + count_words := count_words + 1; + words <= count_words; + exit when words = 14; + end loop; + dut_end <= '1'; + wait until pclk'event and pclk = '1'; + dut_end <= '0'; + dut_di_wr <= '0'; + if dut_error /= '1' and dut_do_valid /= '1' then + while dut_error /= '1' and dut_do_valid /= '1' loop + wait until pclk'event and pclk = '1'; + end loop; + end if; + wait for CLK_PERIOD*20; + + -- expected: d29751f2 649b32ff 572b5e0a 9f541ea6 60a50f94 ff0beedf b0b692b9 24cc8025 + assert dut_H0 = x"d29751f2" report "test #12 failed on H0" severity error; + assert dut_H1 = x"649b32ff" report "test #12 failed on H1" severity error; + assert dut_H2 = x"572b5e0a" report "test #12 failed on H2" severity error; + assert dut_H3 = x"9f541ea6" report "test #12 failed on H3" severity error; + assert dut_H4 = x"60a50f94" report "test #12 failed on H4" severity error; + assert dut_H5 = x"ff0beedf" report "test #12 failed on H5" severity error; + assert dut_H6 = x"b0b692b9" report "test #12 failed on H6" severity error; + assert dut_H7 = x"24cc8025" report "test #12 failed on H7" severity error; + + + assert false report "End Simulation" severity failure; -- stop simulation + end process tb1; + -- End Test Bench +END;
diff --git a/verilog/rtl/opencore_hasher/wave.ghw b/verilog/rtl/opencore_hasher/wave.ghw new file mode 100755 index 0000000..58c022f --- /dev/null +++ b/verilog/rtl/opencore_hasher/wave.ghw Binary files differ
diff --git a/verilog/rtl/opencore_hasher/work-obj93.cf b/verilog/rtl/opencore_hasher/work-obj93.cf new file mode 100755 index 0000000..111e92e --- /dev/null +++ b/verilog/rtl/opencore_hasher/work-obj93.cf
@@ -0,0 +1,28 @@ +v 4 +file . "sha256_test.vhd" "f1efabeebed5214ce18ab6c6e5016693c442a5bb" "20220528165543.057": + entity testbench at 210( 24082) + 0 on 27; + architecture behavior of testbench at 221( 24411) + 0 on 28; +file . "sha256_regs.vhd" "b9f2ad25b22857f96daf6074a22f73895c9d0d20" "20220528165501.808": + entity sha256_regs at 51( 3370) + 0 on 23; + architecture rtl of sha256_regs at 95( 6117) + 0 on 24; +file . "sha256_msg_sch.vhd" "14439ed9b692d079a254ae432215955400927f55" "20220528165501.797": + entity sha256_msg_sch at 49( 3221) + 0 on 19; + architecture rtl of sha256_msg_sch at 64( 3945) + 0 on 20; +file . "sha256_Ki_rom.vhd" "640ea588c8916859276a8d77b0cfa273b26dbe76" "20220528165501.786": + entity sha256_ki_rom at 52( 3300) + 0 on 15; + architecture behavioral of sha256_ki_rom at 69( 4032) + 0 on 16; +file . "sha256_control.vhd" "d58a8fcfde113550506d450e680a97efc0f260da" "20220528163721.834": + entity sha256_control at 246( 27857) + 0 on 11; + architecture rtl of sha256_control at 278( 30388) + 0 on 12; +file . "sha256_hash_core.vhd" "8b364f812d791f909883188c6b389ed7aa4546e7" "20220528165501.782": + entity sha256_hash_core at 55( 3844) + 0 on 13; + architecture rtl of sha256_hash_core at 86( 6066) + 0 on 14; +file . "sha256_Kt_rom.vhd" "fdb82f96cf4686ca4d13e86d8c48bee201f6a801" "20220528165501.792": + entity sha256_kt_rom at 55( 3430) + 0 on 17; + architecture behavioral of sha256_kt_rom at 66( 3799) + 0 on 18; +file . "sha256_padding.vhd" "c6095a0d6fe5dccb4df01cea1267c207baeede26" "20220528165501.803": + entity sha256_padding at 53( 3577) + 0 on 21; + architecture rtl of sha256_padding at 70( 4534) + 0 on 22; +file . "gv_sha256.vhd" "342ab9df5eb4315826013f83389fbe934d0af809" "20220528165527.420": + entity gv_sha256 at 75( 5513) + 0 on 25; + architecture rtl of gv_sha256 at 108( 7292) + 0 on 26;