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foss-eda-tools/third_party/shuttle/sky130/mpw-007/slot-016/df2a54ed685b41190e635f74490adf9a05bfd886^!/.
commit
df2a54ed685b41190e635f74490adf9a05bfd886
[log]
author
Soma Szabo <soma.szabo15@gmail.com>
Mon May 16 01:37:44 2022 -0500
committer
Soma Szabo <soma.szabo15@gmail.com>
Mon May 16 01:37:44 2022 -0500
tree
c79503d508f76b527199dd495e6d061c6b9c9116
parent
c9b520bcbf9ef2091f092c0662244b8ce0eb11cc [diff]
working mpw-6c for hardening adder. still need hardening adjustments

diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
index c4bbdc6..32fafa0 100644
--- a/gds/user_proj_example.gds
+++ b/gds/user_proj_example.gds
Binary files differ

diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag
index 5d31d39..72870db 100644
--- a/mag/user_proj_example.mag
+++ b/mag/user_proj_example.mag

@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1651267418
+timestamp 1652680847
 << viali >>
 rect 2697 117249 2731 117283
 rect 4261 117249 4295 117283

diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag
index 43b5bb1..9d65e00 100644
--- a/maglef/user_proj_example.mag
+++ b/maglef/user_proj_example.mag

@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1651267446
+timestamp 1652680876
 << obsli1 >>
 rect 1104 2159 178848 117521
 << obsm1 >>
@@ -2489,7 +2489,7 @@
 string LEFclass BLOCK
 string LEFview TRUE
 string GDS_END 8544028
-string GDS_FILE /Users/somasz/Documents/GitHub/mpw_6c/caravel_tutorial/caravel_example/openlane/user_proj_example/runs/user_proj_example/results/finishing/user_proj_example.magic.gds
+string GDS_FILE /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/results/finishing/user_proj_example.magic.gds
 string GDS_START 308790
 << end >>
 

diff --git a/openlane/Makefile b/openlane/Makefile
deleted file mode 120000
index 0e855df..0000000
--- a/openlane/Makefile
+++ /dev/null

@@ -1 +0,0 @@
-../caravel/openlane/Makefile

diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 0000000..548a1ba
--- /dev/null
+++ b/openlane/Makefile

@@ -0,0 +1,109 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG ?= 2021.11.23_01.42.34
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+	@echo "Missing $@. Please create a configuration for that design"
+	@exit 1
+
+.PHONY: $(BLOCKS)
+$(BLOCKS) : % : ./%/config.tcl
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+ifeq ($(PDK_ROOT),)
+	@echo "Please export PDK_ROOT"
+	@exit 1
+endif
+	@echo "###############################################"
+	@sleep 1
+
+	@if [ -f ./$*/interactive.tcl ]; then\
+		docker run --rm -v $(OPENLANE_ROOT):/openlane \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:$(PWD)/.. \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+		-e PDK=$(PDK) \
+		-e TEST_MISMATCHES=tools \
+		-e MISMATCHES_OK=1 \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+	else\
+		docker run --rm -v $(OPENLANE_ROOT):/openlane \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:$(PWD)/.. \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		-e PDK=$(PDK) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+		-e TEST_MISMATCHES=tools \
+		-e MISMATCHES_OK=1 \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+	fi
+	mkdir -p ../signoff/$*/
+	cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+	cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
+	cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane: check-openlane-env
+	if [ -d "$(OPENLANE_ROOT)" ]; then\
+		echo "Deleting exisiting $(OPENLANE_ROOT)" && \
+		rm -rf $(OPENLANE_ROOT) && sleep 2; \
+	fi
+	git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+		cd $(OPENLANE_ROOT) && \
+		export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		$(MAKE) pull-openlane
+
+.PHONY: check-openlane-env
+check-openlane-env:
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+
+FORCE:
+
+clean:
+	@echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+	rm -rf runs/$*
+	rm -rf ../gds/$**
+	rm -rf ../mag/$**
+	rm -rf ../lef/$**
+

diff --git a/signoff/user_proj_example/final_summary_report.csv b/signoff/user_proj_example/final_summary_report.csv
index f39a03e..3c324b6 100644
--- a/signoff/user_proj_example/final_summary_report.csv
+++ b/signoff/user_proj_example/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/Users/somasz/Documents/GitHub/mpw_6c/caravel_tutorial/caravel_example/openlane/user_proj_example,user_proj_example,user_proj_example,flow completed,0h12m55s0ms,0h8m44s0ms,2151.851851851852,0.54,1075.925925925926,0.92,2352.09,581,0,0,0,0,0,0,0,11,0,0,-1,110221,8454,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,66866361.0,0.0,5.41,5.45,4.59,2.32,-1,342,1149,29,836,0,0,0,380,37,0,14,31,46,17,15,129,174,67,13,424,7276,0,7700,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.05,0.3,sky130_fd_sc_hd,4,4
+0,/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example,user_proj_example,user_proj_example,flow completed,0h13m35s0ms,0h9m33s0ms,2151.851851851852,0.54,1075.925925925926,0.92,2246.07,581,0,0,0,0,0,0,0,11,0,0,-1,110221,8454,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,66866361.0,0.0,5.41,5.45,4.59,2.32,-1,342,1149,29,836,0,0,0,380,37,0,14,31,46,17,15,129,174,67,13,424,7276,0,7700,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.05,0.3,sky130_fd_sc_hd,4,4

diff --git a/verilog/dv/adder_test1/RTL-adder_test1.vcd b/verilog/dv/adder_test1/RTL-adder_test1.vcd
index a37483e..c238ce5 100644
--- a/verilog/dv/adder_test1/RTL-adder_test1.vcd
+++ b/verilog/dv/adder_test1/RTL-adder_test1.vcd
Binary files differ

diff --git a/verilog/dv/adder_test2/RTL-adder_test2.vcd b/verilog/dv/adder_test2/RTL-adder_test2.vcd
index e420da7..9b66551 100644
--- a/verilog/dv/adder_test2/RTL-adder_test2.vcd
+++ b/verilog/dv/adder_test2/RTL-adder_test2.vcd
Binary files differ

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 93c7dd2..59871ac 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v

@@ -27,4 +27,4 @@
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
     `include "user_adder.v"
-`endif
\ No newline at end of file
+`endif

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 209c068..6202f5a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v

@@ -92,7 +92,6 @@
 //     .wb_rst_i(wb_rst_i),
 
 //     // MGMT SoC Wishbone Slave
-
 //     .wbs_cyc_i(wbs_cyc_i),
 //     .wbs_stb_i(wbs_stb_i),
 //     .wbs_we_i(wbs_we_i),
@@ -103,13 +102,11 @@
 //     .wbs_dat_o(wbs_dat_o),
 
 //     // Logic Analyzer
-
 //     .la_data_in(la_data_in),
 //     .la_data_out(la_data_out),
 //     .la_oenb (la_oenb),
 
 //     // IO Pads
-
 //     .io_in (io_in),
 //     .io_out(io_out),
 //     .io_oeb(io_oeb),