Corrected wrapper config
diff --git a/openlane/btc_miner_top/config.tcl b/openlane/btc_miner_top/config.tcl index a77a522..cc9d5b3 100755 --- a/openlane/btc_miner_top/config.tcl +++ b/openlane/btc_miner_top/config.tcl
@@ -40,8 +40,8 @@ set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.4 -set ::env(FP_CORE_UTIL) 20 +set ::env(PL_TARGET_DENSITY) 0.1 +set ::env(FP_CORE_UTIL) 5 # with 10%: detailed placement faild and had setup violations # with 50%: detailed placement faild and had setup violations # with 100% and 0.7: "Utilization exceeds 100%." Ran out of space? @@ -77,9 +77,12 @@ # with 10% and 0.3: There are hold violations in the design at the typical corner. Antenna pins violated: 86, nets violated: 86 (about -2ns violated) # DIE_AREA: "0 0 900 600" (absolute) -# with 20% and 0.4: +# with 20% and 0.4: There are hold violations in the design at the typical corner. Antenna pins violated: 73, nets violated: 72 (about -2.9ns violated) +# DIE_AREA: "0 0 900 600" (absolute) +# TODO with 5% and 0.1: + # Not sure how FP_SIZING absolute and relative works excatly and how DIE_AREA affects the overall size and constraints # set ::env(ROUTING_CORES) 4
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json index 1618cd8..ccb10dc 100644 --- a/openlane/user_project_wrapper/config.json +++ b/openlane/user_project_wrapper/config.json
@@ -9,8 +9,8 @@ "DESIGN_NAME" : "user_project_wrapper", "DIE_AREA" : "0 0 2920 3520", "DIODE_INSERTION_STRATEGY" : "0", - "EXTRA_GDS_FILES" : "../../gds/user_adder.gds", - "EXTRA_LEFS" : "../../lef/user_adder.lef", + "EXTRA_GDS_FILES" : "../../gds/btc_miner_top.gds", + "EXTRA_LEFS" : "../../lef/btc_miner_top.lef", "FILL_INSERTION" : "0", "FP_IO_HEXTEND" : "4.8", "FP_IO_HLENGTH" : "2.4", @@ -53,6 +53,6 @@ "TAP_DECAP_INSERTION" : "0", "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2", "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"], - "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_adder.v"] + "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/btc_miner_top.v"] }
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 393a727..4e7465c 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -54,13 +54,13 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_adder.v" + $script_dir/../../verilog/rtl/btc_miner_top.v" set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/user_adder.lef" + $script_dir/../../lef/btc_miner_top.lef" set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/user_adder.gds" + $script_dir/../../gds/btc_miner_top.gds" # set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}