working simplified design
diff --git a/openlane/btc_miner_top/config.tcl b/openlane/btc_miner_top/config.tcl index 36b0bc6..9b35b6d 100755 --- a/openlane/btc_miner_top/config.tcl +++ b/openlane/btc_miner_top/config.tcl
@@ -38,7 +38,7 @@ # no matter what PL or GLB parameters I set. tried increasing both HOLD_MAX_BUFFER_PERCENT and HOLD_SLACK_MARGIN to 80% and 0.3ns set ::env(FP_SIZING) absolute # max area in wrapper: 0 0 2920 3520 -set ::env(DIE_AREA) "0 0 20000 20000" +set ::env(DIE_AREA) "0 0 2920 3520" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
diff --git a/verilog/dv/btc_miner_top_test2/Makefile b/verilog/dv/btc_miner_top_test2/Makefile new file mode 100644 index 0000000..2bff07e --- /dev/null +++ b/verilog/dv/btc_miner_top_test2/Makefile
@@ -0,0 +1,30 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + + +include $(MCW_ROOT)/verilog/dv/make/env.makefile +include $(MCW_ROOT)/verilog/dv/make/var.makefile +include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +include $(MCW_ROOT)/verilog/dv/make/sim.makefile
diff --git a/verilog/dv/btc_miner_top_test2/btc_miner_top_test2.c b/verilog/dv/btc_miner_top_test2/btc_miner_top_test2.c new file mode 100644 index 0000000..27313a7 --- /dev/null +++ b/verilog/dv/btc_miner_top_test2/btc_miner_top_test2.c
@@ -0,0 +1,302 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include <defs.h> +#include <stub.c> + +// global variables +uint32_t data_in0; +uint32_t data_in1; +uint32_t data_in2; +uint32_t data_in3; +uint32_t data_in4; +uint32_t data_in5; +uint32_t data_in6; +uint32_t data_in7; +uint32_t data_in8; +uint32_t data_in9; +uint32_t data_in10; +uint32_t data_in11; +uint32_t data_in12; +uint32_t data_in13; +uint32_t data_in14; +uint32_t data_in15; + +uint32_t data_out0; +uint32_t data_out1; +uint32_t data_out2; +uint32_t data_out3; +uint32_t data_out4; +uint32_t data_out5; +uint32_t data_out6; +uint32_t data_out7; + +/* + Miner test 1 + - checks if automated state machine works as expected +*/ + +// void *memcpy(void *dest, const void *src, uint32_t n) +// { +// for (uint32_t i = 0; i < n; i++) +// { +// ((char*)dest)[i] = ((char*)src)[i]; +// } +// } + + +// void *memcpy (void *dest, const void *src, uint32_t len) +// { +// char *d = dest; +// const char *s = src; +// while (len--) +// *d++ = *s++; +// return dest; +// } + +int is_data_out_valid() +{ + return ((data_in0 + data_in1) == data_out0) && ((data_in2 + data_in3) == data_out1) && + ((data_in4 + data_in5) == data_out2) && ((data_in6 + data_in7) == data_out3) && + ((data_in8 + data_in9) == data_out4) && ((data_in10 + data_in11) == data_out5) && + ((data_in12 + data_in13) == data_out6) && ((data_in14 + data_in15) == data_out7); +} + +void main() +{ + // boolean for validating all tests + uint32_t testsPassed = 1; + + // set variables + data_in0 = 0x0FAB0FAB; + data_in1 = 0x000F00D1; + data_in2 = 0x000F00D2; + data_in3 = 0x000F00D3; + data_in4 = 0x000F00D4; + data_in5 = 0x000F00D5; + data_in6 = 0x000F00D6; + data_in7 = 0x000F00D7; + data_in8 = 0x000F00D8; + data_in9 = 0x000F00D9; + data_in10 = 0x000F00DA; + data_in11 = 0x000F00DB; + data_in12 = 0x000F00DC; + data_in13 = 0x000F00DD; + data_in14 = 0x000F00DE; + data_in15 = 0x000F00DF; + + data_out0 = 0; + data_out1 = 0; + data_out2 = 0; + data_out3 = 0; + data_out4 = 0; + data_out5 = 0; + data_out6 = 0; + data_out7 = 0; + + // SHA info + // uint32_t index = 0; + // const uint32_t sha256_input[] = { + // 0x00000001, 0x00000002, 0x00000003, 0x00000004, + // 0x00000005, 0x00000006, 0x00000007, 0x00000008, + // 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, + // 0x0000000D, 0x0000000E, 0x0000000F, 0x00000010 + // }; + + + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + reg_spi_enable = 1; + reg_wb_enable = 1; + // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, + // connect to housekeeping SPI + + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // LA probes [31:0] input to MGMT from USER + reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0] + // LA probes [63:32] input to MGMT from USER + reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] + // LA probes [95:64] input to MGMT from USER + reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64] + // LA probes [127:96] output from MGMT into USER + reg_la3_oenb = reg_la3_iena = 0xFFFF3FFF; // [127:96] + + // Flag start of the test + reg_mprj_datal = 0xFEEDFEED; + // reg_mprj_datah = 0x00000000; + + // set control information to SHA256: sha_mode, sha_init, auto_ctrl, and start_ctrl + // *init bit starts sha_core, but only write to control register after reading in 512-bit input! + reg_la3_data = 0x00050C00; + + reg_mprj_slave = data_in0; + + // set control information to SHA256: disable start_ctrl + reg_la3_data = 0x00050800; + + reg_mprj_slave = data_in1; + reg_mprj_slave = data_in2; + reg_mprj_slave = data_in3; + reg_mprj_slave = data_in4; + reg_mprj_slave = data_in5; + reg_mprj_slave = data_in6; + reg_mprj_slave = data_in7; + reg_mprj_slave = data_in8; + reg_mprj_slave = data_in9; + reg_mprj_slave = data_in10; + reg_mprj_slave = data_in11; + reg_mprj_slave = data_in12; + reg_mprj_slave = data_in13; + reg_mprj_slave = data_in14; + reg_mprj_slave = data_in15; + + // read valid output hash (digest) + data_out0 = reg_mprj_slave; + data_out1 = reg_mprj_slave; + data_out2 = reg_mprj_slave; + data_out3 = reg_mprj_slave; + data_out4 = reg_mprj_slave; + data_out5 = reg_mprj_slave; + data_out6 = reg_mprj_slave; + data_out7 = reg_mprj_slave; + + + if (is_data_out_valid()) + { + // Success + testsPassed = testsPassed & 1; + } + else + { + testsPassed = testsPassed & 0; + } + + + // * 2nd round of additions + // set global variables + data_in0 = 0x000DABB1; + data_in1 = 0x00FDABB2; + data_in2 = 0x0A0DABB3; + data_in3 = 0x000DABB4; + data_in4 = 0x0E0DABB5; + data_in5 = 0x000DABB6; + data_in6 = 0x50EDABB7; + data_in7 = 0x000DABB8; + data_in8 = 0x700DABB9; + data_in9 = 0x000DABBA; + data_in10 = 0x600DABBB; + data_in11 = 0x300DABBC; + data_in12 = 0x000DABBD; + data_in13 = 0x100DABBE; + data_in14 = 0x000DABBF; + data_in15 = 0x0FEDABC0; + + data_out0 = 0; + data_out1 = 0; + data_out2 = 0; + data_out3 = 0; + data_out4 = 0; + data_out5 = 0; + data_out6 = 0; + data_out7 = 0; + + // set control information to SHA256: sha_mode, sha_init, auto_ctrl, and start_ctrl + reg_la3_data = 0x00050C00; + + reg_mprj_slave = data_in0; + + // set control information to SHA256: disable start_ctrl + reg_la3_data = 0x00050800; + + reg_mprj_slave = data_in1; + reg_mprj_slave = data_in2; + reg_mprj_slave = data_in3; + reg_mprj_slave = data_in4; + reg_mprj_slave = data_in5; + reg_mprj_slave = data_in6; + reg_mprj_slave = data_in7; + reg_mprj_slave = data_in8; + reg_mprj_slave = data_in9; + reg_mprj_slave = data_in10; + reg_mprj_slave = data_in11; + reg_mprj_slave = data_in12; + reg_mprj_slave = data_in13; + reg_mprj_slave = data_in14; + reg_mprj_slave = data_in15; + + // read valid output hash (digest) + data_out0 = reg_mprj_slave; + data_out1 = reg_mprj_slave; + data_out2 = reg_mprj_slave; + data_out3 = reg_mprj_slave; + data_out4 = reg_mprj_slave; + data_out5 = reg_mprj_slave; + data_out6 = reg_mprj_slave; + data_out7 = reg_mprj_slave; + + if (is_data_out_valid() && testsPassed) + { + // Successfully ended test + testsPassed = testsPassed & 1; + reg_mprj_datal = 0xDEADDEAD; + } + else + { + testsPassed = testsPassed & 0; + reg_mprj_datal = 0xBAD0BAD0; + } +}
diff --git a/verilog/dv/btc_miner_top_test2/btc_miner_top_test2_tb.v b/verilog/dv/btc_miner_top_test2/btc_miner_top_test2_tb.v new file mode 100644 index 0000000..a423b66 --- /dev/null +++ b/verilog/dv/btc_miner_top_test2/btc_miner_top_test2_tb.v
@@ -0,0 +1,149 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +module btc_miner_top_test2_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + wire [15:0] checkbits; + + // TODO assign check bits + assign checkbits = mprj_io[31:16]; + + assign mprj_io[3] = 1'b1; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("btc_miner_top_test2.vcd"); + $dumpvars(0, btc_miner_top_test2_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (100) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Timeout, Miner Test 2 (GL) Failed"); + `else + $display ("Monitor: Timeout, Miner Test 2 (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + // TODO change finish conditions + initial begin + wait(checkbits == 16'hFEED); + $display("Monitor: Miner Test 2 Started"); + wait(checkbits == 16'hDEAD); + `ifdef GL + $display("Monitor: Miner Test 2 (GL) Passed"); + `else + $display("Monitor: Miner Test 2 (RTL) Passed"); + `endif + $finish; + end + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #100000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vddio_2 (VDD3V3), + .vssio (VSS), + .vssio_2 (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda1_2 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa1_2 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("btc_miner_top_test2.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire \ No newline at end of file
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project index eb69d6e..75cc078 100644 --- a/verilog/includes/includes.gl+sdf.caravel_user_project +++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -4,6 +4,3 @@ $USER_PROJECT_VERILOG/gl/user_adder.v $USER_PROJECT_VERILOG/gl/btc_miner_top.v $USER_PROJECT_VERILOG/gl/sha256.v -$USER_PROJECT_VERILOG/gl/sha256_core.v -$USER_PROJECT_VERILOG/gl/sha256_k_constants.v -$USER_PROJECT_VERILOG/gl/sha256_w_mem.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index 0969155..49c3fc0 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -4,6 +4,3 @@ -v $(USER_PROJECT_VERILOG)/gl/user_adder.v -v $(USER_PROJECT_VERILOG)/gl/btc_miner_top.v -v $(USER_PROJECT_VERILOG)/gl/sha256.v --v $(USER_PROJECT_VERILOG)/gl/sha256_core.v --v $(USER_PROJECT_VERILOG)/gl/sha256_k_constants.v --v $(USER_PROJECT_VERILOG)/gl/sha256_w_mem.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 561fa3a..46e42c0 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -4,6 +4,3 @@ -v $(USER_PROJECT_VERILOG)/rtl/user_adder.v -v $(USER_PROJECT_VERILOG)/rtl/btc_miner_top.v -v $(USER_PROJECT_VERILOG)/rtl/sha256.v --v $(USER_PROJECT_VERILOG)/rtl/sha256_core.v --v $(USER_PROJECT_VERILOG)/rtl/sha256_k_constants.v --v $(USER_PROJECT_VERILOG)/rtl/sha256_w_mem.v
diff --git a/verilog/rtl/sha256.v b/verilog/rtl/sha256.v index 3fe2a92..a27c56b 100644 --- a/verilog/rtl/sha256.v +++ b/verilog/rtl/sha256.v
@@ -111,10 +111,14 @@ //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- - wire core_ready; + // wire core_ready; wire [511 : 0] core_block; - wire [255 : 0] core_digest; - wire core_digest_valid; + // wire [255 : 0] core_digest; + // wire core_digest_valid; + + // simplified design + wire [31:0] added_data [7:0]; + // wire [63:0] multiplied_data [3:0]; reg [31 : 0] tmp_read_data; reg tmp_error; @@ -131,25 +135,39 @@ assign read_data = tmp_read_data; assign error = tmp_error; + assign added_data[0] = block_reg[00] + block_reg[01]; + assign added_data[1] = block_reg[02] + block_reg[03]; + assign added_data[2] = block_reg[04] + block_reg[05]; + assign added_data[3] = block_reg[06] + block_reg[07]; + assign added_data[4] = block_reg[08] + block_reg[09]; + assign added_data[5] = block_reg[10] + block_reg[11]; + assign added_data[6] = block_reg[12] + block_reg[13]; + assign added_data[7] = block_reg[14] + block_reg[15]; + + // assign multiplied_data[0] = block_reg[00] * block_reg[01]; + // assign multiplied_data[1] = block_reg[02] * block_reg[03]; + // assign multiplied_data[2] = block_reg[04] * block_reg[05]; + // assign multiplied_data[3] = block_reg[06] * block_reg[07]; + //---------------------------------------------------------------- // core instantiation. //---------------------------------------------------------------- - sha256_core core( - .clk(clk), - .reset_n(reset_n), + // sha256_core core( + // .clk(clk), + // .reset_n(reset_n), - .init(init_reg), - .next(next_reg), - .mode(mode_reg), + // .init(init_reg), + // .next(next_reg), + // .mode(mode_reg), - .block(core_block), + // .block(core_block), - .ready(core_ready), + // .ready(core_ready), // output - .digest(core_digest), - .digest_valid(core_digest_valid) - ); + // .digest(core_digest), // output + // .digest_valid(core_digest_valid) // output + // ); //---------------------------------------------------------------- @@ -177,19 +195,30 @@ end else begin - ready_reg <= core_ready; - digest_valid_reg <= core_digest_valid; + // temporarily make design add 512-bit input + // ready_reg <= core_ready; + ready_reg <= 1'b1; + // digest_valid_reg <= core_digest_valid; init_reg <= init_new; next_reg <= next_new; if (mode_we) mode_reg <= mode_new; - if (core_digest_valid) - digest_reg <= core_digest; + // if (core_digest_valid) + // digest_reg <= core_digest; - if (block_we) + // simplified, if digest valid (when not writing to block) assign added_data to output + if (digest_valid_reg) + digest_reg <= {added_data[0], added_data[1], added_data[2], added_data[3], added_data[4], added_data[5], added_data[6], added_data[7]}; + + if (block_we) begin block_reg[address[3 : 0]] <= write_data; + digest_valid_reg <= 1'b0; + end + else begin + digest_valid_reg <= 1'b1; + end end end // reg_update @@ -228,7 +257,7 @@ else begin - // read + // read if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) tmp_read_data = block_reg[address[3 : 0]];