potential btc_miner_change and decoder created

caravel

diff --git a/caravel b/caravel
new file mode 160000
index 0000000..477c17f
--- /dev/null
+++ b/caravel
@@ -0,0 +1 @@
+Subproject commit 477c17fb986b0d3f7f3581e940095b68bd62422f

mgmt_core_wrapper

diff --git a/mgmt_core_wrapper b/mgmt_core_wrapper
new file mode 160000
index 0000000..3fee299
--- /dev/null
+++ b/mgmt_core_wrapper
@@ -0,0 +1 @@
+Subproject commit 3fee299f8177cebf7919eb0e6da7f0f5ad7af31d

verilog/rtl/btc_miner_top.sv

diff --git a/verilog/rtl/btc_miner_top.sv b/verilog/rtl/btc_miner_top.sv
index 0aabcf2..1773d9e 100644
--- a/verilog/rtl/btc_miner_top.sv
+++ b/verilog/rtl/btc_miner_top.sv
@@ -239,7 +239,7 @@
 
             if (wb_we) begin
               // TODO? read WB data into block header
-              block_header[BITS*count +:BITS] <= wdata;
+              block_header[BITS*count + 31 : BITS*count] <= wdata;
               if (count == 18) begin
                 // TODO pass encoded_target into decoder module
                 encoded_target <= wdata;

verilog/rtl/decoder.sv

diff --git a/verilog/rtl/decoder.sv b/verilog/rtl/decoder.sv
new file mode 100644
index 0000000..45e2556
--- /dev/null
+++ b/verilog/rtl/decoder.sv
@@ -0,0 +1,21 @@
+`default_nettype none

+`timescale 1 ns / 10 ps

+/*

+ *-------------------------------------------------------------

+ *

+ * decoder

+ *

+ * Used to transform a 32 bit target into a 256 bit target using math magic.

+ *

+ *

+ *-------------------------------------------------------------

+ */

+

+module decoder #(input logic [31:0] target,

+                    output logic [255:0] fullTarget);

+

+	logic [7:0] size;

+    size<=target[31:24];

+    

+

+endmodule