fixed decoder

verilog/dv/decoder_test/decoder.sv

diff --git a/verilog/dv/decoder_test/decoder.sv b/verilog/dv/decoder_test/decoder.sv
index 94d8e2a..02a0a56 100644
--- a/verilog/dv/decoder_test/decoder.sv
+++ b/verilog/dv/decoder_test/decoder.sv
@@ -13,36 +13,20 @@
 module decoder (input logic [31:0] target,

                     output logic [255:0] fullTarget);

 

-	logic [3:0] sizeTens;

-    logic [3:0] sizeOnes;

-    logic [255:0] decoded;

-    integer spacing;

-    integer leftBuffer;

+	logic [7:0] shift_amount;

+    logic [255:0] temp_reg;

     integer i;

     initial begin

-        sizeTens=target[31:28];

-        sizeOnes=target[27:24];

 

-        //IDK if this is legal

-        spacing  = sizeTens*16+sizeOnes;

+        shift_amount=target[31:24];

 

-        leftBuffer = 32-spacing;

-

-        //Pad left side based on first 2 bytes

-        for(i=255;i>254-leftBuffer;i--)

-            decoded[i] = 0;

+        for(i = 23;i>-1;i--)

+            temp_reg[232+i]=target[i];

         

-        //Set value within middle of target

-        i=0;

-        while(i<24) begin

-            decoded[255-leftBuffer-25+i] = target[i];

-            i++;

-        end

-        //Pad the rest

-        for(i=255-leftBuffer-26;i>-1;i--)

-            decoded[i]=0;

+        for(i = 231;i>-1;i--)

+            temp_reg[i]=0;

 

-        fullTarget = decoded;

+        assign fullTarget = temp_reg >> shift_amount;

     end

 

 

verilog/rtl/decoder.sv

diff --git a/verilog/rtl/decoder.sv b/verilog/rtl/decoder.sv
index 9564e49..02a0a56 100644
--- a/verilog/rtl/decoder.sv
+++ b/verilog/rtl/decoder.sv
@@ -7,31 +7,27 @@
  *

  * Used to transform a 32 bit target into a 256 bit target using math magic.

  *

- *

  *-------------------------------------------------------------

  */

 

-module decoder #(input logic [31:0] target,

+module decoder (input logic [31:0] target,

                     output logic [255:0] fullTarget);

 

-	logic [3:0] sizeTens;

-    logic [3:0] sizeOnes;

+	logic [7:0] shift_amount;

+    logic [255:0] temp_reg;

+    integer i;

+    initial begin

 

-    sizeTens<=target[31:28];

-    sizeOnes<=target[27:24];

+        shift_amount=target[31:24];

 

-    //IDK if this is legal

-    integer spacing  = sizeTens*16+sizeOnes;

+        for(i = 23;i>-1;i--)

+            temp_reg[232+i]=target[i];

+        

+        for(i = 231;i>-1;i--)

+            temp_reg[i]=0;

 

-    integer leftBuffer = 32-spacing;

-

-    //Todo figure out how to set all these values to 0

-    fullTarget[255:255-leftBuffer] = 0;

-    

-    //Todo figure out how to set all these values to target[23:0]

-    fullTarget[255-leftBuffer-1:255-leftBuffer-25] = target[23:0];

-

-    fullTarget[255-leftBuffer-26:0]=0;

+        assign fullTarget = temp_reg >> shift_amount;

+    end

 

 

 endmodule