Made decoder and test got both to compile. Seems to not work as expected need to look into more
diff --git a/openlane/user_proj_example/console_out1.txt b/openlane/user_proj_example/console_out1.txt new file mode 100644 index 0000000..6cafa6f --- /dev/null +++ b/openlane/user_proj_example/console_out1.txt
@@ -0,0 +1,133 @@ +CVC: Reading device model settings... +CVC: Reading power settings... +CVC: Parsing netlist /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/tmp/finishing/user_proj_example.cdl + +Cdl fixed data size 826214 +Usage CDL: Time: 0 Memory: 32288 I/O: 4520 Swap: 0 +CVC: Counting and linking... +CVC: Assigning IDs ... +Usage DB: Time: 0 Memory: 35888 I/O: 4520 Swap: 0 +CVC: 53232(53232) instances, 3346(3346) nets, 80044(80044) devices. +Setting power for mode... +Setting models... +CVC: Setting models ... +Setting model tolerances... +CVC: Shorting switches... + model short... + Shorted 212 short +Setting instance power... +CVC: Linking devices... + +Usage EQUIV: Time: 0 Memory: 40320 I/O: 4576 Swap: 0 +Power nets 377 +CVC: Shorting non conducting resistors... +CVC: Calculating resistor voltages... +Usage RES: Time: 0 Memory: 40320 I/O: 4576 Swap: 0 +Power nets 377 +CVC: Calculating min/max voltages... +Processing trivial nets found 1465 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX1: Time: 0 Memory: 40640 I/O: 4576 Swap: 0 +Power nets 1088 +! Checking forward bias diode errors: + +! Checking nmos source/drain vs bias errors: + +! Checking nmos gate vs source errors: + +! Checking pmos source/drain vs bias errors: + +! Checking pmos gate vs source errors: + +Usage ERROR: Time: 0 Memory: 40640 I/O: 4576 Swap: 0 +Saving min/max voltages... +CVC: Propagating Simulation voltages 1... +Usage SIM1: Time: 0 Memory: 40904 I/O: 4576 Swap: 0 +Power nets 1088 +Saving simulation voltages... +CVC: Propagating Simulation voltages 3... +Usage SIM2: Time: 0 Memory: 40904 I/O: 4576 Swap: 0 +Power nets 1088 +Added 0 latch voltages +CVC: Calculating min/max voltages... +Processing trivial nets found 1465 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX2: Time: 0 Memory: 40904 I/O: 4576 Swap: 0 +Power nets 1799 +! Checking overvoltage errors + +! Checking nmos possible leak errors: + +! Checking pmos possible leak errors: + +! Checking mos floating input errors: + +! Checking expected values: + +CVC: Error Counts +CVC: Fuse Problems: 0 +CVC: Min Voltage Conflicts: 0 +CVC: Max Voltage Conflicts: 0 +CVC: Leaks: 0 +CVC: LDD drain->source: 0 +CVC: HI-Z Inputs: 0 +CVC: Forward Bias Diodes: 0 +CVC: NMOS Source vs Bulk: 0 +CVC: NMOS Gate vs Source: 0 +CVC: NMOS Possible Leaks: 0 +CVC: PMOS Source vs Bulk: 0 +CVC: PMOS Gate vs Source: 0 +CVC: PMOS Possible Leaks: 0 +CVC: Overvoltage-VBG: 0 +CVC: Overvoltage-VBS: 0 +CVC: Overvoltage-VDS: 0 +CVC: Overvoltage-VGS: 0 +CVC: Model errors: 0 +CVC: Unexpected voltage : 0 +CVC: Total: 0 +Usage Total: Time: 0 Memory: 41428 I/O: 4616 Swap: 0 +Virtual net update/access 22346/4164138 +CVC: Log output to /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/reports/finishing/user_proj_example.rpt +CVC: End: Mon May 16 21:17:41 2022 + +[INFO]: Saving final set of views in '/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/results/final'... +[INFO]: Saving final set of views in '/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic'... +[INFO]: Calculating Runtime From the Start... +[INFO]: Saving runtime environment... +[INFO]: Generating Final Summary Report... +[INFO]: Design Name: user_proj_example +Run Directory: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example +---------------------------------------- + +Magic DRC Summary: +Source: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/reports/finishing/drc.rpt +Total Magic DRC violations is 0 +---------------------------------------- + +LVS Summary: +Source: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/logs/finishing/34-user_proj_example.lvs.lef.log +LVS reports no net, device, pin, or property mismatches. +Total errors = 0 +---------------------------------------- + +Antenna Summary: +Source: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/reports/finishing/antenna.rpt +Number of pins violated: 11 +Number of nets violated: 11 +[INFO]: check full report here: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv +[INFO]: There are no max slew violations in the design at the typical corner. +[INFO]: There are no hold violations in the design at the typical corner. +[INFO]: There are no setup violations in the design at the typical corner. +[SUCCESS]: Flow complete. +mkdir -p ../signoff/user_proj_example/ +cp user_proj_example/runs/user_proj_example/OPENLANE_VERSION ../signoff/user_proj_example/ +cp user_proj_example/runs/user_proj_example/PDK_SOURCES ../signoff/user_proj_example/ +cp user_proj_example/runs/user_proj_example/reports/final_summary_report.csv ../signoff/user_proj_example/
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json index d83d5bb..1618cd8 100644 --- a/openlane/user_project_wrapper/config.json +++ b/openlane/user_project_wrapper/config.json
@@ -9,8 +9,8 @@ "DESIGN_NAME" : "user_project_wrapper", "DIE_AREA" : "0 0 2920 3520", "DIODE_INSERTION_STRATEGY" : "0", - "EXTRA_GDS_FILES" : "../../gds/user_proj_example.gds", - "EXTRA_LEFS" : "../../lef/user_proj_example.lef", + "EXTRA_GDS_FILES" : "../../gds/user_adder.gds", + "EXTRA_LEFS" : "../../lef/user_adder.lef", "FILL_INSERTION" : "0", "FP_IO_HEXTEND" : "4.8", "FP_IO_HLENGTH" : "2.4", @@ -53,6 +53,6 @@ "TAP_DECAP_INSERTION" : "0", "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2", "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"], - "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"] + "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_adder.v"] }
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index f720e39..393a727 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -54,13 +54,13 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../verilog/rtl/user_adder.v" set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/user_proj_example.lef" + $script_dir/../../lef/user_adder.lef" set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/user_proj_example.gds" + $script_dir/../../gds/user_adder.gds" # set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/user_project_wrapper/console_out1.txt b/openlane/user_project_wrapper/console_out1.txt new file mode 100644 index 0000000..d9b51ed --- /dev/null +++ b/openlane/user_project_wrapper/console_out1.txt
@@ -0,0 +1,354 @@ +Magic 8.3 revision 269 - Compiled on Fri Feb 18 11:40:47 UTC 2022. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design .magicrc for technology sky130A ... +2 Magic internal units = 1 Lambda +Input style sky130(vendor): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + mvobsactive ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading sky130A Device Generator Menu ... +Loading "/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/finishing/spice.tcl" from command line. +Reading LEF data from file /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef. +This action cannot be undone. +LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. +LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. +LEF read, Line 111 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring. +LEF read, Line 113 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. +LEF read, Line 114 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. +LEF read, Line 120 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. +LEF read, Line 121 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. +LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. +LEF read, Line 154 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring. +LEF read, Line 162 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. +LEF read, Line 163 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. +LEF read, Line 165 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. +LEF read, Line 166 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. +LEF read, Line 167 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. +LEF read, Line 203 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. +LEF read, Line 204 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. +LEF read, Line 206 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. +LEF read, Line 207 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. +LEF read, Line 208 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. +LEF read, Line 244 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. +LEF read, Line 245 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. +LEF read, Line 247 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. +LEF read, Line 248 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. +LEF read, Line 249 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. +LEF read, Line 285 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. +LEF read, Line 286 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. +LEF read: Processed 792 lines. +Reading LEF data from file /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/../../lef/user_proj_example.lef. +This action cannot be undone. +LEF read: Processed 5547 lines. +Reading DEF data from file /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.def. +This action cannot be undone. + Processed 2 vias total. + Processed 1 subcell instances total. + Processed 645 pins total. + Processed 8 special nets total. + Processed 637 nets total. +DEF read: Processed 14496 lines. +Processing user_project_wrapper +Extracting user_proj_example into user_proj_example.ext: +Extracting user_project_wrapper into user_project_wrapper.ext: +exttospice finished. +Using technology "sky130A", version 1.0.283-0-g7519dfb +[INFO]: No illegal overlaps detected during extraction. +[INFO]: Incremented step index to 27. +[INFO]: Writing Powered Verilog... +OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 +This program is licensed under the BSD-3 license. See the LICENSE file for details. +Components of this program may be licensed under more restrictive licenses which must be honored. +[INFO ODB-0222] Reading LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef +[INFO ODB-0223] Created 13 technology layers +[INFO ODB-0224] Created 25 technology vias +[INFO ODB-0225] Created 442 library cells +[INFO ODB-0226] Finished LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef +[INFO ODB-0127] Reading DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.def +[INFO ODB-0128] Design: user_project_wrapper +[INFO ODB-0130] Created 645 pins. +[INFO ODB-0131] Created 1 components and 609 component-terminals. +[INFO ODB-0132] Created 8 special nets and 0 connections. +[INFO ODB-0133] Created 637 nets and 607 connections. +[INFO ODB-0134] Finished DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.def +[INFO ODB-0222] Reading LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef +[INFO ODB-0223] Created 13 technology layers +[INFO ODB-0224] Created 25 technology vias +[INFO ODB-0225] Created 442 library cells +[INFO ODB-0226] Finished LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef +[INFO ODB-0127] Reading DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/pg_define.def +[INFO ODB-0128] Design: user_project_wrapper +[INFO ODB-0130] Created 645 pins. +[INFO ODB-0131] Created 1 components and 609 component-terminals. +[INFO ODB-0133] Created 645 nets and 609 connections. +[INFO ODB-0134] Finished DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/pg_define.def +Top-level design name: user_project_wrapper +Default power net: vccd1 +Default ground net: vssd1 +Found a total of 4 power ports. +Found a total of 4 ground ports. +Modified power connections of 1 cells (Remaining: 0 ). +STDOUT: +OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 +This program is licensed under the BSD-3 license. See the LICENSE file for details. +Components of this program may be licensed under more restrictive licenses which must be honored. +warning: `//.tclsh-history' is not writable. +openroad> read_lef /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/carav +<omasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/u + +<_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/u + +<_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/me + +<r_project_wrapper/runs/user_project_wrapper/tmp/merged.lef +[INFO ODB-0222] Reading LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef +[INFO ODB-0223] Created 13 technology layers +[INFO ODB-0224] Created 25 technology vias +[INFO ODB-0225] Created 442 library cells +[INFO ODB-0226] Finished LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef +openroad> read_verilog /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/c +<rs/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openla + +</mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/ru + +<avel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tm + +</user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/pg_define.v +openroad> link_design user_project_wrapper +[WARNING ORD-1011] LEF master user_proj_example has no liberty cell. +openroad> write_def /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/cara +<somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/ + +<w_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/ + +<l_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/s + +<er_project_wrapper/runs/user_project_wrapper/tmp/synthesis/pg_define.def +openroad> exit +unable to write history to `//.tclsh-history' +STDERR: + +openroad exit code: 0 +Successfully created a new database +Modified connections between vccd1 and mprj +Modified connections between vssd1 and mprj +[INFO]: Incremented step index to 28. +[INFO]: Writing Verilog... +OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 +This program is licensed under the BSD-3 license. See the LICENSE file for details. +Components of this program may be licensed under more restrictive licenses which must be honored. +[INFO ODB-0222] Reading LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef +[INFO ODB-0223] Created 13 technology layers +[INFO ODB-0224] Created 25 technology vias +[INFO ODB-0225] Created 442 library cells +[INFO ODB-0226] Finished LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef +[INFO ODB-0127] Reading DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/finishing/27-powered_def.def +[INFO ODB-0128] Design: user_project_wrapper +[INFO ODB-0130] Created 645 pins. +[INFO ODB-0131] Created 1 components and 609 component-terminals. +[INFO ODB-0132] Created 8 special nets and 0 connections. +[INFO ODB-0133] Created 639 nets and 609 connections. +[INFO ODB-0134] Finished DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/finishing/27-powered_def.def +[INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is. +[INFO]: Changing netlist from /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/17-detailed.v to /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/finishing/27-powered_netlist.v +[INFO]: Incremented step index to 29. +[INFO]: Running LEF LVS... +[INFO]: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.spice against /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/finishing/27-powered_netlist.v +Netgen 1.5.219 compiled on Wed Feb 9 05:50:10 UTC 2022 +Warning: netgen command 'format' use fully-qualified name '::netgen::format' +Warning: netgen command 'global' use fully-qualified name '::netgen::global' +Generating JSON file result +Reading netlist file /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.spice +Reading netlist file /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/finishing/27-powered_netlist.v +Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match. +Creating placeholder cell definition for module user_proj_example. +Reading setup file /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl +Comparison output logged to file /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/30-user_project_wrapper.lef.log +Logging to file "/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/30-user_project_wrapper.lef.log" enabled +Circuit user_proj_example contains no devices. + +Contents of circuit 1: Circuit: 'user_project_wrapper' +Circuit user_project_wrapper contains 1 device instances. + Class: user_proj_example instances: 1 +Circuit contains 609 nets, and 36 disconnected pins. +Contents of circuit 2: Circuit: 'user_project_wrapper' +Circuit user_project_wrapper contains 1 device instances. + Class: user_proj_example instances: 1 +Circuit contains 609 nets, and 36 disconnected pins. + +Circuit 1 contains 1 devices, Circuit 2 contains 1 devices. +Circuit 1 contains 609 nets, Circuit 2 contains 609 nets. + +Netlists match uniquely. +Result: Circuits match uniquely. +Logging to file "/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/30-user_project_wrapper.lef.log" disabled +LVS Done. +LVS reports no net, device, pin, or property mismatches. + +Total errors = 0 +[INFO]: No LVS mismatches. +[INFO]: Incremented step index to 30. +[INFO]: Running Magic DRC... + +Magic 8.3 revision 269 - Compiled on Fri Feb 18 11:40:47 UTC 2022. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design .magicrc for technology sky130A ... +2 Magic internal units = 1 Lambda +Input style sky130(vendor): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + mvobsactive ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading sky130A Device Generator Menu ... +Loading "/openlane/scripts/magic/drc.tcl" from command line. +Warning: Calma reading is not undoable! I hope that's OK. +Library written using GDS-II Release 3.0 +Library name: user_project_wrapper +Reading "sky130_fd_sc_hd__conb_1". +Reading "sky130_fd_sc_hd__decap_3". +Reading "sky130_fd_sc_hd__decap_4". +Reading "sky130_fd_sc_hd__fill_2". +Reading "sky130_fd_sc_hd__tapvpwrvgnd_1". +Reading "sky130_fd_sc_hd__decap_8". +Reading "sky130_fd_sc_hd__decap_12". +Reading "sky130_fd_sc_hd__buf_2". +Reading "sky130_fd_sc_hd__fill_1". +Reading "sky130_fd_sc_hd__diode_2". +Reading "sky130_fd_sc_hd__decap_6". +Reading "sky130_fd_sc_hd__clkbuf_1". +Reading "sky130_fd_sc_hd__nor2_1". +Reading "sky130_fd_sc_hd__clkbuf_2". +Reading "sky130_fd_sc_hd__nand2_1". +Reading "sky130_fd_sc_hd__inv_2". +Reading "sky130_fd_sc_hd__o21ai_1". +Reading "sky130_fd_sc_hd__clkinv_2". +Reading "sky130_fd_sc_hd__and4_1". +Reading "sky130_fd_sc_hd__and3_1". +Reading "sky130_fd_sc_hd__and2_1". +Reading "sky130_fd_sc_hd__or2_1". +Reading "sky130_fd_sc_hd__a21oi_1". +Reading "sky130_fd_sc_hd__nand4_2". +Reading "sky130_fd_sc_hd__a31o_1". +Reading "sky130_fd_sc_hd__a21o_1". +Reading "sky130_fd_sc_hd__clkinv_16". +Reading "sky130_fd_sc_hd__o21a_1". +Reading "sky130_fd_sc_hd__dfxtp_4". +Reading "sky130_fd_sc_hd__nand3_1". +Reading "sky130_fd_sc_hd__and4_2". +Reading "sky130_fd_sc_hd__mux2_1". +Reading "sky130_fd_sc_hd__xnor2_1". +Reading "sky130_fd_sc_hd__o211a_1". +Reading "sky130_fd_sc_hd__a32o_1". +Reading "sky130_fd_sc_hd__a21oi_2". +Reading "sky130_fd_sc_hd__clkbuf_16". +Reading "sky130_fd_sc_hd__dfxtp_2". +Reading "sky130_fd_sc_hd__or3b_1". +Reading "sky130_fd_sc_hd__and3b_1". +Reading "sky130_fd_sc_hd__dlymetal6s2s_1". +Reading "sky130_fd_sc_hd__a221o_1". +Reading "sky130_fd_sc_hd__and2_2". +Reading "sky130_fd_sc_hd__a41o_1". +Reading "sky130_fd_sc_hd__and3_2". +Reading "sky130_fd_sc_hd__buf_1". +Reading "sky130_fd_sc_hd__o32a_1". +Reading "sky130_fd_sc_hd__and2b_2". +Reading "sky130_fd_sc_hd__mux2_2". +Reading "sky130_fd_sc_hd__buf_4". +Reading "sky130_fd_sc_hd__clkbuf_4". +Reading "sky130_fd_sc_hd__and4b_1". +Reading "sky130_fd_sc_hd__nand2_4". +Reading "user_proj_example". + 5000 uses + 10000 uses + 15000 uses + 20000 uses + 25000 uses + 30000 uses + 35000 uses + 40000 uses + 45000 uses + 50000 uses +Reading "user_project_wrapper". +[INFO]: Loading user_project_wrapper + +DRC style is now "drc(full)" +Loading DRC CIF style. +No errors found. +[INFO]: COUNT: 0 +[INFO]: Should be divided by 3 or 4 +[INFO]: DRC Checking DONE (/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/reports/finishing/drc.rpt) +[INFO]: Saving mag view with DRC errors (/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.drc.mag) +[INFO]: Saved +[INFO]: Converting Magic DRC Violations to Magic Readable Format... +[INFO]: Converting Magic DRC Violations to Klayout XML Database... +[INFO]: Converting DRC Violations to RDB Format... +[INFO]: Converted DRC Violations to RDB Format +[INFO]: No DRC violations after GDS streaming out. +[INFO]: Running Antenna Checks... +[INFO]: Incremented step index to 31. +[INFO]: Running OpenROAD Antenna Rule Checker... +OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 +This program is licensed under the BSD-3 license. See the LICENSE file for details. +Components of this program may be licensed under more restrictive licenses which must be honored. +[INFO ODB-0222] Reading LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef +[INFO ODB-0223] Created 13 technology layers +[INFO ODB-0224] Created 25 technology vias +[INFO ODB-0225] Created 442 library cells +[INFO ODB-0226] Finished LEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef +[WARNING ORD-0033] -order_wires is deprecated. +[INFO ODB-0127] Reading DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.def +[INFO ODB-0128] Design: user_project_wrapper +[INFO ODB-0130] Created 645 pins. +[INFO ODB-0131] Created 1 components and 609 component-terminals. +[INFO ODB-0132] Created 8 special nets and 0 connections. +[INFO ODB-0133] Created 637 nets and 607 connections. +[INFO ODB-0134] Finished DEF file: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.def +[INFO ANT-0001] Found 0 pin violations. +[INFO ANT-0002] Found 0 net violations in 637 nets. +[INFO]: Skipping CVC... +[INFO]: Saving final set of views in '/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/results/final'... +[INFO]: Saving final set of views in '/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic'... +[INFO]: Calculating Runtime From the Start... +[INFO]: Saving runtime environment... +[INFO]: Generating Final Summary Report... +[INFO]: Design Name: user_project_wrapper +Run Directory: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper +---------------------------------------- + +Magic DRC Summary: +Source: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/reports/finishing/drc.rpt +Total Magic DRC violations is 0 +---------------------------------------- + +LVS Summary: +Source: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/30-user_project_wrapper.lvs.lef.log +LVS reports no net, device, pin, or property mismatches. +Total errors = 0 +---------------------------------------- + +Antenna Summary: +Source: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/reports/finishing/antenna.rpt +Number of pins violated: 0 +Number of nets violated: 0 +[INFO]: check full report here: /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv +[WARNING]: There are max slew violations in the design at the typical corner. Please refer to /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/reports/routing/22-parasitics_sta.slew.rpt +[INFO]: There are no hold violations in the design at the typical corner. +[INFO]: There are no setup violations in the design at the typical corner. +[SUCCESS]: Flow complete. +[INFO]: Note that the following warnings have been generated: +[WARNING]: Skipping Tap/Decap Insertion. +[WARNING]: All internal macros will not be connected to power. +[WARNING]: All internal macros will not be connected to power. +[WARNING]: All internal macros will not be connected to power. +[WARNING]: There are max slew violations in the design at the typical corner. Please refer to /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/user_project_wrapper/reports/routing/22-parasitics_sta.slew.rpt + +mkdir -p ../signoff/user_project_wrapper/ +cp user_project_wrapper/runs/user_project_wrapper/OPENLANE_VERSION ../signoff/user_project_wrapper/ +cp user_project_wrapper/runs/user_project_wrapper/PDK_SOURCES ../signoff/user_project_wrapper/ +cp user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv ../signoff/user_project_wrapper/ +
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 5341298..23413ce 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/Users/somasz/Documents/GitHub/mpw_6c/caravel_tutorial/caravel_example/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h8m47s0ms,0h4m57s0ms,-2.0,-1,-1,-1,482.25,1,0,0,0,0,0,0,0,0,0,-1,-1,1384170,1949,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,1.92,6.58,0.48,0.29,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h9m22s0ms,0h5m11s0ms,-2.0,-1,-1,-1,483.11,1,0,0,0,0,0,0,0,0,0,-1,-1,1384170,1949,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,1.92,6.58,0.48,0.29,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/verilog/rtl/btc_miner_top.sv b/verilog/rtl/btc_miner_top.v similarity index 82% rename from verilog/rtl/btc_miner_top.sv rename to verilog/rtl/btc_miner_top.v index 1773d9e..1372de4 100644 --- a/verilog/rtl/btc_miner_top.sv +++ b/verilog/rtl/btc_miner_top.v
@@ -90,10 +90,11 @@ wire [31:0] la_write3; // Bitcoin mining variables - wire [BITS-1:0] nonce; - wire idle; - wire [639:0] block_header; - wire [255:0] target; + wire [BITS-1:0] o_nonce; + wire o_idle; + logic [639:0] o_block_header; + wire [255:0] o_target; + reg [127:0] la_data_out; // TODO // TODO use top 32-bits of LA to control muxing and other variables like starting state machine wire [2:0] la_sel; @@ -106,7 +107,7 @@ assign wdata = wbs_dat_i; // IO - assign io_out = nonce; + assign io_out = o_nonce; assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; // IRQ @@ -124,22 +125,25 @@ assign rst = (~la_oenb[97]) ? la_data_in[97] : wb_rst_i; // TODO more LA muxing - always @(la_data_in || la_data_out || la_oenb || la_sel || nonce || block_header || target) begin + // la_data_in or la_data_out or la_oenb or la_sel or nonce or block_header or target + always @(la_data_in || la_oenb || la_sel || o_nonce || o_block_header || o_target) begin case (la_sel) - 2'b00 : la_data_out[95:0] <= {{(95-BITS){1'b0}}, nonce}; - 2'b01 : la_data_out[95:0] <= block_header[95:0]; - 2'b10 : la_data_out[95:0] <= block_header[191:96]; - 2'b11 : la_data_out[95:0] <= block_header[287:192]; + 3'b000: + la_data_out[95:0] <= {{(95-BITS){1'b0}}, o_nonce}; + 3'b001: + la_data_out[95:0] <= o_block_header[95:0]; + 3'b010: + la_data_out[95:0] <= o_block_header[191:96]; + 3'b011: + la_data_out[95:0] <= o_block_header[287:192]; - default: - // should not happen endcase end // TODO create state machine for reading block header and passing to miner miner_ctrl #( .BITS(BITS) - ) miner_ctrl ( + ) miner_ctrl( .clk(clk), .rst(rst), .valid(valid), @@ -151,18 +155,18 @@ .la_input3(la_data_in[127:96]), .ready(wbs_ack_o), .rdata(rdata), - .block_header(block_header), - .target(target), - .nonce(nonce), + .block_header(o_block_header), + .target(o_target), + .nonce(o_nonce), .idle(o_idle) - ) + ); endmodule // btc_miner_top // miner_ctrl module miner_ctrl #( - parameter BITS 32 + parameter BITS = 32 )( input clk, input rst, @@ -175,14 +179,17 @@ input [BITS-1:0] la_input3, output ready, output [BITS-1:0] rdata, - output block_header, - output target, - output nonce, + output [639:0] block_header, + output [255:0] target, + output [BITS-1:0] nonce, output idle ); // enum logic [1:0] {WAIT_IN=2'b00, READ_IN=2'b01, COMPUTE=2'b10, CHECK=2'b11, WRITE_OUT=} state; - enum int unsigned {WAIT_IN=0, READ_IN=1, COMPUTE=2, INCR_NONCE=3, WRITE_OUT=4} state; + // enum integer unsigned {WAIT_IN=0, READ_IN=1, COMPUTE=2, INCR_NONCE=3, WRITE_OUT=4} state; + localparam WAIT_IN=0, READ_IN=1, COMPUTE=2, INCR_NONCE=3, WRITE_OUT=4; + + reg [2:0] state; reg ready; reg [BITS-1:0] rdata; @@ -200,10 +207,10 @@ wire start; assign idle = (state == WAIT_IN) ? 1'b1 : 1'b0; - assign start = la_write[2] ? la_input3[2] : 1'b0; + assign start = la_write3[2] ? la_input3[2] : 1'b0; // need to count to 640/32 = 20 (decimal). Only to 19 b/c nonce is last 32-bits - int unsigned count; + integer unsigned count; always @(posedge clk) begin if (rst) begin @@ -223,14 +230,15 @@ // state machine for controlling miner and I/O case (state) - WAIT_IN: + WAIT_IN: begin // TODO? miner_rst <= 1; if (start == 1) begin state <= READ_IN; end + end - READ_IN: + READ_IN: begin // TODO miner_rst <= 1; @@ -238,8 +246,39 @@ ready <= 1'b1; if (wb_we) begin - // TODO? read WB data into block header - block_header[BITS*count + 31 : BITS*count] <= wdata; + // TODO read WB data into block header + if (count == 0) begin + block_header[BITS-1:0] <= wdata; + count <= count + 1; + end else if (count == 1) begin + block_header[BITS*2-1:BITS] <= wdata; + count <= count + 1; + end else if (count == 2) begin + block_header[BITS*3-1:BITS*2] <= wdata; + count <= count + 1; + end else if (count == 3) begin + block_header[BITS*4-1:BITS*3] <= wdata; + count <= count + 1; + end else if (count == 4) begin + block_header[BITS*5-1:BITS*4] <= wdata; + count <= count + 1; + end else if (count == 5) begin + block_header[BITS*6-1:BITS*5] <= wdata; + count <= count + 1; + end else if (count == 6) begin + block_header[BITS*7-1:BITS*6] <= wdata; + count <= count + 1; + end else if (count == 7) begin + block_header[BITS*8-1:BITS*7] <= wdata; + count <= count + 1; + end else if (count == 8) begin + block_header[BITS*9-1:BITS*8] <= wdata; + count <= count + 1; + end else if (count == 9) begin + block_header[BITS*10-1:BITS*9] <= wdata; + count <= count + 1; + end + if (count == 18) begin // TODO pass encoded_target into decoder module encoded_target <= wdata; @@ -256,13 +295,14 @@ end end end + end - COMPUTE: + COMPUTE: begin // start miner if (o_done_hash) begin // TODO target if (o_hash_val < target) begin - state <= WRITE_OUT + state <= WRITE_OUT; end else begin miner_rst <= 1; block_header[639:608] <= nonce; @@ -271,14 +311,16 @@ end else begin miner_rst <= 0; end + end - INCR_NONCE: + INCR_NONCE: begin // TODO? miner_rst <= 0; nonce <= nonce + 1; state <= COMPUTE; + end - WRITE_OUT: + WRITE_OUT: begin // TODO if (valid && !ready) begin ready <= 1'b1; @@ -296,9 +338,8 @@ end end end + end - default: - // should not happen endcase end end @@ -357,7 +398,9 @@ logic[PADDED_SIZE-1:0] padded; sha_padder #(.MSG_SIZE(MSG_SIZE), .PADDED_SIZE(PADDED_SIZE)) padder (.message(message), .padded(padded)); - sha_mainloop #(.PADDED_SIZE(PADDED_SIZE)) loop (.padded(padded), .hashed(hashed), .clk(clk), .rst(rst), .done(done)); + // sha_mainloop #(.PADDED_SIZE(PADDED_SIZE)) loop (.padded(padded), .hashed(hashed), .clk(clk), .rst(rst), .done(done)); + assign hashed = 0; + assign done = 0; endmodule // sha_256 @@ -452,6 +495,7 @@ logic [31:0] ch_efg, maj_abc, sum0_a, sum1_e, kj, wj; + // (e or f or g or ch_efg) always_comb begin ch_efg = ch(e,f,g); maj_abc = maj(a,b,c);