Hardened user project example now work on sha1 hardening
diff --git a/.gitignore b/.gitignore index c3a755e..7129600 100644 --- a/.gitignore +++ b/.gitignore
@@ -10,3 +10,4 @@ /sdc/* /sdf/* /spef/* +/dependencies/*
diff --git a/Makefile b/Makefile index e318397..98538f1 100644 --- a/Makefile +++ b/Makefile
@@ -192,7 +192,7 @@ -e PDK_ROOT=$(PDK_ROOT) \ -e PDKPATH=$(PDKPATH) \ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \ - efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)" + efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
diff --git a/caravel b/caravel index 477c17f..de98d51 160000 --- a/caravel +++ b/caravel
@@ -1 +1 @@ -Subproject commit 477c17fb986b0d3f7f3581e940095b68bd62422f +Subproject commit de98d514aa6c642ef020876a64c4cdb2c9ea9a8a
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds index f5b9132..58d01d4 100644 --- a/gds/user_proj_example.gds +++ b/gds/user_proj_example.gds Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds index 597f672..34084b0 100644 --- a/gds/user_project_wrapper.gds +++ b/gds/user_project_wrapper.gds Binary files differ
diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag index 69ccd18..1053699 100644 --- a/mag/user_proj_example.mag +++ b/mag/user_proj_example.mag
@@ -1,7 +1,7 @@ magic tech sky130B magscale 1 2 -timestamp 1657064812 +timestamp 1661547474 << viali >> rect 4077 117249 4111 117283 rect 5089 117249 5123 117283 @@ -138615,7 +138615,7 @@ rect 173400 2144 173416 2208 rect 173480 2144 173488 2208 rect 173168 2128 173488 2144 -use sky130_fd_sc_hd__diode_2 ANTENNA__341__A1 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__diode_2 ANTENNA__341__A1 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 104604 0 1 4352 box -38 -48 222 592 @@ -141427,7 +141427,7 @@ timestamp 1649977179 transform -1 0 29072 0 1 25024 box -38 -48 222 592 -use sky130_ef_sc_hd__decap_12 FILLER_0_3 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_ef_sc_hd__decap_12 FILLER_0_3 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 1380 0 1 2176 box -38 -48 1142 592 @@ -141435,7 +141435,7 @@ timestamp 1649977179 transform 1 0 2484 0 1 2176 box -38 -48 1142 592 -use sky130_fd_sc_hd__fill_1 FILLER_0_27 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__fill_1 FILLER_0_27 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 3588 0 1 2176 box -38 -48 130 592 @@ -141447,7 +141447,7 @@ timestamp 1649977179 transform 1 0 4876 0 1 2176 box -38 -48 1142 592 -use sky130_fd_sc_hd__decap_3 FILLER_0_53 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__decap_3 FILLER_0_53 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 5980 0 1 2176 box -38 -48 314 592 @@ -141515,7 +141515,7 @@ timestamp 1649977179 transform 1 0 19228 0 1 2176 box -38 -48 1142 592 -use sky130_fd_sc_hd__decap_8 FILLER_0_209 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__decap_8 FILLER_0_209 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 20332 0 1 2176 box -38 -48 774 592 @@ -141523,7 +141523,7 @@ timestamp 1649977179 transform 1 0 21068 0 1 2176 box -38 -48 130 592 -use sky130_fd_sc_hd__decap_4 FILLER_0_220 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__decap_4 FILLER_0_220 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 21344 0 1 2176 box -38 -48 406 592 @@ -141563,7 +141563,7 @@ timestamp 1649977179 transform 1 0 27600 0 1 2176 box -38 -48 406 592 -use sky130_fd_sc_hd__decap_6 FILLER_0_302 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__decap_6 FILLER_0_302 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 28888 0 1 2176 box -38 -48 590 592 @@ -141795,7 +141795,7 @@ timestamp 1649977179 transform 1 0 65136 0 1 2176 box -38 -48 406 592 -use sky130_fd_sc_hd__fill_2 FILLER_0_701 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__fill_2 FILLER_0_701 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 65596 0 1 2176 box -38 -48 222 592 @@ -319051,7 +319051,7 @@ timestamp 1649977179 transform -1 0 178848 0 -1 117504 box -38 -48 314 592 -use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_424 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_424 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 3680 0 1 2176 box -38 -48 130 592 @@ -348155,51 +348155,51 @@ timestamp 1649977179 transform 1 0 176272 0 -1 117504 box -38 -48 130 592 -use sky130_fd_sc_hd__and2b_1 _340_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and2b_1 _340_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 105708 0 -1 4352 box -38 -48 590 592 -use sky130_fd_sc_hd__a21oi_4 _341_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a21oi_4 _341_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 106168 0 1 4352 box -38 -48 1234 592 -use sky130_fd_sc_hd__clkbuf_4 _342_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__clkbuf_4 _342_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 104972 0 -1 17408 box -38 -48 590 592 -use sky130_fd_sc_hd__inv_12 _343_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__inv_12 _343_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 108468 0 -1 22848 box -38 -48 1234 592 -use sky130_fd_sc_hd__mux2_2 _344_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__mux2_2 _344_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 21896 0 1 4352 box -38 -48 866 592 -use sky130_fd_sc_hd__buf_1 _345_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__buf_1 _345_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 21804 0 -1 5440 box -38 -48 314 592 -use sky130_fd_sc_hd__nand2_4 _346_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__nand2_4 _346_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 23920 0 1 4352 box -38 -48 866 592 -use sky130_fd_sc_hd__nor2_2 _347_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__nor2_2 _347_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 23736 0 -1 7616 box -38 -48 498 592 -use sky130_fd_sc_hd__buf_4 _348_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__buf_4 _348_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 64860 0 -1 9792 box -38 -48 590 592 -use sky130_fd_sc_hd__nand2_8 _349_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__nand2_8 _349_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 101660 0 1 13056 box -38 -48 1510 592 -use sky130_fd_sc_hd__buf_2 _350_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__buf_2 _350_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 16100 0 1 11968 box -38 -48 406 592 -use sky130_fd_sc_hd__clkinv_2 _351_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__clkinv_2 _351_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 13524 0 -1 6528 box -38 -48 406 592 @@ -348207,23 +348207,23 @@ timestamp 1649977179 transform -1 0 105708 0 -1 20672 box -38 -48 590 592 -use sky130_fd_sc_hd__inv_2 _353_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__inv_2 _353_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 27140 0 1 9792 box -38 -48 314 592 -use sky130_fd_sc_hd__clkbuf_2 _354_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__clkbuf_2 _354_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 46000 0 -1 10880 box -38 -48 406 592 -use sky130_fd_sc_hd__dlymetal6s2s_1 _355_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__dlymetal6s2s_1 _355_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 43424 0 -1 8704 box -38 -48 958 592 -use sky130_fd_sc_hd__nand2_1 _356_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__nand2_1 _356_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 42688 0 1 9792 box -38 -48 314 592 -use sky130_fd_sc_hd__and2_4 _357_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and2_4 _357_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 24380 0 1 4352 box -38 -48 682 592 @@ -348235,7 +348235,7 @@ timestamp 1649977179 transform -1 0 84364 0 -1 10880 box -38 -48 406 592 -use sky130_fd_sc_hd__a41o_1 _360_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a41o_1 _360_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 79304 0 -1 9792 box -38 -48 774 592 @@ -348251,7 +348251,7 @@ timestamp 1649977179 transform 1 0 86848 0 1 9792 box -38 -48 774 592 -use sky130_fd_sc_hd__and3_1 _364_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and3_1 _364_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 86664 0 1 8704 box -38 -48 498 592 @@ -348271,19 +348271,19 @@ timestamp 1649977179 transform 1 0 79304 0 1 4352 box -38 -48 774 592 -use sky130_fd_sc_hd__and4_1 _369_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and4_1 _369_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 74152 0 -1 6528 box -38 -48 682 592 -use sky130_fd_sc_hd__and4b_2 _370_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and4b_2 _370_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 72036 0 -1 9792 box -38 -48 866 592 -use sky130_fd_sc_hd__a21o_2 _371_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a21o_2 _371_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 42596 0 1 10880 box -38 -48 682 592 -use sky130_fd_sc_hd__and3_2 _372_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and3_2 _372_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 43148 0 1 8704 box -38 -48 590 592 @@ -348291,19 +348291,19 @@ timestamp 1649977179 transform -1 0 86756 0 -1 10880 box -38 -48 406 592 -use sky130_fd_sc_hd__and3b_2 _374_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and3b_2 _374_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 78016 0 -1 9792 box -38 -48 774 592 -use sky130_fd_sc_hd__a221o_1 _375_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a221o_1 _375_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 27508 0 1 9792 box -38 -48 774 592 -use sky130_fd_sc_hd__and2_1 _376_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and2_1 _376_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 29256 0 -1 21760 box -38 -48 498 592 -use sky130_fd_sc_hd__clkbuf_1 _377_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__clkbuf_1 _377_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 28428 0 1 22848 box -38 -48 314 592 @@ -348323,7 +348323,7 @@ timestamp 1649977179 transform 1 0 7912 0 1 15232 box -38 -48 314 592 -use sky130_fd_sc_hd__or2_1 _382_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__or2_1 _382_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 7912 0 1 16320 box -38 -48 498 592 @@ -348347,7 +348347,7 @@ timestamp 1649977179 transform 1 0 49220 0 -1 6528 box -38 -48 958 592 -use sky130_fd_sc_hd__a32o_2 _388_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a32o_2 _388_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 48208 0 1 4352 box -38 -48 866 592 @@ -348359,15 +348359,15 @@ timestamp 1649977179 transform -1 0 23828 0 1 18496 box -38 -48 406 592 -use sky130_fd_sc_hd__o21a_1 _391_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__o21a_1 _391_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 8924 0 1 17408 box -38 -48 590 592 -use sky130_fd_sc_hd__nand3_1 _392_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__nand3_1 _392_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 7820 0 1 14144 box -38 -48 406 592 -use sky130_fd_sc_hd__a21o_1 _393_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a21o_1 _393_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 8464 0 -1 15232 box -38 -48 590 592 @@ -348399,7 +348399,7 @@ timestamp 1649977179 transform -1 0 15180 0 -1 18496 box -38 -48 314 592 -use sky130_fd_sc_hd__a31o_1 _401_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a31o_1 _401_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 10488 0 1 15232 box -38 -48 682 592 @@ -348423,11 +348423,11 @@ timestamp 1649977179 transform 1 0 21528 0 1 19584 box -38 -48 958 592 -use sky130_fd_sc_hd__o21ai_1 _407_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__o21ai_1 _407_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 19688 0 1 18496 box -38 -48 406 592 -use sky130_fd_sc_hd__a21oi_1 _408_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a21oi_1 _408_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 19596 0 -1 19584 box -38 -48 406 592 @@ -348483,7 +348483,7 @@ timestamp 1649977179 transform 1 0 25484 0 1 17408 box -38 -48 406 592 -use sky130_fd_sc_hd__or3b_4 _422_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__or3b_4 _422_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 81420 0 -1 11968 box -38 -48 866 592 @@ -348491,11 +348491,11 @@ timestamp 1649977179 transform 1 0 29532 0 1 7616 box -38 -48 314 592 -use sky130_fd_sc_hd__o211a_1 _424_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__o211a_1 _424_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 29532 0 1 17408 box -38 -48 774 592 -use sky130_fd_sc_hd__nor2_1 _425_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__nor2_1 _425_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 27784 0 1 25024 box -38 -48 314 592 @@ -348523,7 +348523,7 @@ timestamp 1649977179 transform -1 0 61364 0 1 6528 box -38 -48 958 592 -use sky130_fd_sc_hd__a32o_1 _432_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a32o_1 _432_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 57868 0 1 5440 box -38 -48 774 592 @@ -348543,7 +348543,7 @@ timestamp 1649977179 transform -1 0 44068 0 -1 11968 box -38 -48 590 592 -use sky130_fd_sc_hd__xnor2_1 _437_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__xnor2_1 _437_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 39652 0 -1 17408 box -38 -48 682 592 @@ -348619,7 +348619,7 @@ timestamp 1649977179 transform 1 0 46092 0 -1 19584 box -38 -48 406 592 -use sky130_fd_sc_hd__or3b_2 _456_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__or3b_2 _456_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 85192 0 -1 13056 box -38 -48 682 592 @@ -348791,7 +348791,7 @@ timestamp 1649977179 transform 1 0 46552 0 -1 9792 box -38 -48 314 592 -use sky130_fd_sc_hd__a21o_4 _499_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__a21o_4 _499_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 48852 0 1 10880 box -38 -48 1142 592 @@ -348799,7 +348799,7 @@ timestamp 1649977179 transform 1 0 81328 0 1 18496 box -38 -48 406 592 -use sky130_fd_sc_hd__o32a_1 _501_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__o32a_1 _501_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 82800 0 1 17408 box -38 -48 774 592 @@ -349047,7 +349047,7 @@ timestamp 1649977179 transform 1 0 97336 0 -1 10880 box -38 -48 314 592 -use sky130_fd_sc_hd__and3_4 _563_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and3_4 _563_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 45080 0 -1 9792 box -38 -48 866 592 @@ -349067,7 +349067,7 @@ timestamp 1649977179 transform -1 0 102120 0 1 28288 box -38 -48 498 592 -use sky130_fd_sc_hd__and4_2 _568_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and4_2 _568_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 100464 0 1 28288 box -38 -48 774 592 @@ -349119,7 +349119,7 @@ timestamp 1649977179 transform -1 0 96508 0 -1 17408 box -38 -48 682 592 -use sky130_fd_sc_hd__and3b_1 _581_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__and3b_1 _581_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 95956 0 1 11968 box -38 -48 682 592 @@ -349215,7 +349215,7 @@ timestamp 1649977179 transform -1 0 108928 0 1 11968 box -38 -48 590 592 -use sky130_fd_sc_hd__nand4_1 _605_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__nand4_1 _605_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 108008 0 1 16320 box -38 -48 498 592 @@ -349243,7 +349243,7 @@ timestamp 1649977179 transform -1 0 110952 0 1 22848 box -38 -48 314 592 -use sky130_fd_sc_hd__mux2_1 _612_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__mux2_1 _612_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 7636 0 1 10880 box -38 -48 866 592 @@ -349523,15 +349523,15 @@ timestamp 1649977179 transform 1 0 63572 0 -1 11968 box -38 -48 314 592 -use sky130_fd_sc_hd__dfxtp_1 _682_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__dfxtp_1 _682_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 14260 0 -1 6528 box -38 -48 1510 592 -use sky130_fd_sc_hd__dfxtp_2 _683_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__dfxtp_2 _683_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 28704 0 -1 25024 box -38 -48 1602 592 -use sky130_fd_sc_hd__dfxtp_4 _684_ dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__dfxtp_4 _684_ dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 6716 0 1 19584 box -38 -48 1786 592 @@ -350055,11 +350055,11 @@ timestamp 1649977179 transform -1 0 76912 0 1 10880 box -38 -48 314 592 -use sky130_fd_sc_hd__clkbuf_16 clkbuf_0_counter.clk dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__clkbuf_16 clkbuf_0_counter.clk dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 61732 0 1 18496 box -38 -48 1878 592 -use sky130_fd_sc_hd__clkbuf_8 clkbuf_1_0_0_counter.clk dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__clkbuf_8 clkbuf_1_0_0_counter.clk dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 47196 0 1 18496 box -38 -48 1050 592 @@ -351135,7 +351135,7 @@ timestamp 1649977179 transform -1 0 106812 0 -1 115328 box -38 -48 406 592 -use sky130_fd_sc_hd__buf_6 repeater254 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__buf_6 repeater254 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform 1 0 108376 0 1 22848 box -38 -48 866 592 @@ -351199,7 +351199,7 @@ timestamp 1649977179 transform -1 0 30360 0 1 25024 box -38 -48 866 592 -use sky130_fd_sc_hd__conb_1 user_proj_example_270 dep/pdk/sky130B/libs.ref/sky130_fd_sc_hd/mag +use sky130_fd_sc_hd__conb_1 user_proj_example_270 dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/mag timestamp 1649977179 transform -1 0 177100 0 -1 117504 box -38 -48 314 592
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag index 45c638d..1c220f9 100644 --- a/mag/user_project_wrapper.mag +++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@ magic tech sky130B magscale 1 2 -timestamp 1657065155 +timestamp 1661549118 << metal1 >> rect 71774 702992 71780 703044 rect 71832 703032 71838 703044
diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag index 55535af..f887a47 100644 --- a/maglef/user_proj_example.mag +++ b/maglef/user_proj_example.mag
@@ -1,7 +1,7 @@ magic tech sky130B magscale 1 2 -timestamp 1657064826 +timestamp 1661547502 << nwell >> rect 1066 116677 178886 117243 rect 1066 115589 178886 116155 @@ -2588,7 +2588,7 @@ string LEFclass BLOCK string LEFview TRUE string GDS_END 7763560 -string GDS_FILE /home/kareem_farid/cup_5-7-22/openlane/user_proj_example/runs/user_proj_example/results/signoff/user_proj_example.magic.gds +string GDS_FILE /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/22_08_26_15_53/results/signoff/user_proj_example.magic.gds string GDS_START 391678 << end >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag index c4f8a63..f1d940f 100644 --- a/maglef/user_project_wrapper.mag +++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@ magic tech sky130B magscale 1 2 -timestamp 1657065162 +timestamp 1661549129 << obsli1 >> rect 236104 340159 413848 455521 << obsm1 >> @@ -3791,7 +3791,7 @@ string LEFclass BLOCK string LEFview TRUE string GDS_END 9575458 -string GDS_FILE /home/kareem_farid/cup_5-7-22/openlane/user_project_wrapper/runs/user_project_wrapper/results/signoff/user_project_wrapper.magic.gds +string GDS_FILE /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper/runs/22_08_26_16_20/results/signoff/user_project_wrapper.magic.gds string GDS_START 7763614 << end >>
diff --git a/mgmt_core_wrapper b/mgmt_core_wrapper index 3fee299..ca8f316 160000 --- a/mgmt_core_wrapper +++ b/mgmt_core_wrapper
@@ -1 +1 @@ -Subproject commit 3fee299f8177cebf7919eb0e6da7f0f5ad7af31d +Subproject commit ca8f31620b55ef8b10a750a0c570e400e07cd9f8
diff --git a/openlane/btc_miner_top/config.tcl b/openlane/btc_miner_top/config.tcl index 92eb997..8d75f74 100755 --- a/openlane/btc_miner_top/config.tcl +++ b/openlane/btc_miner_top/config.tcl
@@ -13,7 +13,7 @@ # limitations under the License. # SPDX-License-Identifier: Apache-2.0 -set ::env(PDK) "sky130A" +set ::env(PDK) $::env(PDK) set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" set script_dir [file dirname [file normalize [info script]]]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 4e549e5..b7d3480 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -54,13 +54,13 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/btc_miner_top.v" + $script_dir/../../verilog/rtl/user_proj_example.v" ;# TODO change set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/btc_miner_top.lef" + $script_dir/../../lef/user_proj_example.lef" ;# TODO change set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/btc_miner_top.gds" + $script_dir/../../gds/user_proj_example.gds" ;# TODO change # set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/signoff/user_proj_example/metrics.csv b/signoff/user_proj_example/metrics.csv new file mode 100644 index 0000000..f5e6155 --- /dev/null +++ b/signoff/user_proj_example/metrics.csv
@@ -0,0 +1,2 @@ +design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example,user_proj_example,22_08_26_15_53,flow completed,0h22m21s0ms,0h3m19s0ms,-2.0,0.54,-1,0.92,1732.05,-1,0,0,0,0,0,0,0,3,0,-1,-1,74321,5952,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,68512977.0,0.0,5.54,4.39,0.35,0.0,-1,342,1149,29,836,0,0,0,380,37,0,14,31,46,17,15,129,174,67,13,424,7276,0,7700,514032.2304,0.000437,0.000323,5.2e-06,0.000547,0.00041,3.26e-08,0.000626,0.000481,3.55e-08,5.45,11.0,90.9090909090909,10,AREA 0,5,50,1,153.6,153.18,0.05,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/metrics.csv b/signoff/user_project_wrapper/metrics.csv new file mode 100644 index 0000000..3422bf5 --- /dev/null +++ b/signoff/user_project_wrapper/metrics.csv
@@ -0,0 +1,2 @@ +design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_project_wrapper,user_project_wrapper,22_08_26_16_20,flow completed,0h7m41s0ms,0h3m50s0ms,-2.0,-1,-1,-1,473.93,1,0,0,0,0,0,0,0,0,0,-1,-1,1411423,2085,0.0,-1,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,-1,0.0,2.16,6.54,0.26,0.36,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,10176240.2304,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,11.0,90.9090909090909,10,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/verilog/dv/btc_miner_top_test2/RTL-btc_miner_top_test2.vcd b/verilog/dv/btc_miner_top_test2/RTL-btc_miner_top_test2.vcd new file mode 100644 index 0000000..3c5977e --- /dev/null +++ b/verilog/dv/btc_miner_top_test2/RTL-btc_miner_top_test2.vcd Binary files differ
diff --git a/verilog/dv/io_ports/RTL-io_ports.vcd b/verilog/dv/io_ports/RTL-io_ports.vcd index fe0e287..fe8df41 100644 --- a/verilog/dv/io_ports/RTL-io_ports.vcd +++ b/verilog/dv/io_ports/RTL-io_ports.vcd Binary files differ
diff --git a/verilog/dv/la_test1/RTL-la_test1.vcd b/verilog/dv/la_test1/RTL-la_test1.vcd index a14a726..b6717d0 100644 --- a/verilog/dv/la_test1/RTL-la_test1.vcd +++ b/verilog/dv/la_test1/RTL-la_test1.vcd Binary files differ
diff --git a/verilog/dv/la_test2/RTL-la_test2.vcd b/verilog/dv/la_test2/RTL-la_test2.vcd new file mode 100644 index 0000000..0e48e38 --- /dev/null +++ b/verilog/dv/la_test2/RTL-la_test2.vcd Binary files differ
diff --git a/verilog/dv/mprj_stimulus/RTL-mprj_stimulus.vcd b/verilog/dv/mprj_stimulus/RTL-mprj_stimulus.vcd index 6002f1b..6386a5b 100644 --- a/verilog/dv/mprj_stimulus/RTL-mprj_stimulus.vcd +++ b/verilog/dv/mprj_stimulus/RTL-mprj_stimulus.vcd Binary files differ
diff --git a/verilog/dv/wb_port/RTL-wb_port.vcd b/verilog/dv/wb_port/RTL-wb_port.vcd deleted file mode 100644 index f927537..0000000 --- a/verilog/dv/wb_port/RTL-wb_port.vcd +++ /dev/null Binary files differ
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project index 75cc078..d6304e2 100644 --- a/verilog/includes/includes.gl+sdf.caravel_user_project +++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -1,6 +1,7 @@ // Caravel user project includes -$USER_PROJECT_VERILOG/gl/user_project_wrapper.v +$USER_PROJECT_VERILOG/gl/user_project_wrapper.v $USER_PROJECT_VERILOG/gl/user_proj_example.v -$USER_PROJECT_VERILOG/gl/user_adder.v -$USER_PROJECT_VERILOG/gl/btc_miner_top.v -$USER_PROJECT_VERILOG/gl/sha256.v +$USER_PROJECT_VERILOG/gl/sha1_top.v +$USER_PROJECT_VERILOG/gl/sha1.v +$USER_PROJECT_VERILOG/gl/sha1_core.v +$USER_PROJECT_VERILOG/gl/sha1_w_mem.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index 49c3fc0..2ea593f 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,6 +1,7 @@ -# Caravel user project includes --v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v +# Caravel user project includes +-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v -v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v --v $(USER_PROJECT_VERILOG)/gl/user_adder.v --v $(USER_PROJECT_VERILOG)/gl/btc_miner_top.v --v $(USER_PROJECT_VERILOG)/gl/sha256.v +-v $(USER_PROJECT_VERILOG)/gl/sha1_top.v +-v $(USER_PROJECT_VERILOG)/gl/sha1.v +-v $(USER_PROJECT_VERILOG)/gl/sha1_core.v +-v $(USER_PROJECT_VERILOG)/gl/sha1_w_mem.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 46e42c0..ea5e383 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,6 +1,7 @@ # Caravel user project includes --v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v +-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v --v $(USER_PROJECT_VERILOG)/rtl/user_adder.v --v $(USER_PROJECT_VERILOG)/rtl/btc_miner_top.v --v $(USER_PROJECT_VERILOG)/rtl/sha256.v +-v $(USER_PROJECT_VERILOG)/rtl/sha1_top.v +-v $(USER_PROJECT_VERILOG)/rtl/sha1.v +-v $(USER_PROJECT_VERILOG)/rtl/sha1_core.v +-v $(USER_PROJECT_VERILOG)/rtl/sha1_w_mem.v
diff --git a/verilog/rtl/sha1.v b/verilog/rtl/sha1.v new file mode 100644 index 0000000..ac8e940 --- /dev/null +++ b/verilog/rtl/sha1.v
@@ -0,0 +1,244 @@ +//====================================================================== +// +// sha1.v +// ------ +// Top level wrapper for the SHA-1 hash function providing +// a simple memory like interface with 32 bit data access. +// +// +// Author: Joachim Strombergson +// Copyright (c) 2013 Secworks Sweden AB +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +`default_nettype none + +module sha1( + // Clock and reset. + input wire clk, + input wire reset_n, + + // Control. + input wire cs, + input wire we, + + // Data ports. + input wire [7 : 0] address, + input wire [31 : 0] write_data, + output wire [31 : 0] read_data, + output wire error + ); + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + localparam ADDR_NAME0 = 8'h00; + localparam ADDR_NAME1 = 8'h01; + localparam ADDR_VERSION = 8'h02; + + localparam ADDR_CTRL = 8'h08; + localparam CTRL_INIT_BIT = 0; + localparam CTRL_NEXT_BIT = 1; + + localparam ADDR_STATUS = 8'h09; + localparam STATUS_READY_BIT = 0; + localparam STATUS_VALID_BIT = 1; + + localparam ADDR_BLOCK0 = 8'h10; + localparam ADDR_BLOCK15 = 8'h1f; + + localparam ADDR_DIGEST0 = 8'h20; + localparam ADDR_DIGEST4 = 8'h24; + + localparam CORE_NAME0 = 32'h73686131; // "sha1" + localparam CORE_NAME1 = 32'h20202020; // " " + localparam CORE_VERSION = 32'h302e3630; // "0.60" + + + //---------------------------------------------------------------- + // Registers including update variables and write enable. + //---------------------------------------------------------------- + reg init_reg; + reg init_new; + + reg next_reg; + reg next_new; + + reg ready_reg; + + reg [31 : 0] block_reg [0 : 15]; + reg block_we; + + reg [159 : 0] digest_reg; + + reg digest_valid_reg; + + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + wire core_ready; + wire [511 : 0] core_block; + wire [159 : 0] core_digest; + wire core_digest_valid; + + reg [31 : 0] tmp_read_data; + reg tmp_error; + + + //---------------------------------------------------------------- + // Concurrent connectivity for ports etc. + //---------------------------------------------------------------- + assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03], + block_reg[04], block_reg[05], block_reg[06], block_reg[07], + block_reg[08], block_reg[09], block_reg[10], block_reg[11], + block_reg[12], block_reg[13], block_reg[14], block_reg[15]}; + + assign read_data = tmp_read_data; + assign error = tmp_error; + + + //---------------------------------------------------------------- + // core instantiation. + //---------------------------------------------------------------- + sha1_core core( + .clk(clk), + .reset_n(reset_n), + + .init(init_reg), + .next(next_reg), + + .block(core_block), + + .ready(core_ready), + + .digest(core_digest), + .digest_valid(core_digest_valid) + ); + + + //---------------------------------------------------------------- + // reg_update + // Update functionality for all registers in the core. + // All registers are positive edge triggered with + // asynchronous active low reset. + //---------------------------------------------------------------- + always @ (posedge clk or negedge reset_n) + begin : reg_update + integer i; + + if (!reset_n) + begin + init_reg <= 1'h0; + next_reg <= 1'h0; + ready_reg <= 1'h0; + digest_reg <= 160'h0; + digest_valid_reg <= 1'h0; + + for (i = 0 ; i < 16 ; i = i + 1) + block_reg[i] <= 32'h0; + end + else + begin + ready_reg <= core_ready; + digest_valid_reg <= core_digest_valid; + init_reg <= init_new; + next_reg <= next_new; + + if (block_we) + block_reg[address[3 : 0]] <= write_data; + + if (core_digest_valid) + digest_reg <= core_digest; + end + end // reg_update + + //---------------------------------------------------------------- + // api + // + // The interface command decoding logic. + //---------------------------------------------------------------- + always @* + begin : api + init_new = 1'h0; + next_new = 1'h0; + block_we = 1'h0; + tmp_read_data = 32'h0; + tmp_error = 1'h0; + + if (cs) + begin + if (we) + begin + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) + block_we = 1'h1; + + if (address == ADDR_CTRL) + begin + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + end + end // if (write_read) + else + begin + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) + tmp_read_data = block_reg[address[3 : 0]]; + + if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4)) + tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32]; + + case (address) + // Read operations. + ADDR_NAME0: + tmp_read_data = CORE_NAME0; + + ADDR_NAME1: + tmp_read_data = CORE_NAME1; + + ADDR_VERSION: + tmp_read_data = CORE_VERSION; + + ADDR_CTRL: + tmp_read_data = {30'h0, next_reg, init_reg}; + + ADDR_STATUS: + tmp_read_data = {30'h0, digest_valid_reg, ready_reg}; + + default: + begin + tmp_error = 1'h1; + end + endcase // case (addr) + end + end + end // addr_decoder +endmodule // sha1 + +//====================================================================== +// EOF sha1.v +//======================================================================
diff --git a/verilog/rtl/sha1_core.v b/verilog/rtl/sha1_core.v new file mode 100644 index 0000000..8b8eeaf --- /dev/null +++ b/verilog/rtl/sha1_core.v
@@ -0,0 +1,433 @@ +//====================================================================== +// +// sha1_core.v +// ----------- +// Verilog 2001 implementation of the SHA-1 hash function. +// This is the internal core with wide interfaces. +// +// +// Copyright (c) 2013 Secworks Sweden AB +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +`default_nettype none + +module sha1_core( + input wire clk, + input wire reset_n, + + input wire init, + input wire next, + + input wire [511 : 0] block, + + output wire ready, + + output wire [159 : 0] digest, + output wire digest_valid + ); + + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter H0_0 = 32'h67452301; + parameter H0_1 = 32'hefcdab89; + parameter H0_2 = 32'h98badcfe; + parameter H0_3 = 32'h10325476; + parameter H0_4 = 32'hc3d2e1f0; + + parameter SHA1_ROUNDS = 79; + + parameter CTRL_IDLE = 0; + parameter CTRL_ROUNDS = 1; + parameter CTRL_DONE = 2; + + + //---------------------------------------------------------------- + // Registers including update variables and write enable. + //---------------------------------------------------------------- + reg [31 : 0] a_reg; + reg [31 : 0] a_new; + reg [31 : 0] b_reg; + reg [31 : 0] b_new; + reg [31 : 0] c_reg; + reg [31 : 0] c_new; + reg [31 : 0] d_reg; + reg [31 : 0] d_new; + reg [31 : 0] e_reg; + reg [31 : 0] e_new; + reg a_e_we; + + reg [31 : 0] H0_reg; + reg [31 : 0] H0_new; + reg [31 : 0] H1_reg; + reg [31 : 0] H1_new; + reg [31 : 0] H2_reg; + reg [31 : 0] H2_new; + reg [31 : 0] H3_reg; + reg [31 : 0] H3_new; + reg [31 : 0] H4_reg; + reg [31 : 0] H4_new; + reg H_we; + + reg [6 : 0] round_ctr_reg; + reg [6 : 0] round_ctr_new; + reg round_ctr_we; + reg round_ctr_inc; + reg round_ctr_rst; + + reg digest_valid_reg; + reg digest_valid_new; + reg digest_valid_we; + + reg [1 : 0] sha1_ctrl_reg; + reg [1 : 0] sha1_ctrl_new; + reg sha1_ctrl_we; + + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + reg digest_init; + reg digest_update; + reg state_init; + reg state_update; + reg first_block; + reg ready_flag; + reg w_init; + reg w_next; + wire [31 : 0] w; + + + //---------------------------------------------------------------- + // Module instantiantions. + //---------------------------------------------------------------- + sha1_w_mem w_mem_inst( + .clk(clk), + .reset_n(reset_n), + + .block(block), + + .init(w_init), + .next(w_next), + + .w(w) + ); + + + //---------------------------------------------------------------- + // Concurrent connectivity for ports etc. + //---------------------------------------------------------------- + assign ready = ready_flag; + assign digest = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg}; + assign digest_valid = digest_valid_reg; + + + //---------------------------------------------------------------- + // reg_update + // Update functionality for all registers in the core. + // All registers are positive edge triggered with + // asynchronous active low reset. + //---------------------------------------------------------------- + always @ (posedge clk or negedge reset_n) + begin : reg_update + if (!reset_n) + begin + a_reg <= 32'h0; + b_reg <= 32'h0; + c_reg <= 32'h0; + d_reg <= 32'h0; + e_reg <= 32'h0; + H0_reg <= 32'h0; + H1_reg <= 32'h0; + H2_reg <= 32'h0; + H3_reg <= 32'h0; + H4_reg <= 32'h0; + digest_valid_reg <= 1'h0; + round_ctr_reg <= 7'h0; + sha1_ctrl_reg <= CTRL_IDLE; + end + else + begin + if (a_e_we) + begin + a_reg <= a_new; + b_reg <= b_new; + c_reg <= c_new; + d_reg <= d_new; + e_reg <= e_new; + end + + if (H_we) + begin + H0_reg <= H0_new; + H1_reg <= H1_new; + H2_reg <= H2_new; + H3_reg <= H3_new; + H4_reg <= H4_new; + end + + if (round_ctr_we) + round_ctr_reg <= round_ctr_new; + + if (digest_valid_we) + digest_valid_reg <= digest_valid_new; + + if (sha1_ctrl_we) + sha1_ctrl_reg <= sha1_ctrl_new; + end + end // reg_update + + + //---------------------------------------------------------------- + // digest_logic + // + // The logic needed to init as well as update the digest. + //---------------------------------------------------------------- + always @* + begin : digest_logic + H0_new = 32'h0; + H1_new = 32'h0; + H2_new = 32'h0; + H3_new = 32'h0; + H4_new = 32'h0; + H_we = 0; + + if (digest_init) + begin + H0_new = H0_0; + H1_new = H0_1; + H2_new = H0_2; + H3_new = H0_3; + H4_new = H0_4; + H_we = 1; + end + + if (digest_update) + begin + H0_new = H0_reg + a_reg; + H1_new = H1_reg + b_reg; + H2_new = H2_reg + c_reg; + H3_new = H3_reg + d_reg; + H4_new = H4_reg + e_reg; + H_we = 1; + end + end // digest_logic + + + //---------------------------------------------------------------- + // state_logic + // + // The logic needed to init as well as update the state during + // round processing. + //---------------------------------------------------------------- + always @* + begin : state_logic + reg [31 : 0] a5; + reg [31 : 0] f; + reg [31 : 0] k; + reg [31 : 0] t; + + a5 = 32'h0; + f = 32'h0; + k = 32'h0; + t = 32'h0; + a_new = 32'h0; + b_new = 32'h0; + c_new = 32'h0; + d_new = 32'h0; + e_new = 32'h0; + a_e_we = 1'h0; + + if (state_init) + begin + if (first_block) + begin + a_new = H0_0; + b_new = H0_1; + c_new = H0_2; + d_new = H0_3; + e_new = H0_4; + a_e_we = 1; + end + else + begin + a_new = H0_reg; + b_new = H1_reg; + c_new = H2_reg; + d_new = H3_reg; + e_new = H4_reg; + a_e_we = 1; + end + end + + if (state_update) + begin + if (round_ctr_reg <= 19) + begin + k = 32'h5a827999; + f = ((b_reg & c_reg) ^ (~b_reg & d_reg)); + end + else if ((round_ctr_reg >= 20) && (round_ctr_reg <= 39)) + begin + k = 32'h6ed9eba1; + f = b_reg ^ c_reg ^ d_reg; + end + else if ((round_ctr_reg >= 40) && (round_ctr_reg <= 59)) + begin + k = 32'h8f1bbcdc; + f = ((b_reg | c_reg) ^ (b_reg | d_reg) ^ (c_reg | d_reg)); + end + else if (round_ctr_reg >= 60) + begin + k = 32'hca62c1d6; + f = b_reg ^ c_reg ^ d_reg; + end + + a5 = {a_reg[26 : 0], a_reg[31 : 27]}; + t = a5 + e_reg + f + k + w; + + a_new = t; + b_new = a_reg; + c_new = {b_reg[1 : 0], b_reg[31 : 2]}; + d_new = c_reg; + e_new = d_reg; + a_e_we = 1; + end + end // state_logic + + + //---------------------------------------------------------------- + // round_ctr + // + // Update logic for the round counter, a monotonically + // increasing counter with reset. + //---------------------------------------------------------------- + always @* + begin : round_ctr + round_ctr_new = 7'h0; + round_ctr_we = 1'h0; + + if (round_ctr_rst) + begin + round_ctr_new = 7'h0; + round_ctr_we = 1'h1; + end + + if (round_ctr_inc) + begin + round_ctr_new = round_ctr_reg + 1'h1; + round_ctr_we = 1; + end + end // round_ctr + + + //---------------------------------------------------------------- + // sha1_ctrl_fsm + // Logic for the state machine controlling the core behaviour. + //---------------------------------------------------------------- + always @* + begin : sha1_ctrl_fsm + digest_init = 1'h0; + digest_update = 1'h0; + state_init = 1'h0; + state_update = 1'h0; + first_block = 1'h0; + ready_flag = 1'h0; + w_init = 1'h0; + w_next = 1'h0; + round_ctr_inc = 1'h0; + round_ctr_rst = 1'h0; + digest_valid_new = 1'h0; + digest_valid_we = 1'h0; + sha1_ctrl_new = CTRL_IDLE; + sha1_ctrl_we = 1'h0; + + case (sha1_ctrl_reg) + CTRL_IDLE: + begin + ready_flag = 1; + + if (init) + begin + digest_init = 1'h1; + w_init = 1'h1; + state_init = 1'h1; + first_block = 1'h1; + round_ctr_rst = 1'h1; + digest_valid_new = 1'h0; + digest_valid_we = 1'h1; + sha1_ctrl_new = CTRL_ROUNDS; + sha1_ctrl_we = 1'h1; + end + + if (next) + begin + w_init = 1'h1; + state_init = 1'h1; + round_ctr_rst = 1'h1; + digest_valid_new = 1'h0; + digest_valid_we = 1'h1; + sha1_ctrl_new = CTRL_ROUNDS; + sha1_ctrl_we = 1'h1; + end + end + + + CTRL_ROUNDS: + begin + state_update = 1'h1; + round_ctr_inc = 1'h1; + w_next = 1'h1; + + if (round_ctr_reg == SHA1_ROUNDS) + begin + sha1_ctrl_new = CTRL_DONE; + sha1_ctrl_we = 1'h1; + end + end + + + CTRL_DONE: + begin + digest_update = 1'h1; + digest_valid_new = 1'h1; + digest_valid_we = 1'h1; + sha1_ctrl_new = CTRL_IDLE; + sha1_ctrl_we = 1'h1; + end + endcase // case (sha1_ctrl_reg) + end // sha1_ctrl_fsm + +endmodule // sha1_core + +//====================================================================== +// EOF sha1_core.v +//======================================================================
diff --git a/verilog/rtl/sha1_top.v b/verilog/rtl/sha1_top.v new file mode 100644 index 0000000..31601b4 --- /dev/null +++ b/verilog/rtl/sha1_top.v
@@ -0,0 +1,386 @@ +// TODO edit btc_miner_top to suit sha1 spec. + +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * sha1_top + * TODO! + * + * A top wrapper for controlling the SHA 1 HW accelerator + * + *------------------------------------------------------------- + */ + +module sha1_top #( + parameter BITS = 32 +)( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb, + + // IRQ + output [2:0] irq +); + wire clk; + wire rst; + + wire [`MPRJ_IO_PADS-1:0] io_in; + wire [`MPRJ_IO_PADS-1:0] io_out; + wire [`MPRJ_IO_PADS-1:0] io_oeb; + + // WB wires + wire [31:0] rdata; + wire [31:0] wdata; + + wire valid; + wire [3:0] wstrb; + + // LA wires + wire [31:0] la_write0; + wire [31:0] la_write1; + wire [31:0] la_write2; + wire [31:0] la_write3; + + // SHA module variables + wire o_error; + wire o_idle; + wire o_sha_cs; + wire o_sha_we; + wire [7:0] o_sha_address; + wire [BITS-1:0] o_sha_read_data; + + // TODO use top 32-bits of LA to control muxing and other variables like starting state machine + wire [5:0] la_sel; + assign la_sel = la_data_in[127:122]; + wire [75:0] la_data_out_w; + + // WB MI A + assign valid = wbs_cyc_i && wbs_stb_i; + assign wstrb = wbs_sel_i & {4{wbs_we_i}}; + assign wbs_dat_o = rdata; + assign wdata = wbs_dat_i; + + // IO + assign io_out = rdata; + assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; + + // IRQ + assign irq = 3'b000; // TODO? could use it to signal when ready or done with sha + + // Assuming LA probes [31:0] (aka: la_write0) are for controlling the nonce register. + // * NOTE: These are used as a mask for the la_data_in[?:?] + assign la_write0 = ~la_oenb[31:0] & ~{BITS{valid}}; + assign la_write1 = ~la_oenb[63:32] & ~{BITS{valid}}; + assign la_write2 = ~la_oenb[95:64] & ~{BITS{valid}}; + assign la_write3 = ~la_oenb[127:96] & ~{BITS{valid}}; + + assign la_data_out_w = {o_idle, o_error, o_sha_we, o_sha_cs, o_sha_address, o_sha_read_data, rdata}; + + // Assuming LA probes [111:110] are for controlling the reset & clock + assign clk = (~la_oenb[110]) ? la_data_in[110] : wb_clk_i; + assign rst = (~la_oenb[111]) ? la_data_in[111] : wb_rst_i; + + // TODO more LA muxing + assign la_data_out = (la_sel == 6'b000000) ? {{52{1'b0}}, la_data_out_w} : ((la_sel == 6'b000001) ? {{52{1'b0}}, la_data_out_w} : {{52{1'b0}}, la_data_out_w}); + // always @(clk || la_data_in || la_oenb || la_sel || la_data_out_w) begin + // if (rst) begin + // la_data_out <= 0; + // end else begin + // case (la_sel) + // 6'b000000: + // la_data_out <= {{52{1'b0}}, la_data_out_w}; + + // default: + // begin + // la_data_out <= {{52{1'b0}}, la_data_out_w}; + // end + // endcase + // end + // end + + // module for controlling the sha module + sha1_ctrl #( + .BITS(BITS) + ) sha1_ctrl_inst( + .clk(clk), + .rst(rst), + .valid(valid), + .wb_wr_mask(wstrb), + .wdata(wbs_dat_i), + .la_write3(la_write3), + .la_input3(la_data_in[127:96]), + .rdata(rdata), + .ready(wbs_ack_o), + .error(o_error), + .idle(o_idle), + .reg_sha_cs(o_sha_cs), + .reg_sha_we(o_sha_we), + .sha_address(o_sha_address), + .sha_read_data(o_sha_read_data) + ); + +endmodule // sha1_top + + +// sha1_ctrl +module sha1_ctrl #( + parameter BITS = 32 +)( + input wire clk, + input wire rst, + input wire valid, + input wire [3:0] wb_wr_mask, + input wire [BITS-1:0] wdata, + input wire [BITS-1:0] la_write3, + input wire [BITS-1:0] la_input3, + output reg [BITS-1:0] rdata, + output reg ready, + output wire error, + output wire idle, + output reg reg_sha_cs, + output reg reg_sha_we, + output wire [7:0] sha_address, + output wire [BITS-1:0] sha_read_data // output from sha1 +); + + // sha1 internal constants and parameters + localparam ADDR_NAME0 = 8'h00; + localparam ADDR_NAME1 = 8'h01; + localparam ADDR_VERSION = 8'h02; + + localparam ADDR_CTRL = 8'h08; + localparam CTRL_INIT_BIT = 0; + localparam CTRL_NEXT_BIT = 1; + + localparam ADDR_STATUS = 8'h09; + localparam STATUS_READY_BIT = 0; + localparam STATUS_VALID_BIT = 1; + + localparam ADDR_BLOCK0 = 8'h10; + localparam ADDR_BLOCK15 = 8'h1f; + + localparam ADDR_DIGEST0 = 8'h20; + localparam ADDR_DIGEST4 = 8'h24; + + localparam CORE_NAME0 = 32'h73686131; // "sha1" + localparam CORE_NAME1 = 32'h20202020; // " " + localparam CORE_VERSION = 32'h302e3630; // "0.60" + + // enum logic [1:0] {WAIT_IN=2'b00, READ_IN=2'b01, WAIT_COMPUTE=2'b10, CHECK=2'b11, WRITE_OUT=} state; + // enum integer unsigned {WAIT_IN=0, READ_IN=1, WAIT_COMPUTE=2, INCR_NONCE=3, WRITE_OUT=4} state; + localparam WAIT_IN=0, READ_IN=1, WRITE_CTRL=2, WAIT_COMPUTE=3, WRITE_OUT=4; + + reg [2:0] state; + + wire start_ctrl; + wire sha_cs; + wire sha_we; + reg [7:0] reg_sha_address; + + // sha_mode, sha_next, sha_init. Map to ADDR_CTRL register [2:0] + wire [1:0] sha_ctrl_bits; + wire read_status_flag; + + reg [BITS-1:0] sha_write_data; // input to sha1 + + wire sha_in_ready; + wire sha_digest_valid; + wire auto_ctrl; + + assign idle = (state == WAIT_IN) ? 1'b1 : 1'b0; + + // * la_write is 0 when valid is 1 !! + // assign start_ctrl = la_input3[10] & la_write3[10]; + assign start_ctrl = la_input3[10]; + + // automated and manual control + assign read_status_flag = sha_cs && !sha_we && (sha_address == ADDR_STATUS); + assign sha_in_ready = read_status_flag ? sha_read_data[STATUS_READY_BIT] : 1'b0; + assign sha_digest_valid = read_status_flag ? sha_read_data[STATUS_VALID_BIT] : 1'b0; + + // assign auto_ctrl = la_input3[11] & la_write3[11]; + assign auto_ctrl = la_input3[11]; + + // assign sha_cs = auto_ctrl ? reg_sha_cs : (la_input3[8] & la_write3[8]); + // assign sha_we = auto_ctrl ? reg_sha_we : (la_input3[9] & la_write3[9]); + // assign sha_address = auto_ctrl ? reg_sha_address : (la_input3[7:0] & la_write3[7:0]); + // assign sha_ctrl_bits = la_input3[17:16] & la_write3[17:16]; + assign sha_cs = auto_ctrl ? reg_sha_cs : la_input3[8]; + assign sha_we = auto_ctrl ? reg_sha_we : la_input3[9]; + assign sha_address = auto_ctrl ? reg_sha_address : la_input3[7:0]; + assign sha_ctrl_bits = la_input3[17:16]; + + + always @(posedge clk) begin + if (rst) begin + rdata <= 0; + ready <= 0; + reg_sha_cs <= 0; + reg_sha_we <= 0; + reg_sha_address <= 0; + sha_write_data <= 0; + state <= WAIT_IN; + end else if (auto_ctrl) begin + ready <= 1'b0; + + // state machine for controlling SHA module and I/O + case (state) + WAIT_IN: begin + // wait for LA start input and for sha module to be ready + reg_sha_cs <= 1'b1; + reg_sha_we <= 1'b0; + reg_sha_address <= ADDR_STATUS; + + if (start_ctrl && sha_in_ready) begin + reg_sha_cs <= 1'b1; + reg_sha_we <= 1'b1; + state <= READ_IN; + end + end + + READ_IN: begin + // read in 512-bit input to sha module through WB + reg_sha_cs <= 1'b1; + reg_sha_we <= 1'b1; + + if (valid && !ready) begin + ready <= 1'b1; + sha_write_data <= wdata; + + if (wb_wr_mask == 4'b1111) begin + // read up to the last address + if (sha_address == ADDR_BLOCK14) begin + // new addr will be ADDR_BLOCK15 + reg_sha_address <= reg_sha_address + 1; + state <= WRITE_CTRL; + end else begin + // check if 1st write coming from WAIT_IN + if (sha_address == ADDR_STATUS) begin + reg_sha_address <= ADDR_BLOCK0; + end else begin + reg_sha_address <= reg_sha_address + 1; + end + end + end + + end + end + + WRITE_CTRL: begin + // write sha control register according to LA + reg_sha_cs <= 1'b1; + reg_sha_address <= ADDR_CTRL; + sha_write_data <= {{(BITS-2){1'b0}}, {sha_ctrl_bits}}; + + // write and read back to ensure CTRL is set + if (reg_sha_we == 1'b0) begin + if (sha_read_data[1:0] == sha_ctrl_bits) begin + state <= WAIT_COMPUTE; + end else begin + reg_sha_we <= 1'b1; + end + end else begin + reg_sha_we <= 1'b0; + end + end + + WAIT_COMPUTE: begin + // read status register to determine when done + reg_sha_cs <= 1'b1; + reg_sha_we <= 1'b0; + reg_sha_address <= ADDR_STATUS; + + if (sha_digest_valid) begin + reg_sha_address <= ADDR_DIGEST0; + state <= WRITE_OUT; + end + end + + WRITE_OUT: begin + // write valid 256-bit digest to WB + reg_sha_cs <= 1'b1; + reg_sha_we <= 1'b0; + + if (valid && !ready) begin + ready <= 1'b1; + + // Place output hash on wishbone + if (wb_wr_mask == 4'b0000) begin + rdata <= sha_read_data; + + if (sha_address == ADDR_DIGEST4) begin + reg_sha_address <= ADDR_STATUS; + state <= WAIT_IN; + end else begin + reg_sha_address <= reg_sha_address + 1; + end + end + end + end + + endcase + end else begin + // TODO? not automated control. FW controls all wr/rd and addresses and needs to look at LA + if (sha_address == ADDR_CTRL) begin + sha_write_data <= {{(BITS-2){1'b0}}, {sha_ctrl_bits}}; + end else begin + sha_write_data <= wdata; + end + end + + end + + sha1 sha1_inst0( + .clk(clk), + .reset_n(~rst), + .cs(sha_cs), + .we(sha_we), + .address(sha_address), // 8-bit address + .write_data(sha_write_data), // 32-bit reg input + .read_data(sha_read_data), // 32-bit output + .error(error) // 1-bit output + ); + +endmodule // sha1_ctrl + +`default_nettype wire +
diff --git a/verilog/rtl/sha1_w_mem.v b/verilog/rtl/sha1_w_mem.v new file mode 100644 index 0000000..77e1c24 --- /dev/null +++ b/verilog/rtl/sha1_w_mem.v
@@ -0,0 +1,265 @@ +//====================================================================== +// +// sha1_w_mem_reg.v +// ----------------- +// The SHA-1 W memory. This memory includes functionality to +// expand the block into 80 words. +// +// +// Copyright (c) 2013 Secworks Sweden AB +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +`default_nettype none + +module sha1_w_mem( + input wire clk, + input wire reset_n, + + input wire [511 : 0] block, + + input wire init, + input wire next, + + output wire [31 : 0] w + ); + + + //---------------------------------------------------------------- + // Registers including update variables and write enable. + //---------------------------------------------------------------- + reg [31 : 0] w_mem [0 : 15]; + reg [31 : 0] w_mem00_new; + reg [31 : 0] w_mem01_new; + reg [31 : 0] w_mem02_new; + reg [31 : 0] w_mem03_new; + reg [31 : 0] w_mem04_new; + reg [31 : 0] w_mem05_new; + reg [31 : 0] w_mem06_new; + reg [31 : 0] w_mem07_new; + reg [31 : 0] w_mem08_new; + reg [31 : 0] w_mem09_new; + reg [31 : 0] w_mem10_new; + reg [31 : 0] w_mem11_new; + reg [31 : 0] w_mem12_new; + reg [31 : 0] w_mem13_new; + reg [31 : 0] w_mem14_new; + reg [31 : 0] w_mem15_new; + reg w_mem_we; + + reg [6 : 0] w_ctr_reg; + reg [6 : 0] w_ctr_new; + reg w_ctr_we; + + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + reg [31 : 0] w_tmp; + reg [31 : 0] w_new; + + + //---------------------------------------------------------------- + // Concurrent connectivity for ports etc. + //---------------------------------------------------------------- + assign w = w_tmp; + + + //---------------------------------------------------------------- + // reg_update + // + // Update functionality for all registers in the core. + // All registers are positive edge triggered with + // asynchronous active low reset. + //---------------------------------------------------------------- + always @ (posedge clk or negedge reset_n) + begin : reg_update + integer i; + + if (!reset_n) + begin + for (i = 0 ; i < 16 ; i = i + 1) + w_mem[i] <= 32'h0; + + w_ctr_reg <= 7'h0; + end + else + begin + if (w_mem_we) + begin + w_mem[00] <= w_mem00_new; + w_mem[01] <= w_mem01_new; + w_mem[02] <= w_mem02_new; + w_mem[03] <= w_mem03_new; + w_mem[04] <= w_mem04_new; + w_mem[05] <= w_mem05_new; + w_mem[06] <= w_mem06_new; + w_mem[07] <= w_mem07_new; + w_mem[08] <= w_mem08_new; + w_mem[09] <= w_mem09_new; + w_mem[10] <= w_mem10_new; + w_mem[11] <= w_mem11_new; + w_mem[12] <= w_mem12_new; + w_mem[13] <= w_mem13_new; + w_mem[14] <= w_mem14_new; + w_mem[15] <= w_mem15_new; + end + + if (w_ctr_we) + w_ctr_reg <= w_ctr_new; + end + end // reg_update + + + //---------------------------------------------------------------- + // select_w + // + // W word selection logic. Returns either directly from the + // memory or the next w value calculated. + //---------------------------------------------------------------- + always @* + begin : select_w + if (w_ctr_reg < 16) + w_tmp = w_mem[w_ctr_reg[3 : 0]]; + else + w_tmp = w_new; + end // select_w + + + //---------------------------------------------------------------- + // w_mem_update_logic + // + // Update logic for the W memory. This is where the scheduling + // based on a sliding window is implemented. + //---------------------------------------------------------------- + always @* + begin : w_mem_update_logic + reg [31 : 0] w_0; + reg [31 : 0] w_2; + reg [31 : 0] w_8; + reg [31 : 0] w_13; + reg [31 : 0] w_16; + + w_mem00_new = 32'h0; + w_mem01_new = 32'h0; + w_mem02_new = 32'h0; + w_mem03_new = 32'h0; + w_mem04_new = 32'h0; + w_mem05_new = 32'h0; + w_mem06_new = 32'h0; + w_mem07_new = 32'h0; + w_mem08_new = 32'h0; + w_mem09_new = 32'h0; + w_mem10_new = 32'h0; + w_mem11_new = 32'h0; + w_mem12_new = 32'h0; + w_mem13_new = 32'h0; + w_mem14_new = 32'h0; + w_mem15_new = 32'h0; + w_mem_we = 1'h0; + + w_0 = w_mem[0]; + w_2 = w_mem[2]; + w_8 = w_mem[8]; + w_13 = w_mem[13]; + w_16 = w_13 ^ w_8 ^ w_2 ^ w_0; + w_new = {w_16[30 : 0], w_16[31]}; + + if (init) + begin + w_mem00_new = block[511 : 480]; + w_mem01_new = block[479 : 448]; + w_mem02_new = block[447 : 416]; + w_mem03_new = block[415 : 384]; + w_mem04_new = block[383 : 352]; + w_mem05_new = block[351 : 320]; + w_mem06_new = block[319 : 288]; + w_mem07_new = block[287 : 256]; + w_mem08_new = block[255 : 224]; + w_mem09_new = block[223 : 192]; + w_mem10_new = block[191 : 160]; + w_mem11_new = block[159 : 128]; + w_mem12_new = block[127 : 96]; + w_mem13_new = block[95 : 64]; + w_mem14_new = block[63 : 32]; + w_mem15_new = block[31 : 0]; + w_mem_we = 1'h1; + end + + if (next && (w_ctr_reg > 15)) + begin + w_mem00_new = w_mem[01]; + w_mem01_new = w_mem[02]; + w_mem02_new = w_mem[03]; + w_mem03_new = w_mem[04]; + w_mem04_new = w_mem[05]; + w_mem05_new = w_mem[06]; + w_mem06_new = w_mem[07]; + w_mem07_new = w_mem[08]; + w_mem08_new = w_mem[09]; + w_mem09_new = w_mem[10]; + w_mem10_new = w_mem[11]; + w_mem11_new = w_mem[12]; + w_mem12_new = w_mem[13]; + w_mem13_new = w_mem[14]; + w_mem14_new = w_mem[15]; + w_mem15_new = w_new; + w_mem_we = 1'h1; + end + end // w_mem_update_logic + + + //---------------------------------------------------------------- + // w_ctr + // + // W schedule adress counter. Counts from 0x10 to 0x3f and + // is used to expand the block into words. + //---------------------------------------------------------------- + always @* + begin : w_ctr + w_ctr_new = 7'h0; + w_ctr_we = 1'h0; + + if (init) + begin + w_ctr_new = 7'h0; + w_ctr_we = 1'h1; + end + + if (next) + begin + w_ctr_new = w_ctr_reg + 7'h01; + w_ctr_we = 1'h1; + end + end // w_ctr +endmodule // sha1_w_mem + +//====================================================================== +// sha1_w_mem.v +//======================================================================
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 3d60902..e04d5ad 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -82,38 +82,38 @@ /* User project is instantiated here */ /*--------------------------------------*/ -// user_proj_example mprj ( -// `ifdef USE_POWER_PINS -// .vccd1(vccd1), // User area 1 1.8V power -// .vssd1(vssd1), // User area 1 digital ground -// `endif +user_proj_example mprj ( +`ifdef USE_POWER_PINS + .vccd1(vccd1), // User area 1 1.8V power + .vssd1(vssd1), // User area 1 digital ground +`endif -// .wb_clk_i(wb_clk_i), -// .wb_rst_i(wb_rst_i), + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), -// // MGMT SoC Wishbone Slave -// .wbs_cyc_i(wbs_cyc_i), -// .wbs_stb_i(wbs_stb_i), -// .wbs_we_i(wbs_we_i), -// .wbs_sel_i(wbs_sel_i), -// .wbs_adr_i(wbs_adr_i), -// .wbs_dat_i(wbs_dat_i), -// .wbs_ack_o(wbs_ack_o), -// .wbs_dat_o(wbs_dat_o), + // MGMT SoC Wishbone Slave + .wbs_cyc_i(wbs_cyc_i), + .wbs_stb_i(wbs_stb_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o), + .wbs_dat_o(wbs_dat_o), -// // Logic Analyzer -// .la_data_in(la_data_in), -// .la_data_out(la_data_out), -// .la_oenb (la_oenb), + // Logic Analyzer + .la_data_in(la_data_in), + .la_data_out(la_data_out), + .la_oenb (la_oenb), -// // IO Pads -// .io_in (io_in), -// .io_out(io_out), -// .io_oeb(io_oeb), + // IO Pads + .io_in (io_in), + .io_out(io_out), + .io_oeb(io_oeb), -// // IRQ -// .irq(user_irq) -// ); + // IRQ + .irq(user_irq) +); // user_adder uaddr ( // `ifdef USE_POWER_PINS @@ -148,38 +148,72 @@ // ); +// top level Bitcoin miner module +// btc_miner_top btc_miner_top_inst ( +// `ifdef USE_POWER_PINS +// .vccd1(vccd1), // User area 1 1.8V power +// .vssd1(vssd1), // User area 1 digital ground +// `endif +// .wb_clk_i(wb_clk_i), +// .wb_rst_i(wb_rst_i), + +// // MGMT SoC Wishbone Slave +// .wbs_stb_i(wbs_stb_i), +// .wbs_cyc_i(wbs_cyc_i), +// .wbs_we_i(wbs_we_i), +// .wbs_sel_i(wbs_sel_i), +// .wbs_dat_i(wbs_dat_i), +// .wbs_adr_i(wbs_adr_i), +// .wbs_ack_o(wbs_ack_o), +// .wbs_dat_o(wbs_dat_o), + +// // Logic Analyzer +// .la_data_in(la_data_in), +// .la_data_out(la_data_out), +// .la_oenb (la_oenb), + +// // IO Pads +// .io_in (io_in), +// .io_out(io_out), +// .io_oeb(io_oeb), + +// // IRQ +// .irq(user_irq) +// ); + + // top level SHA module -btc_miner_top btc_miner_top_inst ( - `ifdef USE_POWER_PINS - .vccd1(vccd1), // User area 1 1.8V power - .vssd1(vssd1), // User area 1 digital ground -`endif - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), +// sha1_top sha1_top_inst ( +// `ifdef USE_POWER_PINS +// .vccd1(vccd1), // User area 1 1.8V power +// .vssd1(vssd1), // User area 1 digital ground +// `endif +// .wb_clk_i(wb_clk_i), +// .wb_rst_i(wb_rst_i), - // MGMT SoC Wishbone Slave - .wbs_stb_i(wbs_stb_i), - .wbs_cyc_i(wbs_cyc_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_dat_i(wbs_dat_i), - .wbs_adr_i(wbs_adr_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), +// // MGMT SoC Wishbone Slave +// .wbs_stb_i(wbs_stb_i), +// .wbs_cyc_i(wbs_cyc_i), +// .wbs_we_i(wbs_we_i), +// .wbs_sel_i(wbs_sel_i), +// .wbs_dat_i(wbs_dat_i), +// .wbs_adr_i(wbs_adr_i), +// .wbs_ack_o(wbs_ack_o), +// .wbs_dat_o(wbs_dat_o), - // Logic Analyzer - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), +// // Logic Analyzer +// .la_data_in(la_data_in), +// .la_data_out(la_data_out), +// .la_oenb (la_oenb), - // IO Pads - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), +// // IO Pads +// .io_in (io_in), +// .io_out(io_out), +// .io_oeb(io_oeb), - // IRQ - .irq(user_irq) -); +// // IRQ +// .irq(user_irq) +// ); endmodule // user_project_wrapper