| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY | |
| /home/htamas/progs/trainable-nn-resub4/openlane/trainable_nn,trainable_nn,22_12_05_11_34,flow completed,5h8m6s0ms,3h38m36s0ms,80601.48148148147,3.0,36270.666666666664,34.02,6352.86,108812,0,0,0,0,0,0,-1,-1,-1,-1,-1,6366966,1036961,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4107130970.0,0.0,46.99,56.73,23.41,45.91,-1,142024,193763,1225,52964,0,0,0,143667,3258,79,2241,20712,16272,25612,16803,4225,2162,1975,97,1454,41917,0,43371,2943538.0863999994,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,200.0,5.0,200,AREA 0,10,45,1,153.6,153.18,0.45,0.3,sky130_fd_sc_hd,4 |