44ef3c31f67449e1b1275874adf8e312c8d098fd - third_party/shuttle/sky130/mpw-007/slot-013

commit	44ef3c31f67449e1b1275874adf8e312c8d098fd	[log] [tgz]
author	Soumil Jain <soumil@capella.ucsd.edu>	Tue Sep 06 22:11:34 2022 -0700
committer	Soumil Jain <soumil@capella.ucsd.edu>	Tue Sep 06 22:11:34 2022 -0700
tree	60c8980400942e3c22817e241c136002773214a7
parent	a1b3d690c27336c2ec18375ae5dce129c3e1ce48 [diff]

add reram crossbar files

README.md[diff]
caravel[diff]
gds/user_analog_project_wrapper.gds[diff]
netgen/.user_analog_project_wrapper.spice.swp[Added - diff]
netgen/user_analog_project_wrapper.spice[diff]
verilog/rtl/.reram_crossbar.v.swp[Added - diff]
verilog/rtl/.user_analog_project_wrapper.v.swp[Added - diff]
verilog/rtl/reram_crossbar.v[Added - diff]
verilog/rtl/user_analog_project_wrapper.v[diff]

9 files changed

tree: 60c8980400942e3c22817e241c136002773214a7

.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md

README.md

ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel analog read for vector-matrix multiplication. All characterisation is fully digitally controlled over the logic analyser.