| /root/isa_16-bit_microprocessor/Makefile |
| /root/isa_16-bit_microprocessor/docs/Makefile |
| /root/isa_16-bit_microprocessor/docs/environment.yml |
| /root/isa_16-bit_microprocessor/docs/source/conf.py |
| /root/isa_16-bit_microprocessor/docs/source/index.rst |
| /root/isa_16-bit_microprocessor/docs/source/quickstart.rst |
| /root/isa_16-bit_microprocessor/openlane/Makefile |
| /root/isa_16-bit_microprocessor/openlane/cpu/config.tcl |
| /root/isa_16-bit_microprocessor/openlane/soc_config/config.tcl |
| /root/isa_16-bit_microprocessor/openlane/spi_master/config.tcl |
| /root/isa_16-bit_microprocessor/openlane/user_proj_example/config.tcl |
| /root/isa_16-bit_microprocessor/openlane/user_project_wrapper/config.tcl |
| /root/isa_16-bit_microprocessor/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl |
| /root/isa_16-bit_microprocessor/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl |
| /root/isa_16-bit_microprocessor/verilog/dv/Makefile |
| /root/isa_16-bit_microprocessor/verilog/dv/io_ports/Makefile |
| /root/isa_16-bit_microprocessor/verilog/dv/io_ports/io_ports.c |
| /root/isa_16-bit_microprocessor/verilog/dv/io_ports/io_ports_tb.v |
| /root/isa_16-bit_microprocessor/verilog/dv/la_test1/Makefile |
| /root/isa_16-bit_microprocessor/verilog/dv/la_test1/la_test1.c |
| /root/isa_16-bit_microprocessor/verilog/dv/la_test1/la_test1_tb.v |
| /root/isa_16-bit_microprocessor/verilog/dv/la_test2/Makefile |
| /root/isa_16-bit_microprocessor/verilog/dv/la_test2/la_test2.c |
| /root/isa_16-bit_microprocessor/verilog/dv/la_test2/la_test2_tb.v |
| /root/isa_16-bit_microprocessor/verilog/dv/mprj_stimulus/Makefile |
| /root/isa_16-bit_microprocessor/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/isa_16-bit_microprocessor/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/isa_16-bit_microprocessor/verilog/dv/wb_port/Makefile |
| /root/isa_16-bit_microprocessor/verilog/dv/wb_port/wb_port.c |
| /root/isa_16-bit_microprocessor/verilog/dv/wb_port/wb_port_tb.v |
| /root/isa_16-bit_microprocessor/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/isa_16-bit_microprocessor/verilog/includes/includes.gl.caravel_user_project |
| /root/isa_16-bit_microprocessor/verilog/includes/includes.rtl.caravel_user_project |
| /root/isa_16-bit_microprocessor/verilog/rtl/cpu.v |
| /root/isa_16-bit_microprocessor/verilog/rtl/soc_config.v |
| /root/isa_16-bit_microprocessor/verilog/rtl/spi_master.v |
| /root/isa_16-bit_microprocessor/verilog/rtl/uprj_netlists.v |
| /root/isa_16-bit_microprocessor/verilog/rtl/user_defines.v |
| /root/isa_16-bit_microprocessor/verilog/rtl/user_proj_example.v |
| /root/isa_16-bit_microprocessor/verilog/rtl/user_project_wrapper.v |
