| 2022-11-24 16:42:24 - [INFO] - {{Project Git Info}} Repository: https://github.com/alokerdas/uP16_efabless.git | Branch: main | Commit: 0141df9440feef68797b4ae93eb0f03eca262181 |
| 2022-11-24 16:42:24 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: isa_16-bit_microprocessor |
| 2022-11-24 16:42:24 - [INFO] - {{Project Type Info}} digital |
| 2022-11-24 16:42:24 - [INFO] - {{Project GDS Info}} user_project_wrapper: b86fe5dd128f3b1e04bdba079b44221f26b2f202 |
| 2022-11-24 16:42:25 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340 |
| 2022-11-24 16:42:25 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f |
| 2022-11-24 16:42:25 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'isa_16-bit_microprocessor/jobs/mpw_precheck/4ec322f8-94a1-4f3d-9da3-4bbc3451f217/logs' |
| 2022-11-24 16:42:25 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea] |
| 2022-11-24 16:42:25 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License |
| 2022-11-24 16:42:25 - [INFO] - An approved LICENSE (Apache-2.0) was found in isa_16-bit_microprocessor. |
| 2022-11-24 16:42:25 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root. |
| 2022-11-24 16:42:26 - [INFO] - An approved LICENSE (Apache-2.0) was found in isa_16-bit_microprocessor. |
| 2022-11-24 16:42:26 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules |
| 2022-11-24 16:42:26 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 40 non-compliant file(s) with the SPDX Standard. |
| 2022-11-24 16:42:26 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['isa_16-bit_microprocessor/Makefile', 'isa_16-bit_microprocessor/docs/Makefile', 'isa_16-bit_microprocessor/docs/environment.yml', 'isa_16-bit_microprocessor/docs/source/conf.py', 'isa_16-bit_microprocessor/docs/source/index.rst', 'isa_16-bit_microprocessor/docs/source/quickstart.rst', 'isa_16-bit_microprocessor/openlane/Makefile', 'isa_16-bit_microprocessor/openlane/cpu/config.tcl', 'isa_16-bit_microprocessor/openlane/soc_config/config.tcl', 'isa_16-bit_microprocessor/openlane/spi_master/config.tcl', 'isa_16-bit_microprocessor/openlane/user_proj_example/config.tcl', 'isa_16-bit_microprocessor/openlane/user_project_wrapper/config.tcl', 'isa_16-bit_microprocessor/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl', 'isa_16-bit_microprocessor/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl', 'isa_16-bit_microprocessor/verilog/dv/Makefile'] |
| 2022-11-24 16:42:26 - [INFO] - For the full SPDX compliance report check: isa_16-bit_microprocessor/jobs/mpw_precheck/4ec322f8-94a1-4f3d-9da3-4bbc3451f217/logs/spdx_compliance_report.log |
| 2022-11-24 16:42:26 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile |
| 2022-11-24 16:42:26 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid. |
| 2022-11-24 16:42:26 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default |
| 2022-11-24 16:42:26 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md' |
| 2022-11-24 16:42:26 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds' |
| 2022-11-24 16:42:26 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation |
| 2022-11-24 16:42:26 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate. |
| 2022-11-24 16:42:26 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency |
| 2022-11-24 16:42:31 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. |
| 2022-11-24 16:42:31 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (92 instances). |
| 2022-11-24 16:42:31 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural. |
| 2022-11-24 16:42:31 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel. |
| 2022-11-24 16:42:31 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power |
| 2022-11-24 16:42:31 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks. |
| 2022-11-24 16:42:31 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports |
| 2022-11-24 16:42:31 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (10 instances). |
| 2022-11-24 16:42:31 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural. |
| 2022-11-24 16:42:31 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist. |
| 2022-11-24 16:42:31 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power |
| 2022-11-24 16:42:31 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types. |
| 2022-11-24 16:42:31 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks. |
| 2022-11-24 16:42:31 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid. |
| 2022-11-24 16:42:31 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines |
| 2022-11-24 16:42:31 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'isa_16-bit_microprocessor/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v'] |
| 2022-11-24 16:42:33 - [INFO] - GPIO-DEFINES report path: isa_16-bit_microprocessor/jobs/mpw_precheck/4ec322f8-94a1-4f3d-9da3-4bbc3451f217/outputs/reports/gpio_defines.report |
| 2022-11-24 16:42:33 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid. |
| 2022-11-24 16:42:33 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR |
| 2022-11-24 16:43:02 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view isa_16-bit_microprocessor/jobs/mpw_precheck/4ec322f8-94a1-4f3d-9da3-4bbc3451f217/outputs/user_project_wrapper.xor.gds |
| 2022-11-24 16:43:02 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations. |
| 2022-11-24 16:43:02 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC |
| 2022-11-24 16:43:57 - [ERROR] - Violation Message 'Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d)' found 151 times. |
| 2022-11-24 16:43:57 - [ERROR] - 151 DRC violations |
| 2022-11-24 16:43:57 - [WARNING] - {{MAGIC DRC CHECK FAILED}} The GDS file, user_project_wrapper.gds, has DRC violations. |
| 2022-11-24 16:43:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL |
| 2022-11-24 16:44:19 - [INFO] - No DRC Violations found |
| 2022-11-24 16:44:19 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-11-24 16:44:19 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL |
| 2022-11-24 16:45:51 - [INFO] - No DRC Violations found |
| 2022-11-24 16:45:51 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-11-24 16:45:51 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid |
| 2022-11-24 16:46:08 - [INFO] - No DRC Violations found |
| 2022-11-24 16:46:08 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-11-24 16:46:08 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density |
| 2022-11-24 16:46:17 - [INFO] - No DRC Violations found |
| 2022-11-24 16:46:17 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-11-24 16:46:17 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing |
| 2022-11-24 16:46:25 - [INFO] - No DRC Violations found |
| 2022-11-24 16:46:25 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-11-24 16:46:25 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea |
| 2022-11-24 16:46:27 - [INFO] - No DRC Violations found |
| 2022-11-24 16:46:27 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-11-24 16:46:27 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'isa_16-bit_microprocessor/jobs/mpw_precheck/4ec322f8-94a1-4f3d-9da3-4bbc3451f217/logs' |
| 2022-11-24 16:46:27 - [INFO] - {{SUCCESS}} All Checks Passed !!! |
