| Tim Edwards | 5cc020d | 2021-05-06 11:54:28 -0400 | [diff] [blame] | 1 | v {xschem version=2.9.9 file_version=1.2 } |
| 2 | G {} |
| 3 | K {type=subcircuit |
| 4 | format="@name @pinlist @symname" |
| 5 | template="name=x1" |
| 6 | } |
| 7 | V {} |
| 8 | S {} |
| 9 | E {} |
| 10 | L 4 -130 -190 130 -190 {} |
| 11 | L 4 -130 190 130 190 {} |
| 12 | L 4 -130 -190 -130 190 {} |
| 13 | L 4 130 -190 130 190 {} |
| 14 | L 4 -150 -180 -130 -180 {} |
| 15 | L 4 -150 -160 -130 -160 {} |
| 16 | L 4 -150 -140 -130 -140 {} |
| 17 | L 4 -150 -120 -130 -120 {} |
| 18 | L 4 -150 -100 -130 -100 {} |
| 19 | L 4 -150 -80 -130 -80 {} |
| 20 | L 4 -150 -60 -130 -60 {} |
| 21 | L 4 -150 -40 -130 -40 {} |
| 22 | L 4 130 -20 150 -20 {} |
| 23 | L 4 130 0 150 0 {} |
| 24 | L 4 -150 -20 -130 -20 {} |
| 25 | L 4 130 20 150 20 {} |
| 26 | L 4 -150 0 -130 0 {} |
| 27 | L 4 -150 20 -130 20 {} |
| 28 | L 4 -150 40 -130 40 {} |
| 29 | L 4 130 40 150 40 {} |
| 30 | L 4 130 60 150 60 {} |
| 31 | L 4 -150 60 -130 60 {} |
| 32 | L 4 130 180 150 180 {} |
| 33 | L 7 130 -180 150 -180 {} |
| 34 | L 7 130 -160 150 -160 {} |
| 35 | L 7 130 -140 150 -140 {} |
| 36 | L 7 130 -120 150 -120 {} |
| 37 | L 7 130 -100 150 -100 {} |
| 38 | L 7 130 -80 150 -80 {} |
| 39 | L 7 130 -60 150 -60 {} |
| 40 | L 7 130 -40 150 -40 {} |
| 41 | L 7 130 80 150 80 {} |
| 42 | L 7 130 100 150 100 {} |
| 43 | L 7 130 120 150 120 {} |
| 44 | L 7 130 140 150 140 {} |
| 45 | L 7 130 160 150 160 {} |
| 46 | B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout } |
| 47 | B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout } |
| 48 | B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout } |
| 49 | B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout } |
| 50 | B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout } |
| 51 | B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout } |
| 52 | B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout } |
| 53 | B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout } |
| 54 | B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in } |
| 55 | B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in } |
| 56 | B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in } |
| 57 | B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in } |
| 58 | B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in } |
| 59 | B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in } |
| 60 | B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in } |
| 61 | B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in } |
| 62 | B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out } |
| 63 | B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out } |
| 64 | B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in } |
| 65 | B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out } |
| 66 | B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in } |
| 67 | B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in } |
| 68 | B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in } |
| 69 | B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out } |
| 70 | B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out } |
| 71 | B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout } |
| 72 | B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout } |
| 73 | B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout } |
| 74 | B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout } |
| 75 | B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout } |
| 76 | B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in } |
| 77 | B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out } |
| 78 | T {@symname} -119.5 114 0 0 0.3 0.3 {} |
| 79 | T {@name} 135 -202 0 0 0.2 0.2 {} |
| 80 | T {vdda1} 125 -184 0 1 0.2 0.2 {} |
| 81 | T {vdda2} 125 -164 0 1 0.2 0.2 {} |
| 82 | T {vssa1} 125 -144 0 1 0.2 0.2 {} |
| 83 | T {vssa2} 125 -124 0 1 0.2 0.2 {} |
| 84 | T {vccd1} 125 -104 0 1 0.2 0.2 {} |
| 85 | T {vccd2} 125 -84 0 1 0.2 0.2 {} |
| 86 | T {vssd1} 125 -64 0 1 0.2 0.2 {} |
| 87 | T {vssd2} 125 -44 0 1 0.2 0.2 {} |
| 88 | T {wb_clk_i} -125 -184 0 0 0.2 0.2 {} |
| 89 | T {wb_rst_i} -125 -164 0 0 0.2 0.2 {} |
| 90 | T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {} |
| 91 | T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {} |
| 92 | T {wbs_we_i} -125 -104 0 0 0.2 0.2 {} |
| 93 | T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {} |
| 94 | T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {} |
| 95 | T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {} |
| 96 | T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {} |
| 97 | T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {} |
| 98 | T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {} |
| 99 | T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {} |
| 100 | T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {} |
| 101 | T {io_in[26:0]} -125 16 0 0 0.2 0.2 {} |
| 102 | T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {} |
| 103 | T {io_out[26:0]} 125 36 0 1 0.2 0.2 {} |
| 104 | T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {} |
| 105 | T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {} |
| 106 | T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {} |
| 107 | T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {} |
| 108 | T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {} |
| 109 | T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {} |
| 110 | T {user_clock2} -125 56 0 0 0.2 0.2 {} |
| 111 | T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {} |
