Update cell design using less wide transistors.

doitcode/sram.py

diff --git a/doitcode/sram.py b/doitcode/sram.py
index b0ddb51..afcdc78 100644
--- a/doitcode/sram.py
+++ b/doitcode/sram.py
@@ -142,7 +142,9 @@
         _tie_bb = tie_cell.layout.boundary
         assert _tie_bb is not None
 
-        sram_cell = mem_fab.block(words=512, word_size=8, we_size=1)
+        sram_cell = mem_fab.block(
+            address_groups=(3, 4, 2), word_size=8, we_size=1, cell_name="512x8",
+        )
         self.a_bits = sram_cell.a_bits
         self.word_size = sram_cell.word_size
 

gds/user_analog_project_wrapper.gds.gz

diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index 551aec6..e0c643f 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ