| commit | 8f0276738bd190c80cc6e79cdada563b39811901 | [log] [tgz] |
|---|---|---|
| author | Staf Verhaegen <staf@fibraservi.eu> | Fri Jun 03 15:38:04 2022 +0200 |
| committer | Staf Verhaegen <staf@fibraservi.eu> | Fri Jun 03 15:38:04 2022 +0200 |
| tree | 3dab25ebc1d0687f2cc01220bc6d8a390460f1e8 | |
| parent | 5703d3c506a871b5eadaebb6774232d405796dcf [diff] |
DRC fixing.
diff --git a/doitcode/sram.py b/doitcode/sram.py index 24bac9b..e89f7ab 100644 --- a/doitcode/sram.py +++ b/doitcode/sram.py
@@ -196,7 +196,6 @@ dpsram_bb = dpsram_lay.boundary assert dpsram_bb is not None - # Make three rows of to place standard cells in # dbound = 4.0
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz index e410f8a..352b5df 100644 --- a/gds/user_analog_project_wrapper.gds.gz +++ b/gds/user_analog_project_wrapper.gds.gz Binary files differ