commit 3d1a8113d97907c87f94efb81c43218be12f79b2
author Staf Verhaegen <staf@fibraservi.eu> Mon Mar 21 16:00:16 2022 +0100
committer Staf Verhaegen <staf@fibraservi.eu> Mon Mar 21 16:00:16 2022 +0100
tree e60269e194b4eb74dfe8b0e0e9897fc0ccb26e10
parent 49bdb7d6eccfb2d45ed9e6ca2e2fcbb38c399351

Consistency pt.2

Verilog files.

verilog/rtl/blocks.v

diff --git a/verilog/rtl/blocks.v b/verilog/rtl/blocks.v
index 325de4a..c4db2d6 100644
--- a/verilog/rtl/blocks.v
+++ b/verilog/rtl/blocks.v
@@ -1,6 +1,14 @@
 // SPDX-License-Identifier: LGPL-2.1-or-later
 `timesacle 1 ns / 1 ps
 
+module ConnectedSRAM (
+    inout vss,
+    inout vdd
+);
+
+endmodule
+
+
 module user_analog_project_wrapper_empty (
     inout vdda1,
     inout vdda2,

verilog/rtl/user_analog_project_wrapper.v

diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index ab89225..95fc0c5 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -86,4 +86,9 @@
     .user_irq(user_irq)
 )
 
+ConnectedSRAM sram (
+    .vss(io_analog[4]),
+    .vdd(io_analog[5])
+)
+
 endmodule	// user_analog_project_wrapper