uartm auto detect + Manual Placement Pll + Pwm changes
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl index aec92b4..15648c1 100755 --- a/openlane/pinmux_top/config.tcl +++ b/openlane/pinmux_top/config.tcl
@@ -45,19 +45,23 @@ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_top.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_reg.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_top.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_reg.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_top.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_reg.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/gpio/src/gpio_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/gpio/src/gpio_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/gpio/src/gpio_intr.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/gpio/src/gpio_dglicth.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pwm/src/pwm_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pwm/src/pwm_core.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pwm/src/pwm_glbl_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pwm/src/pwm_blk_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pwm/src/pwm_cfg_dglitch.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pwm/src/pwm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/timer/src/timer_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/timer/src/timer_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/timer/src/timer.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/semaphore_reg.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_top.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_driver.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/ws281x/src/ws281x_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/ws281x/src/ws281x_driver.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/ws281x/src/ws281x_reg.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/strap_ctrl.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_rst_reg.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \ @@ -88,7 +92,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 500 750" +set ::env(DIE_AREA) "0 0 500 800" # If you're going to use multiple power domains, then keep this disabled. @@ -98,8 +102,8 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.38" -set ::env(CELL_PAD) "4" +set ::env(PL_TARGET_DENSITY) "0.39" +set ::env(CELL_PAD) "8" #set ::env(GRT_ADJUSTMENT) {0.2}
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index 08d18dd..e7b8753 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -59,6 +59,7 @@ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2wb.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2_core.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart_auto_det.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_if.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/spi2wb.sv \
diff --git a/verilog/dv/uart_master_test2/Makefile b/verilog/dv/uart_master_test2/Makefile new file mode 100644 index 0000000..b333a87 --- /dev/null +++ b/verilog/dv/uart_master_test2/Makefile
@@ -0,0 +1,207 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) + +# ---- Include Partitioned Makefiles ---- + +DESIGNS?=../../.. +CONFIG = caravel_user_project +TOOLS?=/opt/riscv32i/ + +######################################################## +#include $(MCW_ROOT)/verilog/dv/make/env.makefile +######################################################## +####################################################################### +## Global Environment Variables for local repo +####################################################################### + +export PDK_PATH = $(PDK_ROOT)/sky130A +export VIP_PATH = $(CORE_VERILOG_PATH)/dv/vip +export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +export CARAVEL_VERILOG_PATH ?= $(CARAVEL_ROOT)/verilog +export CORE_VERILOG_PATH ?= $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog + +export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH) +export VERILOG_PATH = $(CORE_VERILOG_PATH) + +####################################################################### +## Compiler Information +####################################################################### + +export TOOLS ?= /opt/riscv32i +export GCC_PATH ?= $(TOOLS)/bin +GCC_PREFIX?=riscv32-unknown-elf + + + + + + + + +######################################################## +#include $(MCW_ROOT)/verilog/dv/make/var.makefile +######################################################## + +CPU=vexriscv +CPUFAMILY=riscv +CPUFLAGS=-march=rv32i -mabi=ilp32 -D__vexriscv__ +CPUENDIANNESS=little +CLANG=0 + + +###################################################### +# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +###################################################### + +ifeq ($(CPU),picorv32) + LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds + SOURCE_FILES=$(FIRMWARE_PATH)/start.s + VERILOG_FILES= +endif + +ifeq ($(CPU),ibex) + LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld + SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c +# VERILOG_FILES=../ibex/* + VERILOG_FILES= +endif + +ifeq ($(CPU),vexriscv) +# LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds +# SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s + LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds + SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c + VERILOG_FILES= +endif + + + +##################################################### +#include $(MCW_ROOT)/verilog/dv/make/sim.makefile +###################################################### + +export IVERILOG_DUMPER = fst + +# RTL/GL/GL_SDF +SIM?=RTL +DUMP?=OFF + + +.SUFFIXES: + + +all: ${BLOCKS:=.vcd} ${BLOCKS:=.vvp} + + +#.SUFFIXES: + + +############################################################################## +# Runing the simulations +############################################################################## + +%.vvp: %_tb.v + +## RTL +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -o $@ $< + else + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -o $@ $< + endif +endif + +##GL +ifeq ($(SIM),GL) + ifeq ($(DUMP),OFF) + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< + else + iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< + endif +endif + +## GL+SDF +ifeq ($(SIM),GL_SDF) + ifeq ($(CONFIG),caravel_user_project) + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \ + -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $< + else + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \ + -f $CARAVEL_PATH/gl/__user_project_wrapper.v $< + endif +endif + +%.vcd: %.vvp + vvp $< + +# twinwave: RTL-%.vcd GL-%.vcd +# twinwave RTL-$@ * + GL-$@ * + +check-env: +ifndef PDK_ROOT + $(error PDK_ROOT is undefined, please export it before running make) +endif +ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) + $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) +endif +ifeq (,$(wildcard $(GCC_PREFIX)-gcc )) + $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +endif +# check for efabless style installation +ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) +SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE +endif + + +# ---- Clean ---- + +clean: + \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe + +.PHONY: clean hex all + + + + + +
diff --git a/verilog/dv/uart_master_test2/run_verilog b/verilog/dv/uart_master_test2/run_verilog new file mode 100644 index 0000000..5ffed3c --- /dev/null +++ b/verilog/dv/uart_master_test2/run_verilog
@@ -0,0 +1,20 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// + +#iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl -I ../../../verilog wb_port_tb.v -o wb_port.vvp +iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl -I ../../../verilog wb_port_tb.v -o wb_port.vvp
diff --git a/verilog/dv/uart_master_test2/uart_master_test2_tb.v b/verilog/dv/uart_master_test2/uart_master_test2_tb.v new file mode 100644 index 0000000..6ed5609 --- /dev/null +++ b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
@@ -0,0 +1,317 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps +`include "uart_agent.v" + +`define TB_HEX "uart_master.hex" +`define TB_TOP uart_master_tb +module `TB_TOP; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + wire [15:0] checkbits; + +//---------------------------------- +// Uart Configuration +// --------------------------------- +reg [1:0] uart_data_bit ; +reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; +reg uart_stick_parity ; // 1: force even parity +reg uart_parity_en ; // parity enable +reg uart_even_odd_parity ; // 0: odd parity; 1: even parity + +reg [7:0] uart_data ; +reg [15:0] uart_divisor ; // divided by n * 16 +reg [15:0] uart_timeout ;// wait time limit + +reg [15:0] uart_rx_nu ; +reg [15:0] uart_tx_nu ; +reg [7:0] uart_write_data [0:39]; +reg uart_fifo_enable ; // fifo mode disable + +reg [31:0] read_data ; +reg flag; +reg test_fail ; +reg [15:0] strap_in; + + + assign checkbits = mprj_io[31:16]; + + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(2, `TB_TOP); + $dumpvars(0, `TB_TOP.tb_master_uart); + $dumpvars(0, `TB_TOP.u_top.mprj.u_wb_host.u_uart2wb); + $dumpvars(1, `TB_TOP.tb_master_uart); + $dumpvars(0, `TB_TOP.u_top.mprj.u_pinmux); + end + `endif + + initial begin + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (400) begin + repeat (10000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("##########################################################"); + `ifdef GL + $display ("Monitor: Timeout, %m (GL) Failed"); + `else + $display ("Monitor: Timeout, %m (RTL) Failed"); + `endif + $display ("##########################################################"); + $display("%c[0m",27); + $finish; + end + /************************************************************************* + * This is Baud Rate to clock divider conversion for Test Bench + * Note: DUT uses 16x baud clock, where are test bench uses directly + * baud clock, Due to 16x Baud clock requirement at RTL, there will be + * some resolution loss, we expect at lower baud rate this resolution + * loss will be less. For Quick simulation perpose higher baud rate used + * *************************************************************************/ + task tb_set_uart_baud; + input [31:0] ref_clk; + input [31:0] baud_rate; + output [31:0] baud_div; + reg [31:0] baud_div; + begin + // for 230400 Baud = (50Mhz/230400) = 216.7 + baud_div = ref_clk/baud_rate; // Get the Bit Baud rate + // Baud 16x = 216/16 = 13 + baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench + // Test bench baud clock , 16x of above value + // 13 * 16 = 208, + // (Note if you see original value was 216, now it's 208 ) + baud_div = baud_div * 16; + // Test bench half cycle counter to toggle it + // 208/2 = 104 + baud_div = baud_div/2; + //As counter run's from 0 , substract from 1 + baud_div = baud_div-1; + end + endtask + + initial begin + + strap_in = 0; + strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA + apply_strap(strap_in); + + uart_data_bit = 2'b11; + uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; + uart_stick_parity = 0; // 1: force even parity + uart_parity_en = 0; // parity enable + uart_even_odd_parity = 1; // 0: odd parity; 1: even parity + tb_set_uart_baud(50000000,288000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 + uart_timeout = 200;// wait time limit + uart_fifo_enable = 0; // fifo mode disable + tb_master_uart.debug_mode = 0; // disable debug display + + #200; // Wait for reset removal + + // wait(checkbits == 16'h AB60); + // $display("Monitor: UART Master Test Started"); + + repeat (10000) @(posedge clock); + tb_master_uart.uart_init; + tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, + uart_stick_parity, uart_timeout, uart_divisor); + tb_master_uart.write_char(8'hA); // New line for auto detect + //$write ("\n(%t)Response:\n",$time); + // Wait for Initial Command Format from the uart master + flag = 0; + while(flag == 0) + begin + tb_master_uart.read_char(read_data,flag); + $write ("%c",read_data); + end + + + + // Remove Wb Reset + uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + repeat (2) @(posedge clock); + #1; + + $display("Monitor: Writing expected value"); + + test_fail = 0; + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); + + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); + + $display("###################################################"); + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: %m (GL) Passed"); + `else + $display("Monitor: %m (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: %m (GL) Failed"); + `else + $display("Monitor: %m (RTL) Failed"); + `endif + end + $display("###################################################"); + #100 + + $finish; + end + + initial begin + RSTB <= 1'b0; + //CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #170000; + //CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + //always @(mprj_io) begin + // #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + //end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; + + caravel u_top ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + +/*** No Caravel SPI needed ************** + spiflash #( + .FILENAME("uart_master.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); +************************/ + + + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + end +`endif + + +//--------------------------- +// UART Agent integration +// -------------------------- +wire uart_txd,uart_rxd; + +assign uart_txd = mprj_io[7]; +assign mprj_io[6] = uart_rxd ; + +uart_agent tb_master_uart( + .mclk (clock ), + .txd (uart_rxd ), + .rxd (uart_txd ) + ); + + +`include "caravel_task.sv" +`include "uart_master_tasks.sv" + +endmodule + +`default_nettype wire
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index 2cdec85..b8bce21 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -87,7 +87,9 @@ reg [31:0] pwm3_period; reg [31:0] pwm4_period; reg [31:0] pwm5_period; - integer test_step; + + reg [15:0] check_sum; + integer test_step,i; wire clock_mon; @@ -119,26 +121,20 @@ repeat (2) @(posedge clock); #1; - // Remove the reset - // Remove WB and SPI/UART Reset, Keep CORE under Reset - //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); - - // config 1us based on system clock - 1000/25ns = 40 - wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39); - test_fail = 0; + check_sum = 0; repeat (200) @(posedge clock); wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 $display("########################################"); $display("Step-1, PWM Square Waveform"); + test_step = 1; pwm0_period = 20*256; pwm1_period = 20*2*256; pwm2_period = 20*4*256; - pwm3_period = 20*8*256; - pwm4_period = 20*16*256; - pwm5_period = 20*32*256; - test_step = 1; + pwm3_period = 20*256; // pwm3 is connected to pwm0 + pwm4_period = 20*2*256; // pwm4 is connected to pwm1 + pwm5_period = 20*4*256; // pwm5 is conneted to pwm2 wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_8000); // No Scale wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFFFF wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h0000_007F); // COMP0 = 0xFF @@ -151,25 +147,26 @@ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFFFF wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h0000_007F); // COMP0 = 0xFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG0,'h0000_8003); // Scale 2^3 = 8 - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG1,'h0000_00FF); // Period 0xFFFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG2,'h0000_007F); // COMP0 = 0xFF + // PWm3 to 5 Removed + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG0,'h0000_8003); // Scale 2^3 = 8 + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG1,'h0000_00FF); // Period 0xFFFF + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG2,'h0000_007F); // COMP0 = 0xFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG0,'h0000_8004); // Scale 2^4 = 16 - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG1,'h0000_00FF); // Period 0xFFFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG2,'h0000_007F); // COMP0 = 0xFF + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG0,'h0000_8004); // Scale 2^4 = 16 + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG1,'h0000_00FF); // Period 0xFFFF + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG2,'h0000_007F); // COMP0 = 0xFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG0,'h0000_8005); // Scale 2^5 = 32 - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG1,'h0000_00FF); // Period 0xFFFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG2,'h0000_007F); // COMP0 = 0xFF + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG0,'h0000_8005); // Scale 2^5 = 32 + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG1,'h0000_00FF); // Period 0xFFFF + //wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG2,'h0000_007F); // COMP0 = 0xFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_003F); // Enable PWM - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_003F); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM + RUN pwm_monitor(pwm0_period,pwm1_period,pwm2_period,pwm3_period,pwm4_period,pwm5_period); - wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_003F); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_003F); // Clear Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status @@ -181,12 +178,6 @@ end $display("########################################"); $display("Step-2, PWM One Shot"); - pwm0_period = 20*256; - pwm1_period = 20*2*256; - pwm2_period = 20*4*256; - pwm3_period = 20*8*256; - pwm4_period = 20*16*256; - pwm5_period = 20*32*256; test_step = 2; wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_8010); // No Scale wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFFFF @@ -200,30 +191,29 @@ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFFFF wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h0000_007F); // COMP0 = 0xFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG0,'h0000_8013); // Scale 2^3 = 8 - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG1,'h0000_00FF); // Period 0xFFFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG2,'h0000_007F); // COMP0 = 0xFF - - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG0,'h0000_8014); // Scale 2^4 = 16 - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG1,'h0000_00FF); // Period 0xFFFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG2,'h0000_007F); // COMP0 = 0xFF - - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG0,'h0000_8015); // Scale 2^5 = 32 - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG1,'h0000_00FF); // Period 0xFFFF - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG2,'h0000_007F); // COMP0 = 0xFF - - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_003F); // Enable PWM - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_003F); // Enable PWM Interrupt - read_data = 8'h3F; - while(read_data != 8'h00) begin // Wait for De-assertion on Enable - wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data); - repeat (100) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM + Run + read_data[15:8] = 8'h7; + fork + begin + while(read_data[15:8] != 8'h00) begin // Wait for De-assertion on Run + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any - wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_003F); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_003F); // Clear Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status @@ -234,6 +224,524 @@ $display("STATUS: Step-2, PWM One Shot - PASSED"); end + $display("########################################"); + $display("Step-3, PWM One Shot + Hold last data "); + test_step = 3; + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_8810); // No Scale + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFFFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h0000_007F); // COMP0 = 0xFF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_8811); // Scale 2^1 = 2 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFFFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h0000_007F); // COMP0 = 0xFF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_8812); // Scale 2^2 = 4 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFFFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h0000_007F); // COMP0 = 0xFF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM + Run + read_data[15:8] = 8'h7; + fork + begin + while(read_data[15:8] != 8'h00) begin // Wait for De-assertion on Run + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-3, PWM One Shot + Hold last data - FAILED"); + end else begin + $display("STATUS: Step-3, PWM One Shot + Hold last data - PASSED"); + end + + $display("########################################"); + $display("Step-4, PWM One Shot + mode:1 "); + test_step = 4; + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_9010); // No Scale + One Shot + Mode:1 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h0000_0000); // COMP2 = 0x00, COMP3= 0x00 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_9011); // Scale 2^1 = 2 + One Shot + Mode:1 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h0000_0000); // COMP2 = 0x00, COMP3= 0x00 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_9012); // Scale 2^2 = 4 + One Shot + Mode:1 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h0000_0000); // COMP2 = 0x00, COMP3= 0x00 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM + Run + read_data[15:8] = 8'h7; + fork + begin + while(read_data[15:8] != 8'h00) begin // Wait for De-assertion on Run + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-4, PWM One Shot + mode:1 - FAILED"); + end else begin + $display("STATUS: Step-4, PWM One Shot + mode:1 - PASSED"); + end + + $display("########################################"); + $display("Step-5, PWM One Shot + mode:2 "); + test_step = 5; + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_A010); // No Scale + One Shot + Mode:2 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h0000_00AF); // COMP2 = 0xAF, COMP3= 0x00 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_A011); // Scale 2^1 = 2 + One Shot + Mode:2 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h0000_00AF); // COMP2 = 0xAF, COMP3= 0x00 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_A012); // Scale 2^2 = 4 + One Shot + Mode:2 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h0000_00AF); // COMP2 = 0xAF, COMP3= 0x00 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM + Run + read_data[15:8] = 8'h7; + fork + begin + while(read_data[15:8] != 8'h00) begin // Wait for De-assertion on Run + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-5, PWM One Shot + mode:2 - FAILED"); + end else begin + $display("STATUS: Step-5, PWM One Shot + mode:2 - PASSED"); + end + $display("########################################"); + $display("Step-6, PWM One Shot + mode:3 "); + test_step = 6; + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_B010); // No Scale + One Shot + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_B011); // Scale 2^1 = 2 + One Shot + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_B012); // Scale 2^2 = 4 + One Shot + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM+Run + read_data[15:8] = 8'h7; + fork + begin + while(read_data[15:8] != 8'h00) begin // Wait for De-assertion on Run + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-6, PWM One Shot + mode:3 - FAILED"); + end else begin + $display("STATUS: Step-6, PWM One Shot + mode:3 - PASSED"); + end + $display("########################################"); + $display("Step-7, PWM Free Running + mode:3 "); + test_step = 7; + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_B000); // No Scale + Free Run + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_B001); // Scale 2^1 = 2 + Free Run + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_B002); // Scale 2^2 = 4 + Free Run + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM+Run + read_data = 8'h0; + fork + begin + while(read_data != 8'h07) begin // Wait for Overflow Interrupt + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-7, PWM Free Run + mode:3 - FAILED"); + end else begin + $display("STATUS: Step-7, PWM Free Run + mode:3 - PASSED"); + end + $display("########################################"); + $display("Step-8, PWM Gpio: 0x3 Pos Edge , One Shot + mode:3 "); + test_step = 8; + // Pin-26 17 PC3/usb_dn/ADC3 digital_io[25]/analog_io[14] + + force u_top.io_in[25] = 1'b0; // force PC3 to 0 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_B350); // No Scale + One Shot + GPIO: 0x3, Posedge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_B351); // Scale 2^1 = 2 + One Shot + GPIO: 0x3, Posedge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_B352); // Scale 2^2 = 4 + One Shot + GPIO: 0x3, Posedge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Interrupt Enable + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0007); // PWM Enable + No Run (Expect GPIO generate Run) + + // Generate 4 GPIO Edge Sequence + for(i=0; i < 4; i=i+1) begin + read_data = 8'h0; + // Generate Pos Egde + force u_top.io_in[25] = 1'b1; // force PC3 to 1 + repeat (10) @(posedge clock); + force u_top.io_in[25] = 1'b0; // force PC3 to 0 + + fork + begin + while(read_data != 8'h07) begin // Wait for Overflow Interrupt + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + if(i < 3) begin + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data); + end + end + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-8, PWM Gpio: 0x3 Pos Edge , One Shot + mode:3 - FAILED"); + end else begin + $display("STATUS: Step-8, PWM Gpio: 0x3 Pos Edge , One Shot + mode:3 - PASSED"); + end + $display("########################################"); + $display("Step-9, PWM Gpio: 0x3 Neg Edge , One Shot + mode:3 "); + test_step = 9; + // Pin-26 17 PC3/usb_dn/ADC3 digital_io[25]/analog_io[14] + + force u_top.io_in[25] = 1'b1; // force PC3 to 1 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_B3D0); // No Scale + One Shot + GPIO: 0x3, Neg Edge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_B3D1); // Scale 2^1 = 2 + One Shot + GPIO: 0x3, Neg Edge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_B3D2); // Scale 2^2 = 4 + One Shot + GPIO: 0x3, Neg Edge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Interrupt Enable + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0007); // PWM Enable + No Run (Expect GPIO generate Run) + + repeat (100) @(posedge clock); // Wait for PWM enable command propagaton + // Generate 4 GPIO Edge Sequence + for(i=0; i < 4; i=i+1) begin + read_data = 8'h0; + // Generate Neg Egde + force u_top.io_in[25] = 1'b0; // force PC3 to 0 + repeat (10) @(posedge clock); + force u_top.io_in[25] = 1'b1; // force PC3 to 1 + + fork + begin + while(read_data != 8'h07) begin // Wait for Overflow Interrupt + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + if(i < 3) begin + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data); + end + end + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-9, PWM Gpio: 0x3 Neg Edge , One Shot + mode:3 - FAILED"); + end else begin + $display("STATUS: Step-9, PWM Gpio: 0x3 Neg Edge , One Shot + mode:3 - PASSED"); + end + $display("########################################"); + $display("Step-10, PWM Gpio: 0x3 Neg Edge , One Shot + mode:3 + Waveform Invert "); + test_step = 10; + // Pin-26 17 PC3/usb_dn/ADC3 digital_io[25]/analog_io[14] + + force u_top.io_in[25] = 1'b1; // force PC3 to 1 + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_F3D0); // No Scale + One Shot + Clk Inv + GPIO: 0x3, Neg Edge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_F3D1); // Scale 2^1 = 2 + One Shot + Clk Inv + GPIO: 0x3, Neg Edge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_F3D2); // Scale 2^2 = 4 + One Shot + Clk Inv + GPIO: 0x3, Neg Edge + Mode:3 + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Interrupt Enable + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0007); // PWM Enable + No Run (Expect GPIO generate Run) + + repeat (100) @(posedge clock); // Wait for PWM enable command propagaton + // Generate 4 GPIO Edge Sequence + for(i=0; i < 4; i=i+1) begin + read_data = 8'h0; + // Generate Neg Egde + force u_top.io_in[25] = 1'b0; // force PC3 to 0 + repeat (10) @(posedge clock); + force u_top.io_in[25] = 1'b1; // force PC3 to 1 + + fork + begin + while(read_data != 8'h07) begin // Wait for Overflow Interrupt + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + if(i < 3) begin + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data); + end + end + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-9, PWM Gpio: 0x3 Neg Edge , One Shot + mode:3 - FAILED"); + end else begin + $display("STATUS: Step-9, PWM Gpio: 0x3 Neg Edge , One Shot + mode:3 - PASSED"); + end + $display("########################################"); + $display("Step-10, PWM One Shot + mode:3 + Comparator Center "); + test_step = 10; + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0007_0000); // Disable Cfg Update + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h000F_B010); // No Scale + One Shot + Mode:3 + Comparator Center + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_FFFF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h000F_B010); // No Scale + One Shot + Mode:3 + Comparator Center + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_FFFF); // Period 0xFF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h008F_006F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h000F_B010); // No Scale + One Shot + Mode:3 + Comparator Center + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_FFFF); // Period 0x80FF + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h008F_0F6F); // COMP0 = 0x6F, COMP1= 0x8F + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG3,'h00CF_00AF); // COMP2 = 0xAF, COMP3= 0xCF + + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_0007); // Enable PWM Interrupt + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Remove config update block + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0707); // Enable PWM+Run + read_data[15:8] = 8'h7; + fork + begin + while(read_data[15:8] != 8'h00) begin // Wait for De-assertion on Run + wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data); + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + begin + while(1) begin + check_sum = check_sum + pwm_wfm; + repeat (100) @(posedge clock); + end + end + join_any + + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0007); // Check Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_0007); // Clear Interrupt + wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status + + if(test_fail == 1) begin + $display("ERROR: Step-10, PWM One Shot + mode:3 + Comparator Center - FAILED"); + end else begin + $display("STATUS: Step-10, PWM One Shot + mode:3 + Comparator Center - PASSED"); + end + $display("Check Sum: %x ",check_sum); + if(check_sum != 16'hc638) test_fail = 1; repeat (100) @(posedge clock); // $display("+1000 cycles"); @@ -255,14 +763,19 @@ $finish; end +wire [5:0] pwm_wfm = {io_out[19], + io_out[18], + io_out[17], + io_out[14], + io_out[13], + io_out[9]}; -wire pwm0 = io_out[9]; -wire pwm1 = io_out[13]; -wire pwm2 = io_out[14]; -wire pwm3 = io_out[17]; -wire pwm4 = io_out[18]; -wire pwm5 = io_out[19]; - +wire pwm0 = pwm_wfm[0]; +wire pwm1 = pwm_wfm[1]; +wire pwm2 = pwm_wfm[2]; +wire pwm3 = pwm_wfm[3]; +wire pwm4 = pwm_wfm[4]; +wire pwm5 = pwm_wfm[5]; task pwm_monitor; input [31:0] pwm0_period;
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv index 46e5140..cc2912e 100644 --- a/verilog/rtl/pinmux/src/glbl_reg.sv +++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -136,9 +136,6 @@ logic [31:0] reg_6; // logic [31:0] reg_7; // logic [31:0] reg_8; // -logic [31:0] reg_9; // -logic [31:0] reg_10; // -logic [31:0] reg_11; // logic [31:0] reg_12; // Latched Strap logic [31:0] reg_13; // Strap Sticky logic [31:0] reg_14; // System Strap @@ -152,14 +149,6 @@ logic [31:0] reg_21; // Software Reg-5 - s_reset logic [31:0] reg_22; // Software Reg-6 - s_reset logic [31:0] reg_23; // Software Reg-7 - s_reset -logic [31:0] reg_24; // Reserved -logic [31:0] reg_25; // Reserved -logic [31:0] reg_26; // Reserved -logic [31:0] reg_27; // Reserved -logic [31:0] reg_28; // Reserved -logic [31:0] reg_29; // Reserved -logic [31:0] reg_30; // Reserved -logic [31:0] reg_31; // Reserved logic cs_int; logic [3:0] cfg_mon_sel; @@ -656,9 +645,9 @@ 5'b00110 : reg_out [31:0] = reg_6 ; 5'b00111 : reg_out [31:0] = reg_7 ; 5'b01000 : reg_out [31:0] = reg_8 ; - 5'b01001 : reg_out [31:0] = reg_9 ; - 5'b01010 : reg_out [31:0] = reg_10 ; - 5'b01011 : reg_out [31:0] = reg_11 ; + 5'b01001 : reg_out [31:0] = 'h0 ; + 5'b01010 : reg_out [31:0] = 'h0 ; + 5'b01011 : reg_out [31:0] = 'h0 ; 5'b01100 : reg_out [31:0] = reg_12 ; 5'b01101 : reg_out [31:0] = reg_13 ; 5'b01110 : reg_out [31:0] = reg_14 ; @@ -671,14 +660,14 @@ 5'b10101 : reg_out [31:0] = reg_21 ; 5'b10110 : reg_out [31:0] = reg_22 ; 5'b10111 : reg_out [31:0] = reg_23 ; - 5'b11000 : reg_out [31:0] = reg_24 ; - 5'b11001 : reg_out [31:0] = reg_25 ; - 5'b11010 : reg_out [31:0] = reg_26 ; - 5'b11011 : reg_out [31:0] = reg_27 ; - 5'b11100 : reg_out [31:0] = reg_28 ; - 5'b11101 : reg_out [31:0] = reg_29 ; - 5'b11110 : reg_out [31:0] = reg_30 ; - 5'b11111 : reg_out [31:0] = reg_31 ; + 5'b11000 : reg_out [31:0] = 'h0 ; + 5'b11001 : reg_out [31:0] = 'h0 ; + 5'b11010 : reg_out [31:0] = 'h0 ; + 5'b11011 : reg_out [31:0] = 'h0 ; + 5'b11100 : reg_out [31:0] = 'h0 ; + 5'b11101 : reg_out [31:0] = 'h0 ; + 5'b11110 : reg_out [31:0] = 'h0 ; + 5'b11111 : reg_out [31:0] = 'h0 ; default : reg_out [31:0] = 32'h0; endcase end
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv index 706cbf0..491a4a0 100755 --- a/verilog/rtl/pinmux/src/pinmux_top.sv +++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -499,7 +499,7 @@ .reg_ack (reg_timer_ack ), .pulse_1us (pulse_1us ), - .pulse_1ms (pulse_1ms ), + .pulse_1ms (pulse1m_mclk ), .timer_intr (timer_intr ) );
diff --git a/verilog/rtl/pinmux/src/pwm.sv b/verilog/rtl/pinmux/src/pwm.sv deleted file mode 100644 index 7a30772..0000000 --- a/verilog/rtl/pinmux/src/pwm.sv +++ /dev/null
@@ -1,44 +0,0 @@ - -//------------------------------------------------------------------- -// PWM waveform period: 1000/((cfg_pwm_high+1) + (cfg_pwm_low+1)) -// For 1 Second with Duty cycle 50 = 1000/((499+1) + (499+1)) -// For 1 Second with 1ms On and 999ms Off = 1000/((0+1) + (998+1)) -// Timing Run's with 1 Milisecond pulse -//------------------------------------------------------------------- - -module pwm( - output logic waveform, - - input logic h_reset_n, - input logic mclk, - input logic pulse1m_mclk, - input logic cfg_pwm_enb, - input logic [15:0] cfg_pwm_high, - input logic [15:0] cfg_pwm_low -); - -logic [15:0] pwm_cnt ; // PWM on/off counter - - -always @(posedge mclk or negedge h_reset_n) -begin - if ( ~h_reset_n ) - begin - pwm_cnt <= 16'h0; - waveform <= 1'b0; - end - else if ( pulse1m_mclk && cfg_pwm_enb) - begin - if ( pwm_cnt == 16'h0 && waveform == 1'b0) begin - pwm_cnt <= cfg_pwm_high; - waveform <= ~waveform; - end else if ( pwm_cnt == 16'h0 && waveform == 1'b1) begin - pwm_cnt <= cfg_pwm_low; - waveform <= ~waveform; - end else begin - pwm_cnt <= pwm_cnt - 1; - end - end -end - -endmodule
diff --git a/verilog/rtl/pinmux/src/pwm_blk_reg.sv b/verilog/rtl/pinmux/src/pwm_blk_reg.sv deleted file mode 100644 index 702c138..0000000 --- a/verilog/rtl/pinmux/src/pwm_blk_reg.sv +++ /dev/null
@@ -1,255 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -////////////////////////////////////////////////////////////////////// -//// //// -//// PWM Register //// -//// //// -//// This file is part of the riscduino cores project //// -//// https://github.com/dineshannayya/riscduino.git //// -//// //// -//// Description //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// -//// //// -//// Revision : //// -//// 0.1 - 15th Aug 2022, Dinesh A //// -//// initial version //// -////////////////////////////////////////////////////////////////////// -// -module pwm_reg ( - // System Signals - // Inputs - input logic mclk , - input logic h_reset_n , - - // Reg Bus Interface Signal - input logic reg_cs , - input logic reg_wr , - input logic [2:0] reg_addr , - input logic [31:0] reg_wdata , - input logic [3:0] reg_be , - - // Outputs - output logic [31:0] reg_rdata , - output logic reg_ack , - - output logic [15:0] cfg_pwm0_high , - output logic [15:0] cfg_pwm0_low , - output logic [15:0] cfg_pwm1_high , - output logic [15:0] cfg_pwm1_low , - output logic [15:0] cfg_pwm2_high , - output logic [15:0] cfg_pwm2_low , - output logic [15:0] cfg_pwm3_high , - output logic [15:0] cfg_pwm3_low , - output logic [15:0] cfg_pwm4_high , - output logic [15:0] cfg_pwm4_low , - output logic [15:0] cfg_pwm5_high , - output logic [15:0] cfg_pwm5_low - - ); - -//----------------------------------------------------------------------- -// Internal Wire Declarations -//----------------------------------------------------------------------- - -logic sw_rd_en ; -logic sw_wr_en ; -logic [2:0] sw_addr ; // addressing 16 registers -logic [31:0] sw_reg_wdata ; -logic [3:0] sw_be ; - -logic [31:0] reg_out ; -logic [31:0] reg_0 ; // CONFIG - Unused -logic [31:0] reg_1 ; // PWM-REG-0 -logic [31:0] reg_2 ; // PWM-REG-1 -logic [31:0] reg_3 ; // PWM-REG-2 -logic [31:0] reg_4 ; // PWM-REG-3 -logic [31:0] reg_5 ; // PWM-REG-4 -logic [31:0] reg_6 ; // PWM-REG-5 - -assign sw_addr = reg_addr; -assign sw_rd_en = reg_cs & !reg_wr; -assign sw_wr_en = reg_cs & reg_wr; -assign sw_be = reg_be; -assign sw_reg_wdata = reg_wdata; - -//----------------------------------------------------------------------- -// register read enable and write enable decoding logic -//----------------------------------------------------------------------- -wire sw_wr_en_0 = sw_wr_en & (sw_addr == 3'h0); -wire sw_wr_en_1 = sw_wr_en & (sw_addr == 3'h1); -wire sw_wr_en_2 = sw_wr_en & (sw_addr == 3'h2); -wire sw_wr_en_3 = sw_wr_en & (sw_addr == 3'h3); -wire sw_wr_en_4 = sw_wr_en & (sw_addr == 3'h4); -wire sw_wr_en_5 = sw_wr_en & (sw_addr == 3'h5); -wire sw_wr_en_6 = sw_wr_en & (sw_addr == 3'h6); - -wire sw_rd_en_0 = sw_rd_en & (sw_addr == 3'h0); -wire sw_rd_en_1 = sw_rd_en & (sw_addr == 3'h1); -wire sw_rd_en_2 = sw_rd_en & (sw_addr == 3'h2); -wire sw_rd_en_3 = sw_rd_en & (sw_addr == 3'h3); -wire sw_rd_en_4 = sw_rd_en & (sw_addr == 3'h4); -wire sw_rd_en_5 = sw_rd_en & (sw_addr == 3'h5); -wire sw_rd_en_6 = sw_rd_en & (sw_addr == 3'h6); - - -always @ (posedge mclk or negedge h_reset_n) -begin : preg_out_Seq - if (h_reset_n == 1'b0) begin - reg_rdata <= 'h0; - reg_ack <= 1'b0; - end else if (reg_cs && !reg_ack) begin - reg_rdata <= reg_out; - reg_ack <= 1'b1; - end else begin - reg_ack <= 1'b0; - end -end - -//-------------------------------------------- -// reg-0: Reserve for pwm global config -//--------------------------------------------- -assign reg_0 = 'h0; -//----------------------------------------------------------------------- -// Logic for PWM-0 Config -//----------------------------------------------------------------------- -assign cfg_pwm0_low = reg_1[15:0]; // low period of w/f -assign cfg_pwm0_high = reg_1[31:16]; // high period of w/f - -gen_32b_reg #(32'h0) u_reg_1 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_1 ), - .we (sw_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_1 ) - ); - - -//----------------------------------------------------------------------- -// Logic for PWM-1 Config -//----------------------------------------------------------------------- -assign cfg_pwm1_low = reg_2[15:0]; // low period of w/f -assign cfg_pwm1_high = reg_2[31:16]; // high period of w/f -gen_32b_reg #(32'h0) u_reg_2 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_2 ), - .we (sw_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_2 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-2 Config -//----------------------------------------------------------------------- -assign cfg_pwm2_low = reg_3[15:0]; // low period of w/f -assign cfg_pwm2_high = reg_3[31:16]; // high period of w/f -gen_32b_reg #(32'h0) u_reg_3 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_3 ), - .we (sw_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_3 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-3 Config -//----------------------------------------------------------------------- -assign cfg_pwm3_low = reg_4[15:0]; // low period of w/f -assign cfg_pwm3_high = reg_4[31:16]; // high period of w/f -gen_32b_reg #(32'h0) u_reg_4 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_4 ), - .we (sw_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_4 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-4 Config -//----------------------------------------------------------------------- -assign cfg_pwm4_low = reg_5[15:0]; // low period of w/f -assign cfg_pwm4_high = reg_5[31:16]; // high period of w/f - -gen_32b_reg #(32'h0) u_reg_5 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_5 ), - .we (sw_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_5 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-5 Config -//----------------------------------------------------------------------- -assign cfg_pwm5_low = reg_6[15:0]; // low period of w/f -assign cfg_pwm5_high = reg_6[31:16]; // high period of w/f - -gen_32b_reg #(32'h0) u_reg_6 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_6 ), - .we (sw_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_6 ) - ); - - -always_comb -begin - reg_out [31:0] = 32'h0; - - case (sw_addr [2:0]) - 3'b000 : reg_out [31:0] = reg_0 [31:0]; - 3'b001 : reg_out [31:0] = reg_1 [31:0]; - 3'b010 : reg_out [31:0] = reg_2 [31:0]; - 3'b011 : reg_out [31:0] = reg_3 [31:0]; - 3'b100 : reg_out [31:0] = reg_4 [31:0]; - 3'b101 : reg_out [31:0] = reg_5 [31:0]; - 3'b110 : reg_out [31:0] = reg_6 [31:0]; - default : reg_out [31:0] = 32'h0; - endcase -end - -endmodule
diff --git a/verilog/rtl/pinmux/src/pwm_top.sv b/verilog/rtl/pinmux/src/pwm_top.sv deleted file mode 100644 index 2b8d3a5..0000000 --- a/verilog/rtl/pinmux/src/pwm_top.sv +++ /dev/null
@@ -1,172 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -////////////////////////////////////////////////////////////////////// -//// //// -//// PWM Top //// -//// //// -//// This file is part of the riscduino cores project //// -//// https://github.com/dineshannayya/riscduino.git //// -//// //// -//// Description //// -/// Includes 6 PWM //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// -//// //// -//// Revision : //// -//// 0.1 - 15th Aug 2022, Dinesh A //// -//// initial version //// -////////////////////////////////////////////////////////////////////// - -module pwm_top ( - // System Signals - // Inputs - input logic mclk, - input logic h_reset_n, - - // Reg Bus Interface Signal - input logic reg_cs, - input logic reg_wr, - input logic [2:0] reg_addr, - input logic [31:0] reg_wdata, - input logic [3:0] reg_be, - - // Outputs - output logic [31:0] reg_rdata, - output logic reg_ack, - - - input logic pulse_1ms, - input logic [5:0] cfg_pwm_enb, - output logic [5:0] pwm_wfm - - ); - -//--------------------------------------------------- -// 6 PWM variabled -//--------------------------------------------------- - -logic [15:0] cfg_pwm0_high ; -logic [15:0] cfg_pwm0_low ; -logic [15:0] cfg_pwm1_high ; -logic [15:0] cfg_pwm1_low ; -logic [15:0] cfg_pwm2_high ; -logic [15:0] cfg_pwm2_low ; -logic [15:0] cfg_pwm3_high ; -logic [15:0] cfg_pwm3_low ; -logic [15:0] cfg_pwm4_high ; -logic [15:0] cfg_pwm4_low ; -logic [15:0] cfg_pwm5_high ; -logic [15:0] cfg_pwm5_low ; - - - -pwm_reg u_reg ( - .mclk (mclk ), - .h_reset_n (h_reset_n ), - - // Reg Bus Interface Signal - .reg_cs (reg_cs ), - .reg_wr (reg_wr ), - .reg_addr (reg_addr ), - .reg_wdata (reg_wdata ), - .reg_be (reg_be ), - - // Outputs - .reg_rdata (reg_rdata ), - .reg_ack (reg_ack ), - - .cfg_pwm0_high (cfg_pwm0_high ), - .cfg_pwm0_low (cfg_pwm0_low ), - .cfg_pwm1_high (cfg_pwm1_high ), - .cfg_pwm1_low (cfg_pwm1_low ), - .cfg_pwm2_high (cfg_pwm2_high ), - .cfg_pwm2_low (cfg_pwm2_low ), - .cfg_pwm3_high (cfg_pwm3_high ), - .cfg_pwm3_low (cfg_pwm3_low ), - .cfg_pwm4_high (cfg_pwm4_high ), - .cfg_pwm4_low (cfg_pwm4_low ), - .cfg_pwm5_high (cfg_pwm5_high ), - .cfg_pwm5_low (cfg_pwm5_low ) - - ); - - -// 6 PWM Waveform Generator -pwm u_pwm_0 ( - .waveform (pwm_wfm[0] ), - .h_reset_n (h_reset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[0] ), - .cfg_pwm_high (cfg_pwm0_high ), - .cfg_pwm_low (cfg_pwm0_low ) - ); - -pwm u_pwm_1 ( - .waveform (pwm_wfm[1] ), - .h_reset_n (h_reset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[1] ), - .cfg_pwm_high (cfg_pwm1_high ), - .cfg_pwm_low (cfg_pwm1_low ) - ); - -pwm u_pwm_2 ( - .waveform (pwm_wfm[2] ), - .h_reset_n (h_reset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[2] ), - .cfg_pwm_high (cfg_pwm2_high ), - .cfg_pwm_low (cfg_pwm2_low ) - ); - -pwm u_pwm_3 ( - .waveform (pwm_wfm[3] ), - .h_reset_n (h_reset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[3] ), - .cfg_pwm_high (cfg_pwm3_high ), - .cfg_pwm_low (cfg_pwm3_low ) - ); -pwm u_pwm_4 ( - .waveform (pwm_wfm[4] ), - .h_reset_n (h_reset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[4] ), - .cfg_pwm_high (cfg_pwm4_high ), - .cfg_pwm_low (cfg_pwm4_low ) - ); -pwm u_pwm_5 ( - .waveform (pwm_wfm[5] ), - .h_reset_n (h_reset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[5] ), - .cfg_pwm_high (cfg_pwm5_high ), - .cfg_pwm_low (cfg_pwm5_low ) - ); - -endmodule
diff --git a/verilog/rtl/pwm/src/pwm.sv b/verilog/rtl/pwm/src/pwm.sv index df9cf3a..922c369 100644 --- a/verilog/rtl/pwm/src/pwm.sv +++ b/verilog/rtl/pwm/src/pwm.sv
@@ -19,6 +19,7 @@ input logic [7:0] pad_gpio , input logic cfg_pwm_enb , // pwm operation enable + input logic cfg_pwm_run , // pwm operation enable input logic [3:0] cfg_pwm_scale , // pwm clock scaling input logic cfg_pwm_oneshot , // pwm OneShot mode input logic cfg_pwm_frun , // pwm is free running @@ -49,7 +50,6 @@ logic comp1_match ; logic comp2_match ; logic comp3_match ; -logic gpio_fedge ; // GPIO first edge detection //-------------------------------- // Counter Scaling // In GPIO mode, wait for first GPIO transition @@ -60,15 +60,15 @@ if ( ~h_reset_n ) begin pwm_scnt <= 15'h0; end else begin - if(cfg_pwm_enb) begin - if(gpio_tgr || (cfg_pwm_gpio_enb && !gpio_fedge)) begin - pwm_scnt <= 15'h0; - end else begin - pwm_scnt <= pwm_scnt + 1; - end + //------------------------------------------------------- + // Added additional case to handle when new gpio trigger + // generated before completing the current Run + //------------------------------------------------------- + if(cfg_pwm_enb && cfg_pwm_run && !gpio_tgr) begin + pwm_scnt <= pwm_scnt + 1; end else begin - pwm_scnt <= 15'h0; - end + pwm_scnt <= 15'h0; + end end end @@ -125,10 +125,12 @@ pwm_ovflow_l <= 1'b0; end else begin pwm_ovflow_l <= pwm_ovflow; - if(cfg_pwm_enb) begin - if(gpio_tgr || (cfg_pwm_gpio_enb && !gpio_fedge)) begin - pwm_cnt <= 'h0; - end else if(cnt_trg) begin + //------------------------------------------------------- + // Added additional case to handle when new gpio trigger + // generated before completing the current Run + //------------------------------------------------------- + if(cfg_pwm_enb && cfg_pwm_run && !gpio_tgr) begin + if(cnt_trg) begin if(pwm_ovflow) begin pwm_cnt <= 'h0; end else begin @@ -229,7 +231,7 @@ else pwm_wfm_o = pwm_wfm_hold; end else begin if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_i; - pwm_wfm_o = pwm_wfm_i; + else pwm_wfm_o = pwm_wfm_i; end end @@ -247,21 +249,18 @@ begin if ( ~h_reset_n ) begin gpio_l <= 1'b0; - gpio_fedge <= 1'b0; gpio_tgr <= 1'b0; end else begin gpio_l <= gpio; if(cfg_pwm_enb && cfg_pwm_gpio_enb) begin + gpio_l <= gpio; if(cfg_pwm_gpio_edge) begin gpio_tgr <= gpio_ne; - gpio_fedge <= 1'b1; // gpio first edge detect end else begin gpio_tgr <= gpio_pe; - gpio_fedge <= 1'b1; end end else begin gpio_l <= 1'b0; - gpio_fedge <= 1'b0; gpio_tgr <= 1'b0; end end
diff --git a/verilog/rtl/pwm/src/pwm_blk_reg.sv b/verilog/rtl/pwm/src/pwm_blk_reg.sv index 450b580..9d9554d 100644 --- a/verilog/rtl/pwm/src/pwm_blk_reg.sv +++ b/verilog/rtl/pwm/src/pwm_blk_reg.sv
@@ -141,7 +141,7 @@ assign cfg_pwm_oneshot = pwm_cfg0[4]; assign cfg_pwm_frun = pwm_cfg0[5]; assign cfg_pwm_gpio_enb = pwm_cfg0[6]; -assign cfg_pwm_gpio_edge = pwm_cfg0[7]; +assign cfg_pwm_gpio_edge = pwm_cfg0[7]; // 1 -> negedge assign cfg_pwm_gpio_sel = pwm_cfg0[10:8]; assign cfg_pwm_hold = pwm_cfg0[11]; assign cfg_pwm_mode = pwm_cfg0[13:12];
diff --git a/verilog/rtl/pwm/src/pwm_core.sv b/verilog/rtl/pwm/src/pwm_core.sv index 9c708db..b0bb234 100644 --- a/verilog/rtl/pwm/src/pwm_core.sv +++ b/verilog/rtl/pwm/src/pwm_core.sv
@@ -33,6 +33,7 @@ output logic reg_ack , input logic cfg_pwm_enb , // pwm operation enable + input logic cfg_pwm_run , // pwm operation Run input logic cfg_pwm_dupdate , // Disable Config update input logic [7:0] pad_gpio , output logic pwm_wfm_o , @@ -120,6 +121,7 @@ .pad_gpio (pad_gpio ), .cfg_pwm_enb (cfg_pwm_enb ), + .cfg_pwm_run (cfg_pwm_run ), .cfg_pwm_scale (cfg_pwm_scale ), .cfg_pwm_oneshot (cfg_pwm_oneshot ), .cfg_pwm_frun (cfg_pwm_frun ),
diff --git a/verilog/rtl/pwm/src/pwm_glbl_reg.sv b/verilog/rtl/pwm/src/pwm_glbl_reg.sv index 3868a78..f3d9ae6 100644 --- a/verilog/rtl/pwm/src/pwm_glbl_reg.sv +++ b/verilog/rtl/pwm/src/pwm_glbl_reg.sv
@@ -55,6 +55,7 @@ output logic reg_ack , output logic [5:0] cfg_pwm_enb , // PWM operation enable + output logic [5:0] cfg_pwm_run , // PWM operation Run output logic [5:0] cfg_pwm_dupdate , // Disable Config update input logic [5:0] pwm_os_done , // Indicate oneshot sequence over @@ -77,7 +78,7 @@ logic [3:0] sw_be ; logic [31:0] reg_out ; -logic [5:0] reg_0 ; // CONFIG - Unused +logic [31:0] reg_0 ; // CONFIG - Unused logic [31:0] reg_1 ; // PWM-REG-0 logic [31:0] reg_2 ; // PWM-REG-1 logic [31:0] reg_3 ; // PWM-REG-2 @@ -120,41 +121,56 @@ // PWM Enable Generation //---------------------------------------- -assign cfg_pwm_enb = reg_0[5:0]; +assign cfg_pwm_enb = {3'b0,reg_0[2:0]}; +assign cfg_pwm_run = {3'b0,reg_0[10:8]}; +assign cfg_pwm_dupdate = {3'b0,reg_0[18:16]}; //------------------------------------------------------------------------ // Design wise has avoided the pwm_os_done & gpio_tgr occur at same cycle //------------------------------------------------------------------------ +logic [2:0] reg_0_0; always @ (posedge mclk or negedge h_reset_n) begin if (h_reset_n == 1'b0) begin - reg_0[5:0] <= 'h0; - end else if (reg_cs && sw_wr_en_0 && sw_be[0]) begin - reg_0[5:0] <= sw_reg_wdata[5:0] | gpio_tgr; - end else begin - reg_0[5:0] <= (reg_0[5:0] | gpio_tgr) ^ pwm_os_done; + reg_0_0[2:0] <= 'h0; + end else if (reg_cs && sw_wr_en_0 && sw_be[0] && reg_ack) begin + reg_0_0[2:0] <= sw_reg_wdata[2:0] ; end end +assign reg_0[2:0] = reg_0_0; // Modified due to iverilog issue +assign reg_0[7:3] = 'h0; +logic [2:0] reg_0_1; +always @ (posedge mclk or negedge h_reset_n) +begin + if (h_reset_n == 1'b0) begin + reg_0_1[2:0] <= 'h0; + end else if (reg_cs && sw_wr_en_0 && sw_be[1] && reg_ack) begin + reg_0_1[2:0] <= sw_reg_wdata[10:8] | gpio_tgr; + end else begin + reg_0_1[2:0] <= (reg_0_1[2:0] | gpio_tgr) ^ pwm_os_done; + end +end +assign reg_0[10:8] = reg_0_1; // Modified due to iverilog issue +assign reg_0[15:11] = 'h0; + +logic [2:0] reg_0_2; +always @ (posedge mclk or negedge h_reset_n) +begin + if (h_reset_n == 1'b0) begin + reg_0_2[2:0] <= 'h0; + end else if (reg_cs && sw_wr_en_0 && sw_be[2] && reg_ack) begin + reg_0_2[2:0] <= sw_reg_wdata[18:16] ; + end +end +assign reg_0[18:16] = reg_0_2; // Modified due to iverilog issue +assign reg_0[31:19] = 'h0; //----------------------------------------------------------------------- -// Logic for PWM-1 Config +// Logic for PWM-1 Config - Reserved //----------------------------------------------------------------------- -assign cfg_pwm_dupdate = reg_1[5:0]; +assign reg_1 = 'h0; -generic_register #(6,6'h0 ) u_reg_1 ( - .we ({6{sw_wr_en_1 & - reg_ack & - sw_be[0] }} ), - .data_in (sw_reg_wdata[5:0] ), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_1[5:0] ) - ); - -assign reg_1[31:6] = 'h0; //----------------------------------------------------------------------- // Reg-2: Interrupt Mask @@ -201,7 +217,7 @@ reg_out [31:0] = 32'h0; case (sw_addr [1:0]) - 2'b00 : reg_out [31:0] = {26'h0,reg_0 [5:0]}; + 2'b00 : reg_out [31:0] = reg_0 [31:0]; 2'b01 : reg_out [31:0] = reg_1 [31:0]; 2'b10 : reg_out [31:0] = reg_2 [31:0]; 2'b11 : reg_out [31:0] = reg_3 [31:0];
diff --git a/verilog/rtl/pwm/src/pwm_top.sv b/verilog/rtl/pwm/src/pwm_top.sv index e097c93..7e914d2 100644 --- a/verilog/rtl/pwm/src/pwm_top.sv +++ b/verilog/rtl/pwm/src/pwm_top.sv
@@ -62,10 +62,11 @@ ); //--------------------------------------------------- -// 6 PWM variabled +// 3 PWM variabled //--------------------------------------------------- logic [5:0] cfg_pwm_enb ; +logic [5:0] cfg_pwm_run ; logic [5:0] cfg_pwm_dupdate ; logic [5:0] pwm_os_done ; logic [5:0] pwm_ovflow ; @@ -101,18 +102,12 @@ assign reg_rdata = (reg_addr[4:2] == `SEL_GLBL) ? {reg_rdata_glbl} : (reg_addr[4:2] == `SEL_PWM0) ? {reg_rdata_pwm0} : (reg_addr[4:2] == `SEL_PWM1) ? {reg_rdata_pwm1} : - (reg_addr[4:2] == `SEL_PWM2) ? {reg_rdata_pwm2} : - (reg_addr[4:2] == `SEL_PWM3) ? {reg_rdata_pwm3} : - (reg_addr[4:2] == `SEL_PWM4) ? {reg_rdata_pwm4} : - (reg_addr[4:2] == `SEL_PWM5) ? {reg_rdata_pwm5} : 'h0; + (reg_addr[4:2] == `SEL_PWM2) ? {reg_rdata_pwm2} :'h0; assign reg_ack = (reg_addr[4:2] == `SEL_GLBL) ? reg_ack_glbl : (reg_addr[4:2] == `SEL_PWM0) ? reg_ack_pwm0 : (reg_addr[4:2] == `SEL_PWM1) ? reg_ack_pwm1 : - (reg_addr[4:2] == `SEL_PWM2) ? reg_ack_pwm2 : - (reg_addr[4:2] == `SEL_PWM3) ? reg_ack_pwm3 : - (reg_addr[4:2] == `SEL_PWM4) ? reg_ack_pwm4 : - (reg_addr[4:2] == `SEL_PWM5) ? reg_ack_pwm5 : 'h0; + (reg_addr[4:2] == `SEL_PWM2) ? reg_ack_pwm2 : 'h0; assign reg_cs_glbl = (reg_addr[4:2] == `SEL_GLBL) ? reg_cs : 1'b0; assign reg_cs_pwm[0] = (reg_addr[4:2] == `SEL_PWM0) ? reg_cs : 1'b0; @@ -138,6 +133,7 @@ .reg_ack (reg_ack_glbl ), .cfg_pwm_enb (cfg_pwm_enb ), + .cfg_pwm_run (cfg_pwm_run ), .cfg_pwm_dupdate (cfg_pwm_dupdate ), .pwm_os_done (pwm_os_done ), @@ -167,6 +163,7 @@ .reg_ack (reg_ack_pwm0 ), .cfg_pwm_enb (cfg_pwm_enb[0] ), // pwm operation enable + .cfg_pwm_run (cfg_pwm_run[0] ), // pwm operation enable .cfg_pwm_dupdate (cfg_pwm_dupdate[0] ), // Disable Config update .pad_gpio (pad_gpio ), .pwm_os_done (pwm_os_done[0] ), @@ -191,6 +188,7 @@ .reg_ack (reg_ack_pwm1 ), .cfg_pwm_enb (cfg_pwm_enb[1] ), // pwm operation enable + .cfg_pwm_run (cfg_pwm_run[1] ), // pwm operation enable .cfg_pwm_dupdate (cfg_pwm_dupdate[1] ), // Disable Config update .pad_gpio (pad_gpio ), .pwm_os_done (pwm_os_done[1] ), @@ -214,6 +212,7 @@ .reg_ack (reg_ack_pwm2 ), .cfg_pwm_enb (cfg_pwm_enb[2] ), // pwm operation enable + .cfg_pwm_run (cfg_pwm_run[2] ), // pwm operation enable .cfg_pwm_dupdate (cfg_pwm_dupdate[2] ), // Disable Config update .pad_gpio (pad_gpio ), .pwm_os_done (pwm_os_done[2] ), @@ -222,6 +221,9 @@ .pwm_wfm_o (pwm_wfm[2] ) ); + + +/*** pwm_core u_pwm_3( .h_reset_n (h_reset_n ), @@ -237,6 +239,7 @@ .reg_ack (reg_ack_pwm3 ), .cfg_pwm_enb (cfg_pwm_enb[3] ), // pwm operation enable + .cfg_pwm_run (cfg_pwm_run[3] ), // pwm operation enable .cfg_pwm_dupdate (cfg_pwm_dupdate[3] ), // Disable Config update .pad_gpio (pad_gpio ), .pwm_os_done (pwm_os_done[3] ), @@ -245,6 +248,13 @@ .pwm_wfm_o (pwm_wfm[3] ) ); +***/ +assign pwm_wfm[3] = pwm_wfm[0]; +assign pwm_os_done[3] = 1'b0; +assign pwm_ovflow[3] = 1'b0; +assign gpio_tgr[3] = 1'b0; + +/**** pwm_core u_pwm_4( .h_reset_n (h_reset_n ), @@ -260,6 +270,7 @@ .reg_ack (reg_ack_pwm4 ), .cfg_pwm_enb (cfg_pwm_enb[4] ), // pwm operation enable + .cfg_pwm_run (cfg_pwm_run[4] ), // pwm operation enable .cfg_pwm_dupdate (cfg_pwm_dupdate[4] ), // Disable Config update .pad_gpio (pad_gpio ), .pwm_os_done (pwm_os_done[4] ), @@ -268,6 +279,13 @@ .pwm_wfm_o (pwm_wfm[4] ) ); +***/ +assign pwm_wfm[4] = pwm_wfm[1]; +assign pwm_os_done[4] = 1'b0; +assign pwm_ovflow[4] = 1'b0; +assign gpio_tgr[4] = 1'b0; + +/*** pwm_core u_pwm_5( .h_reset_n (h_reset_n ), @@ -283,6 +301,7 @@ .reg_ack (reg_ack_pwm5 ), .cfg_pwm_enb (cfg_pwm_enb[5] ), // pwm operation enable + .cfg_pwm_run (cfg_pwm_run[5] ), // pwm operation enable .cfg_pwm_dupdate (cfg_pwm_dupdate[5] ), // Disable Config update .pad_gpio (pad_gpio ), .pwm_os_done (pwm_os_done[5] ), @@ -292,4 +311,10 @@ ); +**/ +assign pwm_wfm[5] = pwm_wfm[2]; +assign pwm_os_done[5] = 1'b0; +assign pwm_ovflow[5] = 1'b0; +assign gpio_tgr[5] = 1'b0; + endmodule
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv index 6f0f17f..97a3cae 100755 --- a/verilog/rtl/sspim/src/sspim_top.sv +++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -132,6 +132,13 @@ logic cfg_cpol ; // spi clock idle phase logic cfg_cpha ; // spi data sample and lanch phase +logic shift ; +logic sample ; +logic sck_int ; +logic sck_active ; +logic cs_int_n ; +logic load_byte ; + sspim_if u_spi_if ( . clk (clk ),
diff --git a/verilog/rtl/uart/src/uart_cfg.sv b/verilog/rtl/uart/src/uart_cfg.sv index ca4dea6..14297c4 100644 --- a/verilog/rtl/uart/src/uart_cfg.sv +++ b/verilog/rtl/uart/src/uart_cfg.sv
@@ -271,17 +271,17 @@ 4'b0010 : reg_out [7:0] = reg_2 [7:0]; 4'b0011 : reg_out [7:0] = reg_3 [7:0]; 4'b0100 : reg_out [7:0] = reg_4 [7:0]; - 4'b0101 : reg_out [7:0] = reg_5 [7:0]; + 4'b0101 : reg_out [7:0] = 'h0; 4'b0110 : reg_out [7:0] = reg_6 [7:0]; 4'b0111 : reg_out [7:0] = reg_7 [7:0]; 4'b1000 : reg_out [7:0] = reg_8 [7:0]; - 4'b1001 : reg_out [7:0] = reg_9 [7:0]; - 4'b1010 : reg_out [7:0] = reg_10 [7:0]; - 4'b1011 : reg_out [7:0] = reg_11 [7:0]; - 4'b1100 : reg_out [7:0] = reg_12 [7:0]; - 4'b1101 : reg_out [7:0] = reg_13 [7:0]; - 4'b1110 : reg_out [7:0] = reg_14 [7:0]; - 4'b1111 : reg_out [7:0] = reg_15 [7:0]; + 4'b1001 : reg_out [7:0] = 'h0; + 4'b1010 : reg_out [7:0] = 'h0; + 4'b1011 : reg_out [7:0] = 'h0; + 4'b1100 : reg_out [7:0] = 'h0; + 4'b1101 : reg_out [7:0] = 'h0; + 4'b1110 : reg_out [7:0] = 'h0; + 4'b1111 : reg_out [7:0] = 'h0; endcase end
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv index 653e285..b9b0186 100644 --- a/verilog/rtl/uart/src/uart_core.sv +++ b/verilog/rtl/uart/src/uart_core.sv
@@ -192,6 +192,7 @@ //############################################################### wire line_clk_16x_in; +wire line_clk_16x; // OpenSource CTS tool does not work with buffer as source point // changed buf to max with select tied=0
diff --git a/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v b/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v index f83656d..83d444c 100644 --- a/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v +++ b/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v
@@ -633,7 +633,6 @@ //----------------------------------------------------------------- // Tx //----------------------------------------------------------------- -wire out_bit_w = sample_w ? data_q[0] : 1'bz; always @ (posedge clk_i or negedge rstn_i) if (!rstn_i)
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 090578d..048116a 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -756,6 +756,11 @@ wire [1:0] pll_clk_out ; // Two 90 degree clock phases wire [3:0] spi_csn ; +wire xtal_clk ; +wire e_reset_n ; +wire p_reset_n ; +wire s_reset_n ; +wire cfg_strap_pad_ctrl ; //--------------------------------------------------------------------- // Strap
diff --git a/verilog/rtl/ws281x/src/ws281x_reg.sv b/verilog/rtl/ws281x/src/ws281x_reg.sv index 741ece1..0444b92 100644 --- a/verilog/rtl/ws281x/src/ws281x_reg.sv +++ b/verilog/rtl/ws281x/src/ws281x_reg.sv
@@ -171,6 +171,8 @@ .data_out (reg_0[3:0] ) ); +assign reg_0[31:4] = 'h0; + // CONFIG-0 assign cfg_reset_period = reg_1[15:0]; gen_16b_reg #(32'h0) u_reg_1 ( @@ -185,6 +187,8 @@ .data_out (reg_1[15:0] ) ); +assign reg_1[31:16] = 0; + // CONFIG-1 assign cfg_th1_period = reg_2[29:20]; // High Exit Period for Data-1 @@ -237,7 +241,7 @@ generate for (port = 0; $unsigned(port) < NP; port=port+1) begin : gfifo -sync_fifo #(.W(24), .D(8)) u_fifo +sync_fifo #(.W(24), .D(2)) u_fifo ( .clk (mclk ), .reset_n (h_reset_n ),