tb clean up
diff --git a/Makefile b/Makefile index b89e69f..4cd69b5 100644 --- a/Makefile +++ b/Makefile
@@ -86,15 +86,12 @@ $(blocks): % : export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $* -dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d) -dv-targets-rtl=$(dv_patterns:%=verify-%-rtl) -dv-targets-gl=$(dv_patterns:%=verify-%-gl) -dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf) +PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d) +DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv)) TARGET_PATH=$(shell pwd) verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make" -dv_base_dependencies= ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo -docker_run_verify=\ +$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ @@ -107,40 +104,13 @@ -u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:latest \ sh -c $(verify_command) -.PHONY: harden -harden: $(blocks) .PHONY: verify -verify: $(dv-targets) +verify: + cd ./verilog/dv/ && \ + export SIM=${SIM} DUMP=${DUMP} && \ + $(MAKE) -j$(THREADS) -$(dv-targets-rtl): SIM=RTL -$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies) - $(docker_run_verify) - -$(dv-targets-gl): SIM=GL -$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies) - $(docker_run_verify) - -$(dv-targets-gl-sdf): SIM=GL_SDF -$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) - $(docker_run_verify) - -clean-targets=$(blocks:%=clean-%) -.PHONY: $(clean-targets) -$(clean-targets): clean-% : - rm -f ./verilog/gl/$*.v - rm -f ./spef/$*.spef - rm -f ./sdc/$*.sdc - rm -f ./sdf/$*.sdf - rm -f ./gds/$*.gds - rm -f ./mag/$*.mag - rm -f ./lef/$*.lef - rm -f ./maglef/*.maglef - -make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets) -.PHONY: what -what: - # $(make_what) # Install Openlane .PHONY: openlane
diff --git a/README.md b/README.md index b912298..801efe8 100644 --- a/README.md +++ b/README.md
@@ -210,6 +210,7 @@ Following Design changes are done on the basic version of syntacore RISC core ``` * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys + * local Instruction Memory is increased from 4 to 8 location * Instruction Request are changed from Single word to 4 Word Burst * Multiplication and Divsion are changed to improve timing * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index 4422d7d..3ed4d9b 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index 6883700..21064f9 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -4,6 +4,7 @@ SIM ?= RTL DUMP ?= OFF +TOOLS?=/opt/riscv64i/ # PARAMETERS
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile index 0746413..3a63981 100644 --- a/verilog/dv/uart_master/Makefile +++ b/verilog/dv/uart_master/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index 37feef0..a00533a 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile index e7d9b13..edab839 100644 --- a/verilog/dv/user_i2cm/Makefile +++ b/verilog/dv/user_i2cm/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile index 96815e2..03f0bcc 100644 --- a/verilog/dv/user_pwm/Makefile +++ b/verilog/dv/user_pwm/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile index 1932afc..9c375e6 100644 --- a/verilog/dv/user_qspi/Makefile +++ b/verilog/dv/user_qspi/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile index 4a0c488..14a0f1e 100644 --- a/verilog/dv/user_risc_boot/Makefile +++ b/verilog/dv/user_risc_boot/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index 0538cb1..fd2fda2 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -74,6 +74,8 @@ `timescale 1 ns / 1 ns +`include "DFFRAM/DFFRAM.v" + module user_risc_boot_tb; reg clock; reg wb_rst_i;
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile index 9d8bd45..eb764f0 100644 --- a/verilog/dv/user_sspi/Makefile +++ b/verilog/dv/user_sspi/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -73,6 +74,6 @@ # ---- Clean ---- clean: - rm -f *.vvp *.vcd *.log *.fst + rm -rf *.vvp *.vcd *.log *.fst .PHONY: clean hex all
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile index 6520c31..6d04ada 100644 --- a/verilog/dv/user_timer/Makefile +++ b/verilog/dv/user_timer/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v index dab309a..b40fd0f 100644 --- a/verilog/dv/user_timer/user_timer_tb.v +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -66,6 +66,8 @@ `timescale 1 ns / 1 ps +`include "DFFRAM/DFFRAM.v" + `define TB_GLBL user_timer_tb
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile index 97726ee..508b1df 100644 --- a/verilog/dv/user_uart/Makefile +++ b/verilog/dv/user_uart/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile index 046c8df..104d358 100644 --- a/verilog/dv/user_uart1/Makefile +++ b/verilog/dv/user_uart1/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v index 4946c9f..47a5406 100644 --- a/verilog/dv/user_uart1/user_uart1_tb.v +++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -74,7 +74,7 @@ `timescale 1 ns/1 ps -`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "DFFRAM/DFFRAM.v" `include "uart_agent.v"
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile index a25bc69..d6b53cd 100644 --- a/verilog/dv/user_usb/Makefile +++ b/verilog/dv/user_usb/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index f1e498d..ff00f62 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -43,6 +43,7 @@ `define TB_GLBL user_usb_tb `define USB_BFM u_usb_agent +`include "DFFRAM/DFFRAM.v" `include "usb_agents.v" `include "test_control.v" `include "usb1d_defines.v"
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 633a369..b05a05f 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index c07e16e..78e63ae 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -496,24 +496,24 @@ * Pin Mapping ATMGE CONFIG * ATMEGA328 caravel Pin Mapping * Pin-1 PC6/RESET* digital_io[0] -* Pin-2 PD0/RXD digital_io[1] -* Pin-3 PD1/TXD digital_io[2] -* Pin-4 PD2/INT0 digital_io[3] +* Pin-2 PD0/RXD[0] digital_io[1] +* Pin-3 PD1/TXD[0] digital_io[2] +* Pin-4 PD2/RXD[1]/INT0 digital_io[3] * Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] -* Pin-6 PD4 digital_io[5] +* Pin-6 PD4/TXD[1] digital_io[5] * Pin-7 VCC - * Pin-8 GND - * Pin-9 PB6/XTAL1/TOSC1 digital_io[6] -* Pin-10 PB7/XTAL2/TOSC2 digital_io[7] -* Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] -* Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] -* Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] -* Pin-14 PB0/CLKO/ICP1 digital_io[11] -* Pin-15 PB1/OC1A(PWM3) digital_io[12] -* Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] -* Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] -* Pin-18 PB4/MISO digital_io[15] -* Pin-19 PB5/SCK digital_io[16] +* Pin-10 PB7/XTAL2/TOSC2 digital_io[7] +* Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] +* Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] +* Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] +* Pin-14 PB0/CLKO/ICP1 digital_io[11] +* Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[12] +* Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] +* Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] +* Pin-18 PB4/MISO digital_io[15] +* Pin-19 PB5/SCK digital_io[16] * Pin-20 AVCC - * Pin-21 AREF analog_io[10] * Pin-22 GND -