| ############################################################################### |
| # Created by write_sdc |
| # Sat Nov 26 13:14:33 2022 |
| ############################################################################### |
| current_design ycr_iconnect |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name core_clk -period 10.0000 [get_ports {core_clk}] |
| set_clock_transition 0.1500 [get_clocks {core_clk}] |
| set_clock_uncertainty -setup 0.5000 core_clk |
| set_clock_uncertainty -hold 0.2500 core_clk |
| set_propagated_clock [get_clocks {core_clk}] |
| create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {tcm clock0} [get_ports {sram0_clk0}] |
| set_clock_transition 0.1500 [get_clocks {sram0_clk0}] |
| set_clock_uncertainty -setup 0.5000 sram0_clk0 |
| set_clock_uncertainty -hold 0.2500 sram0_clk0 |
| set_propagated_clock [get_clocks {sram0_clk0}] |
| create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {tcm clock1} [get_ports {sram0_clk1}] |
| set_clock_transition 0.1500 [get_clocks {sram0_clk1}] |
| set_clock_uncertainty -setup 0.5000 sram0_clk1 |
| set_clock_uncertainty -hold 0.2500 sram0_clk1 |
| set_propagated_clock [get_clocks {sram0_clk1}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[0]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[10]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[11]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[12]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[13]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[14]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[15]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[16]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[17]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[18]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[19]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[1]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[20]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[21]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[22]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[23]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[24]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[25]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[26]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[27]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[28]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[29]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[2]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[30]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[31]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[3]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[4]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[5]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[6]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[7]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[8]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[9]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_cmd}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_cmd}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_req}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_req}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[0]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[10]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[11]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[12]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[13]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[14]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[15]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[16]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[17]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[18]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[19]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[1]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[20]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[21]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[22]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[23]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[24]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[25]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[26]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[27]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[28]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[29]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[2]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[30]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[31]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[3]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[4]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[5]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[6]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[7]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[8]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[9]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[0]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[1]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[0]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[10]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[11]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[12]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[13]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[14]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[15]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[16]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[17]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[18]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[19]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[1]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[20]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[21]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[22]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[23]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[24]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[25]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[26]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[27]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[28]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[29]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[2]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[30]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[31]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[3]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[4]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[5]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[6]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[7]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[8]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[9]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[0]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[1]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[2]}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_cmd}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_cmd}] |
| set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_req}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_req}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[9]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[0]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[10]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[10]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[11]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[11]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[12]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[12]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[13]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[13]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[14]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[14]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[15]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[15]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[16]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[16]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[17]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[17]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[18]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[18]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[19]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[19]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[1]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[20]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[20]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[21]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[21]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[22]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[22]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[23]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[23]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[24]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[24]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[25]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[25]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[26]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[26]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[27]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[27]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[28]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[28]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[29]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[29]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[2]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[2]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[30]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[30]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[31]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[31]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[3]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[3]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[4]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[4]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[5]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[5]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[6]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[6]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[7]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[7]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[8]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[8]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[9]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[9]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_req_ack}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_req_ack}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[0]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[10]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[10]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[11]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[11]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[12]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[12]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[13]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[13]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[14]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[14]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[15]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[15]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[16]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[16]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[17]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[17]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[18]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[18]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[19]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[19]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[1]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[20]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[20]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[21]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[21]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[22]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[22]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[23]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[23]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[24]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[24]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[25]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[25]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[26]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[26]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[27]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[27]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[28]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[28]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[29]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[29]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[2]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[2]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[30]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[30]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[31]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[31]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[3]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[3]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[4]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[4]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[5]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[5]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[6]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[6]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[7]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[7]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[8]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[8]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[9]}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[9]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_req_ack}] |
| set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_req_ack}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_csb0}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_csb0}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_csb1}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_csb1}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[10]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[10]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[11]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[11]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[12]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[12]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[13]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[13]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[14]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[14]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[15]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[15]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[16]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[16]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[17]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[17]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[18]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[18]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[19]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[19]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[20]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[20]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[21]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[21]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[22]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[22]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[23]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[23]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[24]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[24]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[25]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[25]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[26]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[26]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[27]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[27]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[28]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[28]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[29]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[29]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[30]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[30]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[31]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[31]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[9]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[9]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_web0}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_web0}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[3]}] |
| set_max_delay\ |
| -to [get_ports {core_icache_req}] 5.0000 |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_cmd}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_req}] |
| set_load -pin_load 0.0334 [get_ports {cfg_dcache_force_flush}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_req_ack}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_req_ack}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_soft}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_irq}] |
| set_load -pin_load 0.0334 [get_ports {core_clk_skew}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_cmd}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_req}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_cmd}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_req}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_cmd}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_req}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_cmd}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_req}] |
| set_load -pin_load 0.0334 [get_ports {sram0_clk0}] |
| set_load -pin_load 0.0334 [get_ports {sram0_clk1}] |
| set_load -pin_load 0.0334 [get_ports {sram0_csb0}] |
| set_load -pin_load 0.0334 [get_ports {sram0_csb1}] |
| set_load -pin_load 0.0334 [get_ports {sram0_web0}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_width[1]}] |
| set_load -pin_load 0.0334 [get_ports {aes_dmem_width[0]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {core0_dmem_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_resp[1]}] |
| set_load -pin_load 0.0334 [get_ports {core0_imem_resp[0]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[31]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[30]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[29]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[28]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[27]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[26]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[25]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[24]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[23]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[22]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[21]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[20]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[19]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[18]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[17]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[16]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[15]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[14]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[13]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[12]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[11]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[10]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[9]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[8]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[7]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[6]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[5]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[4]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[3]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[2]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[1]}] |
| set_load -pin_load 0.0334 [get_ports {core0_irq_lines[0]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[63]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[62]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[61]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[60]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[59]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[58]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[57]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[56]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[55]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[54]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[53]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[52]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[51]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[50]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[49]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[48]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[47]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[46]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[45]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[44]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[43]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[42]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[41]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[40]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[39]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[38]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[37]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[36]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[35]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[34]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[33]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[32]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[31]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[30]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[29]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[28]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[27]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[26]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[25]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[24]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[23]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[22]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[21]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[20]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[19]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[18]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[17]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[16]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[15]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[14]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[13]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[12]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[11]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[10]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[9]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[8]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[7]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[6]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[5]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[4]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[3]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[2]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[1]}] |
| set_load -pin_load 0.0334 [get_ports {core0_timer_val[0]}] |
| set_load -pin_load 0.0334 [get_ports {core0_uid[1]}] |
| set_load -pin_load 0.0334 [get_ports {core0_uid[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_width[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_dcache_width[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_bl[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_bl[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_bl[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_width[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_dmem_width[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_bl[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_bl[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_bl[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_width[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_icache_width[0]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_width[1]}] |
| set_load -pin_load 0.0334 [get_ports {fpu_dmem_width[0]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[63]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[62]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[61]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[60]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[59]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[58]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[57]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[56]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[55]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[54]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[53]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[52]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[51]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[50]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[49]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[48]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[47]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[46]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[45]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[44]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[43]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[42]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[41]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[40]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[39]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[38]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[37]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[36]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[35]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[34]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[33]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[32]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[31]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[30]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[29]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[28]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[27]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[26]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[25]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[24]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[23]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[22]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[21]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[20]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[19]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[18]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[17]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[16]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[15]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[14]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[13]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[12]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[11]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[10]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[9]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[8]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[7]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[6]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[5]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[4]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[3]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[2]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[1]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[31]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[30]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[29]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[28]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[27]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[26]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[25]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[24]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[23]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[22]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[21]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[20]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[19]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[18]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[17]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[16]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[15]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[14]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[13]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[12]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[11]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[10]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[9]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_req_ack}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_dcache}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_icache}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_cmd}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_req}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_cmd}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_req}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_req_ack}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_req_ack}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_req_ack}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_soft_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_intf_rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_req_ack}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_width[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_width[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_resp[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_resp[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[0]}] |
| set_case_analysis 0 [get_ports {cfg_sram_lphase[0]}] |
| set_case_analysis 0 [get_ports {cfg_sram_lphase[1]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_transition 1.0000 [current_design] |
| set_max_capacitance 0.2000 [current_design] |
| set_max_fanout 10.0000 [current_design] |
