riscv interrupt changed from 16 to 32 and gpio interrupt bug fix, uart master disable option
diff --git a/.gitmodules b/.gitmodules index 948b37f..72dbb4f 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -1,9 +1,9 @@ [submodule "verilog/rtl/qspim"] path = verilog/rtl/qspim url = https://github.com/dineshannayya/qspim.git -[submodule "verilog/rtl/yifive/ycr1c"] - path = verilog/rtl/yifive/ycr1c - url = https://github.com/dineshannayya/ycr1cr.git [submodule "verilog/dv/common/riscduino_board"] path = verilog/dv/common/riscduino_board url = https://github.com/dineshannayya/riscduino_board.git +[submodule "verilog/rtl/yifive/ycr1cr"] + path = verilog/rtl/yifive/ycr1c + url = https://github.com/dineshannayya/ycr1cr.git
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v index acd36fe..3d47721 100644 --- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v +++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -248,7 +248,7 @@ test_fail = 0; end begin - repeat (30000) @(posedge clock); // wait for Processor Get Ready + repeat (40000) @(posedge clock); // wait for Processor Get Ready test_fail = 1; end join_any
diff --git a/verilog/dv/arduino_gpio_intr/Makefile b/verilog/dv/arduino_gpio_intr/Makefile new file mode 100644 index 0000000..0bf70cf --- /dev/null +++ b/verilog/dv/arduino_gpio_intr/Makefile
@@ -0,0 +1,140 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. +TOOLS?=/opt/riscv32i/ + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC_PREFIX?=riscv32-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = arduino_gpio_intr + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o + ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o + ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o + ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o + ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o + ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o + ${GCC_PREFIX}-ar rcs core.a Print.cpp.o + ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o + ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o + ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o + ${GCC_PREFIX}-ar rcs core.a WString.cpp.o + ${GCC_PREFIX}-ar rcs core.a abi.cpp.o + ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o + ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o + ${GCC_PREFIX}-ar rcs core.a entry.S.o + ${GCC_PREFIX}-ar rcs core.a hooks.c.o + ${GCC_PREFIX}-ar rcs core.a init.S.o + ${GCC_PREFIX}-ar rcs core.a itoa.c.o + ${GCC_PREFIX}-ar rcs core.a main.cpp.o + ${GCC_PREFIX}-ar rcs core.a malloc.c.o + ${GCC_PREFIX}-ar rcs core.a new.cpp.o + ${GCC_PREFIX}-ar rcs core.a sbrk.c.o + ${GCC_PREFIX}-ar rcs core.a start.S.o + ${GCC_PREFIX}-ar rcs core.a wiring.c.o + ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o + ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o + ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o + ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + rm *.o *.a +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + endif +else + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif +endif + +%.vcd: %.vvp + vvp $< +risc_core_id=$(RISC_CORE) + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o + +.PHONY: clean hex all
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino new file mode 100644 index 0000000..fd1a9fe --- /dev/null +++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino
@@ -0,0 +1,73 @@ + +/* + + Analog input, analog output, serial output + + Reads an analog input pin, maps the result to a range from 0 to 255 and uses + + the result to set the pulse width modulation (PWM) of an output pin. + + Also prints the results to the Serial Monitor. + + The circuit: + + - potentiometer connected to analog pin 0. + + Center pin of the potentiometer goes to the analog pin. + + side pins of the potentiometer go to +5V and ground + + - LED connected from digital pin 9 to ground + + created 29 Dec. 2008 + + modified 9 Apr 2012 + + by Tom Igoe + + This example code is in the public domain. + + http://www.arduino.cc/en/Tutorial/AnalogInOutSerial + +*/ + +#include"Arduino.h" +// These constants won't change. They're used to give names to the pins used: + + +int but1=2; +int but2=3; + + +int pwmValue =0; +void setup() { + + // initialize serial communications at 9600 bps: + Serial.begin(9600); + +} + +void loop() { + + attachInterrupt(digitalPinToInterrupt(but1),increase,LOW); + attachInterrupt(digitalPinToInterrupt(but2),reset_pwm,FALLING); + + + + delay(1); +} + + +void increase() + { + pwmValue = pwmValue + 10; + if(pwmValue > 255) pwmValue = 0;; + + Serial.print("String length is: "); + Serial.println(pwmValue); + + + } + void reset_pwm(){ + pwmValue =0; // 0V + } \ No newline at end of file
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino.cpp b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino.cpp new file mode 100644 index 0000000..8c75087 --- /dev/null +++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino.cpp
@@ -0,0 +1,67 @@ + +/* +Testing the GPIO Interrupt + +*/ + +#include"Arduino.h" +// These constants won't change. They're used to give names to the pins used: + + + + +int pwmValue =0; +void setup(); +void loop(); +void increase_2(); +void decrease_1(); +void setup() { + + // initialize serial communications at 9600 bps: + Serial.begin(1152000); + //attachInterrupt(digitalPinToInterrupt(0),increase_2,RISING); // Exclude UART + //attachInterrupt(digitalPinToInterrupt(1),decrease_1,FALLING); // Exclude UART + attachInterrupt(digitalPinToInterrupt(2),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(3),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(4),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(5),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(6),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(7),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(8),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(9),decrease_1,FALLING); + + attachInterrupt(digitalPinToInterrupt(10),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(11),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(12),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(13),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(14),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(15),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(16),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(17),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(18),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(19),decrease_1,FALLING); + + attachInterrupt(digitalPinToInterrupt(20),increase_2,RISING); + attachInterrupt(digitalPinToInterrupt(21),decrease_1,FALLING); + attachInterrupt(digitalPinToInterrupt(22),increase_2,RISING); +} + +void loop() { + + delay(1); +} + + +void decrease_1() { + pwmValue = pwmValue - 1; + + Serial.print("PWM Value Decrease to: "); + Serial.println(pwmValue); + } + +void increase_2() { + pwmValue = pwmValue + 2; + + Serial.print("PWM Value Increase to: "); + Serial.println(pwmValue); + }
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v new file mode 100644 index 0000000..6e509dc --- /dev/null +++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
@@ -0,0 +1,645 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the riscdunio cores project //// +//// https://github.com/dineshannayya/riscdunio.git //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core. //// +//// This test bench to validate Arduino Interrupt //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesh.annayya@gmail.com //// +//// //// +//// Revision : //// +//// 0.1 - 29th July 2022, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ns + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "uart_agent.v" + +`define TB_HEX "arduino_gpio_intr.ino.hex" +`define TB_TOP arduino_gpio_intr_tb + +module `TB_TOP; + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + //---------------------------------- + // Uart Configuration + // --------------------------------- + reg [1:0] uart_data_bit ; + reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; + reg uart_stick_parity ; // 1: force even parity + reg uart_parity_en ; // parity enable + reg uart_even_odd_parity ; // 0: odd parity; 1: even parity + + reg [7:0] uart_data ; + reg [15:0] uart_divisor ; // divided by n * 16 + reg [15:0] uart_timeout ;// wait time limit + + reg [15:0] uart_rx_nu ; + reg [15:0] uart_tx_nu ; + reg [7:0] uart_write_data [0:39]; + reg uart_fifo_enable ; // fifo mode disable + reg flag ; + reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting + + reg [31:0] check_sum ; + + integer d_risc_id; + + integer i,j; + + + + + // 50Mhz CLock + always #10 clock <= (clock === 1'b0); + + initial begin + clock = 0; + flag = 0; + compare_start = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(3, `TB_TOP); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top); + $dumpvars(0, `TB_TOP.u_top.u_pinmux); + end + `endif + + + wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines; + + +/********************************************************************** + Arduino Digital PinMapping + ATMGA328 Pin No Functionality Arduino Pin Carvel Pin Mapping + Pin-2 PD0/RXD[0] 0 digital_io[1] + Pin-3 PD1/TXD[0] 1 digital_io[2] + Pin-4 PD2/RXD[1]/INT0 2 digital_io[3] + Pin-5 PD3/INT1/OC2B(PWM0) 3 digital_io[4] + Pin-6 PD4/TXD[1] 4 digital_io[5] + Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 5 digital_io[8] + Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 6 digital_io[9] /analog_io[2] + Pin-13 PD7/A1N1 7 digital_io[10]/analog_io[3] + Pin-14 PB0/CLKO/ICP1 8 digital_io[11] + Pin-15 PB1/SS[1]OC1A(PWM3) 9 digital_io[12] + Pin-16 PB2/SS[0]/OC1B(PWM4) 10 digital_io[13] + Pin-17 PB3/MOSI/OC2A(PWM5) 11 digital_io[14] + Pin-18 PB4/MISO 12 digital_io[15] + Pin-19 PB5/SCK 13 digital_io[16] + + Pin-23 ADC0 14 digital_io[18] + Pin-24 ADC1 15 digital_io[19] + Pin-25 ADC2 16 digital_io[20] + Pin-26 ADC3 17 digital_io[21] + Pin-27 SDA 18 digital_io[22] + Pin-28 SCL 19 digital_io[23] + + Pin-9 XTAL1 20 digital_io[6] + Pin-10 XTAL2 21 digital_io[7] + Pin-1 RESET 22 digital_io[0] +*****************************************************************************/ + +// Exclude UART TXD/RXD and RESET +reg [21:2] arduino_din; +assign { + //io_in[0], - Exclude RESET + io_in[7], + io_in[6], + io_in[23], + io_in[22], + io_in[21], + io_in[20], + io_in[19], + io_in[18], + io_in[16], + io_in[15], + io_in[14], + io_in[13], + io_in[12], + io_in[11], + io_in[10], + io_in[9], + io_in[8], + io_in[5], + io_in[4], + io_in[3] + // Uart pins io_in[2], io_in[1] are excluded + } = arduino_din; + + /************************************************************************* + * This is Baud Rate to clock divider conversion for Test Bench + * Note: DUT uses 16x baud clock, where are test bench uses directly + * baud clock, Due to 16x Baud clock requirement at RTL, there will be + * some resolution loss, we expect at lower baud rate this resolution + * loss will be less. For Quick simulation perpose higher baud rate used + * *************************************************************************/ + task tb_set_uart_baud; + input [31:0] ref_clk; + input [31:0] baud_rate; + output [31:0] baud_div; + reg [31:0] baud_div; + begin + // for 230400 Baud = (50Mhz/230400) = 216.7 + baud_div = ref_clk/baud_rate; // Get the Bit Baud rate + // Baud 16x = 216/16 = 13 + baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench + // Test bench baud clock , 16x of above value + // 13 * 16 = 208, + // (Note if you see original value was 216, now it's 208 ) + baud_div = baud_div * 16; + // Test bench half cycle counter to toggle it + // 208/2 = 104 + baud_div = baud_div/2; + //As counter run's from 0 , substract from 1 + baud_div = baud_div-1; + end + endtask + + + reg[7:0] pinmap[0:22]; //ardiono to gpio pinmaping + + initial begin + arduino_din[22:2] = 23'b010_1010_1010_1010_1010_10; // Initialise based on test case edge + pinmap[0] = 24; + pinmap[1] = 25; + pinmap[2] = 26; + pinmap[3] = 27; + pinmap[4] = 28; + pinmap[5] = 29; + pinmap[6] = 30; + pinmap[7] = 31; + pinmap[8] = 8; + pinmap[9] = 9; + pinmap[10] = 10; + pinmap[11] = 11; + pinmap[12] = 12; + pinmap[13] = 13; + pinmap[14] = 16; + pinmap[15] = 17; + pinmap[16] = 18; + pinmap[17] = 19; + pinmap[18] = 20; + pinmap[19] = 21; + pinmap[20] = 14; + pinmap[21] = 15; + pinmap[22] = 22; + + + uart_data_bit = 2'b11; + uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; + uart_stick_parity = 0; // 1: force even parity + uart_parity_en = 0; // parity enable + uart_even_odd_parity = 1; // 0: odd parity; 1: even parity + tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 + uart_timeout = 20000;// wait time limit + uart_fifo_enable = 0; // fifo mode disable + + $value$plusargs("risc_core_id=%d", d_risc_id); + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Risc Boot Test Started"); + + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + repeat (2) @(posedge clock); + #1; + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 3"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); + end + + repeat (100) @(posedge clock); // wait for Processor Get Ready + + tb_uart.debug_mode = 0; // disable debug display + tb_uart.uart_init; + tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, + uart_stick_parity, uart_timeout, uart_divisor); + + repeat (80000) @(posedge clock); // wait for Processor Get Ready + flag = 0; + check_sum = 0; + compare_start = 1; + + fork + + begin + $display("Start : Processing One Interrupt At a Time "); + // Interrupt- One After One + for(i =2; i < 22; i = i+1) begin + arduino_din[i] = !arduino_din[i]; // Invert the edge to create interrupt; + repeat (10) @(posedge clock); + arduino_din[i] = !arduino_din[i]; // Invert the edge to remove the interrupt + repeat (10) @(posedge clock); + wait(u_top.u_riscv_top.irq_lines[pinmap[i]] == 1'b1); // Wait for Interrupt assertion + wait(u_top.u_riscv_top.irq_lines[pinmap[i]] == 1'b0); // Wait for Interrupt De-assertion + + end + repeat (10000) @(posedge clock); // Wait for flush our uart message + $display("End : Processing One Interrupt At a Time "); + + // Generate all interrupt and Wait for all interrupt clearing + $display("Start: Processing All Interrupt "); + for(i =2; i < 22; i = i+1) begin + arduino_din[i] = !arduino_din[i]; // Invert the edge to create interrupt; + repeat (5) @(posedge clock); + arduino_din[i] = !arduino_din[i]; // Invert the edge to remove the interrupt + repeat (5) @(posedge clock); + wait(u_top.u_riscv_top.irq_lines[pinmap[i]] == 1'b1); // Wait for Interrupt assertion + + end + wait(u_top.u_riscv_top.irq_lines == 'h0); // Wait for All Interrupt De-assertion + repeat (10000) @(posedge clock); // Wait for flush our uart message + $display("End: Processing All Interrupt "); + end + begin + while(flag == 0) + begin + tb_uart.read_char(read_data,flag); + if(flag == 0) begin + $write ("%c",read_data); + check_sum = check_sum+read_data; + end + end + end + begin + repeat (700000) @(posedge clock); // wait for Processor Get Ready + end + join_any + + #1000 + tb_uart.report_status(uart_rx_nu, uart_tx_nu); + + test_fail = 0; + + $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum); + // Check + // if all the 102 byte received + // if no error + if(uart_rx_nu != 1063) test_fail = 1; + if(check_sum != 32'h143de) test_fail = 1; + if(tb_uart.err_cnt != 0) test_fail = 1; + + + $display("###################################################"); + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: Standalone String (GL) Passed"); + `else + $display("Monitor: Standalone String (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Standalone String (GL) Failed"); + `else + $display("Monitor: Standalone String (RTL) Failed"); + `endif + end + $display("###################################################"); + $finish; + end + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +//assign io_in[16] = 1'b0 ; // SPIS SCK + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + end +`endif + +//------------------------------------------------------ +// Integrate the Serial flash with qurd support to +// user core using the gpio pads +// ---------------------------------------------------- + + wire flash_clk = io_out[24]; + wire flash_csb = io_out[25]; + // Creating Pad Delay + wire #1 io_oeb_29 = io_oeb[29]; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; + + // Quard flash + s25fl256s #(.mem_file_name(`TB_HEX), + .otp_file_name("none"), + .TimingModel("S25FL512SAGMFI010_F_30pF")) + u_spi_flash_256mb ( + // Data Inputs/Outputs + .SI (flash_io0), + .SO (flash_io1), + // Controls + .SCK (flash_clk), + .CSNeg (flash_csb), + .WPNeg (flash_io2), + .HOLDNeg (flash_io3), + .RSTNeg (!wb_rst_i) + + ); + + +//--------------------------- +// UART Agent integration +// -------------------------- +wire uart_txd,uart_rxd; + +assign uart_txd = io_out[2]; +assign io_in[1] = uart_rxd ; + +uart_agent tb_uart( + .mclk (clock ), + .txd (uart_rxd ), + .rxd (uart_txd ) + ); + + +//---------------------------- +// All the task are defined here +//---------------------------- + + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ +endmodule +`include "s25fl256s.sv" +`default_nettype wire
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board index 09f42e8..30c5dc9 160000 --- a/verilog/dv/common/riscduino_board +++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@ -Subproject commit 09f42e80c78b05785fb7088fb3bff16b2044c6c8 +Subproject commit 30c5dc912352049877661b3571064e314aaffcde
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 8dde135..2c53c8c 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -157,6 +157,7 @@ logic [7:0] tem_mem[0:4095]; logic [31:0] mem_data; + integer d_risc_id; parameter P_FSM_C = 4'b0000; // Command Phase Only @@ -220,6 +221,8 @@ wbd_ext_we_i ='h0; // write wbd_ext_dat_i ='h0; // data output wbd_ext_sel_i ='h0; // byte enable + + $value$plusargs("risc_core_id=%d", d_risc_id); end `ifdef WFDUMP @@ -228,6 +231,7 @@ $dumpvars(1, user_risc_regress_tb); $dumpvars(1, user_risc_regress_tb.u_top); $dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top); + $dumpvars(0, user_risc_regress_tb.u_top.u_qspi_master); $dumpvars(0, user_risc_regress_tb.u_top.u_intercon); $dumpvars(0, user_risc_regress_tb.u_top.u_pinmux); end
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv index 6ef9098..bc3de29 100644 --- a/verilog/rtl/pinmux/src/glbl_reg.sv +++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -65,7 +65,7 @@ input logic [1:0] ext_intr_in , // Risc configuration - output logic [15:0] irq_lines , + output logic [31:0] irq_lines , output logic soft_irq , output logic [2:0] user_irq , input logic usb_intr , @@ -76,7 +76,7 @@ input logic [2:0] timer_intr , - input logic gpio_intr + input logic [31:0] gpio_intr ); @@ -228,7 +228,9 @@ .data_out (reg_2 ) ); -assign cfg_riscv_ctrl = reg_2[31:16]; +assign soft_irq = reg_2[3]; +assign user_irq = reg_2[2:0]; +assign cfg_riscv_ctrl = reg_2[31:16]; //----------------------------------------------------------------------- // reg-3 : Global Interrupt Mask @@ -249,53 +251,29 @@ //----------------------------------------------------------------------- // reg-4 : Global Interrupt Status //----------------------------------------------------------------- -assign irq_lines = reg_3[15:0] & reg_4[15:0]; -assign soft_irq = reg_3[16] & reg_4[16]; -assign user_irq = reg_3[19:17]& reg_4[19:17]; +assign irq_lines = reg_3[31:0] & reg_4[31:0]; +// In Arduino GPIO[7:0] is corresponds to PORT-A which is not available for user access +wire [31:0] hware_intr_req = {gpio_intr[31:8], 3'b0,usb_intr, i2cm_intr,timer_intr[2:0]}; -generic_register #(8,0 ) u_reg4_be0 ( - .we ({8{sw_wr_en_4 & - wr_be[0] }} ), - .data_in (sw_reg_wdata[7:0] ), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_4[7:0] ) - ); - - -wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]}; - -generic_intr_stat_reg #(.WD(8), +generic_intr_stat_reg #(.WD(32), .RESET_DEFAULT(0)) u_reg4_be1 ( //inputs .clk (mclk ), .reset_n (h_reset_n ), - .reg_we ({8{sw_wr_en_4 & reg_ack & - wr_be[1] }} ), - .reg_din (sw_reg_wdata[15:8] ), + .reg_we ({{8{sw_wr_en_4 & reg_ack & wr_be[3]}}, + {8{sw_wr_en_4 & reg_ack & wr_be[2]}}, + {8{sw_wr_en_4 & reg_ack & wr_be[1]}}, + {8{sw_wr_en_4 & reg_ack & wr_be[0]}}}), + .reg_din (sw_reg_wdata[31:0] ), .hware_req (hware_intr_req ), //outputs - .data_out (reg_4[15:8] ) + .data_out (reg_4[31:0] ) ); -generic_register #(4,0 ) u_reg4_be2 ( - .we ({4{sw_wr_en_4 & - wr_be[2] }} ), - .data_in (sw_reg_wdata[19:16]), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_4[19:16] ) - ); - -assign reg_4[31:20] = '0; //-----------------------------------------------------------------------
diff --git a/verilog/rtl/pinmux/src/gpio_reg.sv b/verilog/rtl/pinmux/src/gpio_reg.sv index be61923..c911cdc 100644 --- a/verilog/rtl/pinmux/src/gpio_reg.sv +++ b/verilog/rtl/pinmux/src/gpio_reg.sv
@@ -64,7 +64,7 @@ output logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt output logic [31:00] cfg_gpio_data_in , - output logic gpio_intr + output logic [31:0] gpio_intr ); @@ -253,7 +253,7 @@ //----------------------------------------------------------------------- wire [31:0] cfg_gpio_int_mask = reg_6[31:0]; // to be used for read -assign gpio_intr = ( | (reg_4 & reg_6) ); // interrupt pin to the RISC +assign gpio_intr = reg_4 & reg_6; // interrupt pin to the RISC // Register-11
diff --git a/verilog/rtl/pinmux/src/gpio_top.sv b/verilog/rtl/pinmux/src/gpio_top.sv index 0a7fd02..b5d747d 100644 --- a/verilog/rtl/pinmux/src/gpio_top.sv +++ b/verilog/rtl/pinmux/src/gpio_top.sv
@@ -57,7 +57,7 @@ input logic [31:0] pad_gpio_in, output logic [31:0] pad_gpio_out, - output logic gpio_intr + output logic [31:0] gpio_intr );
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index 54c0ef9..5c43778 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -34,6 +34,8 @@ //// Revision : //// //// 0.1 - 16th Aug 2022, Dinesh A //// //// Seperated the pinmux from pinmux_top module //// +//// 0.2 - 21th Aug 2022, Dinesh A //// +//// uart_master disable option added //// ////////////////////////////////////////////////////////////////////// /************************************************ * Pin Mapping ATMGE CONFIG @@ -185,6 +187,7 @@ wire cfg_spim_enb = cfg_multi_func_sel[10]; wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11]; wire cfg_i2cm_enb = cfg_multi_func_sel[15]; +wire cfg_muart_dis = cfg_multi_func_sel[31:8]; // 0 - uart master enable, 1 - disable wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0]; wire [7:0] cfg_port_b_dir_sel = cfg_gpio_dir_sel[15:8]; @@ -298,7 +301,7 @@ sflash_di[3] = digital_io_in[32]; // UAR MASTER I/F - uartm_rxd = digital_io_in[34]; + uartm_rxd = (cfg_muart_dis) ? 1'b0 : digital_io_in[34]; usb_dp_i = digital_io_in[36]; usb_dn_i = digital_io_in[37]; @@ -530,7 +533,7 @@ digital_io_oen[33] = 1'b0 ; // UART MASTER digital_io_oen[34] = 1'b1; // RXD - digital_io_oen[35] = 1'b0; // TXD + digital_io_oen[35] = cfg_muart_dis; // TXD // USB 1.1 digital_io_oen[36] = usb_oen;
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv index c84c1a7..02ecb2a 100755 --- a/verilog/rtl/pinmux/src/pinmux_top.sv +++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -45,6 +45,8 @@ //// 0.4 - 20 July 2022, Dinesh A //// //// On Power On, If RESET* = 0, then system will enter //// //// in to SPIS slave mode to support boot //// +//// 0.5 - 21 Aug 2022, Dinesh A //// +//// uart_master disable option added //// ////////////////////////////////////////////////////////////////////// module pinmux_top ( @@ -84,7 +86,7 @@ output logic reg_ack, // Risc configuration - output logic [15:0] irq_lines, + output logic [31:0] irq_lines, output logic soft_irq, output logic [2:0] user_irq, input logic usb_intr, @@ -173,6 +175,7 @@ logic [5:0] pwm_wfm ; +logic [31:0] gpio_intr ; wire [31:0] cfg_gpio_dir_sel ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output wire [31:0] cfg_gpio_out_type ;// GPIO Type, Unused wire [31:0] cfg_multi_func_sel ;// GPIO Multi function type
diff --git a/verilog/rtl/pinmux/src/timer_reg.sv b/verilog/rtl/pinmux/src/timer_reg.sv index cd48587..1a561f6 100644 --- a/verilog/rtl/pinmux/src/timer_reg.sv +++ b/verilog/rtl/pinmux/src/timer_reg.sv
@@ -56,8 +56,7 @@ output logic [2:0] cfg_timer_update , // CPU write to timer register output logic [18:0] cfg_timer0 , // Timer-0 register output logic [18:0] cfg_timer1 , // Timer-1 register - output logic [18:0] cfg_timer2 , // Timer-2 register - output logic [2:0] timer_intr + output logic [18:0] cfg_timer2 // Timer-2 register );
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index ba18819..d3c9ec7 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -235,6 +235,10 @@ //// `define ADDR_SPACE_PWM 32'h1002_0080 //// //// `define ADDR_SPACE_TIMER 32'h1002_00C0 //// //// `define ADDR_SPACE_SEMA 32'h1002_0100 //// +//// 5.1 Aug 21 2022, Dinesh A //// +//// A. GPIO interrupt generation changed from 1 to 32 //// +//// B. Total interrupt to Riscv changed from 16 to 32 //// +//// C. uart_master disable option added at pinmux //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -509,7 +513,7 @@ wire wbd_int_rst_n ; wire wbd_pll_rst_n ; -wire [15:0] irq_lines ; +wire [31:0] irq_lines ; wire soft_irq ; @@ -531,7 +535,7 @@ wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux wire [3:0] cfg_cska_qspi_co_rp ; // clock skew adjust for global reg -wire [15:0] irq_lines_rp ; // Repeater +wire [31:0] irq_lines_rp ; // Repeater wire soft_irq_rp ; // Repeater wire wbd_clk_risc_rp ; @@ -1060,8 +1064,8 @@ wb_interconnect #( `ifndef SYNTHESIS - .CH_CLK_WD (4 ), - .CH_DATA_WD (37 ) + .CH_CLK_WD (4 ), + .CH_DATA_WD (53 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS @@ -1081,24 +1085,24 @@ .ch_data_in ({ soft_irq, - irq_lines[15:0], + irq_lines[31:0], - cfg_cska_qspi_co[3:0], - cfg_cska_pinmux[3:0], - cfg_cska_uart[3:0], - cfg_cska_qspi[3:0], - cfg_cska_riscv[3:0] + cfg_cska_qspi_co[3:0], + cfg_cska_pinmux[3:0], + cfg_cska_uart[3:0], + cfg_cska_qspi[3:0], + cfg_cska_riscv[3:0] } ), .ch_data_out ({ soft_irq_rp, - irq_lines_rp[15:0], + irq_lines_rp[31:0], - cfg_cska_qspi_co_rp[3:0], - cfg_cska_pinmux_rp[3:0], - cfg_cska_uart_rp[3:0], - cfg_cska_qspi_rp[3:0], - cfg_cska_riscv_rp[3:0] + cfg_cska_qspi_co_rp[3:0], + cfg_cska_pinmux_rp[3:0], + cfg_cska_uart_rp[3:0], + cfg_cska_qspi_rp[3:0], + cfg_cska_riscv_rp[3:0] } ), // Clock Skew adjust .wbd_clk_int (wbd_clk_int ),
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c index 03ba3e8..1a3afdf 160000 --- a/verilog/rtl/yifive/ycr1c +++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@ -Subproject commit 03ba3e83768d0c61c3da561183aadf6d13418bc5 +Subproject commit 1a3afdf0887e7a222c08751b8eeab0533cf6694e