repeater update
diff --git a/openlane/bus_rep_east/config.tcl b/openlane/bus_rep_east/config.tcl new file mode 100755 index 0000000..0362cfc --- /dev/null +++ b/openlane/bus_rep_east/config.tcl
@@ -0,0 +1,134 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + +# Global +# ------ + +set script_dir [file dirname [file normalize [info script]]] +# Name +set ::env(DESIGN_NAME) bus_rep_east + + +set ::env(DESIGN_IS_CORE) "1" +set ::env(FP_PDN_CORE_RING) {1} + +# Timing configuration +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "" +set ::env(CLOCK_NET) "" + +set ::env(SYNTH_MAX_FANOUT) 4 +set ::env(SYNTH_BUFFERING) {0} + + +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + +# Sources +# ------- + +# Local sources + no2usb sources +set ::env(VERILOG_FILES) "\ + $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_east.sv \ + " + +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + +set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=45 " + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc + +set ::env(LEC_ENABLE) 0 + +set ::env(VDD_PIN) [list {vccd1}] +set ::env(GND_PIN) [list {vssd1}] + + +# Floorplanning +# ------------- + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg +set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 3420 50" + +#set ::env(GRT_OBS) "met4 0 0 300 1725" + +# If you're going to use multiple power domains, then keep this disabled. +set ::env(RUN_CVC) 0 + +#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl + + + +set ::env(PL_TIME_DRIVEN) 1 +set ::env(PL_TARGET_DENSITY) "0.20" +set ::env(CELL_PAD) "8" +set ::env(GRT_ADJUSTMENT) 0.2 + +# helps in anteena fix +set ::env(USE_ARC_ANTENNA_CHECK) "0" + + +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +set ::env(DIODE_INSERTION_STRATEGY) 4 + +## CTS +set ::env(CLOCK_TREE_SYNTH) {0} + +## Placement +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0" + +## Routing +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" + +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + +#set ::env(GLB_RT_MAXLAYER) 3 +set ::env(RT_MAX_LAYER) {met3} +set ::env(FP_PDN_LOWER_LAYER) {met2} +set ::env(FP_PDN_UPPER_LAYER) {met3} + +set ::env(FP_IO_HLAYER) {met2} +set ::env(FP_IO_VLAYER) {met1} + +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + +## Placement +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 +set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2 +set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500" +set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0" + +set ::env(ECO_ENABLE) {0} +#set ::env(CURRENT_STEP) "synthesis" +#set ::env(LAST_STEP) "parasitics_sta" + +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" +set ::env(QUIT_ON_MAGIC_DRC) "1" +set ::env(QUIT_ON_LVS_ERROR) "1" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_east/interactive.tcl b/openlane/bus_rep_east/interactive.tcl new file mode 100755 index 0000000..5b5c6c8 --- /dev/null +++ b/openlane/bus_rep_east/interactive.tcl
@@ -0,0 +1,337 @@ +#!/usr/bin/env tclsh +# Copyright 2020-2022 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +package require openlane; # provides the utils as well +proc run_placement_step {args} { + if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { + set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) + } + + run_placement +} + +proc run_cts_step {args} { + if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { + set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) + } + + run_cts + run_resizer_timing + if { $::env(RSZ_USE_OLD_REMOVER) == 1} { + remove_buffers_from_nets + } +} + +proc run_routing_step {args} { + if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { + set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) + } + if { $::env(ECO_ENABLE) == 0 } { + run_routing + } +} + +proc run_parasitics_sta_step {args} { + if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } { + set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF) + } + + if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} { + run_parasitics_sta + } +} + +proc run_diode_insertion_2_5_step {args} { + if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { + set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) + } + if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { + run_antenna_check + heal_antenna_violators; # modifies the routed DEF + } + +} + +proc run_irdrop_report_step {args} { + if { $::env(RUN_IRDROP_REPORT) } { + run_irdrop_report + } +} + +proc run_lvs_step {{ lvs_enabled 1 }} { + if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { + set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) + } + + if { $lvs_enabled && $::env(RUN_LVS) } { + run_magic_spice_export; + run_lvs; # requires run_magic_spice_export + } + +} + +proc run_drc_step {{ drc_enabled 1 }} { + if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { + set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) + } + if { $drc_enabled } { + if { $::env(RUN_MAGIC_DRC) } { + run_magic_drc + } + if {$::env(RUN_KLAYOUT_DRC)} { + run_klayout_drc + } + } +} + +proc run_antenna_check_step {{ antenna_check_enabled 1 }} { + if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { + set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) + } + if { $antenna_check_enabled } { + run_antenna_check + } +} + +proc run_erc_step {args} { + if { $::env(RUN_CVC) } { + run_erc + } +} + +proc run_eco_step {args} { + if { $::env(ECO_ENABLE) == 1 } { + run_eco_flow + } +} + +proc run_magic_step {args} { + if {$::env(RUN_MAGIC)} { + run_magic + } +} + +proc run_klayout_step {args} { + if {$::env(RUN_KLAYOUT)} { + run_klayout + } + if {$::env(RUN_KLAYOUT_XOR)} { + run_klayout_gds_xor + } +} + +proc run_post_run_hooks {} { + if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} { + puts_info "Running post run hook" + set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py] + puts_info "$result" + } else { + puts_info "hooks/post_run.py not found, skipping" + } +} + +proc run_floorplan {args} { + # |----------------------------------------------------| + # |---------------- 2. FLOORPLAN ------------------| + # |----------------------------------------------------| + # + # intial fp + init_floorplan + + # check for deprecated io variables + if { [info exists ::env(FP_IO_HMETAL)]} { + set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]] + puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}" + } + + if { [info exists ::env(FP_IO_VMETAL)]} { + set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]] + puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}" + } + + + # place io + if { [info exists ::env(FP_PIN_ORDER_CFG)] } { + place_io_ol + } else { + if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } { + place_io + global_placement_or + place_contextualized_io \ + -lef $::env(FP_CONTEXT_LEF) \ + -def $::env(FP_CONTEXT_DEF) + } else { + place_io + } + } + + apply_def_template + + #if { [info exist ::env(EXTRA_LEFS)] } { + if { [info exist ::env(MACRO_PLACEMENT_CFG)] } { + file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg + manual_macro_placement -f + } else { + # global_placement_or + # basic_macro_placement + } + #} + + if { $::env(RUN_TAP_DECAP_INSERTION) } { + tap_decap_or + } + + scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log + + run_power_grid_generation +} + + + +proc run_flow {args} { + set options { + {-design optional} + {-from optional} + {-to optional} + {-save_path optional} + {-override_env optional} + } + set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui} + parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume + + prep {*}$args + # signal trap SIGINT save_state; + + if { [info exists flags_map(-gui)] } { + or_gui + return + } + if { [info exists arg_values(-override_env)] } { + load_overrides $arg_values(-override_env) + } + + set LVS_ENABLED 1 + set DRC_ENABLED 1 + + set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ] + + set steps [dict create \ + "synthesis" "run_synthesis" \ + "floorplan" "run_floorplan" \ + "placement" "run_placement_step" \ + "cts" "run_cts_step" \ + "routing" "run_routing_step" \ + "parasitics_sta" "run_parasitics_sta_step" \ + "eco" "run_eco_step" \ + "diode_insertion" "run_diode_insertion_2_5_step" \ + "irdrop" "run_irdrop_report_step" \ + "gds_magic" "run_magic_step" \ + "gds_klayout" "run_klayout_step" \ + "lvs" "run_lvs_step $LVS_ENABLED " \ + "drc" "run_drc_step $DRC_ENABLED " \ + "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \ + "cvc" "run_lef_cvc" + ] + + if { [info exists arg_values(-from) ]} { + puts_info "Starting flow at $arg_values(-from)..." + set ::env(CURRENT_STEP) $arg_values(-from) + } elseif { [info exists ::env(CURRENT_STEP) ] } { + puts_info "Resuming flow from $::env(CURRENT_STEP)..." + } else { + set ::env(CURRENT_STEP) "synthesis" + } + + set_if_unset arg_values(-from) $::env(CURRENT_STEP) + set_if_unset arg_values(-to) "cvc" + + set exe 0; + dict for {step_name step_exe} $steps { + if { [ string equal $arg_values(-from) $step_name ] } { + set exe 1; + } + + if { $exe } { + # For when it fails + set ::env(CURRENT_STEP) $step_name + [lindex $step_exe 0] [lindex $step_exe 1] ; + } + + if { [ string equal $arg_values(-to) $step_name ] } { + set exe 0: + break; + } + + } + + # for when it resumes + set steps_as_list [dict keys $steps] + set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] + set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] + + # Saves to <RUN_DIR>/results/final + save_final_views + + # Saves to design directory or custom + if { [info exists flags_map(-save) ] } { + if { ! [info exists arg_values(-save_path)] } { + set arg_values(-save_path) $::env(DESIGN_DIR) + } + save_final_views\ + -save_path $arg_values(-save_path)\ + -tag $::env(RUN_TAG) + } + calc_total_runtime + save_state + generate_final_summary_report + + check_timing_violations + + if { [info exists arg_values(-save_path)]\ + && $arg_values(-save_path) != "" } { + set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]" + } else { + set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final + } + + if {[info exists flags_map(-run_hooks)]} { + run_post_run_hooks + } + + puts_success "Flow complete." + + show_warnings "Note that the following warnings have been generated:" +} + +run_flow {*}$argv
diff --git a/openlane/bus_rep_east/macro.cfg b/openlane/bus_rep_east/macro.cfg new file mode 100644 index 0000000..e84abca --- /dev/null +++ b/openlane/bus_rep_east/macro.cfg
@@ -0,0 +1,46 @@ +u_rp\[0\].u_buf 7.82 10.88 FN +u_rp\[1\].u_buf 85.1 10.88 FN +u_rp\[2\].u_buf 162.38 10.88 FN +u_rp\[3\].u_buf 239.66 10.88 FN +u_rp\[4\].u_buf 316.94 10.88 FN +u_rp\[5\].u_buf 394.22 10.88 FN +u_rp\[6\].u_buf 471.5 10.88 FN +u_rp\[7\].u_buf 548.78 10.88 FN +u_rp\[8\].u_buf 626.06 10.88 FN +u_rp\[9\].u_buf 703.34 10.88 FN +u_rp\[10\].u_buf 780.62 10.88 FN +u_rp\[11\].u_buf 857.9 10.88 FN +u_rp\[12\].u_buf 935.18 10.88 FN +u_rp\[13\].u_buf 1012.46 10.88 FN +u_rp\[14\].u_buf 1089.74 10.88 FN +u_rp\[15\].u_buf 1167.02 10.88 FN +u_rp\[16\].u_buf 1244.3 10.88 FN +u_rp\[17\].u_buf 1321.58 10.88 FN +u_rp\[18\].u_buf 1398.86 10.88 FN +u_rp\[19\].u_buf 1476.14 10.88 FN +u_rp\[20\].u_buf 1553.42 10.88 FN +u_rp\[21\].u_buf 1630.7 10.88 FN +u_rp\[22\].u_buf 1707.98 10.88 FN +u_rp\[23\].u_buf 1785.26 10.88 FN +u_rp\[24\].u_buf 1862.54 10.88 FN +u_rp\[25\].u_buf 1939.82 10.88 FN +u_rp\[26\].u_buf 2017.1 10.88 FN +u_rp\[27\].u_buf 2094.38 10.88 FN +u_rp\[28\].u_buf 2171.66 10.88 FN +u_rp\[29\].u_buf 2248.94 10.88 FN +u_rp\[30\].u_buf 2326.22 10.88 FN +u_rp\[31\].u_buf 2403.5 10.88 FN +u_rp\[32\].u_buf 2480.78 10.88 FN +u_rp\[33\].u_buf 2558.06 10.88 FN +u_rp\[34\].u_buf 2635.34 10.88 FN +u_rp\[35\].u_buf 2712.62 10.88 FN +u_rp\[36\].u_buf 2789.9 10.88 FN +u_rp\[37\].u_buf 2867.18 10.88 FN +u_rp\[38\].u_buf 2944.46 10.88 FN +u_rp\[39\].u_buf 3021.74 10.88 FN +u_rp\[40\].u_buf 3099.02 10.88 FN +u_rp\[41\].u_buf 3176.3 10.88 FN +u_rp\[42\].u_buf 3253.58 10.88 FN +u_rp\[43\].u_buf 3330.86 10.88 FN +u_rp\[44\].u_buf 3408.14 10.88 FN +
diff --git a/openlane/bus_rep_east/pdn.tcl b/openlane/bus_rep_east/pdn.tcl new file mode 100644 index 0000000..1fe689b --- /dev/null +++ b/openlane/bus_rep_east/pdn.tcl
@@ -0,0 +1,49 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Power nets +set ::power_nets $::env(VDD_PIN) +set ::ground_nets $::env(GND_PIN) + +set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" + +pdngen::specify_grid stdcell { + name grid + rails { + met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} + } + straps { + met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + } + connect {{met1 met4} {met4 met5}} +} + +pdngen::specify_grid macro { + power_pins "VPWR" + ground_pins "VGND" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} +} + +set ::halo 5 + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_east/pin_order.cfg b/openlane/bus_rep_east/pin_order.cfg new file mode 100644 index 0000000..bfe94f9 --- /dev/null +++ b/openlane/bus_rep_east/pin_order.cfg
@@ -0,0 +1,99 @@ +#BUS_SORT + +#MANUAL_PLACE + +#N +ch_out\[0\] 0 0 225 +ch_out\[1\] +ch_in\[2\] +ch_out\[3\] +ch_out\[4\] +ch_in\[5\] +ch_out\[6\] +ch_out\[7\] +ch_in\[8\] +ch_out\[9\] +ch_out\[10\] +ch_in\[11\] +ch_out\[12\] +ch_out\[13\] +ch_in\[14\] +ch_out\[15\] +ch_out\[16\] +ch_in\[17\] +ch_out\[18\] +ch_out\[19\] +ch_in\[20\] +ch_out\[21\] +ch_out\[22\] +ch_in\[23\] +ch_out\[24\] +ch_out\[25\] +ch_in\[26\] +ch_out\[27\] +ch_out\[28\] +ch_in\[29\] +ch_out\[30\] +ch_out\[31\] +ch_in\[32\] +ch_out\[33\] +ch_out\[34\] +ch_in\[35\] +ch_out\[36\] +ch_out\[37\] +ch_in\[38\] +ch_out\[39\] +ch_out\[40\] +ch_in\[41\] +ch_out\[42\] +ch_out\[43\] +ch_in\[44\] + +#S +ch_in\[0\] 1140 0 6 +ch_in\[1\] +ch_out\[2\] +ch_in\[3\] +ch_in\[4\] +ch_out\[5\] +ch_in\[6\] +ch_in\[7\] +ch_out\[8\] +ch_in\[9\] +ch_in\[10\] +ch_out\[11\] +ch_in\[12\] +ch_in\[13\] +ch_out\[14\] +ch_in\[15\] +ch_in\[16\] +ch_out\[17\] +ch_in\[18\] +ch_in\[19\] +ch_out\[20\] +ch_in\[21\] +ch_in\[22\] +ch_out\[23\] +ch_in\[24\] +ch_in\[25\] +ch_out\[26\] +ch_in\[27\] +ch_in\[28\] +ch_out\[29\] +ch_in\[30\] +ch_in\[31\] +ch_out\[32\] +ch_in\[33\] +ch_in\[34\] +ch_out\[35\] +ch_in\[36\] +ch_in\[37\] +ch_out\[38\] +ch_in\[39\] +ch_in\[40\] +ch_out\[41\] +ch_in\[42\] +ch_in\[43\] +ch_out\[44\] + +
diff --git a/openlane/bus_rep_north/config.tcl b/openlane/bus_rep_north/config.tcl new file mode 100755 index 0000000..4168921 --- /dev/null +++ b/openlane/bus_rep_north/config.tcl
@@ -0,0 +1,134 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + +# Global +# ------ + +set script_dir [file dirname [file normalize [info script]]] +# Name +set ::env(DESIGN_NAME) bus_rep_north + + +set ::env(DESIGN_IS_CORE) "1" +set ::env(FP_PDN_CORE_RING) {1} + +# Timing configuration +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "" +set ::env(CLOCK_NET) "" + +set ::env(SYNTH_MAX_FANOUT) 4 +set ::env(SYNTH_BUFFERING) {0} + + +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + +# Sources +# ------- + +# Local sources + no2usb sources +set ::env(VERILOG_FILES) "\ + $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_north.sv \ + " + +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + +set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 " + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc + +set ::env(LEC_ENABLE) 0 + +set ::env(VDD_PIN) [list {vccd1}] +set ::env(GND_PIN) [list {vssd1}] + + +# Floorplanning +# ------------- + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg +set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 2650 50" + +#set ::env(GRT_OBS) "met4 0 0 300 1725" + +# If you're going to use multiple power domains, then keep this disabled. +set ::env(RUN_CVC) 0 + +#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl + + + +set ::env(PL_TIME_DRIVEN) 1 +set ::env(PL_TARGET_DENSITY) "0.20" +set ::env(CELL_PAD) "8" +set ::env(GRT_ADJUSTMENT) 0.2 + +# helps in anteena fix +set ::env(USE_ARC_ANTENNA_CHECK) "0" + + +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +set ::env(DIODE_INSERTION_STRATEGY) 4 + +## CTS +set ::env(CLOCK_TREE_SYNTH) {0} + +## Placement +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0" + +## Routing +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" + +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + +#set ::env(GLB_RT_MAXLAYER) 3 +set ::env(RT_MAX_LAYER) {met3} +set ::env(FP_PDN_LOWER_LAYER) {met2} +set ::env(FP_PDN_UPPER_LAYER) {met3} + +set ::env(FP_IO_HLAYER) {met2} +set ::env(FP_IO_VLAYER) {met1} + +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + +## Placement +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 +set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2 +set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500" +set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0" + +set ::env(ECO_ENABLE) {0} +#set ::env(CURRENT_STEP) "synthesis" +#set ::env(LAST_STEP) "parasitics_sta" + +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" +set ::env(QUIT_ON_MAGIC_DRC) "1" +set ::env(QUIT_ON_LVS_ERROR) "1" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_north/interactive.tcl b/openlane/bus_rep_north/interactive.tcl new file mode 100755 index 0000000..5b5c6c8 --- /dev/null +++ b/openlane/bus_rep_north/interactive.tcl
@@ -0,0 +1,337 @@ +#!/usr/bin/env tclsh +# Copyright 2020-2022 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +package require openlane; # provides the utils as well +proc run_placement_step {args} { + if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { + set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) + } + + run_placement +} + +proc run_cts_step {args} { + if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { + set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) + } + + run_cts + run_resizer_timing + if { $::env(RSZ_USE_OLD_REMOVER) == 1} { + remove_buffers_from_nets + } +} + +proc run_routing_step {args} { + if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { + set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) + } + if { $::env(ECO_ENABLE) == 0 } { + run_routing + } +} + +proc run_parasitics_sta_step {args} { + if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } { + set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF) + } + + if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} { + run_parasitics_sta + } +} + +proc run_diode_insertion_2_5_step {args} { + if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { + set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) + } + if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { + run_antenna_check + heal_antenna_violators; # modifies the routed DEF + } + +} + +proc run_irdrop_report_step {args} { + if { $::env(RUN_IRDROP_REPORT) } { + run_irdrop_report + } +} + +proc run_lvs_step {{ lvs_enabled 1 }} { + if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { + set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) + } + + if { $lvs_enabled && $::env(RUN_LVS) } { + run_magic_spice_export; + run_lvs; # requires run_magic_spice_export + } + +} + +proc run_drc_step {{ drc_enabled 1 }} { + if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { + set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) + } + if { $drc_enabled } { + if { $::env(RUN_MAGIC_DRC) } { + run_magic_drc + } + if {$::env(RUN_KLAYOUT_DRC)} { + run_klayout_drc + } + } +} + +proc run_antenna_check_step {{ antenna_check_enabled 1 }} { + if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { + set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) + } + if { $antenna_check_enabled } { + run_antenna_check + } +} + +proc run_erc_step {args} { + if { $::env(RUN_CVC) } { + run_erc + } +} + +proc run_eco_step {args} { + if { $::env(ECO_ENABLE) == 1 } { + run_eco_flow + } +} + +proc run_magic_step {args} { + if {$::env(RUN_MAGIC)} { + run_magic + } +} + +proc run_klayout_step {args} { + if {$::env(RUN_KLAYOUT)} { + run_klayout + } + if {$::env(RUN_KLAYOUT_XOR)} { + run_klayout_gds_xor + } +} + +proc run_post_run_hooks {} { + if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} { + puts_info "Running post run hook" + set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py] + puts_info "$result" + } else { + puts_info "hooks/post_run.py not found, skipping" + } +} + +proc run_floorplan {args} { + # |----------------------------------------------------| + # |---------------- 2. FLOORPLAN ------------------| + # |----------------------------------------------------| + # + # intial fp + init_floorplan + + # check for deprecated io variables + if { [info exists ::env(FP_IO_HMETAL)]} { + set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]] + puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}" + } + + if { [info exists ::env(FP_IO_VMETAL)]} { + set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]] + puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}" + } + + + # place io + if { [info exists ::env(FP_PIN_ORDER_CFG)] } { + place_io_ol + } else { + if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } { + place_io + global_placement_or + place_contextualized_io \ + -lef $::env(FP_CONTEXT_LEF) \ + -def $::env(FP_CONTEXT_DEF) + } else { + place_io + } + } + + apply_def_template + + #if { [info exist ::env(EXTRA_LEFS)] } { + if { [info exist ::env(MACRO_PLACEMENT_CFG)] } { + file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg + manual_macro_placement -f + } else { + # global_placement_or + # basic_macro_placement + } + #} + + if { $::env(RUN_TAP_DECAP_INSERTION) } { + tap_decap_or + } + + scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log + + run_power_grid_generation +} + + + +proc run_flow {args} { + set options { + {-design optional} + {-from optional} + {-to optional} + {-save_path optional} + {-override_env optional} + } + set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui} + parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume + + prep {*}$args + # signal trap SIGINT save_state; + + if { [info exists flags_map(-gui)] } { + or_gui + return + } + if { [info exists arg_values(-override_env)] } { + load_overrides $arg_values(-override_env) + } + + set LVS_ENABLED 1 + set DRC_ENABLED 1 + + set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ] + + set steps [dict create \ + "synthesis" "run_synthesis" \ + "floorplan" "run_floorplan" \ + "placement" "run_placement_step" \ + "cts" "run_cts_step" \ + "routing" "run_routing_step" \ + "parasitics_sta" "run_parasitics_sta_step" \ + "eco" "run_eco_step" \ + "diode_insertion" "run_diode_insertion_2_5_step" \ + "irdrop" "run_irdrop_report_step" \ + "gds_magic" "run_magic_step" \ + "gds_klayout" "run_klayout_step" \ + "lvs" "run_lvs_step $LVS_ENABLED " \ + "drc" "run_drc_step $DRC_ENABLED " \ + "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \ + "cvc" "run_lef_cvc" + ] + + if { [info exists arg_values(-from) ]} { + puts_info "Starting flow at $arg_values(-from)..." + set ::env(CURRENT_STEP) $arg_values(-from) + } elseif { [info exists ::env(CURRENT_STEP) ] } { + puts_info "Resuming flow from $::env(CURRENT_STEP)..." + } else { + set ::env(CURRENT_STEP) "synthesis" + } + + set_if_unset arg_values(-from) $::env(CURRENT_STEP) + set_if_unset arg_values(-to) "cvc" + + set exe 0; + dict for {step_name step_exe} $steps { + if { [ string equal $arg_values(-from) $step_name ] } { + set exe 1; + } + + if { $exe } { + # For when it fails + set ::env(CURRENT_STEP) $step_name + [lindex $step_exe 0] [lindex $step_exe 1] ; + } + + if { [ string equal $arg_values(-to) $step_name ] } { + set exe 0: + break; + } + + } + + # for when it resumes + set steps_as_list [dict keys $steps] + set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] + set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] + + # Saves to <RUN_DIR>/results/final + save_final_views + + # Saves to design directory or custom + if { [info exists flags_map(-save) ] } { + if { ! [info exists arg_values(-save_path)] } { + set arg_values(-save_path) $::env(DESIGN_DIR) + } + save_final_views\ + -save_path $arg_values(-save_path)\ + -tag $::env(RUN_TAG) + } + calc_total_runtime + save_state + generate_final_summary_report + + check_timing_violations + + if { [info exists arg_values(-save_path)]\ + && $arg_values(-save_path) != "" } { + set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]" + } else { + set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final + } + + if {[info exists flags_map(-run_hooks)]} { + run_post_run_hooks + } + + puts_success "Flow complete." + + show_warnings "Note that the following warnings have been generated:" +} + +run_flow {*}$argv
diff --git a/openlane/bus_rep_north/macro.cfg b/openlane/bus_rep_north/macro.cfg new file mode 100644 index 0000000..f743181 --- /dev/null +++ b/openlane/bus_rep_north/macro.cfg
@@ -0,0 +1,27 @@ +u_rp\[0\].u_buf 7.82 10.88 FN +u_rp\[1\].u_buf 97.98 10.88 FN +u_rp\[2\].u_buf 188.14 10.88 FN +u_rp\[3\].u_buf 278.3 10.88 FN +u_rp\[4\].u_buf 368.46 10.88 FN +u_rp\[5\].u_buf 458.62 10.88 FN +u_rp\[6\].u_buf 548.78 10.88 FN +u_rp\[7\].u_buf 638.94 10.88 FN +u_rp\[8\].u_buf 729.1 10.88 FN +u_rp\[9\].u_buf 819.26 10.88 FN +u_rp\[10\].u_buf 909.42 10.88 FN +u_rp\[11\].u_buf 999.58 10.88 FN +u_rp\[12\].u_buf 1089.74 10.88 FN +u_rp\[13\].u_buf 1179.9 10.88 FN +u_rp\[14\].u_buf 1270.06 10.88 FN +u_rp\[15\].u_buf 1360.22 10.88 FN +u_rp\[16\].u_buf 1450.38 10.88 FN +u_rp\[17\].u_buf 1540.54 10.88 FN +u_rp\[18\].u_buf 1630.7 10.88 FN +u_rp\[19\].u_buf 1720.86 10.88 FN +u_rp\[20\].u_buf 1811.02 10.88 FN +u_rp\[21\].u_buf 1901.18 10.88 FN +u_rp\[22\].u_buf 1991.34 10.88 FN +u_rp\[23\].u_buf 2081.5 10.88 FN +u_rp\[24\].u_buf 2171.66 10.88 FN +u_rp\[25\].u_buf 2261.82 10.88 FN +u_rp\[26\].u_buf 2351.98 10.88 FN
diff --git a/openlane/bus_rep_north/pdn.tcl b/openlane/bus_rep_north/pdn.tcl new file mode 100644 index 0000000..1fe689b --- /dev/null +++ b/openlane/bus_rep_north/pdn.tcl
@@ -0,0 +1,49 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Power nets +set ::power_nets $::env(VDD_PIN) +set ::ground_nets $::env(GND_PIN) + +set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" + +pdngen::specify_grid stdcell { + name grid + rails { + met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} + } + straps { + met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + } + connect {{met1 met4} {met4 met5}} +} + +pdngen::specify_grid macro { + power_pins "VPWR" + ground_pins "VGND" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} +} + +set ::halo 5 + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_north/pin_order.cfg b/openlane/bus_rep_north/pin_order.cfg new file mode 100644 index 0000000..d6472e3 --- /dev/null +++ b/openlane/bus_rep_north/pin_order.cfg
@@ -0,0 +1,61 @@ +#BUS_SORT + +#MANUAL_PLACE + +#N +ch_out\[0\] 0 0 250 +ch_out\[1\] +ch_in\[2\] +ch_out\[3\] +ch_out\[4\] +ch_in\[5\] +ch_out\[6\] +ch_out\[7\] +ch_in\[8\] +ch_out\[9\] +ch_out\[10\] +ch_in\[11\] +ch_out\[12\] +ch_out\[13\] +ch_in\[14\] +ch_out\[15\] +ch_out\[16\] +ch_in\[17\] +ch_out\[18\] +ch_out\[19\] +ch_in\[20\] +ch_out\[21\] +ch_out\[22\] +ch_in\[23\] +ch_out\[24\] +ch_out\[25\] +ch_in\[26\] + +#S +ch_in\[0\] 2000 0 64 +ch_in\[1\] +ch_out\[2\] +ch_in\[3\] +ch_in\[4\] +ch_out\[5\] +ch_in\[6\] +ch_in\[7\] +ch_out\[8\] +ch_in\[9\] +ch_in\[10\] +ch_out\[11\] +ch_in\[12\] +ch_in\[13\] +ch_out\[14\] +ch_in\[15\] +ch_in\[16\] +ch_out\[17\] +ch_in\[18\] +ch_in\[19\] +ch_out\[20\] +ch_in\[21\] +ch_in\[22\] +ch_out\[23\] +ch_in\[24\] +ch_in\[25\] +ch_out\[26\]
diff --git a/openlane/bus_rep_south/macro.cfg b/openlane/bus_rep_south/macro.cfg new file mode 100644 index 0000000..535d4ee --- /dev/null +++ b/openlane/bus_rep_south/macro.cfg
@@ -0,0 +1,254 @@ +u_rp\[0\].u_buf 7.82 10.88 FN +u_rp\[1\].u_buf 7.82 16.32 FN +u_rp\[2\].u_buf 20.7 10.88 FN +u_rp\[3\].u_buf 20.7 16.32 FN +u_rp\[4\].u_buf 33.58 10.88 FN +u_rp\[5\].u_buf 33.58 16.32 FN +u_rp\[6\].u_buf 46.46 10.88 FN +u_rp\[7\].u_buf 46.46 16.32 FN +u_rp\[8\].u_buf 59.34 10.88 FN +u_rp\[9\].u_buf 59.34 16.32 FN +u_rp\[10\].u_buf 72.22 10.88 FN +u_rp\[11\].u_buf 72.22 16.32 FN +u_rp\[12\].u_buf 85.1 10.88 FN +u_rp\[13\].u_buf 85.1 16.32 FN +u_rp\[14\].u_buf 97.98 10.88 FN +u_rp\[15\].u_buf 97.98 16.32 FN +u_rp\[16\].u_buf 110.86 10.88 FN +u_rp\[17\].u_buf 110.86 16.32 FN +u_rp\[18\].u_buf 123.74 10.88 FN +u_rp\[19\].u_buf 123.74 16.32 FN +u_rp\[20\].u_buf 136.62 10.88 FN +u_rp\[21\].u_buf 136.62 16.32 FN +u_rp\[22\].u_buf 149.5 10.88 FN +u_rp\[23\].u_buf 149.5 16.32 FN +u_rp\[24\].u_buf 162.38 10.88 FN +u_rp\[25\].u_buf 162.38 16.32 FN +u_rp\[26\].u_buf 175.26 10.88 FN +u_rp\[27\].u_buf 175.26 16.32 FN +u_rp\[28\].u_buf 188.14 10.88 FN +u_rp\[29\].u_buf 188.14 16.32 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diff --git a/openlane/bus_rep_west/config.tcl b/openlane/bus_rep_west/config.tcl new file mode 100755 index 0000000..7cae84a --- /dev/null +++ b/openlane/bus_rep_west/config.tcl
@@ -0,0 +1,134 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + +# Global +# ------ + +set script_dir [file dirname [file normalize [info script]]] +# Name +set ::env(DESIGN_NAME) bus_rep_west + + +set ::env(DESIGN_IS_CORE) "1" +set ::env(FP_PDN_CORE_RING) {1} + +# Timing configuration +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "" +set ::env(CLOCK_NET) "" + +set ::env(SYNTH_MAX_FANOUT) 4 +set ::env(SYNTH_BUFFERING) {0} + + +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + +# Sources +# ------- + +# Local sources + no2usb sources +set ::env(VERILOG_FILES) "\ + $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_west.sv \ + " + +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + +set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=42 " + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc + +set ::env(LEC_ENABLE) 0 + +set ::env(VDD_PIN) [list {vccd1}] +set ::env(GND_PIN) [list {vssd1}] + + +# Floorplanning +# ------------- + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg +set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 3250 50" + +#set ::env(GRT_OBS) "met4 0 0 300 1725" + +# If you're going to use multiple power domains, then keep this disabled. +set ::env(RUN_CVC) 0 + +#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl + + + +set ::env(PL_TIME_DRIVEN) 1 +set ::env(PL_TARGET_DENSITY) "0.20" +set ::env(CELL_PAD) "8" +set ::env(GRT_ADJUSTMENT) 0.2 + +# helps in anteena fix +set ::env(USE_ARC_ANTENNA_CHECK) "0" + + +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +set ::env(DIODE_INSERTION_STRATEGY) 4 + +## CTS +set ::env(CLOCK_TREE_SYNTH) {0} + +## Placement +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0" + +## Routing +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" + +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + +#set ::env(GLB_RT_MAXLAYER) 3 +set ::env(RT_MAX_LAYER) {met3} +set ::env(FP_PDN_LOWER_LAYER) {met2} +set ::env(FP_PDN_UPPER_LAYER) {met3} + +set ::env(FP_IO_HLAYER) {met2} +set ::env(FP_IO_VLAYER) {met1} + +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + +## Placement +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 +set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2 +set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500" +set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0" + +set ::env(ECO_ENABLE) {0} +#set ::env(CURRENT_STEP) "synthesis" +#set ::env(LAST_STEP) "parasitics_sta" + +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" +set ::env(QUIT_ON_MAGIC_DRC) "1" +set ::env(QUIT_ON_LVS_ERROR) "1" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_west/interactive.tcl b/openlane/bus_rep_west/interactive.tcl new file mode 100755 index 0000000..5b5c6c8 --- /dev/null +++ b/openlane/bus_rep_west/interactive.tcl
@@ -0,0 +1,337 @@ +#!/usr/bin/env tclsh +# Copyright 2020-2022 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +package require openlane; # provides the utils as well +proc run_placement_step {args} { + if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { + set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) + } + + run_placement +} + +proc run_cts_step {args} { + if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { + set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) + } + + run_cts + run_resizer_timing + if { $::env(RSZ_USE_OLD_REMOVER) == 1} { + remove_buffers_from_nets + } +} + +proc run_routing_step {args} { + if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { + set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) + } + if { $::env(ECO_ENABLE) == 0 } { + run_routing + } +} + +proc run_parasitics_sta_step {args} { + if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } { + set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF) + } + + if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} { + run_parasitics_sta + } +} + +proc run_diode_insertion_2_5_step {args} { + if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { + set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) + } + if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { + run_antenna_check + heal_antenna_violators; # modifies the routed DEF + } + +} + +proc run_irdrop_report_step {args} { + if { $::env(RUN_IRDROP_REPORT) } { + run_irdrop_report + } +} + +proc run_lvs_step {{ lvs_enabled 1 }} { + if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { + set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) + } + + if { $lvs_enabled && $::env(RUN_LVS) } { + run_magic_spice_export; + run_lvs; # requires run_magic_spice_export + } + +} + +proc run_drc_step {{ drc_enabled 1 }} { + if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { + set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) + } + if { $drc_enabled } { + if { $::env(RUN_MAGIC_DRC) } { + run_magic_drc + } + if {$::env(RUN_KLAYOUT_DRC)} { + run_klayout_drc + } + } +} + +proc run_antenna_check_step {{ antenna_check_enabled 1 }} { + if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { + set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) + } + if { $antenna_check_enabled } { + run_antenna_check + } +} + +proc run_erc_step {args} { + if { $::env(RUN_CVC) } { + run_erc + } +} + +proc run_eco_step {args} { + if { $::env(ECO_ENABLE) == 1 } { + run_eco_flow + } +} + +proc run_magic_step {args} { + if {$::env(RUN_MAGIC)} { + run_magic + } +} + +proc run_klayout_step {args} { + if {$::env(RUN_KLAYOUT)} { + run_klayout + } + if {$::env(RUN_KLAYOUT_XOR)} { + run_klayout_gds_xor + } +} + +proc run_post_run_hooks {} { + if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} { + puts_info "Running post run hook" + set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py] + puts_info "$result" + } else { + puts_info "hooks/post_run.py not found, skipping" + } +} + +proc run_floorplan {args} { + # |----------------------------------------------------| + # |---------------- 2. FLOORPLAN ------------------| + # |----------------------------------------------------| + # + # intial fp + init_floorplan + + # check for deprecated io variables + if { [info exists ::env(FP_IO_HMETAL)]} { + set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]] + puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}" + } + + if { [info exists ::env(FP_IO_VMETAL)]} { + set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]] + puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}" + } + + + # place io + if { [info exists ::env(FP_PIN_ORDER_CFG)] } { + place_io_ol + } else { + if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } { + place_io + global_placement_or + place_contextualized_io \ + -lef $::env(FP_CONTEXT_LEF) \ + -def $::env(FP_CONTEXT_DEF) + } else { + place_io + } + } + + apply_def_template + + #if { [info exist ::env(EXTRA_LEFS)] } { + if { [info exist ::env(MACRO_PLACEMENT_CFG)] } { + file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg + manual_macro_placement -f + } else { + # global_placement_or + # basic_macro_placement + } + #} + + if { $::env(RUN_TAP_DECAP_INSERTION) } { + tap_decap_or + } + + scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log + + run_power_grid_generation +} + + + +proc run_flow {args} { + set options { + {-design optional} + {-from optional} + {-to optional} + {-save_path optional} + {-override_env optional} + } + set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui} + parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume + + prep {*}$args + # signal trap SIGINT save_state; + + if { [info exists flags_map(-gui)] } { + or_gui + return + } + if { [info exists arg_values(-override_env)] } { + load_overrides $arg_values(-override_env) + } + + set LVS_ENABLED 1 + set DRC_ENABLED 1 + + set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ] + + set steps [dict create \ + "synthesis" "run_synthesis" \ + "floorplan" "run_floorplan" \ + "placement" "run_placement_step" \ + "cts" "run_cts_step" \ + "routing" "run_routing_step" \ + "parasitics_sta" "run_parasitics_sta_step" \ + "eco" "run_eco_step" \ + "diode_insertion" "run_diode_insertion_2_5_step" \ + "irdrop" "run_irdrop_report_step" \ + "gds_magic" "run_magic_step" \ + "gds_klayout" "run_klayout_step" \ + "lvs" "run_lvs_step $LVS_ENABLED " \ + "drc" "run_drc_step $DRC_ENABLED " \ + "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \ + "cvc" "run_lef_cvc" + ] + + if { [info exists arg_values(-from) ]} { + puts_info "Starting flow at $arg_values(-from)..." + set ::env(CURRENT_STEP) $arg_values(-from) + } elseif { [info exists ::env(CURRENT_STEP) ] } { + puts_info "Resuming flow from $::env(CURRENT_STEP)..." + } else { + set ::env(CURRENT_STEP) "synthesis" + } + + set_if_unset arg_values(-from) $::env(CURRENT_STEP) + set_if_unset arg_values(-to) "cvc" + + set exe 0; + dict for {step_name step_exe} $steps { + if { [ string equal $arg_values(-from) $step_name ] } { + set exe 1; + } + + if { $exe } { + # For when it fails + set ::env(CURRENT_STEP) $step_name + [lindex $step_exe 0] [lindex $step_exe 1] ; + } + + if { [ string equal $arg_values(-to) $step_name ] } { + set exe 0: + break; + } + + } + + # for when it resumes + set steps_as_list [dict keys $steps] + set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] + set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] + + # Saves to <RUN_DIR>/results/final + save_final_views + + # Saves to design directory or custom + if { [info exists flags_map(-save) ] } { + if { ! [info exists arg_values(-save_path)] } { + set arg_values(-save_path) $::env(DESIGN_DIR) + } + save_final_views\ + -save_path $arg_values(-save_path)\ + -tag $::env(RUN_TAG) + } + calc_total_runtime + save_state + generate_final_summary_report + + check_timing_violations + + if { [info exists arg_values(-save_path)]\ + && $arg_values(-save_path) != "" } { + set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]" + } else { + set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final + } + + if {[info exists flags_map(-run_hooks)]} { + run_post_run_hooks + } + + puts_success "Flow complete." + + show_warnings "Note that the following warnings have been generated:" +} + +run_flow {*}$argv
diff --git a/openlane/bus_rep_west/macro.cfg b/openlane/bus_rep_west/macro.cfg new file mode 100644 index 0000000..5bd9eb4 --- /dev/null +++ b/openlane/bus_rep_west/macro.cfg
@@ -0,0 +1,42 @@ +u_rp\[0\].u_buf 7.82 10.88 FN +u_rp\[1\].u_buf 85.1 10.88 FN +u_rp\[2\].u_buf 162.38 10.88 FN +u_rp\[3\].u_buf 239.66 10.88 FN +u_rp\[4\].u_buf 316.94 10.88 FN +u_rp\[5\].u_buf 394.22 10.88 FN +u_rp\[6\].u_buf 471.5 10.88 FN +u_rp\[7\].u_buf 548.78 10.88 FN +u_rp\[8\].u_buf 626.06 10.88 FN +u_rp\[9\].u_buf 703.34 10.88 FN +u_rp\[10\].u_buf 780.62 10.88 FN +u_rp\[11\].u_buf 857.9 10.88 FN +u_rp\[12\].u_buf 935.18 10.88 FN +u_rp\[13\].u_buf 1012.46 10.88 FN +u_rp\[14\].u_buf 1089.74 10.88 FN +u_rp\[15\].u_buf 1167.02 10.88 FN +u_rp\[16\].u_buf 1244.3 10.88 FN +u_rp\[17\].u_buf 1321.58 10.88 FN +u_rp\[18\].u_buf 1398.86 10.88 FN +u_rp\[19\].u_buf 1476.14 10.88 FN +u_rp\[20\].u_buf 1553.42 10.88 FN +u_rp\[21\].u_buf 1630.7 10.88 FN +u_rp\[22\].u_buf 1707.98 10.88 FN +u_rp\[23\].u_buf 1785.26 10.88 FN +u_rp\[24\].u_buf 1862.54 10.88 FN +u_rp\[25\].u_buf 1939.82 10.88 FN +u_rp\[26\].u_buf 2017.1 10.88 FN +u_rp\[27\].u_buf 2094.38 10.88 FN +u_rp\[28\].u_buf 2171.66 10.88 FN +u_rp\[29\].u_buf 2248.94 10.88 FN +u_rp\[30\].u_buf 2326.22 10.88 FN +u_rp\[31\].u_buf 2403.5 10.88 FN +u_rp\[32\].u_buf 2480.78 10.88 FN +u_rp\[33\].u_buf 2558.06 10.88 FN +u_rp\[34\].u_buf 2635.34 10.88 FN +u_rp\[35\].u_buf 2712.62 10.88 FN +u_rp\[36\].u_buf 2789.9 10.88 FN +u_rp\[37\].u_buf 2867.18 10.88 FN +u_rp\[38\].u_buf 2944.46 10.88 FN +u_rp\[39\].u_buf 3021.74 10.88 FN +u_rp\[40\].u_buf 3099.02 10.88 FN +u_rp\[41\].u_buf 3176.3 10.88 FN
diff --git a/openlane/bus_rep_west/pdn.tcl b/openlane/bus_rep_west/pdn.tcl new file mode 100644 index 0000000..1fe689b --- /dev/null +++ b/openlane/bus_rep_west/pdn.tcl
@@ -0,0 +1,49 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Power nets +set ::power_nets $::env(VDD_PIN) +set ::ground_nets $::env(GND_PIN) + +set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" + +pdngen::specify_grid stdcell { + name grid + rails { + met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} + } + straps { + met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + } + connect {{met1 met4} {met4 met5}} +} + +pdngen::specify_grid macro { + power_pins "VPWR" + ground_pins "VGND" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} +} + +set ::halo 5 + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_west/pin_order.cfg b/openlane/bus_rep_west/pin_order.cfg new file mode 100644 index 0000000..74e6240 --- /dev/null +++ b/openlane/bus_rep_west/pin_order.cfg
@@ -0,0 +1,91 @@ +#BUS_SORT + +#MANUAL_PLACE + +#S +ch_in\[0\] 0 0 225 +ch_out\[1\] +ch_out\[2\] +ch_in\[3\] +ch_out\[4\] +ch_out\[5\] +ch_in\[6\] +ch_out\[7\] +ch_out\[8\] +ch_in\[9\] +ch_out\[10\] +ch_out\[11\] +ch_in\[12\] +ch_out\[13\] +ch_out\[14\] +ch_in\[15\] +ch_out\[16\] +ch_out\[17\] +ch_in\[18\] +ch_out\[19\] +ch_out\[20\] +ch_in\[21\] +ch_out\[22\] +ch_out\[23\] +ch_in\[24\] +ch_out\[25\] +ch_out\[26\] +ch_in\[27\] +ch_out\[28\] +ch_out\[29\] +ch_in\[30\] +ch_out\[31\] +ch_out\[32\] +ch_in\[33\] +ch_out\[34\] +ch_out\[35\] +ch_in\[36\] +ch_out\[37\] +ch_out\[38\] +ch_in\[39\] +ch_out\[40\] +ch_out\[41\] + +#N +ch_out\[0\] 100 0 4 +ch_in\[1\] +ch_in\[2\] +ch_out\[3\] +ch_in\[4\] +ch_in\[5\] +ch_out\[6\] +ch_in\[7\] +ch_in\[8\] +ch_out\[9\] +ch_in\[10\] +ch_in\[11\] +ch_out\[12\] +ch_in\[13\] +ch_in\[14\] +ch_out\[15\] +ch_in\[16\] +ch_in\[17\] +ch_out\[18\] +ch_in\[19\] +ch_in\[20\] +ch_out\[21\] +ch_in\[22\] +ch_in\[23\] +ch_out\[24\] +ch_in\[25\] +ch_in\[26\] +ch_out\[27\] +ch_in\[28\] +ch_in\[29\] +ch_out\[30\] +ch_in\[31\] +ch_in\[32\] +ch_out\[33\] +ch_in\[34\] +ch_in\[35\] +ch_out\[36\] +ch_in\[37\] +ch_in\[38\] +ch_out\[39\] +ch_in\[40\] +ch_in\[41\]
diff --git a/verilog/rtl/bus_rep/bus_rep_east.sv b/verilog/rtl/bus_rep/bus_rep_east.sv new file mode 100644 index 0000000..6e7626d --- /dev/null +++ b/verilog/rtl/bus_rep/bus_rep_east.sv
@@ -0,0 +1,52 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +// Bus Repater // +////////////////////////////////////////////////////////////////////// +module bus_rep_east #( + parameter BUS_REP_WD = 7 + ) ( +`ifdef USE_POWER_PINS + input logic vccd1, // User area 1 1.8V supply + input logic vssd1, // User area 1 digital ground +`endif + // Bus repeaters + input [BUS_REP_WD-1:0] ch_in, + output [BUS_REP_WD-1:0] ch_out + ); + +// channel repeater + +`ifndef SYNTHESIS + +assign ch_out = ch_in; + +`else + + genvar i; + generate + for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp + sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i])); + end + endgenerate + +`endif + + +endmodule +
diff --git a/verilog/rtl/bus_rep/bus_rep_north.sv b/verilog/rtl/bus_rep/bus_rep_north.sv new file mode 100644 index 0000000..bb13510 --- /dev/null +++ b/verilog/rtl/bus_rep/bus_rep_north.sv
@@ -0,0 +1,52 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +// Bus Repater // +////////////////////////////////////////////////////////////////////// +module bus_rep_north #( + parameter BUS_REP_WD = 7 + ) ( +`ifdef USE_POWER_PINS + input logic vccd1, // User area 1 1.8V supply + input logic vssd1, // User area 1 digital ground +`endif + // Bus repeaters + input [BUS_REP_WD-1:0] ch_in, + output [BUS_REP_WD-1:0] ch_out + ); + +// channel repeater + +`ifndef SYNTHESIS + +assign ch_out = ch_in; + +`else + + genvar i; + generate + for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp + sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i])); + end + endgenerate + +`endif + + +endmodule +
diff --git a/verilog/rtl/bus_rep/bus_rep_west.sv b/verilog/rtl/bus_rep/bus_rep_west.sv new file mode 100644 index 0000000..f02c930 --- /dev/null +++ b/verilog/rtl/bus_rep/bus_rep_west.sv
@@ -0,0 +1,52 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +// Bus Repater // +////////////////////////////////////////////////////////////////////// +module bus_rep_west #( + parameter BUS_REP_WD = 7 + ) ( +`ifdef USE_POWER_PINS + input logic vccd1, // User area 1 1.8V supply + input logic vssd1, // User area 1 digital ground +`endif + // Bus repeaters + input [BUS_REP_WD-1:0] ch_in, + output [BUS_REP_WD-1:0] ch_out + ); + +// channel repeater + +`ifndef SYNTHESIS + +assign ch_out = ch_in; + +`else + + genvar i; + generate + for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp + sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i])); + end + endgenerate + +`endif + + +endmodule +