| ############################################################################### |
| # Created by write_sdc |
| # Wed Nov 10 17:01:46 2021 |
| ############################################################################### |
| current_design qspim_top |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name mclk -period 10.0000 [get_ports {mclk}] |
| set_propagated_clock [get_clocks {mclk}] |
| create_generated_clock -name spiclk -add -source [get_ports {mclk}] -master_clock [get_clocks {mclk}] -divide_by 2 -comment {SPI Clock Out} [get_ports {spi_clk}] |
| #Keep in transparent zero delay path |
| set_case_analysis 0 [get_ports {cfg_cska_spi[3]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[0]}] |
| |
| #Keep the Clock Skew in center of the Mux |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}] |
| set_case_analysis 1 [get_ports {cfg_cska_sp_co[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}] |
| |
| set_propagated_clock [get_clocks {spiclk}] |
| |
| set_clock_transition 0.1500 [all_clocks] |
| set_clock_uncertainty -setup 0.2500 [all_clocks] |
| set_clock_uncertainty -hold 0.2500 [all_clocks] |
| |
| set ::env(SYNTH_TIMING_DERATE) 0.05 |
| puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" |
| set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] |
| set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] |
| |
| ### ClkSkew Adjust |
| set_case_analysis 0 [get_ports {cfg_cska_spi[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[3]}] |
| |
| |
| set_max_delay 3.5 -from [get_ports {wbd_clk_int}] |
| set_max_delay 2 -to [get_ports {wbd_clk_spi}] |
| set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_spi |
| |
| #Static Clock Skew control |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}] |
| |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}] |
| |
| set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[0]}] |
| set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[1]}] |
| set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[2]}] |
| set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[3]}] |
| |
| |
| set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[0]}] |
| set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[1]}] |
| set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[2]}] |
| set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[3]}] |
| |
| |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}] |
| |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}] |
| |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[3]}] |
| |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[0]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}] |
| |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}] |
| |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}] |
| set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[3]}] |
| |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_stb_i}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_we_i}] |
| |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[0]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[10]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[11]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[12]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[13]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[14]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[15]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[16]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[17]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[18]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[19]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[1]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[20]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[21]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[22]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[23]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[24]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[25]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[26]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[27]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[28]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[29]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[2]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[30]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[31]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[3]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[4]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[5]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[6]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[7]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[8]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[9]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[0]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[10]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[11]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[12]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[13]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[14]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[15]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[16]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[17]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[18]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[19]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[1]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[20]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[21]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[22]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[23]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[24]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[25]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[26]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[27]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[28]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[29]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[2]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[30]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[31]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[3]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[4]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[5]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[6]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[7]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[8]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[9]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[0]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[1]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[2]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[3]}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_stb_i}] |
| set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_we_i}] |
| |
| set_max_delay 10.0000 -to [get_ports {spi_debug[0]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[10]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[11]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[12]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[13]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[14]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[15]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[16]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[17]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[18]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[19]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[1]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[20]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[21]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[22]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[23]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[24]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[25]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[26]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[27]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[28]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[29]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[2]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[30]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[31]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[3]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[4]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[5]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[6]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[7]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[8]}] |
| set_max_delay 10.0000 -to [get_ports {spi_debug[9]}] |
| |
| set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}] |
| set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}] |
| set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}] |
| |
| set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}] |
| set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}] |
| set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs] |
| set cap_load 0.0334 |
| puts "\[INFO\]: Setting load to: $cap_load" |
| set_load $cap_load [all_outputs] |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
