| [submodule "verilog/rtl/qspim"] |
| path = verilog/rtl/qspim |
| url = https://github.com/dineshannayya/qspim.git |
| [submodule "verilog/dv/common/riscduino_board"] |
| path = verilog/dv/common/riscduino_board |
| url = https://github.com/dineshannayya/riscduino_board.git |
| [submodule "verilog/rtl/yifive/ycr1cr"] |
| path = verilog/rtl/yifive/ycr1c |
| url = https://github.com/dineshannayya/ycr1cr.git |
| [submodule "verilog/rtl/security_core"] |
| path = verilog/rtl/security_core |
| url = https://github.com/dineshannayya/security_core |
| [submodule "verilog/rtl/fpu"] |
| path = verilog/rtl/fpu |
| url = https://github.com/dineshannayya/fpu |
| [submodule "verilog/rtl/rtc"] |
| path = verilog/rtl/rtc |
| url = https://github.com/dineshannayya/rtc |
