clk skew [31:28] default fix
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 9bfe51c..d094fb3 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index c15d4f1..8516507 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 3a0fe8c..f9e05c7 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Fri Dec 9 15:55:05 2022
+# Sat Dec 10 03:27:10 2022
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
index 4e29404..b816558 100644
--- a/sdc/wb_host.sdc
+++ b/sdc/wb_host.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Thu Dec 8 15:54:53 2022
+# Sat Dec 10 02:52:40 2022
###############################################################################
current_design wb_host
###############################################################################
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 9263c42..b8e1f5f 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -92,7 +92,7 @@
`ifdef GL
// Note During wb_host resynth this FF is changes,
// Keep cross-check during Gate Sim
- force u_top.u_wb_host._10184_.Q= 1'b1;
+ force u_top.u_wb_host._10258_.Q= 1'b1;
//force u_top.u_wb_host.u_reg.u_fastsim_buf.u_buf.X = 1'b1;
//force u_top.u_wb_host.u_reg.cfg_fast_sim = 1'b1;
`else
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index fc0b5eb..580b4d2 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -173,7 +173,7 @@
(strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 :
(strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
-assign skew_config[31:28] = 4'b0;
+assign skew_config[31:28] = CLK_SKEW1_RESET_VAL[31:28];
//----------------------------------------------------------
reg [3:0] cpu_clk_cfg,wbs_clk_cfg;
@@ -668,7 +668,7 @@
input real exp_period;
begin
`ifdef GL
- force clock_mon = u_top.u_wb_host._10399_.Q;
+ force clock_mon = u_top.u_wb_host._10372_.Q;
`else
force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
`endif
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index d7543d3..94493cd 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bad1917..32da490 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1036,50 +1036,50 @@
//------------------------------------------------------------------------------
ycr_top_wb u_riscv_top (
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .wbd_clk_int (wbd_clk_risc_rp ),
- .cfg_wcska_riscv_intf(cfg_wcska_riscv_rp ),
- .wbd_clk_skew (wbd_clk_riscv_skew ),
+ .wbd_clk_int (wbd_clk_risc_rp ),
+ .cfg_wcska_riscv_intf (cfg_wcska_riscv_rp ),
+ .wbd_clk_skew (wbd_clk_riscv_skew ),
// Reset
- .pwrup_rst_n (wbd_int_rst_n ),
- .rst_n (wbd_int_rst_n ),
- .cpu_intf_rst_n (cpu_intf_rst_n ),
- .cpu_core_rst_n (cpu_core_rst_n[0] ),
- .riscv_debug (riscv_debug ),
- .cfg_sram_lphase (cfg_riscv_sram_lphase ),
- .cfg_cache_ctrl (cfg_riscv_cache_ctrl ),
- .cfg_bypass_icache (cfg_bypass_icache ),
- .cfg_bypass_dcache (cfg_bypass_dcache ),
+ .pwrup_rst_n (wbd_int_rst_n ),
+ .rst_n (wbd_int_rst_n ),
+ .cpu_intf_rst_n (cpu_intf_rst_n ),
+ .cpu_core_rst_n (cpu_core_rst_n[0] ),
+ .riscv_debug (riscv_debug ),
+ .cfg_sram_lphase (cfg_riscv_sram_lphase ),
+ .cfg_cache_ctrl (cfg_riscv_cache_ctrl ),
+ .cfg_bypass_icache (cfg_bypass_icache ),
+ .cfg_bypass_dcache (cfg_bypass_dcache ),
// Clock
- .core_clk_int (cpu_clk_rp_risc ),
- .cfg_ccska_riscv_intf (cfg_ccska_riscv_intf_rp ),
- .cfg_ccska_riscv_icon (cfg_ccska_riscv_icon_rp ),
- .cfg_ccska_riscv_core0(cfg_ccska_riscv_core0_rp ),
+ .core_clk_int (cpu_clk_rp_risc ),
+ .cfg_ccska_riscv_intf (cfg_ccska_riscv_intf_rp ),
+ .cfg_ccska_riscv_icon (cfg_ccska_riscv_icon_rp ),
+ .cfg_ccska_riscv_core0 (cfg_ccska_riscv_core0_rp ),
- .rtc_clk (rtc_clk ),
+ .rtc_clk (rtc_clk ),
// IRQ
- .irq_lines (irq_lines_rp ),
- .soft_irq (soft_irq_rp ), // TODO - Interrupts
+ .irq_lines (irq_lines_rp ),
+ .soft_irq (soft_irq_rp ), // TODO - Interrupts
// DFT
- // .test_mode (1'b0 ), // Moved inside IP
- // .test_rst_n (1'b1 ), // Moved inside IP
+ // .test_mode (1'b0 ), // Moved inside IP
+ // .test_rst_n (1'b1 ), // Moved inside IP
`ifndef SCR1_TCM_MEM
// SRAM-0 PORT-0
- .sram0_clk0 (sram0_clk0 ),
- .sram0_csb0 (sram0_csb0 ),
- .sram0_web0 (sram0_web0 ),
- .sram0_addr0 (sram0_addr0 ),
- .sram0_wmask0 (sram0_wmask0 ),
- .sram0_din0 (sram0_din0 ),
- .sram0_dout0 (sram0_dout0 ),
+ .sram0_clk0 (sram0_clk0 ),
+ .sram0_csb0 (sram0_csb0 ),
+ .sram0_web0 (sram0_web0 ),
+ .sram0_addr0 (sram0_addr0 ),
+ .sram0_wmask0 (sram0_wmask0 ),
+ .sram0_din0 (sram0_din0 ),
+ .sram0_dout0 (sram0_dout0 ),
// SRAM-0 PORT-0
.sram0_clk1 (sram0_clk1 ),
@@ -1295,25 +1295,25 @@
*************************************************/
aes_top u_aes (
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),
- .vssd1 (vssd1 ),
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
`endif
- .mclk (cpu_clk_aes_skew ),
- .rst_n (cpu_intf_rst_n ),
+ .mclk (cpu_clk_aes_skew ),
+ .rst_n (cpu_intf_rst_n ),
- .cfg_cska (cfg_ccska_aes_rp ),
- .wbd_clk_int (cpu_clk_aes ),
- .wbd_clk_out (cpu_clk_aes_skew ),
+ .cfg_cska (cfg_ccska_aes_rp ),
+ .wbd_clk_int (cpu_clk_aes ),
+ .wbd_clk_out (cpu_clk_aes_skew ),
- .dmem_req (aes_dmem_req ),
- .dmem_cmd (aes_dmem_cmd ),
- .dmem_width (aes_dmem_width ),
- .dmem_addr (aes_dmem_addr ),
- .dmem_wdata (aes_dmem_wdata ),
- .dmem_req_ack (aes_dmem_req_ack ),
- .dmem_rdata (aes_dmem_rdata ),
- .dmem_resp (aes_dmem_resp )
+ .dmem_req (aes_dmem_req ),
+ .dmem_cmd (aes_dmem_cmd ),
+ .dmem_width (aes_dmem_width ),
+ .dmem_addr (aes_dmem_addr ),
+ .dmem_wdata (aes_dmem_wdata ),
+ .dmem_req_ack (aes_dmem_req_ack ),
+ .dmem_rdata (aes_dmem_rdata ),
+ .dmem_resp (aes_dmem_resp )
);
/***********************************************
@@ -1321,8 +1321,8 @@
*************************************************/
fpu_wrapper u_fpu (
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),
- .vssd1 (vssd1 ),
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
`endif
.mclk (cpu_clk_fpu_skew ),
@@ -1344,56 +1344,56 @@
/*********************************************************
* SPI Master
-* This is of an SPI master that is controlled via an AXI bus .
+* This is implementation of an SPI master that is controlled via an AXI bus .
* It has FIFOs for transmitting and receiving data.
* It supports both the normal SPI mode and QPI mode with 4 data lines.
* *******************************************************/
qspim_top
-# (
+#(
`ifndef SYNTHESIS
.WB_WIDTH (WB_WIDTH )
`endif
) u_qspi_master
(
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .mclk (wbd_clk_spi ),
- .rst_n (qspim_rst_n ),
+ .mclk (wbd_clk_spi ),
+ .rst_n (qspim_rst_n ),
- .strap_flash (strap_qspi_flash ),
- .strap_pre_sram (strap_qspi_pre_sram ),
- .strap_sram (strap_qspi_sram ),
- .cfg_init_bypass (strap_qspi_init_bypass ),
+ .strap_flash (strap_qspi_flash ),
+ .strap_pre_sram (strap_qspi_pre_sram ),
+ .strap_sram (strap_qspi_sram ),
+ .cfg_init_bypass (strap_qspi_init_bypass ),
// Clock Skew Adjust
- .cfg_cska_sp_co (cfg_wcska_qspi_co_rp ),
- .cfg_cska_spi (cfg_wcska_qspi_rp ),
- .wbd_clk_int (wbd_clk_qspi_rp ),
- .wbd_clk_spi (wbd_clk_spi ),
+ .cfg_cska_sp_co (cfg_wcska_qspi_co_rp ),
+ .cfg_cska_spi (cfg_wcska_qspi_rp ),
+ .wbd_clk_int (wbd_clk_qspi_rp ),
+ .wbd_clk_spi (wbd_clk_spi ),
- .wbd_stb_i (wbd_spim_stb_o ),
- .wbd_adr_i (wbd_spim_adr_o ),
- .wbd_we_i (wbd_spim_we_o ),
- .wbd_dat_i (wbd_spim_dat_o ),
- .wbd_sel_i (wbd_spim_sel_o ),
- .wbd_bl_i (wbd_spim_bl_o ),
- .wbd_bry_i (wbd_spim_bry_o ),
- .wbd_dat_o (wbd_spim_dat_i ),
- .wbd_ack_o (wbd_spim_ack_i ),
- .wbd_lack_o (wbd_spim_lack_i ),
- .wbd_err_o (wbd_spim_err_i ),
+ .wbd_stb_i (wbd_spim_stb_o ),
+ .wbd_adr_i (wbd_spim_adr_o ),
+ .wbd_we_i (wbd_spim_we_o ),
+ .wbd_dat_i (wbd_spim_dat_o ),
+ .wbd_sel_i (wbd_spim_sel_o ),
+ .wbd_bl_i (wbd_spim_bl_o ),
+ .wbd_bry_i (wbd_spim_bry_o ),
+ .wbd_dat_o (wbd_spim_dat_i ),
+ .wbd_ack_o (wbd_spim_ack_i ),
+ .wbd_lack_o (wbd_spim_lack_i ),
+ .wbd_err_o (wbd_spim_err_i ),
- .spi_debug (spi_debug ),
+ .spi_debug (spi_debug ),
// Pad Interface
- .spi_sdi (sflash_di ),
- .spi_clk (sflash_sck ),
- .spi_csn (spi_csn ),
- .spi_sdo (sflash_do ),
- .spi_oen (sflash_oen )
+ .spi_sdi (sflash_di ),
+ .spi_clk (sflash_sck ),
+ .spi_csn (spi_csn ),
+ .spi_sdo (sflash_do ),
+ .spi_oen (sflash_oen )
);
diff --git a/verilog/rtl/wb_host/src/wbh_reg.sv b/verilog/rtl/wb_host/src/wbh_reg.sv
index ab3ad2b..4c6a5ca 100644
--- a/verilog/rtl/wb_host/src/wbh_reg.sv
+++ b/verilog/rtl/wb_host/src/wbh_reg.sv
@@ -228,7 +228,7 @@
(strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 :
(strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
-assign rst_clk_ctrl1[31:28] = 4'b0;
+assign rst_clk_ctrl1[31:28] = CLK_SKEW1_RESET_VAL[31:28];
always @ (posedge mclk ) begin
