git clean-up large file
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index b9c8247..bf5b965 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -218,6 +218,8 @@ #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv +$(USER_PROJECT_VERILOG)/gl/aes_top.v +$(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
diff --git a/verilog/includes/includes.gl.lib b/verilog/includes/includes.gl.lib index f6100e2..a047636 100644 --- a/verilog/includes/includes.gl.lib +++ b/verilog/includes/includes.gl.lib
@@ -1,12 +1,12 @@ ########################################################### # STD CELLS - they need to be below the defines.v files ########################################################### --v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v --v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v --v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_sc_hd/verilog/primitives.v --v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v --v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v --v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v #$(USER_PROJECT_VERILOG)/gl/digital_pll.v -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv index e8243ad..6ff2dac 100644 --- a/verilog/rtl/pinmux/src/glbl_reg.sv +++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -367,7 +367,26 @@ assign irq_lines = reg_3[31:0] & reg_4[31:0]; // In Arduino GPIO[7:0] is corresponds to PORT-A which is not available for user access -wire [31:0] hware_intr_req = {gpio_intr[31:8], 2'b0,pwm_intr,usb_intr, i2cm_intr,timer_intr[2:0]}; + +logic usb_intr_s,usb_intr_ss; // Usb Interrupt Double Sync +logic i2cm_intr_s,i2cm_intr_ss; // I2C Interrupt Double Sync + +always @ (posedge mclk or negedge s_reset_n) +begin + if (s_reset_n == 1'b0) begin + usb_intr_s <= 'h0; + usb_intr_ss <= 'h0; + i2cm_intr_s <= 'h0; + i2cm_intr_ss <= 'h0; + end else begin + usb_intr_s <= usb_intr; + usb_intr_ss <= usb_intr_s; + i2cm_intr_s <= i2cm_intr; + i2cm_intr_ss <= i2cm_intr_s; + end +end + +wire [31:0] hware_intr_req = {gpio_intr[31:8], 2'b0,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]}; generic_intr_stat_reg #(.WD(32), .RESET_DEFAULT(0)) u_reg4 (
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh index faf789f..6d60270 100644 --- a/verilog/rtl/user_params.svh +++ b/verilog/rtl/user_params.svh
@@ -4,9 +4,9 @@ // ASCI Representation of RISC = 32'h8273_8343 parameter CHIP_SIGNATURE = 32'h8273_8343; // Software Reg-1, Release date: <DAY><MONTH><YEAR> -parameter CHIP_RELEASE_DATE = 32'h0711_2022; +parameter CHIP_RELEASE_DATE = 32'h2011_2022; // Software Reg-2: Poject Revison 5.1 = 0005200 -parameter CHIP_REVISION = 32'h0005_7000; +parameter CHIP_REVISION = 32'h0005_8000; parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_0111_1010_1000_1001_1100; parameter CLK_SKEW2_RESET_VAL = 32'b0000;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 67a8d11..09fd72f 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -288,6 +288,8 @@ //// 5.7 Nov 7, 2022, Dinesh A //// //// A. AES 128 Bit Encription and Decryption integration //// //// B. FPU Integration //// +//// 5.8 Nov 20, 2022, Dinesh A //// +//// A. Pinmux - Double Sync added for usb & i2c inter //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG ////