mpw-7 timing cleanup database
diff --git a/Makefile b/Makefile index a54eedb..2d433bf 100644 --- a/Makefile +++ b/Makefile
@@ -324,6 +324,6 @@ .PHONY: caravel-sta caravel-sta: ./env/spef-mapping.tcl @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ - @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast - @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow +# @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast +# @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow @echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/gds/aes_top.gds.gz b/gds/aes_top.gds.gz new file mode 100644 index 0000000..cbd7222 --- /dev/null +++ b/gds/aes_top.gds.gz Binary files differ
diff --git a/gds/dac_top.gds.gz b/gds/dac_top.gds.gz new file mode 100644 index 0000000..2dbfa41 --- /dev/null +++ b/gds/dac_top.gds.gz Binary files differ
diff --git a/gds/dg_pll.gds.gz b/gds/dg_pll.gds.gz new file mode 100644 index 0000000..d290c13 --- /dev/null +++ b/gds/dg_pll.gds.gz Binary files differ
diff --git a/gds/fpu_wrapper.gds.gz b/gds/fpu_wrapper.gds.gz new file mode 100644 index 0000000..eae5ad0 --- /dev/null +++ b/gds/fpu_wrapper.gds.gz Binary files differ
diff --git a/gds/pinmux_top.gds.gz b/gds/pinmux_top.gds.gz new file mode 100644 index 0000000..8770f2c --- /dev/null +++ b/gds/pinmux_top.gds.gz Binary files differ
diff --git a/gds/qspim_top.gds.gz b/gds/qspim_top.gds.gz new file mode 100644 index 0000000..97eda45 --- /dev/null +++ b/gds/qspim_top.gds.gz Binary files differ
diff --git a/gds/uart_i2c_usb_spi_top.gds.gz b/gds/uart_i2c_usb_spi_top.gds.gz new file mode 100644 index 0000000..127d77d --- /dev/null +++ b/gds/uart_i2c_usb_spi_top.gds.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz new file mode 100644 index 0000000..8ee6bed --- /dev/null +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz new file mode 100644 index 0000000..545827a --- /dev/null +++ b/gds/wb_host.gds.gz Binary files differ
diff --git a/gds/wb_interconnect.gds.gz b/gds/wb_interconnect.gds.gz new file mode 100644 index 0000000..4215a7d --- /dev/null +++ b/gds/wb_interconnect.gds.gz Binary files differ
diff --git a/gds/ycr_core_top.gds.gz b/gds/ycr_core_top.gds.gz new file mode 100644 index 0000000..cc2e1d3 --- /dev/null +++ b/gds/ycr_core_top.gds.gz Binary files differ
diff --git a/gds/ycr_iconnect.gds.gz b/gds/ycr_iconnect.gds.gz new file mode 100644 index 0000000..bf35859 --- /dev/null +++ b/gds/ycr_iconnect.gds.gz Binary files differ
diff --git a/gds/ycr_intf.gds.gz b/gds/ycr_intf.gds.gz new file mode 100644 index 0000000..5d1e7e0 --- /dev/null +++ b/gds/ycr_intf.gds.gz Binary files differ
diff --git a/lef/aes_top.lef.gz b/lef/aes_top.lef.gz new file mode 100644 index 0000000..31232e1 --- /dev/null +++ b/lef/aes_top.lef.gz Binary files differ
diff --git a/lef/dac_top.lef.gz b/lef/dac_top.lef.gz new file mode 100644 index 0000000..90d033e --- /dev/null +++ b/lef/dac_top.lef.gz Binary files differ
diff --git a/lef/dg_pll.lef.gz b/lef/dg_pll.lef.gz new file mode 100644 index 0000000..fcbd319 --- /dev/null +++ b/lef/dg_pll.lef.gz Binary files differ
diff --git a/lef/fpu_wrapper.lef.gz b/lef/fpu_wrapper.lef.gz new file mode 100644 index 0000000..f0dbe37 --- /dev/null +++ b/lef/fpu_wrapper.lef.gz Binary files differ
diff --git a/lef/pinmux_top.lef.gz b/lef/pinmux_top.lef.gz new file mode 100644 index 0000000..bc5b0ce --- /dev/null +++ b/lef/pinmux_top.lef.gz Binary files differ
diff --git a/lef/qspim_top.lef.gz b/lef/qspim_top.lef.gz new file mode 100644 index 0000000..5e80b24 --- /dev/null +++ b/lef/qspim_top.lef.gz Binary files differ
diff --git a/lef/uart_i2c_usb_spi_top.lef.gz b/lef/uart_i2c_usb_spi_top.lef.gz new file mode 100644 index 0000000..b1d98bd --- /dev/null +++ b/lef/uart_i2c_usb_spi_top.lef.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz new file mode 100644 index 0000000..76e768e --- /dev/null +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz new file mode 100644 index 0000000..c319c4f --- /dev/null +++ b/lef/wb_host.lef.gz Binary files differ
diff --git a/lef/wb_interconnect.lef.gz b/lef/wb_interconnect.lef.gz new file mode 100644 index 0000000..9d38f02 --- /dev/null +++ b/lef/wb_interconnect.lef.gz Binary files differ
diff --git a/lef/ycr_core_top.lef.gz b/lef/ycr_core_top.lef.gz new file mode 100644 index 0000000..ca37a90 --- /dev/null +++ b/lef/ycr_core_top.lef.gz Binary files differ
diff --git a/lef/ycr_iconnect.lef.gz b/lef/ycr_iconnect.lef.gz new file mode 100644 index 0000000..8160c33 --- /dev/null +++ b/lef/ycr_iconnect.lef.gz Binary files differ
diff --git a/lef/ycr_intf.lef.gz b/lef/ycr_intf.lef.gz new file mode 100644 index 0000000..a9e1e1d --- /dev/null +++ b/lef/ycr_intf.lef.gz Binary files differ
diff --git a/openlane/aes_top/config.tcl b/openlane/aes_top/config.tcl index 036e145..2d07219 100755 --- a/openlane/aes_top/config.tcl +++ b/openlane/aes_top/config.tcl
@@ -108,7 +108,7 @@ #LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {0} +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5} set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/dg_pll/config.tcl b/openlane/dg_pll/config.tcl index 0a00de1..ab632d6 100644 --- a/openlane/dg_pll/config.tcl +++ b/openlane/dg_pll/config.tcl
@@ -48,7 +48,7 @@ #set ::env(BOTTOM_MARGIN_MULT) 2 #LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {0} +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(CELL_PAD) 0
diff --git a/openlane/dg_pll/pin_order.cfg b/openlane/dg_pll/pin_order.cfg index b4d381d..247fd42 100644 --- a/openlane/dg_pll/pin_order.cfg +++ b/openlane/dg_pll/pin_order.cfg
@@ -1,3 +1,7 @@ + +#BUS_SORT +#MANUAL_PLACE + #N ext_trim\[7\] ext_trim\[8\]
diff --git a/openlane/fpu_wrapper/config.tcl b/openlane/fpu_wrapper/config.tcl index 801561e..cfb0176 100755 --- a/openlane/fpu_wrapper/config.tcl +++ b/openlane/fpu_wrapper/config.tcl
@@ -108,7 +108,7 @@ #LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {0} +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5} set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/pinmux_top/base.sdc b/openlane/pinmux_top/base.sdc index 9c22d9c..e642e15 100644 --- a/openlane/pinmux_top/base.sdc +++ b/openlane/pinmux_top/base.sdc
@@ -7,7 +7,32 @@ # Timing Constraints ############################################################################### create_clock -name mclk -period 10.0000 [get_ports {mclk}] -set_propagated_clock [get_clocks {mclk}] +create_clock -name user_clock1 -period 10.0000 [get_ports {user_clock1}] +create_clock -name user_clock2 -period 10.0000 [get_ports {user_clock2}] +create_clock -name int_pll_clock -period 5.0000 [get_pins {int_pll_clock}] +create_clock -name rtc_ref_clk -period 50.0000 [get_pins {u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}] +create_clock -name rtc_clk -period 50.0000 [get_pins {u_glbl_reg.u_clkbuf_rtc.u_buf/X}] +create_clock -name usb_ref_clk -period 5.0000 [get_pins {u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}] +create_clock -name dbg_ref_clk -period 10.0000 [get_pins {u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}] + + +set_clock_groups \ + -name clock_group \ + -logically_exclusive \ + -group [get_clocks {mclk}]\ + -group [get_clocks {user_clock1}]\ + -group [get_clocks {user_clock2}]\ + -group [get_clocks {int_pll_clock}]\ + -group [get_clocks {rtc_ref_clk}]\ + -group [get_clocks {rtc_clk}]\ + -group [get_clocks {usb_ref_clk}]\ + -group [get_clocks {dbg_ref_clk}]\ + -comment {Async Clock group} + + + +set_propagated_clock [all_clocks] + set_clock_transition 0.1500 [all_clocks] set_clock_uncertainty -setup 0.5000 [all_clocks]
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl index f30df93..d0e0a8f 100755 --- a/openlane/pinmux_top/config.tcl +++ b/openlane/pinmux_top/config.tcl
@@ -93,7 +93,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 520 850" +set ::env(DIE_AREA) "0 0 520 900" # If you're going to use multiple power domains, then keep this disabled. @@ -103,9 +103,9 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.38" +set ::env(PL_TARGET_DENSITY) "0.35" set ::env(CELL_PAD) "8" -set ::env(GRT_ADJUSTMENT) {0.2} +#set ::env(GRT_ADJUSTMENT) {0.2} ######################################################################################
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index b4c0b35..407a338 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -121,7 +121,7 @@ #LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {0} +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5} set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index 160df0d..46e1c2a 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -92,7 +92,7 @@ set ::env(DIODE_INSERTION_STRATEGY) 3 #LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {0} +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5} set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl index 2646b19..0d3f9e8 100644 --- a/openlane/ycr_iconnect/config.tcl +++ b/openlane/ycr_iconnect/config.tcl
@@ -82,7 +82,7 @@ set ::env(DIODE_INSERTION_STRATEGY) 3 #LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {0} +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5} set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index b77103e..048efde 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -79,7 +79,7 @@ set ::env(DIODE_INSERTION_STRATEGY) 3 #LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {0} +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5} set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION index b321d37..fabca1a 100644 --- a/signoff/pinmux_top/OPENLANE_VERSION +++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 9949f5d5f55749dc4b98648a25d355836895dc37 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES index 59f6ae6..ef91c87 100644 --- a/signoff/pinmux_top/PDK_SOURCES +++ b/signoff/pinmux_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION index b5bf449..fabca1a 100644 --- a/signoff/qspim_top/OPENLANE_VERSION +++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@ -openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES index f9d0f46..ef91c87 100644 --- a/signoff/qspim_top/PDK_SOURCES +++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION index b321d37..fabca1a 100644 --- a/signoff/user_project_wrapper/OPENLANE_VERSION +++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 9949f5d5f55749dc4b98648a25d355836895dc37 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES index 59f6ae6..ef91c87 100644 --- a/signoff/user_project_wrapper/PDK_SOURCES +++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION index ef97a7b..fabca1a 100644 --- a/signoff/wb_host/OPENLANE_VERSION +++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 68898e65843d8c9c7fa5fdf609d2ab3ac96b1081 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES index 59f6ae6..ef91c87 100644 --- a/signoff/wb_host/PDK_SOURCES +++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION index ef97a7b..fabca1a 100644 --- a/signoff/wb_interconnect/OPENLANE_VERSION +++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 68898e65843d8c9c7fa5fdf609d2ab3ac96b1081 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES index 59f6ae6..ef91c87 100644 --- a/signoff/wb_interconnect/PDK_SOURCES +++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION index b321d37..fabca1a 100644 --- a/signoff/ycr_core_top/OPENLANE_VERSION +++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 9949f5d5f55749dc4b98648a25d355836895dc37 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES index 59f6ae6..ef91c87 100644 --- a/signoff/ycr_core_top/PDK_SOURCES +++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/ycr_iconnect/OPENLANE_VERSION b/signoff/ycr_iconnect/OPENLANE_VERSION index b321d37..fabca1a 100644 --- a/signoff/ycr_iconnect/OPENLANE_VERSION +++ b/signoff/ycr_iconnect/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 9949f5d5f55749dc4b98648a25d355836895dc37 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/ycr_iconnect/PDK_SOURCES b/signoff/ycr_iconnect/PDK_SOURCES index 59f6ae6..ef91c87 100644 --- a/signoff/ycr_iconnect/PDK_SOURCES +++ b/signoff/ycr_iconnect/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION index ef97a7b..fabca1a 100644 --- a/signoff/ycr_intf/OPENLANE_VERSION +++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 68898e65843d8c9c7fa5fdf609d2ab3ac96b1081 +OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES index 59f6ae6..ef91c87 100644 --- a/signoff/ycr_intf/PDK_SOURCES +++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f +open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index 6dcc9c9..07cd52e 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -22,28 +22,32 @@ read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/RAM128.v + read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/RAM256.v - read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v - - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/buff_flash_clkrst.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/constant_block.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0801.v read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_signal_buffering_alt.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v - read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io_alt.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_signal_buffering.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/buff_flash_clkrst.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v + read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v + # User project netlist @@ -63,111 +67,121 @@ link_design caravel + read_spef -path clock_ctrl $::env(CARAVEL_ROOT)/signoff/caravel_clocking/openlane-signoff/spef/caravel_clocking.nom.spef + read_spef -path flash_clkrst_buffers $::env(CARAVEL_ROOT)/signoff/buff_flash_clkrst/openlane-signoff/spef/buff_flash_clkrst.nom.spef + read_spef -path gpio_control_bidir_1[0] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_bidir_1[1] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_bidir_2[0] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_bidir_2[1] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_bidir_2[2] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[0] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[10] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[1] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[2] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[3] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[4] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[5] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[6] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[7] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[8] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1[9] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1a[0] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1a[1] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1a[2] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1a[3] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1a[4] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_1a[5] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[0] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[10] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[11] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[12] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[13] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[14] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[15] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[1] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[2] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[3] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[4] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[5] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[6] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[7] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[8] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_control_in_2[9] $::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.nom.spef + read_spef -path gpio_defaults_block_0 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_10 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_11 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_12 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_13 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_14 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_15 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_16 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_17 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_18 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_19 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_1 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_20 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_21 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_22 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_23 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_24 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_25 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_26 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_27 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_28 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_29 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_2 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_30 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_31 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_32 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_33 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_34 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_35 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_36 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_3 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_4 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_5 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_6 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_7 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_8 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path gpio_defaults_block_9 $::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef + read_spef -path housekeeping $::env(CARAVEL_ROOT)/signoff/housekeeping/openlane-signoff/spef/housekeeping.nom.spef + read_spef -path mgmt_buffers $::env(CARAVEL_ROOT)/signoff/mgmt_protect/openlane-signoff/spef/mgmt_protect.nom.spef + read_spef -path padframe/constant_value_inst[0] $::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef + read_spef -path padframe/constant_value_inst[1] $::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef + read_spef -path padframe/constant_value_inst[2] $::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef + read_spef -path padframe/constant_value_inst[3] $::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef + read_spef -path padframe/constant_value_inst[4] $::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef + read_spef -path padframe/constant_value_inst[5] $::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef + read_spef -path padframe/constant_value_inst[6] $::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef + read_spef -path padframe $::env(CARAVEL_ROOT)/signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef + read_spef -path pll $::env(CARAVEL_ROOT)/signoff/digital_pll/openlane-signoff/spef/digital_pll.nom.spef + read_spef -path rstb_level $::env(CARAVEL_ROOT)/signoff/xres_buf/openlane-signoff/spef/xres_buf.nom.spef + read_spef -path soc/core.RAM128 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/signoff/RAM128/openlane-signoff/spef/RAM128.nom.spef + read_spef -path soc/core.RAM256 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/signoff/RAM256/openlane-signoff/spef/RAM256.nom.spef + read_spef -path soc $::env(CARAVEL_ROOT)/mgmt_core_wrapper/signoff/mgmt_core_wrapper/openlane-signoff/spef/mgmt_core_wrapper.nom.spef + read_spef -path spare_logic[0] $::env(CARAVEL_ROOT)/signoff/spare_logic_block/openlane-signoff/spef/spare_logic_block.nom.spef + read_spef -path spare_logic[1] $::env(CARAVEL_ROOT)/signoff/spare_logic_block/openlane-signoff/spef/spare_logic_block.nom.spef + read_spef -path spare_logic[2] $::env(CARAVEL_ROOT)/signoff/spare_logic_block/openlane-signoff/spef/spare_logic_block.nom.spef + read_spef -path spare_logic[3] $::env(CARAVEL_ROOT)/signoff/spare_logic_block/openlane-signoff/spef/spare_logic_block.nom.spef - read_spef -path soc/core.RAM128 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/RAM128.spef - read_spef -path soc/core.RAM256 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/RAM256.spef - read_spef -path soc $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core_wrapper.spef - read_spef -path padframe $::env(CARAVEL_ROOT)/spef/chip_io.spef - read_spef -path rstb_level $::env(CARAVEL_ROOT)/spef/xres_buf.spef - read_spef -path pll $::env(CARAVEL_ROOT)/spef/digital_pll.spef - read_spef -path housekeeping $::env(CARAVEL_ROOT)/spef/housekeeping.spef - read_spef -path mgmt_buffers/powergood_check $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef - read_spef -path mgmt_buffers/mprj_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef - read_spef -path mgmt_buffers/mprj2_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef - read_spef -path mgmt_buffers $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef - read_spef -path \gpio_control_bidir_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_bidir_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_bidir_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_bidir_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1a[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1a[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1a[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1a[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1a[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_1a[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[11] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[12] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[13] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[14] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[15] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path \gpio_control_in_2[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef - read_spef -path gpio_defaults_block_0 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef - read_spef -path gpio_defaults_block_1 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef - read_spef -path gpio_defaults_block_2 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef - read_spef -path gpio_defaults_block_3 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef - read_spef -path gpio_defaults_block_4 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef - read_spef -path gpio_defaults_block_5 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_6 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_7 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_8 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_9 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_10 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_11 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_12 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_13 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_14 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_15 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_16 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_17 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_18 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_19 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_20 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_21 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_22 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_23 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_24 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_25 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_26 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_27 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_28 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_29 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_30 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_31 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_32 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_33 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_34 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_35 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_36 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef - read_spef -path flash_clkrst_buffers $::env(CARAVEL_ROOT)/spef/buff_flash_clkrst.spef ## User Project Spef - read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/spef/ycr_iconnect.spef - read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef - read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef - read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux_top.spef - read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef - read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef - read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef - read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef - read_spef -path mprj/u_pll $::env(USER_ROOT)/spef/dg_pll.spef - read_spef -path mprj/u_aes $::env(USER_ROOT)/spef/aes_top.spef - read_spef -path mprj/u_fpu $::env(USER_ROOT)/spef/fpu_wrapper.spef - read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef + read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/signoff/ycr_iconnect/openlane-signoff/spef/ycr_iconnect.nom.spef + read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/signoff/ycr_intf/openlane-signoff/spef/ycr_intf.nom.spef + read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/signoff/ycr_core_top/openlane-signoff/spef/ycr_core_top.nom.spef + read_spef -path mprj/u_pinmux $::env(USER_ROOT)/signoff/pinmux_top/openlane-signoff/spef/pinmux_top.nom.spef + read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/signoff/qspim_top/openlane-signoff/spef/qspim_top.nom.spef + read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/signoff/uart_i2c_usb_spi_top/openlane-signoff/spef/uart_i2c_usb_spi_top.nom.spef + read_spef -path mprj/u_wb_host $::env(USER_ROOT)/signoff/wb_host/openlane-signoff/spef/wb_host.nom.spef + read_spef -path mprj/u_intercon $::env(USER_ROOT)/signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.nom.spef + read_spef -path mprj/u_pll $::env(USER_ROOT)/signoff/dg_pll/openlane-signoff/spef/dg_pll.nom.spef + read_spef -path mprj/u_aes $::env(USER_ROOT)/signoff/aes_top/openlane-signoff/spef/aes_top.nom.spef + read_spef -path mprj/u_fpu $::env(USER_ROOT)/signoff/fpu_wrapper/openlane-signoff/spef/fpu_wrapper.nom.spef + read_spef -path mprj $::env(USER_ROOT)/signoff/user_project_wrapper/openlane-signoff/spef/user_project_wrapper.nom.spef - read_spef $::env(CARAVEL_ROOT)/spef/caravel.spef + read_spef $::env(CARAVEL_ROOT)/signoff/caravel/openlane-signoff/spef/caravel.nom.spef read_sdc -echo ./sdc/caravel.sdc
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index f7a75cc..59520a9 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -1,7 +1,6 @@ -set ::env(SYNTH_TIMING_DERATE) 0.01 -set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25 -set ::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) 0.25 -set ::env(SYNTH_CLOCK_TRANSITION) 0.15 +### Caravel Signoff SDC +### Rev 3 +### Date: 28/10/2022 ## MASTER CLOCKS create_clock -name clk -period 25 [get_ports {clock}] @@ -9,7 +8,7 @@ create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ] create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}] create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}] - +# hk_serial_clk period is x2 core clock ### User Project Clocks create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clk] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i] @@ -34,14 +33,15 @@ create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}] create_clock -name dbg_ref_clk -period 10.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}] +set_clock_uncertainty 0.1000 [all_clocks] set_clock_groups \ -name clock_group \ -logically_exclusive \ -group [get_clocks {wb_clk clk}]\ - -group [get_clocks {hk_serial_clk} ]\ - -group [get_clocks {hk_serial_load} ]\ - -group [get_clocks {hkspi_clk} ]\ + -group [get_clocks {hk_serial_clk}]\ + -group [get_clocks {hk_serial_load}]\ + -group [get_clocks {hkspi_clk}]\ -group [get_clocks {int_pll_clock}]\ -group [get_clocks {wbs_clk_i}]\ -group [get_clocks {wbs_ref_clk}]\ @@ -59,172 +59,13 @@ -group [get_clocks {rtc_ref_clk}]\ -comment {Async Clock group} +# clock <-> hk_serial_clk/load no paths +# future note: CDC stuff +# clock <-> hkspi_clk no paths with careful methods (clock is off) + set_propagated_clock [all_clocks] -set_max_fanout 12 [current_design] -# synthesis max fanout should be less than 12 (7 maybe) - - -###################################################### -# Caravel Case Analysis -####################################################### -#assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk; -#assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk; -#assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk; - -set_case_analysis 0 clock_ctrl/_205_/S -set_case_analysis 0 clock_ctrl/_206_/S -set_case_analysis 0 clock_ctrl/_208_/S - -## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled -set_case_analysis 0 [get_pins housekeeping/_3936_/S] -set_case_analysis 0 [get_pins housekeeping/_3937_/S] - -# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 - -set_case_analysis 1 [get_pins padframe/*_pad/DM[2]] -set_case_analysis 1 [get_pins padframe/*_pad/DM[1]] -set_case_analysis 0 [get_pins padframe/*_pad/DM[0]] -set_case_analysis 0 [get_pins padframe/*_pad/SLOW] -set_case_analysis 0 [get_pins padframe/*_pad/ANALOG_EN] - -set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[2]] -set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[1]] -set_case_analysis 0 [get_pins padframe/*_io_pad*/DM[0]] -set_case_analysis 0 [get_pins padframe/*_io_pad*/SLOW] -set_case_analysis 0 [get_pins padframe/*_io_pad*/ANALOG_EN] - -set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]] -set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]] -set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]] - -set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]] -set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]] -set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]] - -set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]] -set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]] -set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]] - -################################################################# -## User Case analysis -################################################################# - -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}] - -set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}] -set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}] -set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}] -set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}] - -set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] - -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] - -set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}] - -set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}] -set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] -set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}] -set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] - -set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] -set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] -set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] -set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] - -# clock skew cntrl-2 -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}] - -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}] - -set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}] - -#Keept the SRAM clock driving edge at pos edge -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}] - -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}] - -set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[3]}] -set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}] -set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}] -set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}] - -set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[3]}] -set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[2]}] -set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[1]}] -set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[0]}] -############## Caravel False Path ######################################################## -## FALSE PATHS (ASYNCHRONOUS INPUTS) -set_false_path -from [get_ports {resetb}] - -set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]] -set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]] -set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]] -set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]] -set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]] -set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]] -set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]] -set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]] -set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]] -set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]] -set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]] -set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]] -set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]] -set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]] -set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]] -set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]] -set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]] -set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]] -set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]] -set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]] -set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]] -set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]] -set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]] -set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]] -set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]] -set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]] -set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]] -set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]] -set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]] -set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]] -set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]] -set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]] -set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]] -set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]] -set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]] -set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]] - -set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]] -set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]] - - -################ Caravel Timing Constraints ########################################################## - - +## INPUT/OUTPUT DELAYS set input_delay_value 4 set output_delay_value 4 puts "\[INFO\]: Setting output delay to: $output_delay_value" @@ -279,110 +120,209 @@ set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}] set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}] +# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}] -#################################################################################################### +set_max_fanout 12 [current_design] +# synthesis max fanout should be less than 12 (7 maybe) + +## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled +set_case_analysis 0 [get_pins housekeeping/_3936_/S] +set_case_analysis 0 [get_pins housekeeping/_3937_/S] + +# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs + +set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]] +set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]] +set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]] +set_case_analysis 0 [get_pins padframe/*_pad*/SLOW] +set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN] + +# the following pads are set as inputs +set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]] +set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]] +set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]] + +set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]] +set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]] +set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]] +set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]] +set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]] +set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]] + +################################################################# +## User Case analysis +################################################################# + +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}] + +set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}] + +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] +set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] +set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] + +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] + +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}] + +set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}] +set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] +set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}] +set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] + +set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] +set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] +set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] +set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] + +# clock skew cntrl-2 +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}] + +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}] + +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}] + +#Keept the SRAM clock driving edge at pos edge +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}] + +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}] + +set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[3]}] +set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}] +set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}] +set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}] + +set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[3]}] +set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[2]}] +set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[1]}] +set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[0]}] + +## FALSE PATHS (ASYNCHRONOUS INPUTS) +set_false_path -from [get_ports {resetb}] + +## Async USB/I2C Interrupt, Double Sync added inside glbl block +set_false_path -through [get_pins {mprj/u_pinmux/usb_intr}] +set_false_path -through [get_pins {mprj/u_pinmux/i2cm_intr}] + +## UART RXD is async signal +set_false_path -through [get_pins {mprj/u_wb_host/uartm_rxd}] + +##SPI Slave Interface Signal (SCLK/SSN) are double sync with wb_clk +set_false_path -through [get_pins {mprj/u_wb_host/sclk}] +set_false_path -through [get_pins {mprj/u_wb_host/ssn}] +## SDIN sampled on negedge SCLK +set_false_path -through [get_pins {mprj/u_wb_host/sdin}] +# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]] +# reset_path -from [get_ports mprj_io[4]] +# reset_path -from [get_ports mprj_io[2]] +#reset_path is not supported in PT read_sdc ^ -# TODO set this as parameter -set cap_load 10 -puts "\[INFO\]: Setting load to: $cap_load" -set_load $cap_load [all_outputs] +set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]] +set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]] +set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]] +set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]] +set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]] +set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]] +set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]] +set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]] +set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]] +set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]] +set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]] +set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]] +set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]] +set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]] +set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]] +set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]] +set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]] +set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]] +set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]] +set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]] +set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]] +set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]] +set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]] +set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]] +set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]] +set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]] +set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]] +set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]] +set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]] +set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]] +set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]] +set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]] +set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]] +set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]] +set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]] +set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]] -#add input transition for the inputs pins -set_input_transition 2 [all_inputs] +set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]] +set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]] +set_false_path -from [get_ports gpio] -puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" -set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] -set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] +# add loads for output ports (pads) +set min_cap 5 +set max_cap 10 +puts "\[INFO\]: Cap load range: $min_cap : $max_cap" +# set_load 10 [all_outputs] +set_load -min $min_cap [all_outputs] +set_load -max $max_cap [all_outputs] -puts "\[INFO\]: Setting clock setup uncertainity to: $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY)" -puts "\[INFO\]: Setting clock hold uncertainity to: $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY)" -set_clock_uncertainty -setup $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) [all_clocks] -set_clock_uncertainty -hold $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) [all_clocks] +#add input transition for the inputs ports (pads) +# set_input_transition 2 [all_inputs] +#add exception for power pads as 2ns on them results in max_tran violations (false viol) +# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]] +# remove_from_collection is not supported in PT read_sdc ^ +# set_input_transition 2 [all_inputs] +# set_input_transition 0 [get_ports v*] +set min_in_tran 1 +set max_in_tran 4 +puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran" +set_input_transition -min $min_in_tran [all_inputs] +set_input_transition -min 0 [get_ports v*] +set_input_transition -max $max_in_tran [all_inputs] +set_input_transition -max 0 [get_ports v*] -#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}] -#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}] -#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}] -#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}] -#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}] -#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}] -# -#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}] -#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}] -#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}] -#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}] -#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}] -#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}] -# -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}] -#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}] -# -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}] -#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}] +# check ocv table (not provided) -- maybe try 8% +set derate 0.0375 +puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %" +set_timing_derate -early [expr 1-$derate] +set_timing_derate -late [expr 1+$derate] +# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners +# apply the constraint to hd cells at the ss corner only +# if {$::env(PROC_CORNER) == "s"} { +# set max_tran 1.5 +# set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]] +# set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]] +# set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]] +# puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran" +# } +# -filter not supported in PT read_sdc ^
diff --git a/verilog/gl/aes_top.v.gz b/verilog/gl/aes_top.v.gz new file mode 100644 index 0000000..e7eb9a3 --- /dev/null +++ b/verilog/gl/aes_top.v.gz Binary files differ
diff --git a/verilog/gl/dac_top.v.gz b/verilog/gl/dac_top.v.gz new file mode 100644 index 0000000..b1d0048 --- /dev/null +++ b/verilog/gl/dac_top.v.gz Binary files differ
diff --git a/verilog/gl/dg_pll.v.gz b/verilog/gl/dg_pll.v.gz new file mode 100644 index 0000000..c14c7b7 --- /dev/null +++ b/verilog/gl/dg_pll.v.gz Binary files differ
diff --git a/verilog/gl/fpu_wrapper.v.gz b/verilog/gl/fpu_wrapper.v.gz new file mode 100644 index 0000000..d4c7323 --- /dev/null +++ b/verilog/gl/fpu_wrapper.v.gz Binary files differ
diff --git a/verilog/gl/pinmux_top.v.gz b/verilog/gl/pinmux_top.v.gz new file mode 100644 index 0000000..83ae623 --- /dev/null +++ b/verilog/gl/pinmux_top.v.gz Binary files differ
diff --git a/verilog/gl/qspim_top.v.gz b/verilog/gl/qspim_top.v.gz new file mode 100644 index 0000000..f8267cf --- /dev/null +++ b/verilog/gl/qspim_top.v.gz Binary files differ
diff --git a/verilog/gl/uart_i2c_usb_spi_top.v.gz b/verilog/gl/uart_i2c_usb_spi_top.v.gz new file mode 100644 index 0000000..93b01a5 --- /dev/null +++ b/verilog/gl/uart_i2c_usb_spi_top.v.gz Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz new file mode 100644 index 0000000..26c4224 --- /dev/null +++ b/verilog/gl/user_project_wrapper.v.gz Binary files differ
diff --git a/verilog/gl/wb_host.v.gz b/verilog/gl/wb_host.v.gz new file mode 100644 index 0000000..5fcfeb0 --- /dev/null +++ b/verilog/gl/wb_host.v.gz Binary files differ
diff --git a/verilog/gl/wb_interconnect.v.gz b/verilog/gl/wb_interconnect.v.gz new file mode 100644 index 0000000..c2739a5 --- /dev/null +++ b/verilog/gl/wb_interconnect.v.gz Binary files differ
diff --git a/verilog/gl/ycr_core_top.v.gz b/verilog/gl/ycr_core_top.v.gz new file mode 100644 index 0000000..6f6238d --- /dev/null +++ b/verilog/gl/ycr_core_top.v.gz Binary files differ
diff --git a/verilog/gl/ycr_iconnect.v.gz b/verilog/gl/ycr_iconnect.v.gz new file mode 100644 index 0000000..ec91a6a --- /dev/null +++ b/verilog/gl/ycr_iconnect.v.gz Binary files differ
diff --git a/verilog/gl/ycr_intf.v.gz b/verilog/gl/ycr_intf.v.gz new file mode 100644 index 0000000..10a3e88 --- /dev/null +++ b/verilog/gl/ycr_intf.v.gz Binary files differ
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh index 6d60270..d4ae6a0 100644 --- a/verilog/rtl/user_params.svh +++ b/verilog/rtl/user_params.svh
@@ -8,8 +8,8 @@ // Software Reg-2: Poject Revison 5.1 = 0005200 parameter CHIP_REVISION = 32'h0005_8000; -parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_0111_1010_1000_1001_1100; -parameter CLK_SKEW2_RESET_VAL = 32'b0000; +parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_1100_1010_1010_1001_0011; +parameter CLK_SKEW2_RESET_VAL = 32'b0000_0000_0000_0000_0000_0000_0000_0111; parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;