| RISCDUINO Score | |
| 4.6.1 June 24,2022, Dinesh A | |
| First fully arduino compatible based verification | |
| test case arudino_risc_boot added | |
| 4.6 June 13 2022, Dinesh A | |
| 1. icache and dcache bypass config addded | |
| 4.5 June 2 2022, Dinesh A | |
| 1. DFFRAM Replaced by SRAM | |
| 4.4 May 29 2022, Dinesh A | |
| 1. Digital PLL integrated and clock debug signal add | |
| @digitial io [33] port | |
| 4.3 May 24 2022, Dinesh A | |
| Re targetted the design to mpw-6 tools set and risc | |
| core logic are timing optimized to 100mhz | |
| 4.2 April 6 2022, Dinesh A | |
| 1. SSPI CS# increased from 1 to 4 | |
| 2. uart port increase to two | |
| 3.9 Mar 16 2022, Dinesh A | |
| 1. 3 Timer added | |
| 2. Pinmux Register address movement | |
| 3. Risc fuse_mhartid is removed and internal tied | |
| inside risc core | |
| 4. caravel wb addressing issue restrict to 0x300FFFFF | |
| 3.8 Mar 10 2022, Dinesh A | |
| 1. usb chip select bug inside uart_* wrapper | |
| 2. in wb_host, increased usb clk ctrl to 4 to 8 bit | |
| 3.7 Mar 2 2022, Dinesh A | |
| 1. qspi cs# port mapping changed from io 28:25 to 25:28 | |
| 2. sspi, bug fix in reg access and endian support added | |
| 3. Wishbone interconnect now support cross-connect | |
| feature | |
| 3.6 Feb 19, Dinesh A | |
| A. Changed Module: wb_host | |
| wishbone slave clock generation config increase from | |
| 3 to 4 bit support clock source selection | |
| B. Changed Module: qspim | |
| 1. Bug fix in spi rise and fall pulse relation w.r.t | |
| spi_clk. Note: Previous version work only with | |
| spi clock config = 0x2 | |
| 2. spi_oen generation fix for different spi mode | |
| 3. spi_csn de-assertion fix for different spi clk div | |
| 3.5 Feb 16, Dinesh A | |
| As SRAM from sky130A is not yet qualified, | |
| Following changes are done | |
| A. riscv core cache and tcm interface changed to dffram | |
| B. removed the mbist controller + 4 SRAM | |
| C. mbist controller slave port in wb_intern removed | |
| D. Pinmux mbist port are removed | |
| E. mbist related buffering are removed at wb_inter | |
| 3.4 Feb 14, 2022, Dinesh A | |
| burst mode supported added in imem buffer inside | |
| riscv core | |
| We have created seperate repo from this onwards | |
| SRAM based SOC is spin-out to | |
| dineshannayya/riscduino_sram.git | |
| This repo will remove mbist + SRAM and RISC SRAM will be | |
| replaced with DFRAM | |
| 3.3 Feb 08, 2022, Dinesh A | |
| support added spisram support in qspim ip | |
| There are 4 chip select available in qspim | |
| CS#0/CS#1 targeted for SPI FLASH | |
| CS#2/CS#3 targeted for SPI SRAM | |
| 3.2 Feb 02, 2022, Dinesh A | |
| Bug fix around icache/dcache and wishbone burst | |
| access clean-up | |
| 3.1 Jan 15, 2022, Dinesh A | |
| Major changes in qspim logic to handle special mode | |
| 3.0 Jan 14, 2022, Dinesh A | |
| Moving from riscv core from syntacore/scr1 to | |
| yfive/ycr1 on sankranti 2022 (A Hindu New Year) | |
| 2.6 Jan 08, 2022, Dinesh A | |
| Pinmux Interrupt Logic change | |
| 2.5 Jan 06, 2022, Dinesh A | |
| TCM RAM Bug fix inside syntacore | |
| 2.4 Jan 01, 2022, Dinesh A | |
| LA[0] is added as soft reset option at wb_port | |
| 2.3 Dec 24, 2021, Dinesh A | |
| UART Master added with message handler at wb_host | |
| 2.2 Dec 20, 2021, Dinesh A | |
| 1. MBIST design issue fix for yosys | |
| 2. Full chip Timing and Transition clean-up | |
| 2.1 Dec 16, 2021, Dinesh A | |
| 1.4 MBIST controller changed to single one | |
| 2.Added one more SRAM to TCM memory | |
| 3.WishBone Interconnect chang to take care mbist changes | |
| 4.Pinmux change to take care of mbist changes | |
| 2.0 Dec 14, 2021, Dinesh A | |
| Added two more 2K SRAM added into Wishbone Interface | |
| 1.9 Dec 11, 2021, Dinesh A | |
| 2 x 2K SRAM added into Wishbone Interface | |
| Temporary ADC block removed | |
| 1.8 Nov 23, 2021, Dinesh A | |
| Three Chip Specific Signature added at PinMux Reg | |
| reg_22,reg_23,reg_24 | |
| 1.7 Nov 15, 2021, Dinesh A | |
| Bug fix in clk_ctrl High/Low counter width | |
| Removed sram_clock | |
| 1.6 Nov 14, 2021, Dinesh A | |
| Major bug, clock divider inside the wb_host reset | |
| connectivity open is fixed | |
| 1.5 - 6th Nov 2021, Dinesh A | |
| Clock Skew block moved inside respective block due | |
| to top-level power hook-up challenges for small IP | |
| 1.4 - 13th Oct 2021, Dinesh A | |
| Basic verification and Synthesis cleanup | |
| 1.3 - 30th Sept 2021, Dinesh.A | |
| 2KB SRAM Interface added to RISC Core | |
| 1.2 - 29th Sept 2021, Dinesh.A | |
| 1. copied the repo from yifive and renames as | |
| riscdunino | |
| 2. Removed the SDRAM controlled | |
| 3. Added PinMux | |
| 4. Added SAR ADC for 6 channel | |
| 1.1 - 1st Aug 2021, Dinesh A | |
| usb1.1 host integrated part of uart_i2cm_usb module, | |
| due to number of IO pin limitation, | |
| Only UART/I2C/USB selected based on config mode | |
| 1.0 - 28th July 2021, Dinesh A | |
| i2cm integrated part of uart_i2cm module, | |
| due to number of IO pin limitation, | |
| Only UART OR I2C selected based on config mode | |
| 0.9 - 7th July 2021, Dinesh A | |
| Removed 2 Unused port connection io_in[31:30] to | |
| spi_master to avoid lvs issue | |
| 0.8 - 6th July 2021, Dinesh A | |
| For Better SDRAM Interface timing we have taping | |
| sdram_clock goint to io_out[29] directly from | |
| global register block, this help in better SDRAM | |
| interface timing control | |
| 0.7 - 28th June 2021, Dinesh A | |
| wb_interconnect master port are interchanged for | |
| better physical placement. | |
| m0 - External HOST | |
| m1 - RISC IMEM | |
| m2 - RISC DMEM | |
| 0.6 - 27th June 2021, Dinesh A | |
| Digital core level tie are moved inside IP to avoid | |
| power hook up at core level | |
| u_risc_top - test_mode & test_rst_n | |
| u_intercon - s*_wbd_err_i | |
| unused wb_cti_i is removed from u_sdram_ctrl | |
| 0.5 - 25th June 2021, Dinesh A | |
| Since carvel gives only 16MB address space for user | |
| space, we have implemented indirect address select | |
| with 8 bit bank select given inside wb_host | |
| core Address = {Bank_Sel[7:0], Wb_Address[23:0] | |
| caravel user address space is | |
| 0x3000_0000 to 0x30FF_FFFF | |
| 0.4 - 25th June 2021, Dinesh A | |
| Moved the pad logic inside sdram,spi,uart block to | |
| avoid logic at digital core level | |
| 0.3 - 20th June 2021, Dinesh A | |
| 1. uart core is integrated | |
| 2. 3rd Slave ported added to wishbone interconnect | |
| 0.2 - 17th June 2021, Dinesh A | |
| 1. In risc core, wishbone and core domain is | |
| created | |
| 2. cpu and rtc clock are generated in glbl reg block | |
| 3. in wishbone interconnect:- Stagging flop are added | |
| at interface to break wishbone timing path | |
| 4. buswidth warning are fixed inside spi_master | |
| modified rtl files are | |
| verilog/rtl/digital_core/src/digital_core.sv | |
| verilog/rtl/digital_core/src/glbl_cfg.sv | |
| verilog/rtl/lib/wb_stagging.sv | |
| verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv | |
| verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv | |
| verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv | |
| verilog/rtl/user_project_wrapper.v | |
| verilog/rtl/wb_interconnect/src/wb_interconnect.sv | |
| verilog/rtl/spi_master/src/spim_clkgen.sv | |
| verilog/rtl/spi_master/src/spim_ctrl.sv | |
| 0.1 - 16th Feb 2021, Dinesh A | |
| Initial integration with Risc-V core + | |
| Wishbone Cross Bar + SPI Master | |