system strap design update
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 8b10c8b..b4df712 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -7,13 +7,17 @@ set ::env(SYNTH_CLOCK_TRANSITION) 0.15 ## MASTER CLOCKS -create_clock [get_ports {"clock"} ] -name "clock" -period 25 +create_clock [get_ports {"clock"} ] -name "master_clock" -period 25 create_clock [get_pins clocking/user_clk ] -name "user_clk2" -period 25 -#create_clock [get_pins housekeeping/_8847_/X ] -name "csclk" -period 25 +create_generated_clock -name csclk -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 1 -invert -comment {csclk} [get_pins housekeeping/_8847_/X] #create_clock [get_pins clocking/pll_clk ] -name "pll_clk" -period 25 #create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25 +create_clock [get_pins housekeeping/serial_clock ] -name "serial_clock" -period 50 +create_clock [get_pins housekeeping/serial_load ] -name "serial_load" -period 50 -create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i] + + +create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i] create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_wb_host/u_clkbuf_pll.u_buf/X}] create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_wbs_ref_clkbuf.u_buf/X}] @@ -22,13 +26,13 @@ create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_cpu_ref_clkbuf.u_buf/X}] create_clock -name cpu_clk -period 10.0000 [get_pins {mprj/u_wb_host/cpu_clk}] -create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}] +create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_pinmux/rtc_clk}] create_clock -name pll_ref_clk -period 20.0000 [get_pins {mprj/u_wb_host/pll_ref_clk}] create_clock -name pll_clk_0 -period 5.0000 [get_pins {mprj/u_pll/ringosc.ibufp01/Y}] -create_clock -name usb_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_usb_ref_clkbuf.u_buf/X}] -create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}] +create_clock -name usb_ref_clk -period 5.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}] +create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_pinmux/usb_clk}] create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}] create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}] create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}] @@ -36,41 +40,41 @@ ## Case analysis +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}] + + +set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}] + +set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] + +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] + +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}] + +set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}] +set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] +set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}] +set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] + +set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] +set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] -set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] -set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] - -set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}] -set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}] -set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}] -set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}] - -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] - -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] - -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}] - -set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] -set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}] -set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] -set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}] - -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] -set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] - #Keept the SRAM clock driving edge at pos edge set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}] @@ -84,8 +88,13 @@ set_propagated_clock [all_clocks] +#set_multicycle_path -setup -from [get_clocks {master_clock}] -to [get_clocks {csclk}] 2 +#set_multicycle_path -hold -from [get_clocks {master_clock}] -to [get_clocks {csclk}] 2 + set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {clock wb_clk }]\ + -group [get_clocks {wb_clk master_clock}]\ + -group [get_clocks {csclk}]\ + -group [get_clocks {serial_clock serial_load }]\ -group [get_clocks {user_clk2}]\ -group [get_clocks {int_pll_clock}]\ -group [get_clocks {wbs_clk_i}]\ @@ -108,50 +117,50 @@ puts "\[INFO\]: Setting output delay to: $output_delay_value" puts "\[INFO\]: Setting input delay to: $input_delay_value" -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {gpio}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}] -set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {gpio}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[0]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[1]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[2]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[3]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[4]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[5]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[6]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[7]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[8]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[9]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[10]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[11]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[12]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[13]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[14]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[15]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[16]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[17]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[18]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[19]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[20]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[21]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[22]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[23]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[24]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[25]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[26]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[27]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[28]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[29]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[30]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[31]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[32]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[33]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[34]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[35]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[36]}] +set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[37]}] -set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}] -set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}] -set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}] -set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}] +set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_csb}] +set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_clk}] +set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_io0}] +set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_io1}] set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design] @@ -265,4 +274,4 @@ puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)" -set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}] +set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {master_clock}]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 27654a3..e5717ba 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema arduino_timer_intr all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/agents/caravel_task.sv b/verilog/dv/agents/caravel_task.sv new file mode 100644 index 0000000..8ce81ef --- /dev/null +++ b/verilog/dv/agents/caravel_task.sv
@@ -0,0 +1,172 @@ + +/******************** +parameter bit [15:0] PAD_STRAP = (2'b00 << `PSTRAP_CLK_SRC ) | + (2'b00 << `PSTRAP_CLK_DIV ) | + (1'b1 << `PSTRAP_UARTM_CFG ) | + (1'b1 << `PSTRAP_QSPI_SRAM ) | + (2'b10 << `PSTRAP_QSPI_FLASH ) | + (1'b1 << `PSTRAP_RISCV_RESET_MODE ) | + (1'b1 << `PSTRAP_RISCV_CACHE_BYPASS ) | + (1'b1 << `PSTRAP_RISCV_SRAM_CLK_EDGE ) | + (2'b00 << `PSTRAP_CLK_SKEW ) | + (1'b0 << `PSTRAP_DEFAULT_VALUE ) ; +****/ + +`ifdef RISC_BOOT // RISCV Based Test case +parameter bit [15:0] PAD_STRAP = 16'b0000_0001_1011_0000; +`else +parameter bit [15:0] PAD_STRAP = 16'b0000_0000_1011_0000; +`endif + +/*********************************************** + +wire [15:0] strap_in; +assign strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1 +assign strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div +assign strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection +assign strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad +assign strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad +assign strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset +assign strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable +assign strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal +assign strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value + +assign strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal +***/ + +initial +begin + // Run in Fast Sim Mode + `ifdef GL + force u_top.mprj.u_wb_host._8654_.Q= 1'b1; + `else + force u_top.mprj.u_wb_host.u_fastsim_buf.X = 1'b1; + `endif + +end +task init; +begin + //#1 - Apply Reset + #1000 RSTB = 1; + repeat (10) @(posedge clock); + #1000 RSTB = 0; + + //#3 - Remove Reset + #1000 RSTB = 1; + repeat (10) @(posedge clock); + //#4 - Wait for Power on reset removal + wait(u_top.mprj.p_reset_n == 1); + + // #5 - Wait for system reset removal + wait(u_top.mprj.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +/**** + //#2 - Apply Strap + strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1 + strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div + strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection + strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad + strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad + strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset + strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable + strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal + strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value + + strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal + + force u_top.io_in[36:29] = strap_in[15:8]; + force u_top.io_in[20:13] = strap_in[7:0]; + repeat (10) @(posedge clock); + + //#3 - Remove Reset + wb_rst_i = 0; // Remove Reset + repeat (10) @(posedge clock); + //#4 - Wait for Power on reset removal + wait(u_top.p_reset_n == 1); + + // #5 - Release the Strap + release u_top.io_in[36:29]; + release u_top.io_in[20:13]; + + // #6 - Wait for system reset removal + wait(u_top.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +***/ + end +endtask + +task apply_strap; +input [15:0] strap; +begin + + repeat (10) @(posedge clock); + //#1 - Apply Reset + RSTB = 0; + //#2 - Apply Strap + force u_top.mprj_io[36:29] = strap[15:8]; + force u_top.mprj_io[20:13] = strap[7:0]; + repeat (10) @(posedge clock); + + //#3 - Remove Reset + RSTB = 1; // Remove Reset + + //#4 - Wait for Power on reset removal + wait(u_top.mprj.p_reset_n == 1); + + // #5 - Release the Strap + release u_top.mprj_io[36:29]; + release u_top.mprj_io[20:13]; + + // #6 - Wait for system reset removal + wait(u_top.mprj.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +end +endtask + +//--------------------------------------------------------- +// Create Pull Up/Down Based on Reset Strap Parameter +//--------------------------------------------------------- + +genvar gCnt; +generate + for(gCnt=0; gCnt<16; gCnt++) begin : g_strap + if(gCnt < 8) begin + if(PAD_STRAP[gCnt]) begin + pullup(mprj_io[13+gCnt]); + end else begin + pulldown(mprj_io[13+gCnt]); + end + end else begin + if(PAD_STRAP[gCnt]) begin + pullup(mprj_io[29+gCnt-8]); + end else begin + pulldown(mprj_io[29+gCnt-8]); + end + end + end + +`ifdef RISC_BOOT // RISCV Based Test case +//------------------------------------------- +task wait_riscv_boot; +begin + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + $display("Status: Waiting for RISCV Core Boot ... "); + + wait(u_top.mprj.u_pinmux.u_glbl_reg.reg_15 == 8'h1); + $display("Status: RISCV Core is Booted "); + +end +endtask + +`endif + + +endgenerate +
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v index 2b12d64..5ca1813 100644 --- a/verilog/dv/agents/uart_agent.v +++ b/verilog/dv/agents/uart_agent.v
@@ -41,6 +41,7 @@ reg [15:0] stop_err2_cnt; reg [15:0] timeout_err_cnt; reg [15:0] err_cnt; +reg uart_rxenb; // uart rx enable reg txd, read, write; wire uart_rx_clk; @@ -56,6 +57,7 @@ initial begin + uart_rxenb = 0; debug_mode = 1; // Keep in debug mode and enable display txd = 1'b1; uart_clk = 0; @@ -77,9 +79,16 @@ always @(posedge mclk) begin - timeout_count = timeout_count + 1; - if (timeout_count == (control_setup.maxtime * 16)) - -> abort; + if(uart_rxenb) begin + timeout_count = timeout_count + 1; + if (timeout_count >= (control_setup.maxtime * 16)) begin + timeout_count = 0; + uart_rxenb = 0; + -> abort; + end + end else begin + timeout_count = 0; + end end always @uart_read_done @@ -118,6 +127,7 @@ //////////////////////////////////////////////////////////////////////////////// task uart_init; begin + uart_rxenb = 0; read = 0; write = 0; tx_count = 0; @@ -147,6 +157,7 @@ data = 8'h0; parity = 1; timeout_count = 0; + uart_rxenb = 1; fork begin : loop_1 @@ -224,6 +235,7 @@ $display ("%m:... Read Data from UART done cnt :%d...",rx_count +1); end join + uart_rxenb = 0; end @@ -233,7 +245,7 @@ task read_char2; output [7:0] rxd_data; output timeout; // 1-> timeout -integer i; +integer j; reg [7:0] rxd_data; reg [7:0] data; reg parity; @@ -243,6 +255,7 @@ parity = 1; timeout_count = 0; timeout = 0; + uart_rxenb = 1; fork begin @@ -260,10 +273,10 @@ // data cycle @(posedge uart_rx_clk ); - for (i = 0; i < data_bit_number; i = i + 1) + for (j = 0; j < data_bit_number; j = j + 1) begin @(posedge uart_rx_clk) - data[i] = rxd; + data[j] = rxd; parity = parity ^ rxd; end @@ -312,6 +325,7 @@ join_any disable fork; //disable pending fork activity + uart_rxenb = 0; end endtask @@ -335,6 +349,7 @@ parity = 1; timeout_count = 0; timeout = 0; + uart_rxenb = 1; fork @@ -409,6 +424,7 @@ end end join + uart_rxenb = 0; end @@ -426,6 +442,7 @@ begin data = 8'h0; parity = 1; + uart_rxenb = 1; fork @@ -484,6 +501,7 @@ rxd_data = data; end join + uart_rxenb = 0; end
diff --git a/verilog/dv/agents/uart_master_tasks.sv b/verilog/dv/agents/uart_master_tasks.sv index f0a1a7d..cd0af94 100644 --- a/verilog/dv/agents/uart_master_tasks.sv +++ b/verilog/dv/agents/uart_master_tasks.sv
@@ -5,8 +5,6 @@ reg [7:0] read_data; reg flag; begin - fork - begin : loop_1 tb_master_uart.write_char("w"); tb_master_uart.write_char("m"); tb_master_uart.write_char(" "); @@ -28,17 +26,13 @@ tb_master_uart.write_char(hex2char(data[7:4])); tb_master_uart.write_char(hex2char(data[3:0])); tb_master_uart.write_char("\n"); - end - begin : loop_2 // Wait for sucess command flag = 0; while(flag == 0) begin tb_master_uart.read_char2(read_data,flag); - //$write ("%c",read_data); + //$write ("%c",read_data); end - end - join end endtask @@ -49,28 +43,24 @@ reg flag; integer i; begin - fork - begin : loop_1 - tb_master_uart.write_char("r"); - tb_master_uart.write_char("m"); - tb_master_uart.write_char(" "); - tb_master_uart.write_char(hex2char(addr[31:28])); - tb_master_uart.write_char(hex2char(addr[27:24])); - tb_master_uart.write_char(hex2char(addr[23:20])); - tb_master_uart.write_char(hex2char(addr[19:16])); - tb_master_uart.write_char(hex2char(addr[15:12])); - tb_master_uart.write_char(hex2char(addr[11:8])); - tb_master_uart.write_char(hex2char(addr[7:4])); - tb_master_uart.write_char(hex2char(addr[3:0])); - tb_master_uart.write_char("\n"); - end - begin : loop_2 - // Wait for sucess command - flag = 0; - i = 0; - while(flag == 0) - begin - tb_master_uart.read_char2(read_data,flag); + tb_master_uart.write_char("r"); + tb_master_uart.write_char("m"); + tb_master_uart.write_char(" "); + tb_master_uart.write_char(hex2char(addr[31:28])); + tb_master_uart.write_char(hex2char(addr[27:24])); + tb_master_uart.write_char(hex2char(addr[23:20])); + tb_master_uart.write_char(hex2char(addr[19:16])); + tb_master_uart.write_char(hex2char(addr[15:12])); + tb_master_uart.write_char(hex2char(addr[11:8])); + tb_master_uart.write_char(hex2char(addr[7:4])); + tb_master_uart.write_char(hex2char(addr[3:0])); + tb_master_uart.write_char("\n"); + // Wait for sucess command + flag = 0; + i = 0; + while(flag == 0) + begin + tb_master_uart.read_char2(read_data,flag); //$write ("%d:%c",i,read_data); case (i) 8'd10 : data[31:28] = char2hex(read_data); @@ -81,12 +71,10 @@ 8'd15 : data[11:8] = char2hex(read_data); 8'd16 : data[7:4] = char2hex(read_data); 8'd17 : data[3:0] = char2hex(read_data); - endcase - i = i+1; - end - end - join + endcase + i = i+1; $display("received Data: %x",data); + end end endtask @@ -99,43 +87,37 @@ reg flag; integer i; begin - fork - begin : loop_1 - tb_master_uart.write_char("r"); - tb_master_uart.write_char("m"); - tb_master_uart.write_char(" "); - tb_master_uart.write_char(hex2char(addr[31:28])); - tb_master_uart.write_char(hex2char(addr[27:24])); - tb_master_uart.write_char(hex2char(addr[23:20])); - tb_master_uart.write_char(hex2char(addr[19:16])); - tb_master_uart.write_char(hex2char(addr[15:12])); - tb_master_uart.write_char(hex2char(addr[11:8])); - tb_master_uart.write_char(hex2char(addr[7:4])); - tb_master_uart.write_char(hex2char(addr[3:0])); - tb_master_uart.write_char("\n"); + tb_master_uart.write_char("r"); + tb_master_uart.write_char("m"); + tb_master_uart.write_char(" "); + tb_master_uart.write_char(hex2char(addr[31:28])); + tb_master_uart.write_char(hex2char(addr[27:24])); + tb_master_uart.write_char(hex2char(addr[23:20])); + tb_master_uart.write_char(hex2char(addr[19:16])); + tb_master_uart.write_char(hex2char(addr[15:12])); + tb_master_uart.write_char(hex2char(addr[11:8])); + tb_master_uart.write_char(hex2char(addr[7:4])); + tb_master_uart.write_char(hex2char(addr[3:0])); + tb_master_uart.write_char("\n"); + // Wait for sucess command + flag = 0; + i = 0; + while(flag == 0) + begin + tb_master_uart.read_char2(read_data,flag); + //$write ("%d:%c",i,read_data); + case (i) + 8'd10 : rxd_data[31:28] = char2hex(read_data); + 8'd11 : rxd_data[27:24] = char2hex(read_data); + 8'd12 : rxd_data[23:20] = char2hex(read_data); + 8'd13 : rxd_data[19:16] = char2hex(read_data); + 8'd14 : rxd_data[15:12] = char2hex(read_data); + 8'd15 : rxd_data[11:8] = char2hex(read_data); + 8'd16 : rxd_data[7:4] = char2hex(read_data); + 8'd17 : rxd_data[3:0] = char2hex(read_data); + endcase + i = i+1; end - begin : loop_2 - // Wait for sucess command - flag = 0; - i = 0; - while(flag == 0) - begin - tb_master_uart.read_char2(read_data,flag); - //$write ("%d:%c",i,read_data); - case (i) - 8'd10 : rxd_data[31:28] = char2hex(read_data); - 8'd11 : rxd_data[27:24] = char2hex(read_data); - 8'd12 : rxd_data[23:20] = char2hex(read_data); - 8'd13 : rxd_data[19:16] = char2hex(read_data); - 8'd14 : rxd_data[15:12] = char2hex(read_data); - 8'd15 : rxd_data[11:8] = char2hex(read_data); - 8'd16 : rxd_data[7:4] = char2hex(read_data); - 8'd17 : rxd_data[3:0] = char2hex(read_data); - endcase - i = i+1; - end - end - join if(rxd_data == exp_data) begin // $display("STATUS: ADDRESS: %x RXD: %x", addr,rxd_data); end else begin
diff --git a/verilog/dv/agents/user_tasks.sv b/verilog/dv/agents/user_tasks.sv new file mode 100644 index 0000000..47bfbab --- /dev/null +++ b/verilog/dv/agents/user_tasks.sv
@@ -0,0 +1,179 @@ + +/******************** +parameter bit [15:0] PAD_STRAP = (2'b00 << `PSTRAP_CLK_SRC ) | + (2'b00 << `PSTRAP_CLK_DIV ) | + (1'b1 << `PSTRAP_UARTM_CFG ) | + (1'b1 << `PSTRAP_QSPI_SRAM ) | + (2'b10 << `PSTRAP_QSPI_FLASH ) | + (1'b1 << `PSTRAP_RISCV_RESET_MODE ) | + (1'b1 << `PSTRAP_RISCV_CACHE_BYPASS ) | + (1'b1 << `PSTRAP_RISCV_SRAM_CLK_EDGE ) | + (2'b00 << `PSTRAP_CLK_SKEW ) | + (1'b0 << `PSTRAP_DEFAULT_VALUE ) ; +****/ + +`ifdef RISC_BOOT // RISCV Based Test case +parameter bit [15:0] PAD_STRAP = 16'b0000_0001_1011_0000; +`else +parameter bit [15:0] PAD_STRAP = 16'b0000_0000_1011_0000; +`endif + +/*********************************************** + +wire [15:0] strap_in; +assign strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1 +assign strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div +assign strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection +assign strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad +assign strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad +assign strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset +assign strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable +assign strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal +assign strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value + +assign strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal +***/ + +initial +begin + // Run in Fast Sim Mode + `ifdef GL + force u_top.u_wb_host._8654_.Q= 1'b1; + `else + force u_top.u_wb_host.u_fastsim_buf.X = 1'b1; + `endif + +end +task init; +begin + //#1 - Apply Reset + #1000 wb_rst_i = 0; + repeat (10) @(posedge clock); + #1000 wb_rst_i = 1; + + //#3 - Remove Reset + #1000 wb_rst_i = 0; + repeat (10) @(posedge clock); + //#4 - Wait for Power on reset removal + wait(u_top.p_reset_n == 1); + + // #5 - Wait for system reset removal + wait(u_top.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +/**** + //#2 - Apply Strap + strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1 + strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div + strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection + strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad + strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad + strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset + strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable + strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal + strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value + + strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal + + force u_top.io_in[36:29] = strap_in[15:8]; + force u_top.io_in[20:13] = strap_in[7:0]; + repeat (10) @(posedge clock); + + //#3 - Remove Reset + wb_rst_i = 0; // Remove Reset + repeat (10) @(posedge clock); + //#4 - Wait for Power on reset removal + wait(u_top.p_reset_n == 1); + + // #5 - Release the Strap + release u_top.io_in[36:29]; + release u_top.io_in[20:13]; + + // #6 - Wait for system reset removal + wait(u_top.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +***/ + end +endtask + +//----------------------------------------------- +// Apply user defined strap at power-on +//----------------------------------------------- + +task apply_strap; +input [15:0] strap; +begin + + repeat (10) @(posedge clock); + //#1 - Apply Reset + wb_rst_i = 1; + //#2 - Apply Strap + force u_top.io_in[36:29] = strap[15:8]; + force u_top.io_in[20:13] = strap[7:0]; + repeat (10) @(posedge clock); + + //#3 - Remove Reset + wb_rst_i = 0; // Remove Reset + + //#4 - Wait for Power on reset removal + wait(u_top.p_reset_n == 1); + + // #5 - Release the Strap + release u_top.io_in[36:29]; + release u_top.io_in[20:13]; + + // #6 - Wait for system reset removal + wait(u_top.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +end +endtask + +//--------------------------------------------------------- +// Create Pull Up/Down Based on Reset Strap Parameter +//--------------------------------------------------------- +genvar gCnt; +generate + for(gCnt=0; gCnt<16; gCnt++) begin : g_strap + if(gCnt < 8) begin + if(PAD_STRAP[gCnt]) begin + pullup(io_in[13+gCnt]); + end else begin + pulldown(io_in[13+gCnt]); + end + end else begin + if(PAD_STRAP[gCnt]) begin + pullup(io_in[29+gCnt-8]); + end else begin + pulldown(io_in[29+gCnt-8]); + end + end + end + +`ifdef RISC_BOOT // RISCV Based Test case +//------------------------------------------- +task wait_riscv_boot; +begin + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + $display("Status: Waiting for RISCV Core Boot ... "); + read_data = 0; + while((read_data >> (d_risc_id*8)) != 8'h1) begin + wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,read_data); + repeat (1000) @(posedge clock); + end + + $display("Status: RISCV Core is Booted "); + +end +endtask + +`endif + + +endgenerate +
diff --git a/verilog/dv/arduino_arrays/Makefile b/verilog/dv/arduino_arrays/Makefile index dad099c..0e61c01 100644 --- a/verilog/dv/arduino_arrays/Makefile +++ b/verilog/dv/arduino_arrays/Makefile
@@ -97,31 +97,31 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v index 3d47721..8f8b4ae 100644 --- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v +++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -69,8 +69,11 @@ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "is62wvs1288.v" +`include "user_params.svh" -module arduino_arrays_tb; +`define TB_HEX "arduino_arrays.hex" +`define TB_TOP arduino_arrays_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -150,63 +153,66 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_arrays_tb); - //$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.i_core_top_0); - //$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.u_connect); - //$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_arrays_tb.u_top.u_pinmux); + $dumpvars(3, `TB_TOP); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_pinmux); end `endif /************* Port-D Mapping ********************************** * Arduino-No - * Pin-2 0 PD0/RXD[0] digital_io[1] - * Pin-3 1 PD1/TXD[0] digital_io[2] - * Pin-4 2 PD2/RXD[1]/INT0 digital_io[3] - * Pin-5 3 PD3/INT1/OC2B(PWM0) digital_io[4] - * Pin-6 4 PD4/TXD[1] digital_io[5] - * Pin-11 5 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] - * Pin-12 6 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2] - * Pin-13 7 PD7/A1N1 digital_io[10]/analog_io[3] + * Pin-2 0 PD0/RXD[0] digital_io[6] + * Pin-3 1 PD1/TXD[0] digital_io[7] + * Pin-4 2 PD2/RXD[1]/INT0 digital_io[8] + * Pin-5 3 PD3/INT1/OC2B(PWM0) digital_io[9] + * Pin-6 4 PD4/TXD[1] digital_io[10] + * Pin-11 5 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[13] + * Pin-12 6 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[14]/analog_io[2] + * Pin-13 7 PD7/A1N1 digital_io[15]/analog_io[3] * ********************************************************/ - wire [7:0] port_d_in = { io_out[10], - io_out[9], - io_out[8], - io_out[5], - io_out[4], - io_out[3], - io_out[2], - io_out[1] + wire [7:0] port_d_in = { io_out[15], + io_out[14], + io_out[13], + io_out[10], + io_out[9], + io_out[8], + io_out[7], + io_out[6] }; initial begin + $value$plusargs("risc_core_id=%d", d_risc_id); #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); + + init(); + wait_riscv_boot(); - $value$plusargs("risc_core_id=%d", d_risc_id); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove WB and SPI Reset and CORE under Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // QSPI SRAM:CS#2 Switch to QSPI Mode - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); + //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); @@ -275,11 +281,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -319,8 +320,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -334,25 +335,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_arrays.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -368,7 +369,7 @@ ); - wire spiram_csb = io_out[27]; + wire spiram_csb = io_out[31]; is62wvs1288 #(.mem_file_name("none")) u_sram ( @@ -525,6 +526,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/arduino_ascii_table/Makefile b/verilog/dv/arduino_ascii_table/Makefile index 30b4cfe..38987f6 100644 --- a/verilog/dv/arduino_ascii_table/Makefile +++ b/verilog/dv/arduino_ascii_table/Makefile
@@ -97,10 +97,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v index b6c4c4c..0927816 100644 --- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v +++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -68,9 +68,12 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" `include "uart_agent.v" -module arduino_ascii_table_tb; +`define TB_HEX "arduino_ascii_table.hex" +`define TB_TOP arduino_ascii_table_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -142,11 +145,11 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_ascii_table_tb); - $dumpvars(0, arduino_ascii_table_tb.u_top.u_riscv_top.i_core_top_0); - $dumpvars(0, arduino_ascii_table_tb.u_top.u_riscv_top.u_connect); - $dumpvars(0, arduino_ascii_table_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_ascii_table_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core); + $dumpvars(3, `TB_TOP); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); end `endif @@ -332,25 +335,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_ascii_table.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -366,14 +369,27 @@ ); + wire spiram_csb = io_out[31]; + + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //--------------------------- // UART Agent integration // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ),
diff --git a/verilog/dv/arduino_character_analysis/Makefile b/verilog/dv/arduino_character_analysis/Makefile index 9293db4..b50000c 100644 --- a/verilog/dv/arduino_character_analysis/Makefile +++ b/verilog/dv/arduino_character_analysis/Makefile
@@ -97,31 +97,31 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v index 46490b2..699f433 100644 --- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v +++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -70,8 +70,11 @@ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "uart_agent.v" `include "is62wvs1288.v" +`include "user_params.svh" -module arduino_character_analysis; +`define TB_HEX "arduino_character_analysis.hex" +`define TB_TOP arduino_character_analysis_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -115,11 +118,12 @@ reg [15:0] uart_tx_nu ; reg [7:0] uart_write_data [0:39]; reg uart_fifo_enable ; // fifo mode disable - reg flag ; + reg flag ; + reg [7:0] dCnt ; // DataCount - reg [31:0] check_sum ; + reg [31:0] check_sum ; - integer d_risc_id; + integer d_risc_id; integer i,j; @@ -168,11 +172,11 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_character_analysis); - $dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.i_core_top_0); - $dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.u_connect); - $dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_character_analysis.u_top.u_uart_i2c_usb_spi.u_uart0_core); + $dumpvars(2, `TB_TOP); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); end `endif @@ -213,7 +217,7 @@ uart_parity_en = 0; // parity enable uart_even_odd_parity = 1; // 0: odd parity; 1: even parity tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 - uart_timeout = 2000;// wait time limit + uart_timeout = 750;// wait time limit uart_fifo_enable = 0; // fifo mode disable $value$plusargs("risc_core_id=%d", d_risc_id); @@ -221,24 +225,27 @@ #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); + + init(); + wait_riscv_boot(); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove WB and SPI Reset and CORE under Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // QSPI SRAM:CS#2 Switch to QSPI Mode - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + // wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + // wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); + // wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); @@ -257,34 +264,36 @@ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (40000) @(posedge clock); // wait for Processor Get Ready flag = 0; check_sum = 0; + dCnt = 0; fork begin fork begin - tb_uart.write_char ("A"); - tb_uart.write_char (" "); - tb_uart.write_char ("\n"); - tb_uart.write_char ("b"); - tb_uart.write_char (";"); - tb_uart.write_char ("F"); - end - begin - while(flag == 0) + while(dCnt < 7 ) begin - tb_uart.read_char(read_data,flag); - if(flag == 0) begin - $write ("%c",read_data); - check_sum = check_sum+read_data; - end + flag = 0; + while(flag == 0) begin + tb_uart.read_char(read_data,flag); + if(flag == 0) begin + $write ("%c",read_data); + check_sum = check_sum+read_data; + end + end + if(dCnt == 0) tb_uart.write_char ("A"); + if(dCnt == 1) tb_uart.write_char (" "); + if(dCnt == 2) tb_uart.write_char ("\n"); + if(dCnt == 3) tb_uart.write_char ("b"); + if(dCnt == 4) tb_uart.write_char (";"); + if(dCnt == 5) tb_uart.write_char ("F"); + dCnt = dCnt+1; end end join end begin - repeat (3000000) @(posedge clock); // wait for Processor Get Ready + repeat (4000000) @(posedge clock); // wait for Processor Get Ready end join_any @@ -362,8 +371,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -377,25 +386,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_character_analysis.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -411,7 +420,7 @@ ); - wire spiram_csb = io_out[27]; + wire spiram_csb = io_out[31]; is62wvs1288 #(.mem_file_name("none")) u_sram ( @@ -430,8 +439,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -569,6 +578,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/arduino_digital_port_control/Makefile b/verilog/dv/arduino_digital_port_control/Makefile index 7168229..7d035ec 100644 --- a/verilog/dv/arduino_digital_port_control/Makefile +++ b/verilog/dv/arduino_digital_port_control/Makefile
@@ -99,31 +99,31 @@ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o ${GCC_PREFIX}-ar rcs core.a SPI.cpp.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp index d4dd6f5..ba6c295 100644 --- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp +++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
@@ -49,16 +49,16 @@ // go through the six channels of the digital pot: for (int channel = 0; channel < 6; channel++) { // change the resistance on this channel from min to max: - for (int level = 0; level < 255; level++) { + for (int level = 0; level < 64; level++) { digitalPotWrite(channel, level); - delayMicroseconds(10); + delayMicroseconds(5); } // wait a second at the top: - delayMicroseconds(100); + delayMicroseconds(20); // change the resistance on this channel from max to min: - for (int level = 0; level < 255; level++) { - digitalPotWrite(channel, 255 - level); - delayMicroseconds(10); + for (int level = 0; level < 64; level++) { + digitalPotWrite(channel, 64 - level); + delayMicroseconds(5); } }
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v index b205431..e91855d 100644 --- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v +++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -71,6 +71,8 @@ `include "is62wvs1288.v" `include "bfm_ad5205.sv" +`define TB_HEX "arduino_digital_port_control.hex" +`define TB_TOP arduino_digital_port_control_tb module arduino_digital_port_control_tb; reg clock; reg wb_rst_i; @@ -152,43 +154,46 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_digital_port_control_tb); - //$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.i_core_top_0); - //$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.u_connect); - //$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_digital_port_control_tb.u_top.u_pinmux); - $dumpvars(0, arduino_digital_port_control_tb.u_top.u_uart_i2c_usb_spi); + $dumpvars(3, `TB_TOP); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_pinmux); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi); end `endif initial begin + $value$plusargs("risc_core_id=%d", d_risc_id); #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); + + init(); + wait_riscv_boot(); - $value$plusargs("risc_core_id=%d", d_risc_id); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove WB and SPI Reset and CORE under Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // QSPI SRAM:CS#2 Switch to QSPI Mode - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); - wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); + //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); @@ -203,27 +208,27 @@ repeat (100) @(posedge clock); // wait for Processor Get Ready - repeat (20000) @(posedge clock); // wait for Processor Get Ready + repeat (1000) @(posedge clock); // wait for Processor Get Ready flag = 1; fork begin - for (channel = 0; channel < 1; channel = channel+1) begin + for (channel = 0; channel < 6; channel = channel+1) begin // change the resistance on this channel from min to max: - for (level = 0; level < 255; level = level+1) begin + for (level = 0; level < 64; level = level+1) begin wait(u_ad5205.channel == channel && u_ad5205.position == level); $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position); end // change the resistance on this channel from min to max: - for (level = 0; level < 255; level = level+1) begin - wait((u_ad5205.channel == channel) && (u_ad5205.position == (255 -level))); + for (level = 0; level < 64; level = level+1) begin + wait((u_ad5205.channel == channel) && (u_ad5205.position == (64 -level))); $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position); end end test_fail = 0; end begin - repeat (6000000) @(posedge clock); // wait for Processor Get Ready + repeat (1000000) @(posedge clock); // wait for Processor Get Ready test_fail = 1; end join_any @@ -249,11 +254,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -292,16 +292,15 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET //------------------------------------------------------------------------------------- // Integrate the Serial SPI to ad5204/5206 (4-/6-Channel Digital Potentiometers) // https://www.analog.com/media/en/technical-documentation/data-sheets/ad5204_5206.pdf // ----------------------------------------------------------------------------------- - wire sspi_sck = io_out[16]; - wire sspi_sdi = io_out[15]; - wire sspi_ssn = io_out[13]; + wire sspi_sck = io_out[21]; + wire sspi_sdi = io_out[20]; + wire sspi_ssn = io_out[18]; wire [2:0] p_channel; // potentiometer channel wire [7:0] p_position; // potentiometer position @@ -327,25 +326,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_digital_port_control.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -361,7 +360,7 @@ ); - wire spiram_csb = io_out[27]; + wire spiram_csb = io_out[31]; is62wvs1288 #(.mem_file_name("none")) u_sram ( @@ -508,6 +507,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/arduino_gpio_intr/Makefile b/verilog/dv/arduino_gpio_intr/Makefile index 0bf70cf..0912a65 100644 --- a/verilog/dv/arduino_gpio_intr/Makefile +++ b/verilog/dv/arduino_gpio_intr/Makefile
@@ -97,31 +97,31 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v index 6e509dc..608d120 100644 --- a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v +++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
@@ -67,9 +67,11 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" +`include "user_params.svh" `include "uart_agent.v" -`define TB_HEX "arduino_gpio_intr.ino.hex" +`define TB_HEX "arduino_gpio_intr.hex" `define TB_TOP arduino_gpio_intr_tb module `TB_TOP; @@ -159,14 +161,14 @@ /********************************************************************** Arduino Digital PinMapping ATMGA328 Pin No Functionality Arduino Pin Carvel Pin Mapping - Pin-2 PD0/RXD[0] 0 digital_io[1] - Pin-3 PD1/TXD[0] 1 digital_io[2] - Pin-4 PD2/RXD[1]/INT0 2 digital_io[3] - Pin-5 PD3/INT1/OC2B(PWM0) 3 digital_io[4] - Pin-6 PD4/TXD[1] 4 digital_io[5] - Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 5 digital_io[8] - Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 6 digital_io[9] /analog_io[2] - Pin-13 PD7/A1N1 7 digital_io[10]/analog_io[3] + Pin-2 PD0/RXD[0] 0 digital_io[6] + Pin-3 PD1/TXD[0] 1 digital_io[7] + Pin-4 PD2/RXD[1]/INT0 2 digital_io[8] + Pin-5 PD3/INT1/OC2B(PWM0) 3 digital_io[9] + Pin-6 PD4/TXD[1] 4 digital_io[10] + Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 5 digital_io[13] + Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 6 digital_io[14]/analog_io[2] + Pin-13 PD7/A1N1 7 digital_io[15]/analog_io[3] Pin-14 PB0/CLKO/ICP1 8 digital_io[11] Pin-15 PB1/SS[1]OC1A(PWM3) 9 digital_io[12] Pin-16 PB2/SS[0]/OC1B(PWM4) 10 digital_io[13] @@ -174,45 +176,45 @@ Pin-18 PB4/MISO 12 digital_io[15] Pin-19 PB5/SCK 13 digital_io[16] - Pin-23 ADC0 14 digital_io[18] - Pin-24 ADC1 15 digital_io[19] - Pin-25 ADC2 16 digital_io[20] - Pin-26 ADC3 17 digital_io[21] - Pin-27 SDA 18 digital_io[22] - Pin-28 SCL 19 digital_io[23] + Pin-23 ADC0 14 digital_io[22] + Pin-24 ADC1 15 digital_io[23] + Pin-25 ADC2 16 digital_io[24] + Pin-26 ADC3 17 digital_io[25] + Pin-27 SDA 18 digital_io[26] + Pin-28 SCL 19 digital_io[27] - Pin-9 XTAL1 20 digital_io[6] - Pin-10 XTAL2 21 digital_io[7] - Pin-1 RESET 22 digital_io[0] + Pin-9 XTAL1 20 digital_io[11] + Pin-10 XTAL2 21 digital_io[12] + Pin-1 RESET 22 digital_io[5] *****************************************************************************/ // Exclude UART TXD/RXD and RESET reg [21:2] arduino_din; assign { //io_in[0], - Exclude RESET - io_in[7], - io_in[6], + io_in[12], + io_in[11], + io_in[27], + io_in[26], + io_in[25], + io_in[24], io_in[23], io_in[22], io_in[21], io_in[20], io_in[19], io_in[18], + io_in[17], io_in[16], io_in[15], io_in[14], io_in[13], - io_in[12], - io_in[11], io_in[10], io_in[9], - io_in[8], - io_in[5], - io_in[4], - io_in[3] + io_in[8] // Uart pins io_in[2], io_in[1] are excluded - } = arduino_din; - + } = (u_top.p_reset_n == 0) ? 23'hZZ_ZZZZ: arduino_din; // Tri-state untill Strap pull completed + /************************************************************************* * This is Baud Rate to clock divider conversion for Test Bench * Note: DUT uses 16x baud clock, where are test bench uses directly @@ -247,29 +249,29 @@ initial begin arduino_din[22:2] = 23'b010_1010_1010_1010_1010_10; // Initialise based on test case edge - pinmap[0] = 24; - pinmap[1] = 25; - pinmap[2] = 26; - pinmap[3] = 27; - pinmap[4] = 28; - pinmap[5] = 29; - pinmap[6] = 30; - pinmap[7] = 31; - pinmap[8] = 8; - pinmap[9] = 9; - pinmap[10] = 10; - pinmap[11] = 11; - pinmap[12] = 12; - pinmap[13] = 13; - pinmap[14] = 16; - pinmap[15] = 17; - pinmap[16] = 18; - pinmap[17] = 19; - pinmap[18] = 20; - pinmap[19] = 21; - pinmap[20] = 14; - pinmap[21] = 15; - pinmap[22] = 22; + pinmap[0] = 24; // PD0 - GPIO-24 + pinmap[1] = 25; // PD1 - GPIO-25 + pinmap[2] = 26; // PD2 - GPIO-26 + pinmap[3] = 27; // PD3 - GPIO-27 + pinmap[4] = 28; // PD4 - GPIO-28 + pinmap[5] = 29; // PD5 - GPIO-29 + pinmap[6] = 30; // PD6 - GPIO-30 + pinmap[7] = 31; // PD7 - GPIO-31 + pinmap[8] = 8; // PB0 - GPIO-8 + pinmap[9] = 9; // PB1 - GPIO-9 + pinmap[10] = 10; // PB2 - GPIO-10 + pinmap[11] = 11; // PB3 - GPIO-11 + pinmap[12] = 12; // PB4 - GPIO-12 + pinmap[13] = 13; // PB5 - GPIO-13 + pinmap[14] = 16; // PC0 - GPIO-16 + pinmap[15] = 17; // PC1 - GPIO-17 + pinmap[16] = 18; // PC2 - GPIO-18 + pinmap[17] = 19; // PC3 - GPIO-19 + pinmap[18] = 20; // PC4 - GPIO-20 + pinmap[19] = 21; // PC5 - GPIO-21 + pinmap[20] = 14; // PB6 - GPIO-14 + pinmap[21] = 15; // PB7 - GPIO-15 + pinmap[22] = 22; // PC6 - GPIO-22 uart_data_bit = 2'b11; @@ -278,24 +280,27 @@ uart_parity_en = 0; // parity enable uart_even_odd_parity = 1; // 0: odd parity; 1: even parity tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 - uart_timeout = 20000;// wait time limit + uart_timeout = 1000;// wait time limit uart_fifo_enable = 0; // fifo mode disable $value$plusargs("risc_core_id=%d", d_risc_id); + + init(); + wait_riscv_boot(); #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); @@ -314,7 +319,7 @@ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (80000) @(posedge clock); // wait for Processor Get Ready + repeat (40000) @(posedge clock); // wait for Processor Get Ready flag = 0; check_sum = 0; compare_start = 1; @@ -361,7 +366,7 @@ end end begin - repeat (700000) @(posedge clock); // wait for Processor Get Ready + repeat (900000) @(posedge clock); // wait for Processor Get Ready end join_any @@ -397,11 +402,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -440,8 +440,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -//assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +//assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -455,26 +455,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash s25fl256s #(.mem_file_name(`TB_HEX), - .otp_file_name("none"), + .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs @@ -489,14 +489,27 @@ ); + wire spiram_csb = io_out[31]; + + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //--------------------------- // UART Agent integration // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -640,6 +653,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/arduino_hello_world/Makefile b/verilog/dv/arduino_hello_world/Makefile index 497a39e..06f0645 100644 --- a/verilog/dv/arduino_hello_world/Makefile +++ b/verilog/dv/arduino_hello_world/Makefile
@@ -97,31 +97,31 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v index 43cfed0..8fc236c 100644 --- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v +++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -68,9 +68,13 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" +`include "user_params.svh" `include "uart_agent.v" -module arduino_hello_world_tb; +`define TB_HEX "arduino_hello_world.hex" +`define TB_TOP arduino_hello_world_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -140,11 +144,11 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_hello_world_tb); - //$dumpvars(0, arduino_hello_world_tb.u_top.u_riscv_top.i_core_top_0); - //$dumpvars(0, arduino_hello_world_tb.u_top.u_riscv_top.u_connect); - //$dumpvars(0, arduino_hello_world_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_hello_world_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core); + $dumpvars(3, `TB_TOP); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); end `endif @@ -194,15 +198,17 @@ repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); + init(); + wait_riscv_boot(); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); @@ -220,7 +226,6 @@ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (45000) @(posedge clock); // wait for Processor Get Ready flag = 1; @@ -320,8 +325,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -335,25 +340,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_hello_world.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -369,14 +374,27 @@ ); + wire spiram_csb = io_out[31]; + + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //--------------------------- // UART Agent integration // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -514,6 +532,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/arduino_i2c_scaner/Makefile b/verilog/dv/arduino_i2c_scaner/Makefile index 7688c67..06dc4bd 100644 --- a/verilog/dv/arduino_i2c_scaner/Makefile +++ b/verilog/dv/arduino_i2c_scaner/Makefile
@@ -98,10 +98,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v index 71a8371..6cb6a4d 100644 --- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v +++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -70,8 +70,11 @@ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "uart_agent.v" `include "i2c_slave_model.v" +`include "is62wvs1288.v" -module arduino_i2c_scaner_tb; +`define TB_HEX "arduino_i2c_scaner.hex" +`define TB_TOP arduino_i2c_scaner_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -145,13 +148,13 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_i2c_scaner_tb); - $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.i_core_top_0); - $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_connect); - $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core); - $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_i2cm); - $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_pinmux); + $dumpvars(3, `TB_TOP); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm); + $dumpvars(0, `TB_TOP.u_top.u_pinmux); end `endif @@ -337,10 +340,10 @@ // -------------------------- tri scl,sda; -assign sda = (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz; -assign scl = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz; -assign io_in[22] = sda; -assign io_in[23] = scl; +assign sda = (io_oeb[26] == 1'b0) ? io_out[26] : 1'bz; +assign scl = (io_oeb[27] == 1'b0) ? io_out[27]: 1'bz; +assign io_in[26] = sda; +assign io_in[27] = scl; pullup p1(scl); // pullup scl line pullup p2(sda); // pullup sda line @@ -383,26 +386,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_i2c_scaner.ino.hex"), - .otp_file_name("none"), + s25fl256s #(.mem_file_name(`TB_HEX), + .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs @@ -417,14 +420,27 @@ ); + wire spiram_csb = io_out[31]; + + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //--------------------------- // UART Agent integration // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ),
diff --git a/verilog/dv/arduino_i2c_wr_rd/Makefile b/verilog/dv/arduino_i2c_wr_rd/Makefile index 8c362aa..b868513 100644 --- a/verilog/dv/arduino_i2c_wr_rd/Makefile +++ b/verilog/dv/arduino_i2c_wr_rd/Makefile
@@ -98,10 +98,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v index 8d3965e..ee7124a 100644 --- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v +++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -68,10 +68,11 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" `include "uart_agent.v" `include "i2c_slave_model.v" -`define TB_HEX "arduino_i2c_wr_rd.ino.hex" +`define TB_HEX "arduino_i2c_wr_rd.hex" `define TB_TOP arduino_i2c_wr_rd_tb module `TB_TOP; reg clock; @@ -328,18 +329,17 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET //--------------------------- // I2C // -------------------------- tri scl,sda; -assign sda = (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz; -assign scl = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz; -assign io_in[22] = sda; -assign io_in[23] = scl; +assign sda = (io_oeb[26] == 1'b0) ? io_out[26] : 1'bz; +assign scl = (io_oeb[27] == 1'b0) ? io_out[27]: 1'bz; +assign io_in[26] = sda; +assign io_in[27] = scl; pullup p1(scl); // pullup scl line pullup p2(sda); // pullup sda line @@ -367,26 +367,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash s25fl256s #(.mem_file_name(`TB_HEX), - .otp_file_name("none"), + .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs @@ -401,14 +401,28 @@ ); + wire spiram_csb = io_out[31]; + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); + +//------------------------------------- //--------------------------- // UART Agent integration // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ),
diff --git a/verilog/dv/arduino_multi_serial/Makefile b/verilog/dv/arduino_multi_serial/Makefile index 8c1fa01..d0899fd 100644 --- a/verilog/dv/arduino_multi_serial/Makefile +++ b/verilog/dv/arduino_multi_serial/Makefile
@@ -97,10 +97,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v index 5dfd94e..8cfeed9 100644 --- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v +++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -69,9 +69,12 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" `include "uart_agent.v" -module arduino_multi_serial_tb; +`define TB_HEX "arduino_multi_serial.hex" +`define TB_TOP arduino_multi_serial_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -144,12 +147,12 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_multi_serial_tb); - //$dumpvars(0, arduino_multi_serial_tb.u_top.u_riscv_top.i_core_top_0); - //$dumpvars(0, arduino_multi_serial_tb.u_top.u_riscv_top.u_connect); - //$dumpvars(0, arduino_multi_serial_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_multi_serial_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core); - $dumpvars(0, arduino_multi_serial_tb.u_top.u_uart_i2c_usb_spi.u_uart1_core); + $dumpvars(3, `TB_TOP); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart1_core); end `endif @@ -364,25 +367,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_multi_serial.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -398,14 +401,26 @@ ); + wire spiram_csb = io_out[31]; + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //--------------------------- // UART-0 Agent integration // -------------------------- wire uart0_txd,uart0_rxd; -assign uart0_txd = io_out[2]; -assign io_in[1] = uart0_rxd ; +assign uart0_txd = io_out[7]; +assign io_in[6] = uart0_rxd ; uart_agent tb_uart0( .mclk (clock ), @@ -418,8 +433,8 @@ // -------------------------- wire uart1_txd,uart1_rxd; -assign uart1_txd = io_out[5]; -assign io_in[3] = uart1_rxd ; +assign uart1_txd = io_out[10]; +assign io_in[8] = uart1_rxd ; uart_agent tb_uart1( .mclk (clock ),
diff --git a/verilog/dv/arduino_risc_boot/Makefile b/verilog/dv/arduino_risc_boot/Makefile index 5c074b3..68dd9fc 100644 --- a/verilog/dv/arduino_risc_boot/Makefile +++ b/verilog/dv/arduino_risc_boot/Makefile
@@ -97,10 +97,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v index bb933b7..eb4d0d0 100644 --- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v +++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -67,7 +67,12 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" -module arduino_risc_boot_tb; +`include "is62wvs1288.v" + +`define TB_HEX "arduino_risc_boot.hex" +`define TB_TOP arduino_risc_boot_tb + +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -117,7 +122,7 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_risc_boot_tb); + $dumpvars(3, `TB_TOP); end `endif @@ -247,25 +252,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_risc_boot.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -281,6 +286,22 @@ ); + wire spiram_csb = io_out[31]; + + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); + +//------------------------------------- +
diff --git a/verilog/dv/arduino_string/Makefile b/verilog/dv/arduino_string/Makefile index 78fc16e..bf750df 100644 --- a/verilog/dv/arduino_string/Makefile +++ b/verilog/dv/arduino_string/Makefile
@@ -97,10 +97,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_string/arduino_string_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v index 3b23622..f57b93f 100644 --- a/verilog/dv/arduino_string/arduino_string_tb.v +++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -68,9 +68,12 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" `include "uart_agent.v" -module arduino_string_tb; +`define TB_HEX "arduino_string.hex" +`define TB_TOP arduino_string_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -144,11 +147,11 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_string_tb); - $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.i_core_top_0); - $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_connect); - $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_string_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core); + $dumpvars(3, `TB_TOP); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); end `endif @@ -320,9 +323,9 @@ .user_irq () ); + // SSPI Slave I/F assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -336,26 +339,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_string.ino.hex"), - .otp_file_name("none"), + s25fl256s #(.mem_file_name(`TB_HEX), + .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs @@ -370,14 +373,27 @@ ); + wire spiram_csb = io_out[31]; + + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //--------------------------- // UART Agent integration // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ),
diff --git a/verilog/dv/arduino_switchCase2/Makefile b/verilog/dv/arduino_switchCase2/Makefile index 2533931..6470aef 100644 --- a/verilog/dv/arduino_switchCase2/Makefile +++ b/verilog/dv/arduino_switchCase2/Makefile
@@ -97,10 +97,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v index 70592df..8a3a7d8 100644 --- a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v +++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -70,7 +70,9 @@ `include "uart_agent.v" `include "is62wvs1288.v" -module arduino_switchCase2_tb; +`define TB_HEX "arduino_switchCase2.hex" +`define TB_TOP arduino_switchCase2_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -167,11 +169,11 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, arduino_switchCase2_tb); - $dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.i_core_top_0); - $dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.u_connect); - $dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.u_intf); - $dumpvars(0, arduino_switchCase2_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core); + $dumpvars(3, `TB_TOP); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); end `endif @@ -207,24 +209,24 @@ /************* Port-D Mapping ********************************** * Arduino-No - * Pin-2 0 PD0/RXD[0] digital_io[1] - * Pin-3 1 PD1/TXD[0] digital_io[2] - * Pin-4 2 PD2/RXD[1]/INT0 digital_io[3] - * Pin-5 3 PD3/INT1/OC2B(PWM0) digital_io[4] - * Pin-6 4 PD4/TXD[1] digital_io[5] - * Pin-11 5 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] - * Pin-12 6 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2] - * Pin-13 7 PD7/A1N1 digital_io[10]/analog_io[3] + * Pin-2 0 PD0/RXD[0] digital_io[6] + * Pin-3 1 PD1/TXD[0] digital_io[7] + * Pin-4 2 PD2/RXD[1]/INT0 digital_io[8] + * Pin-5 3 PD3/INT1/OC2B(PWM0) digital_io[9] + * Pin-6 4 PD4/TXD[1] digital_io[10] + * Pin-11 5 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[13] + * Pin-12 6 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[14]/analog_io[2] + * Pin-13 7 PD7/A1N1 digital_io[15]/analog_io[3] * ********************************************************/ - wire [7:0] port_d_in = { io_out[10], - io_out[9], - io_out[8], - io_out[5], - io_out[4], - io_out[3], - io_out[2], - io_out[1] + wire [7:0] port_d_in = { io_out[15], + io_out[14], + io_out[13], + io_out[10], + io_out[9], + io_out[8], + io_out[7], + io_out[6] }; initial begin uart_data_bit = 2'b11; @@ -393,25 +395,25 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("arduino_switchCase2.ino.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( @@ -427,8 +429,7 @@ ); - - wire spiram_csb = io_out[27]; + wire spiram_csb = io_out[31]; is62wvs1288 #(.mem_file_name("none")) u_sram ( @@ -446,8 +447,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ),
diff --git a/verilog/dv/arduino_timer_intr/Makefile b/verilog/dv/arduino_timer_intr/Makefile index aa946e0..4a23ffa 100644 --- a/verilog/dv/arduino_timer_intr/Makefile +++ b/verilog/dv/arduino_timer_intr/Makefile
@@ -101,10 +101,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp b/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp index d59053a..5c6104b 100644 --- a/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp +++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp
@@ -10,8 +10,8 @@ -int Timer_us =0; -int Timer_ms =0; +uint8_t Timer_us =0; +uint8_t Timer_ms =0; void setup(); void loop(); void timer_us_intr();
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v index 5e423d5..4107a97 100644 --- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v +++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -67,9 +67,10 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" `include "uart_agent.v" -`define TB_HEX "arduino_timer_intr.ino.hex" +`define TB_HEX "arduino_timer_intr.hex" `define TB_TOP arduino_timer_intr_tb module `TB_TOP; @@ -157,62 +158,6 @@ wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines; -/********************************************************************** - Arduino Digital PinMapping - ATMGA328 Pin No Functionality Arduino Pin Carvel Pin Mapping - Pin-2 PD0/RXD[0] 0 digital_io[1] - Pin-3 PD1/TXD[0] 1 digital_io[2] - Pin-4 PD2/RXD[1]/INT0 2 digital_io[3] - Pin-5 PD3/INT1/OC2B(PWM0) 3 digital_io[4] - Pin-6 PD4/TXD[1] 4 digital_io[5] - Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 5 digital_io[8] - Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 6 digital_io[9] /analog_io[2] - Pin-13 PD7/A1N1 7 digital_io[10]/analog_io[3] - Pin-14 PB0/CLKO/ICP1 8 digital_io[11] - Pin-15 PB1/SS[1]OC1A(PWM3) 9 digital_io[12] - Pin-16 PB2/SS[0]/OC1B(PWM4) 10 digital_io[13] - Pin-17 PB3/MOSI/OC2A(PWM5) 11 digital_io[14] - Pin-18 PB4/MISO 12 digital_io[15] - Pin-19 PB5/SCK 13 digital_io[16] - - Pin-23 ADC0 14 digital_io[18] - Pin-24 ADC1 15 digital_io[19] - Pin-25 ADC2 16 digital_io[20] - Pin-26 ADC3 17 digital_io[21] - Pin-27 SDA 18 digital_io[22] - Pin-28 SCL 19 digital_io[23] - - Pin-9 XTAL1 20 digital_io[6] - Pin-10 XTAL2 21 digital_io[7] - Pin-1 RESET 22 digital_io[0] -*****************************************************************************/ - -// Exclude UART TXD/RXD and RESET -reg [21:2] arduino_din; -assign { - //io_in[0], - Exclude RESET - io_in[7], - io_in[6], - io_in[23], - io_in[22], - io_in[21], - io_in[20], - io_in[19], - io_in[18], - io_in[16], - io_in[15], - io_in[14], - io_in[13], - io_in[12], - io_in[11], - io_in[10], - io_in[9], - io_in[8], - io_in[5], - io_in[4], - io_in[3] - // Uart pins io_in[2], io_in[1] are excluded - } = arduino_din; /************************************************************************* * This is Baud Rate to clock divider conversion for Test Bench @@ -244,33 +189,8 @@ endtask - reg[7:0] pinmap[0:22]; //ardiono to gpio pinmaping initial begin - arduino_din[22:2] = 23'b010_1010_1010_1010_1010_10; // Initialise based on test case edge - pinmap[0] = 24; - pinmap[1] = 25; - pinmap[2] = 26; - pinmap[3] = 27; - pinmap[4] = 28; - pinmap[5] = 29; - pinmap[6] = 30; - pinmap[7] = 31; - pinmap[8] = 8; - pinmap[9] = 9; - pinmap[10] = 10; - pinmap[11] = 11; - pinmap[12] = 12; - pinmap[13] = 13; - pinmap[14] = 16; - pinmap[15] = 17; - pinmap[16] = 18; - pinmap[17] = 19; - pinmap[18] = 20; - pinmap[19] = 21; - pinmap[20] = 14; - pinmap[21] = 15; - pinmap[22] = 22; uart_data_bit = 2'b11; @@ -333,7 +253,7 @@ end end begin - repeat (500000) @(posedge clock); // wait for Processor Get Ready + repeat (510000) @(posedge clock); // wait for Processor Get Ready end join_any @@ -412,7 +332,7 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET +assign io_in[5] = 1'b1; // RESET //assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf @@ -427,26 +347,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash s25fl256s #(.mem_file_name(`TB_HEX), - .otp_file_name("none"), + .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs @@ -461,14 +381,26 @@ ); + wire spiram_csb = io_out[31]; + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //--------------------------- // UART Agent integration // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ),
diff --git a/verilog/dv/arduino_ws281x/Makefile b/verilog/dv/arduino_ws281x/Makefile index 8d88be5..0a22bf8 100644 --- a/verilog/dv/arduino_ws281x/Makefile +++ b/verilog/dv/arduino_ws281x/Makefile
@@ -61,12 +61,8 @@ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o - ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/TIMERClass.cpp -o TIMERClass.cpp.o - ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/WS281X/src ${RISCDUINO_BOARD}/libraries/WS281X/src/WS281X.cpp -o WS281X.cpp.o - - ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o @@ -105,10 +101,10 @@ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o - ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf - ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin - ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex - ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump + ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.elf + ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.elf ${PATTERN}.bin + ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF)
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v index 2746a60..a6cc886 100644 --- a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v +++ b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
@@ -67,10 +67,11 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" `include "uart_agent.v" `include "bfm_ws281x.sv" -`define TB_HEX "arduino_ws281x.ino.hex" +`define TB_HEX "arduino_ws281x.hex" `define TB_TOP arduino_ws281x_tb module `TB_TOP; @@ -156,34 +157,34 @@ Arduino Digital PinMapping * Pin Mapping Arduino ATMGE CONFIG * ATMEGA328 Port caravel Pin Mapping -* Pin-1 22 PC6/WS[0]/RESET* digital_io[0] -* Pin-2 0 PD0/WS[0]/RXD[0] digital_io[1] -* Pin-3 1 PD1/WS[0]/TXD[0] digital_io[2] -* Pin-4 2 PD2/WS[0]/RXD[1]/INT0 digital_io[3] -* Pin-5 3 PD3/WS[1]INT1/OC2B(PWM0) digital_io[4] -* Pin-6 4 PD4/WS[1]TXD[1] digital_io[5] +* Pin-1 22 PC6/WS[0]/RESET* digital_io[5] +* Pin-2 0 PD0/WS[0]/RXD[0] digital_io[6] +* Pin-3 1 PD1/WS[0]/TXD[0] digital_io[7] +* Pin-4 2 PD2/WS[0]/RXD[1]/INT0 digital_io[8] +* Pin-5 3 PD3/WS[1]INT1/OC2B(PWM0) digital_io[9] +* Pin-6 4 PD4/WS[1]TXD[1] digital_io[10] * Pin-7 VCC - * Pin-8 GND - -* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[6] -* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[7] -* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[8] -* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2] -* Pin-13 7 PD7/WS[2]/A1N1 digital_io[10]/analog_io[3] -* Pin-14 8 PB0/WS[2]/CLKO/ICP1 digital_io[11] -* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) digital_io[12] -* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[13] -* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[14] -* Pin-18 12 PB4/WS[3]/MISO digital_io[15] -* Pin-19 13 PB5/SCK digital_io[16] +* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[11] +* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[12] +* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[13] +* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 digital_io[14]/analog_io[2] +* Pin-13 7 PD7/WS[2]/A1N1 digital_io[15]/analog_io[3] +* Pin-14 8 PB0/WS[2]/CLKO/ICP1 digital_io[16] +* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) digital_io[17] +* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[18] +* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[19] +* Pin-18 12 PB4/WS[3]/MISO digital_io[20] +* Pin-19 13 PB5/SCK digital_io[21] * Pin-20 AVCC - * Pin-21 AREF analog_io[10] * Pin-22 GND - -* Pin-23 14 PC0/ADC0 digital_io[18]/analog_io[11] -* Pin-24 15 PC1/ADC1 digital_io[19]/analog_io[12] -* Pin-25 16 PC2/ADC2 digital_io[20]/analog_io[13] -* Pin-26 17 PC3/ADC3 digital_io[21]/analog_io[14] -* Pin-27 18 PC4/ADC4/SDA digital_io[22]/analog_io[15] -* Pin-28 19 PC5/ADC5/SCL digital_io[23]/analog_io[16] +* Pin-23 14 PC0/ADC0 digital_io[22]/analog_io[11] +* Pin-24 15 PC1/ADC1 digital_io[23]/analog_io[12] +* Pin-25 16 PC2/ADC2 digital_io[24]/analog_io[13] +* Pin-26 17 PC3/ADC3 digital_io[25]/analog_io[14] +* Pin-27 18 PC4/ADC4/SDA digital_io[26]/analog_io[15] +* Pin-28 19 PC5/ADC5/SCL digital_io[27]/analog_io[16] *****************************************************************************/ @@ -328,26 +329,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash s25fl256s #(.mem_file_name(`TB_HEX), - .otp_file_name("none"), + .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs @@ -362,11 +363,24 @@ ); + wire spiram_csb = io_out[31]; + + is62wvs1288 #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); //----------------------------------------------- // WS281X BFM integration //---------------------------------------------- -assign ws281x_port[0] = io_out[3]; +assign ws281x_port[0] = io_out[8]; bfm_ws281x #( .PORT_ID(0), @@ -380,7 +394,7 @@ //----------------------------------------------- // WS281X BFM integration //---------------------------------------------- -assign ws281x_port[1] = io_out[4]; +assign ws281x_port[1] = io_out[9]; bfm_ws281x #( .PORT_ID(1), @@ -394,7 +408,7 @@ //----------------------------------------------- // WS281X BFM integration //---------------------------------------------- -assign ws281x_port[2] = io_out[8]; +assign ws281x_port[2] = io_out[13]; bfm_ws281x #( .PORT_ID(2), @@ -408,7 +422,7 @@ //----------------------------------------------- // WS281X BFM integration //---------------------------------------------- -assign ws281x_port[3] = io_out[12]; +assign ws281x_port[3] = io_out[17]; bfm_ws281x #( .PORT_ID(3),
diff --git a/verilog/dv/c_func/inc/ext_reg_map.h b/verilog/dv/c_func/inc/ext_reg_map.h index cdb04f3..c5a46c0 100644 --- a/verilog/dv/c_func/inc/ext_reg_map.h +++ b/verilog/dv/c_func/inc/ext_reg_map.h
@@ -11,54 +11,53 @@ #define reg_glbl_intr_msk (*(volatile uint32_t*)0x3002000C) // reg_3 - Global Interrupt Mask #define reg_glbl_intr (*(volatile uint32_t*)0x30020010) // reg_4 - Global Interrupt #define reg_glbl_multi_func (*(volatile uint32_t*)0x30020014) // reg_5 - GPIO Multi Function -#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x30020018) // reg_6 - Soft Register-0 -#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x3002001C) // reg_7 - Sof Register-1 -#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x30020020) // reg_8 - Sof Register-2 -#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x30020024) // reg_9 - Sof Register-3 -#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x30020028) // reg_10 - Sof Register-4 -#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x3002002C) // reg_11 - Sof Register-5 +#define reg_glbl_clk_ctrl (*(volatile uint32_t*)0x30020018) // reg_6 - RTC/USB Clock control +#define reg_glbl_pad_strap (*(volatile uint32_t*)0x30020030) // reg_6 - RTC/USB Clock control +#define reg_glbl_strap_sticky (*(volatile uint32_t*)0x30020034) // reg_6 - RTC/USB Clock control +#define reg_glbl_system_strap (*(volatile uint32_t*)0x30020038) // reg_6 - RTC/USB Clock control +#define reg_glbl_mail_box (*(volatile uint32_t*)0x3002003C) // reg_15 - Mail Box -#define reg_gpio_dsel (*(volatile uint32_t*)0x30020040) // reg_0 - GPIO Direction Select -#define reg_gpio_type (*(volatile uint32_t*)0x30020044) // reg_1 - GPIO TYPE - Static/Waveform -#define reg_gpio_idata (*(volatile uint32_t*)0x30020048) // reg_2 - GPIO Data In -#define reg_gpio_odata (*(volatile uint32_t*)0x3002004C) // reg_3 - GPIO Data Out -#define reg_gpio_intr_stat (*(volatile uint32_t*)0x30020050) // reg_4 - GPIO Interrupt status -#define reg_gpio_intr_clr (*(volatile uint32_t*)0x30020050) // reg_5 - GPIO Interrupt Clear -#define reg_gpio_intr_set (*(volatile uint32_t*)0x30020054) // reg_6 - GPIO Interrupt Set -#define reg_gpio_intr_mask (*(volatile uint32_t*)0x30020058) // reg_7 - GPIO Interrupt Mask -#define reg_gpio_pos_intr (*(volatile uint32_t*)0x3002005C) // reg_8 - GPIO Posedge Interrupt -#define reg_gpio_neg_intr (*(volatile uint32_t*)0x30020060) // reg_9 - GPIO Neg Interrupt +#define reg_gpio_dsel (*(volatile uint32_t*)0x30020080) // reg_0 - GPIO Direction Select +#define reg_gpio_type (*(volatile uint32_t*)0x30020084) // reg_1 - GPIO TYPE - Static/Waveform +#define reg_gpio_idata (*(volatile uint32_t*)0x30020088) // reg_2 - GPIO Data In +#define reg_gpio_odata (*(volatile uint32_t*)0x3002008C) // reg_3 - GPIO Data Out +#define reg_gpio_intr_stat (*(volatile uint32_t*)0x30020090) // reg_4 - GPIO Interrupt status +#define reg_gpio_intr_clr (*(volatile uint32_t*)0x30020090) // reg_5 - GPIO Interrupt Clear +#define reg_gpio_intr_set (*(volatile uint32_t*)0x30020094) // reg_6 - GPIO Interrupt Set +#define reg_gpio_intr_mask (*(volatile uint32_t*)0x30020098) // reg_7 - GPIO Interrupt Mask +#define reg_gpio_pos_intr (*(volatile uint32_t*)0x3002009C) // reg_8 - GPIO Posedge Interrupt +#define reg_gpio_neg_intr (*(volatile uint32_t*)0x300200A0) // reg_9 - GPIO Neg Interrupt -#define reg_pinmux_glbl_cfg (*(volatile uint32_t*)0x30020080) // reg_0 - PWM Reg-0 -#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x30020084) // reg_1 - PWM Reg-0 -#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x30020088) // reg_2 - PWM Reg-1 -#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x3002008C) // reg_3 - PWM Reg-2 -#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x30020090) // reg_4 - PWM Reg-3 -#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x30020094) // reg_5 - PWM Reg-4 -#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x30020098) // reg_6 - PWM Reg-5 +#define reg_pwm_glbl_cfg (*(volatile uint32_t*)0x30020100) // reg_0 - PWM Reg-0 +#define reg_pwm_cfg_pwm0 (*(volatile uint32_t*)0x30020104) // reg_1 - PWM Reg-0 +#define reg_pwm_cfg_pwm1 (*(volatile uint32_t*)0x30020108) // reg_2 - PWM Reg-1 +#define reg_pwm_cfg_pwm2 (*(volatile uint32_t*)0x3002010C) // reg_3 - PWM Reg-2 +#define reg_pwm_cfg_pwm3 (*(volatile uint32_t*)0x30020110) // reg_4 - PWM Reg-3 +#define reg_pwm_cfg_pwm4 (*(volatile uint32_t*)0x30020114) // reg_5 - PWM Reg-4 +#define reg_pwm_cfg_pwm5 (*(volatile uint32_t*)0x30020118) // reg_6 - PWM Reg-5 -#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x300200C0) // reg_0 - Global config -#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x300200C4) // reg_1 - Timer-0 -#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x300200C8) // reg_2 - Timer-1 -#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x300200CC) // reg_3 - Timer-2 +#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x30020180) // reg_0 - Global config +#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x30020184) // reg_1 - Timer-0 +#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x30020188) // reg_2 - Timer-1 +#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x3002018C) // reg_3 - Timer-2 -#define reg_sema_lock0 (*(volatile uint32_t*)0x30020100) // reg_0 - Hardware Lock-0 -#define reg_sema_lock1 (*(volatile uint32_t*)0x30020104) // reg_1 - Hardware Lock-1 -#define reg_sema_lock2 (*(volatile uint32_t*)0x30020108) // reg_2 - Hardware Lock-2 -#define reg_sema_lock3 (*(volatile uint32_t*)0x3002010C) // reg_3 - Hardware Lock-3 -#define reg_sema_lock4 (*(volatile uint32_t*)0x30020110) // reg_4 - Hardware Lock-4 -#define reg_sema_lock5 (*(volatile uint32_t*)0x30020114) // reg_5 - Hardware Lock-5 -#define reg_sema_lock6 (*(volatile uint32_t*)0x30020118) // reg_6 - Hardware Lock-6 -#define reg_sema_lock7 (*(volatile uint32_t*)0x3002011C) // reg_7 - Hardware Lock-7 -#define reg_sema_lock8 (*(volatile uint32_t*)0x30020120) // reg_8 - Hardware Lock-8 -#define reg_sema_lock9 (*(volatile uint32_t*)0x30020124) // reg_9 - Hardware Lock-9 -#define reg_sema_lock10 (*(volatile uint32_t*)0x30020128) // reg_10 - Hardware Lock-10 -#define reg_sema_lock11 (*(volatile uint32_t*)0x3002012C) // reg_11 - Hardware Lock-11 -#define reg_sema_lock12 (*(volatile uint32_t*)0x30020130) // reg_12 - Hardware Lock-12 -#define reg_sema_lock13 (*(volatile uint32_t*)0x30020134) // reg_13 - Hardware Lock-13 -#define reg_sema_lock14 (*(volatile uint32_t*)0x30020138) // reg_14 - Hardware Lock-14 -#define reg_sema_lock_cfg (*(volatile uint32_t*)0x3002013C) // reg_15 - Hardware Lock config -#define reg_sema_lock_stat (*(volatile uint32_t*)0x3002013C) // reg_15 - Hardware Lock Status +#define reg_sema_lock0 (*(volatile uint32_t*)0x30020200) // reg_0 - Hardware Lock-0 +#define reg_sema_lock1 (*(volatile uint32_t*)0x30020204) // reg_1 - Hardware Lock-1 +#define reg_sema_lock2 (*(volatile uint32_t*)0x30020208) // reg_2 - Hardware Lock-2 +#define reg_sema_lock3 (*(volatile uint32_t*)0x3002020C) // reg_3 - Hardware Lock-3 +#define reg_sema_lock4 (*(volatile uint32_t*)0x30020210) // reg_4 - Hardware Lock-4 +#define reg_sema_lock5 (*(volatile uint32_t*)0x30020214) // reg_5 - Hardware Lock-5 +#define reg_sema_lock6 (*(volatile uint32_t*)0x30020218) // reg_6 - Hardware Lock-6 +#define reg_sema_lock7 (*(volatile uint32_t*)0x3002021C) // reg_7 - Hardware Lock-7 +#define reg_sema_lock8 (*(volatile uint32_t*)0x30020220) // reg_8 - Hardware Lock-8 +#define reg_sema_lock9 (*(volatile uint32_t*)0x30020224) // reg_9 - Hardware Lock-9 +#define reg_sema_lock10 (*(volatile uint32_t*)0x30020228) // reg_10 - Hardware Lock-10 +#define reg_sema_lock11 (*(volatile uint32_t*)0x3002022C) // reg_11 - Hardware Lock-11 +#define reg_sema_lock12 (*(volatile uint32_t*)0x30020230) // reg_12 - Hardware Lock-12 +#define reg_sema_lock13 (*(volatile uint32_t*)0x30020234) // reg_13 - Hardware Lock-13 +#define reg_sema_lock14 (*(volatile uint32_t*)0x30020238) // reg_14 - Hardware Lock-14 +#define reg_sema_lock_cfg (*(volatile uint32_t*)0x3002023C) // reg_15 - Hardware Lock config +#define reg_sema_lock_stat (*(volatile uint32_t*)0x3002023C) // reg_15 - Hardware Lock Status #define reg_uart0_ctrl (*(volatile uint32_t*)0x30010000) // Reg-0 @@ -81,3 +80,6 @@ #define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x3001011C) // Reg-7 #define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x30010120) // Reg-8 + + +#define reg_mprj_wbhost_ctrl (*(volatile uint32_t*)0x30080000)
diff --git a/verilog/dv/c_func/inc/int_reg_map.h b/verilog/dv/c_func/inc/int_reg_map.h index 669499d..3e38aed 100644 --- a/verilog/dv/c_func/inc/int_reg_map.h +++ b/verilog/dv/c_func/inc/int_reg_map.h
@@ -10,55 +10,62 @@ #define reg_glbl_cfg1 (*(volatile uint32_t*)0x10020008) // reg_2 - Global Config-1 #define reg_glbl_intr_msk (*(volatile uint32_t*)0x1002000C) // reg_3 - Global Interrupt Mask #define reg_glbl_intr (*(volatile uint32_t*)0x10020010) // reg_4 - Global Interrupt -#define reg_glbl_multi_func (*(volatile uint32_t*)0x10020014) // reg_5 - GPIO Multi Function -#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x10020018) // reg_6 - Soft Register-0 -#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x1002001C) // reg_7 - Sof Register-1 -#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x10020020) // reg_8 - Sof Register-2 -#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x10020024) // reg_9 - Sof Register-3 -#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x10020028) // reg_10 - Sof Register-4 -#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x1002002C) // reg_11 - Sof Register-5 +#define reg_glbl_multi_func (*(volatile uint32_t*)0x10020014) // reg_5 - GPIO Multi Function +#define reg_glbl_clk_ctrl (*(volatile uint32_t*)0x10020018) // reg_6 - RTC/USB Clock control +#define reg_glbl_pad_strap (*(volatile uint32_t*)0x10020030) // reg_6 - RTC/USB Clock control +#define reg_glbl_strap_sticky (*(volatile uint32_t*)0x10020034) // reg_6 - RTC/USB Clock control +#define reg_glbl_system_strap (*(volatile uint32_t*)0x10020038) // reg_6 - RTC/USB Clock control +#define reg_glbl_mail_box (*(volatile uint32_t*)0x1002003C) // reg_15 - Mail Box +#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x10020040) // reg_16 - Soft Register-0 +#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x10020044) // reg_17 - Soft Register-1 +#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x10020048) // reg_18 - Soft Register-2 +#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x1002004C) // reg_19 - Soft Register-3 +#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x10020050) // reg_20 - Soft Register-4 +#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x10020054) // reg_21 - Soft Register-5 +#define reg_glbl_soft_reg_6 (*(volatile uint32_t*)0x10020058) // reg_22 - Soft Register-6 +#define reg_glbl_soft_reg_7 (*(volatile uint32_t*)0x1002005C) // reg_23 - Soft Register-7 -#define reg_gpio_dsel (*(volatile uint32_t*)0x10020040) // reg_0 - GPIO Direction Select -#define reg_gpio_type (*(volatile uint32_t*)0x10020044) // reg_1 - GPIO TYPE - Static/Waveform -#define reg_gpio_idata (*(volatile uint32_t*)0x10020048) // reg_2 - GPIO Data In -#define reg_gpio_odata (*(volatile uint32_t*)0x1002004C) // reg_3 - GPIO Data Out -#define reg_gpio_intr_stat (*(volatile uint32_t*)0x10020050) // reg_4 - GPIO Interrupt status -#define reg_gpio_intr_clr (*(volatile uint32_t*)0x10020050) // reg_5 - GPIO Interrupt Clear -#define reg_gpio_intr_set (*(volatile uint32_t*)0x10020054) // reg_6 - GPIO Interrupt Set -#define reg_gpio_intr_mask (*(volatile uint32_t*)0x10020058) // reg_7 - GPIO Interrupt Mask -#define reg_gpio_pos_intr (*(volatile uint32_t*)0x1002005C) // reg_8 - GPIO Posedge Interrupt -#define reg_gpio_neg_intr (*(volatile uint32_t*)0x10020060) // reg_9 - GPIO Neg Interrupt +#define reg_gpio_dsel (*(volatile uint32_t*)0x10020080) // reg_0 - GPIO Direction Select +#define reg_gpio_type (*(volatile uint32_t*)0x10020084) // reg_1 - GPIO TYPE - Static/Waveform +#define reg_gpio_idata (*(volatile uint32_t*)0x10020088) // reg_2 - GPIO Data In +#define reg_gpio_odata (*(volatile uint32_t*)0x1002008C) // reg_3 - GPIO Data Out +#define reg_gpio_intr_stat (*(volatile uint32_t*)0x10020090) // reg_4 - GPIO Interrupt status +#define reg_gpio_intr_clr (*(volatile uint32_t*)0x10020090) // reg_5 - GPIO Interrupt Clear +#define reg_gpio_intr_set (*(volatile uint32_t*)0x10020094) // reg_6 - GPIO Interrupt Set +#define reg_gpio_intr_mask (*(volatile uint32_t*)0x10020098) // reg_7 - GPIO Interrupt Mask +#define reg_gpio_pos_intr (*(volatile uint32_t*)0x1002009C) // reg_8 - GPIO Posedge Interrupt +#define reg_gpio_neg_intr (*(volatile uint32_t*)0x100200A0) // reg_9 - GPIO Neg Interrupt -#define reg_pinmux_glbl_cfg (*(volatile uint32_t*)0x10020080) // reg_0 - PWM Reg-0 -#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x10020084) // reg_1 - PWM Reg-0 -#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x10020088) // reg_2 - PWM Reg-1 -#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x1002008C) // reg_3 - PWM Reg-2 -#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x10020090) // reg_4 - PWM Reg-3 -#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x10020094) // reg_5 - PWM Reg-4 -#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x10020098) // reg_6 - PWM Reg-5 +#define reg_pwm_glbl_cfg (*(volatile uint32_t*)0x10020100) // reg_0 - PWM Reg-0 +#define reg_pwm_cfg_pwm0 (*(volatile uint32_t*)0x10020104) // reg_1 - PWM Reg-0 +#define reg_pwm_cfg_pwm1 (*(volatile uint32_t*)0x10020108) // reg_2 - PWM Reg-1 +#define reg_pwm_cfg_pwm2 (*(volatile uint32_t*)0x1002011C) // reg_3 - PWM Reg-2 +#define reg_pwm_cfg_pwm3 (*(volatile uint32_t*)0x10020110) // reg_4 - PWM Reg-3 +#define reg_pwm_cfg_pwm4 (*(volatile uint32_t*)0x10020114) // reg_5 - PWM Reg-4 +#define reg_pwm_cfg_pwm5 (*(volatile uint32_t*)0x10020118) // reg_6 - PWM Reg-5 -#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x100200C0) // reg_0 - Global config -#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x100200C4) // reg_1 - Timer-0 -#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x100200C8) // reg_2 - Timer-1 -#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x100200CC) // reg_3 - Timer-2 +#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x10020180) // reg_0 - Global config +#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x10020184) // reg_1 - Timer-0 +#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x10020188) // reg_2 - Timer-1 +#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x1002018C) // reg_3 - Timer-2 -#define reg_sema_lock0 (*(volatile uint32_t*)0x10020100) // reg_0 - Hardware Lock-0 -#define reg_sema_lock1 (*(volatile uint32_t*)0x10020104) // reg_1 - Hardware Lock-1 -#define reg_sema_lock2 (*(volatile uint32_t*)0x10020108) // reg_2 - Hardware Lock-2 -#define reg_sema_lock3 (*(volatile uint32_t*)0x1002010C) // reg_3 - Hardware Lock-3 -#define reg_sema_lock4 (*(volatile uint32_t*)0x10020110) // reg_4 - Hardware Lock-4 -#define reg_sema_lock5 (*(volatile uint32_t*)0x10020114) // reg_5 - Hardware Lock-5 -#define reg_sema_lock6 (*(volatile uint32_t*)0x10020118) // reg_6 - Hardware Lock-6 -#define reg_sema_lock7 (*(volatile uint32_t*)0x1002011C) // reg_7 - Hardware Lock-7 -#define reg_sema_lock8 (*(volatile uint32_t*)0x10020120) // reg_8 - Hardware Lock-8 -#define reg_sema_lock9 (*(volatile uint32_t*)0x10020124) // reg_9 - Hardware Lock-9 -#define reg_sema_lock10 (*(volatile uint32_t*)0x10020128) // reg_10 - Hardware Lock-10 -#define reg_sema_lock11 (*(volatile uint32_t*)0x1002012C) // reg_11 - Hardware Lock-11 -#define reg_sema_lock12 (*(volatile uint32_t*)0x10020130) // reg_12 - Hardware Lock-12 -#define reg_sema_lock13 (*(volatile uint32_t*)0x10020134) // reg_13 - Hardware Lock-13 -#define reg_sema_lock14 (*(volatile uint32_t*)0x10020138) // reg_14 - Hardware Lock-14 -#define reg_sema_lock_cfg (*(volatile uint32_t*)0x1002013C) // reg_15 - Hardware Lock config -#define reg_sema_lock_stat (*(volatile uint32_t*)0x1002013C) // reg_15 - Hardware Lock Status +#define reg_sema_lock0 (*(volatile uint32_t*)0x10020200) // reg_0 - Hardware Lock-0 +#define reg_sema_lock1 (*(volatile uint32_t*)0x10020204) // reg_1 - Hardware Lock-1 +#define reg_sema_lock2 (*(volatile uint32_t*)0x10020208) // reg_2 - Hardware Lock-2 +#define reg_sema_lock3 (*(volatile uint32_t*)0x1002020C) // reg_3 - Hardware Lock-3 +#define reg_sema_lock4 (*(volatile uint32_t*)0x10020210) // reg_4 - Hardware Lock-4 +#define reg_sema_lock5 (*(volatile uint32_t*)0x10020214) // reg_5 - Hardware Lock-5 +#define reg_sema_lock6 (*(volatile uint32_t*)0x10020218) // reg_6 - Hardware Lock-6 +#define reg_sema_lock7 (*(volatile uint32_t*)0x1002021C) // reg_7 - Hardware Lock-7 +#define reg_sema_lock8 (*(volatile uint32_t*)0x10020220) // reg_8 - Hardware Lock-8 +#define reg_sema_lock9 (*(volatile uint32_t*)0x10020224) // reg_9 - Hardware Lock-9 +#define reg_sema_lock10 (*(volatile uint32_t*)0x10020228) // reg_10 - Hardware Lock-10 +#define reg_sema_lock11 (*(volatile uint32_t*)0x1002022C) // reg_11 - Hardware Lock-11 +#define reg_sema_lock12 (*(volatile uint32_t*)0x10020230) // reg_12 - Hardware Lock-12 +#define reg_sema_lock13 (*(volatile uint32_t*)0x10020234) // reg_13 - Hardware Lock-13 +#define reg_sema_lock14 (*(volatile uint32_t*)0x10020238) // reg_14 - Hardware Lock-14 +#define reg_sema_lock_cfg (*(volatile uint32_t*)0x1002023C) // reg_15 - Hardware Lock config +#define reg_sema_lock_stat (*(volatile uint32_t*)0x1002023C) // reg_15 - Hardware Lock Status #define reg_uart0_ctrl (*(volatile uint32_t*)0x10010000) // Reg-0
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board index 5b5dd05..ec9ef12 160000 --- a/verilog/dv/common/riscduino_board +++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@ -Subproject commit 5b5dd057677b00948b02288291ad2141f0543108 +Subproject commit ec9ef12933c2435d28bb91d4f653bfc99377f151
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index 2601fc5..f9bb9f4 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -113,6 +113,7 @@ # RTL/GL/GL_SDF SIM?=RTL DUMP?=OFF +RISC_CORE?=0 .SUFFIXES: @@ -164,11 +165,11 @@ ## RTL ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif @@ -177,11 +178,11 @@ ##GL ifeq ($(SIM),GL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DGL -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -Ttyp -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< endif @@ -205,7 +206,7 @@ endif %.vcd: %.vvp - vvp $< + vvp $< +risc_core_id=$(RISC_CORE) # twinwave: RTL-%.vcd GL-%.vcd # twinwave RTL-$@ * + GL-$@ * @@ -229,7 +230,7 @@ # ---- Clean ---- clean: - \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe + \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe *.dump .PHONY: clean hex all
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index 8ff48ff..d7c3275 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -18,155 +18,11 @@ // This include is relative to $CARAVEL_PATH (see Makefile) #include <defs.h> #include <stub.c> -#include "../c_func/inc/user_reg_map.h" - -// User Project Slaves (0x3000_0000) - -#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30080000) - -#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000) -#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004) -#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008) -#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C) -#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010) -#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014) -#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018) -#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C) -#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020) - -#define GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP 0x1C00 -/* - RiscV Hello World test. - - Wake up the Risc V - - Boot from SPI Flash - - Riscv Write Hello World to SDRAM, - - External Wishbone read back validation the data -*/ -int i = 0; -int clk = 0; void main() { - int bFail = 0; - /* - IO Control Registers - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | - Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - */ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spi_enable = 1; - reg_wb_enable = 1; - // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] - - // Flag start of the test - reg_mprj_datal = 0xAB600000; - - //----------------------------------------------------- - // Start of User Functionality and take over the GPIO Pins - // ------------------------------------------------------ - // User block decide on the GPIO function - reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - //reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - reg_la0_data = 0x001; // Remove Soft Reset - reg_la0_data = 0x000; - reg_la0_data = 0x001; // Remove Soft Reset - - - // Remove Wishbone Reset - reg_mprj_wbhost_reg0 = 0x1; - - - // Remove All Reset - reg_glbl_cfg0 = 0x11F; - - // Enable UART Multi Functional Ports - - reg_glbl_multi_func = 0x100; - - // configure the user uart - reg_mprj_uart_reg0 = 0x7; }
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v index e9865d9..594f534 100644 --- a/verilog/dv/risc_boot/risc_boot_tb.v +++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -72,6 +72,7 @@ `timescale 1 ns / 1 ps `include "uart_agent.v" +`include "user_params.svh" module risc_boot_tb; reg clock; @@ -103,6 +104,7 @@ reg [7:0] uart_write_data [0:39]; reg uart_fifo_enable ; // fifo mode disable reg test_fail ; + integer d_risc_id; integer i,j; //--------------------------------- @@ -130,9 +132,9 @@ $dumpfile("simx.vcd"); $dumpvars(1,risc_boot_tb); //$dumpvars(1,risc_boot_tb.u_spi_flash_256mb); - //$dumpvars(2,risc_boot_tb.uut); - $dumpvars(1,risc_boot_tb.uut.mprj); - $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host); + //$dumpvars(2,risc_boot_tb.u_top); + $dumpvars(1,risc_boot_tb.u_top.mprj); + $dumpvars(0,risc_boot_tb.u_top.mprj.u_wb_host); //$dumpvars(0,risc_boot_tb.tb_uart); //$dumpvars(0,risc_boot_tb.u_user_spiflash); $display("Waveform Dump started"); @@ -160,6 +162,11 @@ initial begin + + $value$plusargs("risc_core_id=%d", d_risc_id); + + init(); + uart_data_bit = 2'b11; uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; uart_stick_parity = 0; // 1: force even parity @@ -172,15 +179,16 @@ #200; // Wait for reset removal // Wait for Managment core to boot up - wait(checkbits == 16'h AB60); - $display("Monitor: Test User Risc Boot Started"); // Wait for user risc core to boot up - repeat (50000) @(posedge clock); tb_uart.uart_init; tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); + + wait_riscv_boot(); + repeat (50000) @(posedge clock); + for (i=0; i<40; i=i+1) uart_write_data[i] = $random; @@ -238,10 +246,8 @@ initial begin - RSTB <= 1'b0; CSB <= 1'b1; // Force CSB high #2000; - RSTB <= 1'b1; // Release reset #170000; CSB = 1'b0; // CSB can be released end @@ -276,7 +282,7 @@ wire USER_VDD1V8 = power4; wire VSS = 1'b0; - caravel uut ( + caravel u_top ( .vddio (VDD3V3), .vssio (VSS), .vdda (VDD3V3), @@ -316,8 +322,8 @@ // Connect Quad Flash to for usr Risc Core //----------------------------------------- - wire user_flash_clk = mprj_io[24]; - wire user_flash_csb = mprj_io[25]; + wire user_flash_clk = mprj_io[28]; + wire user_flash_csb = mprj_io[29]; //tri user_flash_io0 = mprj_io[26]; //tri user_flash_io1 = mprj_io[27]; //tri user_flash_io2 = mprj_io[28]; @@ -330,13 +336,13 @@ .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs - .SI (mprj_io[29]), - .SO (mprj_io[30]), + .SI (mprj_io[33]), + .SO (mprj_io[34]), // Controls .SCK (user_flash_clk), .CSNeg (user_flash_csb), - .WPNeg (mprj_io[31]), - .HOLDNeg (mprj_io[32]), + .WPNeg (mprj_io[35]), + .HOLDNeg (mprj_io[36]), .RSTNeg (RSTB) ); @@ -346,8 +352,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = mprj_io[2]; -assign mprj_io[1] = uart_rxd ; +assign uart_txd = mprj_io[7]; +assign mprj_io[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -361,6 +367,7 @@ initial begin end `endif +`include "caravel_task.sv" endmodule // SSFLASH has 1ps/1ps time scale `include "s25fl256s.sv"
diff --git a/verilog/dv/risc_boot/user_uart.c b/verilog/dv/risc_boot/user_uart.c index 29805f7..b19a157 100644 --- a/verilog/dv/risc_boot/user_uart.c +++ b/verilog/dv/risc_boot/user_uart.c
@@ -16,42 +16,33 @@ // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> // ////////////////////////////////////////////////////////////////////////// #define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long +#include "../c_func/inc/int_reg_map.h" +#include "common_misc.h" +#include "common_bthread.h" -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C) -#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010000) -#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010004) -#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010008) -#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001000C) -#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010010) -#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010014) -#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010018) -#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001001C) -#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010020) int main() { + reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART + reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0 + reg_glbl_multi_func |=0x100; // Enable UART Multi func + reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1} + + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + + reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main + while(1) { // Check UART RX fifo has data, if available loop back the data - if(reg_mprj_uart_reg8 != 0) { - reg_mprj_uart_reg5 = reg_mprj_uart_reg6; + // Also check txfifo is not full + if((reg_uart0_rxfifo_stat != 0) && ((reg_uart0_status & 0x1) != 0x1)) { + reg_uart0_txdata = reg_uart0_rxdata; } }
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile index 3ec839e..12331ba 100644 --- a/verilog/dv/uart_master/Makefile +++ b/verilog/dv/uart_master/Makefile
@@ -155,12 +155,14 @@ ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< + -o $@ $< else iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< + -o $@ $< endif endif
diff --git a/verilog/dv/uart_master/uart_master.c b/verilog/dv/uart_master/uart_master.c index 46d6e97..e1a4bf0 100644 --- a/verilog/dv/uart_master/uart_master.c +++ b/verilog/dv/uart_master/uart_master.c
@@ -18,7 +18,7 @@ // This include is relative to $CARAVEL_PATH (see Makefile) #include <defs.h> #include <stub.c> -#include "../c_func/inc/user_reg_map.h" +#include "../c_func/inc/ext_reg_map.h" // User Project Slaves (0x3000_0000) @@ -40,7 +40,7 @@ void main() { - int bFail = 0; + //int bFail = 0; /* IO Control Registers | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | @@ -62,8 +62,8 @@ /* Set up the housekeeping SPI to be connected internally so */ /* that external pin changes don't affect it. */ - reg_spi_enable = 1; - reg_wb_enable = 1; + //reg_spi_enable = 1; + //reg_wb_enable = 1; // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, // connect to housekeeping SPI @@ -71,26 +71,26 @@ // so that the CSB line is not left floating. This allows // all of the GPIO pins to be used for user functions. - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + //reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); + // /* Apply configuration */ + //reg_mprj_xfer = 1; + //while (reg_mprj_xfer == 1); reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] @@ -99,50 +99,53 @@ //----------------------------------------------------- // Start of User Functionality and take over the GPIO Pins - // ------------------------------------------------------ + // -------------------------------------------------------------------- // User block decide on the GPIO function - reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + // io[6] to 37 are set to default bio-direction using user_define.h file + //--------------------------------------------------------------------- - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); + //reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + + // /* Apply configuration */ + //reg_mprj_xfer = 1; + //while (reg_mprj_xfer == 1); reg_la0_data = 0x000; //reg_la0_data = 0x000;
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v index f49daab..ea30b91 100644 --- a/verilog/dv/uart_master/uart_master_tb.v +++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -18,7 +18,9 @@ `timescale 1 ns / 1 ps `include "uart_agent.v" -module uart_master_tb; +`define TB_HEX "uart_master.hex" +`define TB_TOP uart_master_tb +module `TB_TOP; reg clock; reg RSTB; reg CSB; @@ -70,13 +72,11 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(1, uart_master_tb); - $dumpvars(1, uart_master_tb.uut); - $dumpvars(1, uart_master_tb.uut.mprj); - $dumpvars(1, uart_master_tb.uut.mprj.u_wb_host); - $dumpvars(1, uart_master_tb.uut.mprj.u_wb_host.u_uart2wb); - $dumpvars(1, uart_master_tb.tb_master_uart); - //$dumpvars(2, uart_master_tb.uut.mprj.u_pinmux); + $dumpvars(2, `TB_TOP); + $dumpvars(0, `TB_TOP.tb_master_uart); + $dumpvars(0, `TB_TOP.uut.mprj.u_wb_host.u_uart2wb); + $dumpvars(1, `TB_TOP.tb_master_uart); + $dumpvars(0, `TB_TOP.uut.mprj.u_pinmux); end `endif @@ -84,7 +84,7 @@ // Repeat cycles of 1000 clock edges as needed to complete testbench repeat (400) begin - repeat (1000) @(posedge clock); + repeat (10000) @(posedge clock); // $display("+1000 cycles"); end $display("%c[1;31m",27); @@ -101,25 +101,26 @@ initial begin uart_data_bit = 2'b11; - uart_stop_bits = 1; // 0: 1 stop bit; 1: 2 stop bit; + uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; uart_stick_parity = 0; // 1: force even parity uart_parity_en = 0; // parity enable uart_even_odd_parity = 1; // 0: odd parity; 1: even parity uart_divisor = 15;// divided by n * 16 - uart_timeout = 600;// wait time limit + uart_timeout = 200;// wait time limit uart_fifo_enable = 0; // fifo mode disable tb_master_uart.debug_mode = 0; // disable debug display #200; // Wait for reset removal - wait(checkbits == 16'h AB60); - $display("Monitor: UART Master Test Started"); + // wait(checkbits == 16'h AB60); + // $display("Monitor: UART Master Test Started"); - repeat (50000) @(posedge clock); + repeat (10000) @(posedge clock); tb_master_uart.uart_init; tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); //$write ("\n(%t)Response:\n",$time); + // Wait for Initial Command Format from the uart master flag = 0; while(flag == 0) begin @@ -174,11 +175,11 @@ initial begin RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high + //CSB <= 1'b1; // Force CSB high #2000; RSTB <= 1'b1; // Release reset #170000; - CSB = 1'b0; // CSB can be released + //CSB = 1'b0; // CSB can be released end initial begin // Power-up sequence @@ -262,8 +263,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = mprj_io[35]; -assign mprj_io[34] = uart_rxd ; +assign uart_txd = mprj_io[23]; +assign mprj_io[22] = uart_rxd ; uart_agent tb_master_uart( .mclk (clock ), @@ -276,6 +277,4 @@ endmodule -// SSFLASH has 1ps/1ps time scale -`include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 3a0b083..3317eab 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -71,16 +71,20 @@ `default_nettype wire -`timescale 1 ns/10 ps +`timescale 1 ns/1 ps `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "user_params.svh" module user_basic_tb; parameter CLK1_PERIOD = 10; -parameter CLK2_PERIOD = 2; +parameter CLK2_PERIOD = 2.5; +parameter IPLL_PERIOD = 5.008; +parameter XTAL_PERIOD = 6; reg clock ; reg clock2 ; +reg xtal_clk ; reg wb_rst_i ; reg power1, power2; reg power3, power4; @@ -104,6 +108,7 @@ wire [37:0] mprj_io ; wire [7:0] mprj_io_0 ; reg test_fail ; +reg [31:0] write_data ; reg [31:0] read_data ; //---------------------------------- // Uart Configuration @@ -125,6 +130,81 @@ wire clock_mon; integer test_step; +reg [15:0] strap_in; +wire [31:0] strap_sticky; +reg [7:0] test_id; + +assign io_in = {26'h0,xtal_clk,11'h0}; + +wire [14:0] pstrap_select; + +assign pstrap_select = (strap_in[15] == 1'b1) ? PSTRAP_DEFAULT_VALUE : strap_in[14:0]; + + +assign strap_sticky = { + 2'b0 , // bit[31:30] - reserved + pstrap_select[12:11] , // bit[29:28] - cfg_cska_qspi_co Skew selection + pstrap_select[12:11] , // bit[27:26] - cfg_cska_pinmux Skew selection + pstrap_select[12:11] , // bit[25:24] - cfg_cska_uart Skew selection + pstrap_select[12:11] , // bit[23:22] - cfg_cska_qspi Skew selection + pstrap_select[12:11] , // bit[21:20] - cfg_cska_riscv Skew selection + pstrap_select[12:11] , // bit[19:18] - cfg_cska_wh Skew selection + pstrap_select[12:11] , // bit[17:16] - cfg_cska_wi Skew selection + 1'b0 , // bit[15] - Soft Reboot Request - Need to double sync to local clock + pstrap_select[10] , // bit[14] - Riscv SRAM clock edge selection + pstrap_select[9] , // bit[13] - Riscv Cache Bypass + pstrap_select[8] , // bit[12] - Riscv Reset control + pstrap_select[7:6] , // bit[11:10] - QSPI FLASH Mode Selection CS#0 + pstrap_select[5] , // bit[9] - QSPI SRAM Mode Selection CS#2 + pstrap_select[4] , // bit[8] - uart master config control + pstrap_select[3:2] , // bit[7:6] - riscv clock div + pstrap_select[1:0] , // bit[5:4] - riscv clock source sel + pstrap_select[3:2] , // bit[3:2] - wbs clock division + pstrap_select[1:0] // bit[1:0] - wbs clock source sel + }; + + +reg [1:0] strap_skew; +wire [31:0] skew_config; + +assign skew_config[3:0] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[3:0] : + (strap_skew == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 : + (strap_skew == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4; + +assign skew_config[7:4] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[7:4] : + (strap_skew == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 : + (strap_skew == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4; + +assign skew_config[11:8] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[11:8] : + (strap_skew == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 : + (strap_skew == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4; + +assign skew_config[15:12] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[15:12] : + (strap_skew == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 : + (strap_skew == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4; + +assign skew_config[19:16] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[19:16] : + (strap_skew == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 : + (strap_skew == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4; + +assign skew_config[23:20] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[23:20] : + (strap_skew == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 : + (strap_skew == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4; + +assign skew_config[27:24] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[27:24] : + (strap_skew == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 : + (strap_skew == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4; + +assign skew_config[31:28] = 4'b0; + +//---------------------------------------------------------- +reg [3:0] cpu_clk_cfg,wbs_clk_cfg; +wire [7:0] clk_ctrl2 = {cpu_clk_cfg,wbs_clk_cfg}; + + + +//----------------------------------------------------------- + integer i,j; @@ -134,6 +214,7 @@ always #(CLK1_PERIOD/2) clock <= (clock === 1'b0); always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0); + always #(XTAL_PERIOD/2) xtal_clk <= (xtal_clk === 1'b0); initial begin test_step = 0; @@ -151,18 +232,20 @@ initial begin $dumpfile("simx.vcd"); $dumpvars(1, user_basic_tb); - //$dumpvars(1, user_basic_tb.u_top); + $dumpvars(1, user_basic_tb.u_top); //$dumpvars(0, user_basic_tb.u_top.u_pll); $dumpvars(0, user_basic_tb.u_top.u_wb_host); + //$dumpvars(0, user_basic_tb.u_top.u_intercon); //$dumpvars(1, user_basic_tb.u_top.u_intercon); - //$dumpvars(1, user_basic_tb.u_top.u_intercon); - //$dumpvars(1, user_basic_tb.u_top.u_pinmux); + $dumpvars(0, user_basic_tb.u_top.u_pinmux); end `endif initial begin + wb_rst_i <= 1'b0; + #1000; wb_rst_i <= 1'b1; - #100; + #1000; wb_rst_i <= 1'b0; // Release reset end @@ -177,118 +260,191 @@ repeat (2) @(posedge clock); test_fail=0; + fork - begin - // Default Value Check - // cfg_wb_clk_ctrl = cfg_clk_ctrl2[7:0]; - // cfg_rtc_clk_ctrl = cfg_clk_ctrl2[15:8]; - // cfg_cpu_clk_ctrl = cfg_clk_ctrl2[23:16]; - // cfg_usb_clk_ctrl = cfg_clk_ctrl2[31:24]; - - - $display("Step-1, CPU: CLOCK1, USB: CLOCK2,RTC: CLOCK2 *2, WBS:CLOCK1"); - test_step = 1; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h0,8'h0,8'h0}); - clock_monitor(CLK1_PERIOD,CLK1_PERIOD,CLK2_PERIOD*2,CLK1_PERIOD); - - $display("Step-2, CPU: CLOCK2, USB: CLOCK2/2, RTC: CLOCK2/(2+1), WBS:CLOCK2"); - test_step = 2; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h40,8'h60,8'h1,8'h40}); - clock_monitor(CLK2_PERIOD,2*CLK2_PERIOD,(3)*CLK2_PERIOD,CLK2_PERIOD); - - $display("Step-3, CPU: CLOCK1/2,USB: CLOCK2/(2+1), RTC: CLOCK2/(2+2), WBS:CLOCK1/2"); - test_step = 3; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h20,8'h61,8'h2,8'h20}); - clock_monitor(2*CLK1_PERIOD,(3)*CLK2_PERIOD,4*CLK2_PERIOD,2*CLK1_PERIOD); - - $display("Step-4, CPU: CLOCK1/3, USB: CLOCK2/(2+2), RTC: CLOCK2/(2+3), WBS:CLOCK1/3"); - test_step = 4; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h21,8'h62,8'h3,8'h21}); - clock_monitor(3*CLK1_PERIOD,4*CLK2_PERIOD,5*CLK2_PERIOD,3*CLK1_PERIOD); - - $display("Step-5, CPU: CLOCK1/4, USB: CLOCK2/(2+3), RTC: CLOCK2/(2+4), WBS:CLOCK1/4"); - test_step = 5; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h22,8'h63,8'h4,8'h22}); - clock_monitor(4*CLK1_PERIOD,5*CLK2_PERIOD,6*CLK2_PERIOD,4*CLK1_PERIOD); - - $display("Step-6, CPU: CLOCK1/(2+3),USB: CLOCK2/(2+4), RTC: CLOCK2/(2+5), WBS:CLOCK1/(2+3)"); - test_step = 6; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h23,8'h64,8'h5,8'h23}); - clock_monitor(5*CLK1_PERIOD,6*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD); - - $display("Step-7, CPU: CLOCK2/(2), USB: CLOCK2/(2+5), RTC: CLOCK2/(2+6), WBS:CLOCK2/(2)"); - test_step = 7; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h60,8'h65,8'h6,8'h60}); - clock_monitor(2*CLK2_PERIOD,7*CLK2_PERIOD,8*CLK2_PERIOD,2*CLK2_PERIOD); - - $display("Step-8, CPU: CLOCK2/3, USB: CLOCK2/(2+6), RTC: CLOCK2/(2+7), WBS:CLOCK2/3"); - test_step = 8; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h61,8'h66,8'h7,8'h61}); - clock_monitor(3*CLK2_PERIOD,8*CLK2_PERIOD,9*CLK2_PERIOD,3*CLK2_PERIOD); - - $display("Step-9, CPU: CLOCK2/4,USB: CLOCK2/(2+7), RTC: CLOCK2/(2+8), WBS:CLOCK2/4"); - test_step = 9; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h62,8'h67,8'h8,8'h62}); - clock_monitor(4*CLK2_PERIOD,9*CLK2_PERIOD,10*CLK2_PERIOD,4*CLK2_PERIOD); - - $display("Step-10, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+8), RTC: CLOCK2/(2+128), WBS:CLOCK1/(2+3)"); - test_step = 10; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h68,8'h80,8'h63}); - clock_monitor(5*CLK2_PERIOD,10*CLK2_PERIOD,130*CLK2_PERIOD,5*CLK2_PERIOD); - - $display("Step-11, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)"); - test_step = 10; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); - clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD); + begin + $display("##########################################################"); + $display("Step-1, Checking the Strap Loading"); + test_id = 1; + for(i = 0; i < 16; i = i+1) begin + strap_in = 0; + strap_in = 1 << i; + apply_strap(strap_in); + + //#7 - Check the strap reg value + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,strap_sticky); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SYSTEM_STRAP,read_data,strap_sticky); + test_step = 7; + end - `ifndef GL - $display("###################################################"); - $display("Monitor: Checking the PLL:"); - $display("###################################################"); - test_step = 11; - // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03 - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2}); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000}); - repeat (100) @(posedge clock); - pll_clock_monitor(5); + + if(test_fail == 1) begin + $display("ERROR: Step-1, Checking the Strap Loading - FAILED"); + end else begin + $display("STATUS: Step-1, Checking the Strap Loading - PASSED"); + end + $display("##########################################################"); + $display("Step-2, Checking the Clock Skew Configuration"); + test_id = 2; + for(i = 0; i < 4; i = i+1) begin + strap_in = 0; + strap_in[12:11] = i; + strap_skew = i; + apply_strap(strap_in); - test_step = 12; - // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); - repeat (100) @(posedge clock); - pll_clock_monitor(4); + //#7 - Check the strap reg value + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,strap_sticky); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SYSTEM_STRAP,read_data,strap_sticky); + wb_user_core_read_check(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL1,read_data,skew_config); + end + if(test_fail == 1) begin + $display("ERROR: Step-2, Checking the Clock Skew Configuration - FAILED"); + end else begin + $display("STATUS: Step-2, Checking the Clock Skew Configuration - PASSED"); + end + $display("##########################################################"); + $display("Step-3, Checking the riscv/wbs clock Selection though Strap"); + test_id = 3; + for(i = 0; i < 4; i = i+1) begin + for(j = 0; j < 4; j = j+1) begin + strap_in = 0; + strap_in[1:0] = i; + cpu_clk_cfg[1:0]=i; + wbs_clk_cfg[1:0]=i; + strap_in[3:2] = j; + cpu_clk_cfg[3:2]=j; + wbs_clk_cfg[3:2]=j; + strap_in[3:2] = j; + + apply_strap(strap_in); - $display("###################################################"); - $display("Monitor: Monitor Clock output:"); - $display("###################################################"); - $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)"); - test_step = 13; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); + //#7 - Check the strap reg value + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,strap_sticky); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SYSTEM_STRAP,read_data,strap_sticky); + wb_user_core_read_check(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,read_data,clk_ctrl2); + clock_monitor2(cpu_clk_cfg,wbs_clk_cfg); + end + end + if(test_fail == 1) begin + $display("ERROR: Step-3, Checking the riscv/wbs clock Selection though Strap - FAILED"); + end else begin + $display("STATUS: Step-3, Checking the riscv/wbs clock Selection though Strap - PASSED"); + end + $display("##########################################################"); - // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); - dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD); - `endif - - $display("###################################################"); - $display("Monitor: Checking the chip signature :"); - $display("###################################################"); - test_step = 14; - // Remove Wb/PinMux Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + $display("##########################################################"); + $display("Step-4, Checking the soft reboot sequence"); + test_id = 4; + for(i = 0; i < 31; i = i+1) begin + // #1 - Write Data to Sticky bit and Set Reboot Request + wait(u_top.s_reset_n == 1); // Wait for system reset removal + write_data = (1<< i) ; // bit[31] = 1 in soft reboot request + write_data = write_data + (1 << `STRAP_SOFT_REBOOT_REQ); // bit[STRAP_SOFT_REBOOT_REQ] = 1 in soft reboot request + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,write_data); - wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h2408_2022); - wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_1000); + // #3 - Wait for system reset removal + wait(u_top.s_reset_n == 1); // Wait for system reset removal + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,{1'b0,write_data[30:0]}); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SYSTEM_STRAP,read_data,write_data); + repeat (10) @(posedge clock); + + end + + if(test_fail == 1) begin + $display("ERROR: Step-4, Checking the soft reboot sequence - FAILED"); + end else begin + $display("STATUS: Step-4, Checking the soft reboot sequence - PASSED"); + end + $display("##########################################################"); + /**** + $display("Step-5, Checking the uart Master baud-16x clock is 9600* 16"); + test_id = 5; + + apply_strap(16'h10); // [4] - // uart master config control - constant value based on system clock selection + + uartm_clock_monitor(6510); // 1/(9600*16) = 6510 ns + + if(test_fail == 1) begin + $display("ERROR: Step-5, Checking the uart Master baud-16x clock - FAILED"); + end else begin + $display("STATUS: Step-5, Checking the uart Master baud-16x clock - PASSED"); + end + $display("##########################################################"); + ***/ + /*** + `ifndef GL + $display("###################################################"); + $display("Step-5,Monitor: Checking the PLL:"); + $display("###################################################"); + test_id = 5; + // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000}); + repeat (100) @(posedge clock); + pll_clock_monitor(5.101); + + test_step = 12; + // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); + repeat (100) @(posedge clock); + pll_clock_monitor(4.080); + + if(test_fail == 1) begin + $display("ERROR: Step-5, Checking the PLL - FAILED"); + end else begin + $display("STATUS: Step-5, Checking the PLL - PASSED"); + end + $display("##########################################################"); + + $display("###################################################"); + $display("Step-6,Monitor: PLL Monitor Clock output:"); + $display("###################################################"); + $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)"); + test_id = 6; + test_step = 13; + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); + + // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); + dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD); + `endif + + if(test_fail == 1) begin + $display("ERROR: Step-6, PLL Monitor Clock output - FAILED"); + end else begin + $display("STATUS: Step-6, PLL Monitor Clock output - PASSED"); + end + ****/ + $display("##########################################################"); + $display("Step-7,Monitor: Checking the chip signature :"); + $display("###################################################"); + test_id = 7; + test_step = 14; + // Remove Wb/PinMux Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h0309_2022); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_3000); + if(test_fail == 1) begin + $display("ERROR: Step-7,Monitor: Checking the chip signature - FAILED"); + end else begin + $display("STATUS: Step-7,Monitor: Checking the chip signature - PASSED"); + + $display("##########################################################"); + + end end - begin - repeat (30000) @(posedge clock); - // $display("+1000 cycles"); - test_fail = 1; + repeat (30000) @(posedge clock); + // $display("+1000 cycles"); + test_fail = 1; end join_any disable fork; //disable pending fork activity @@ -345,7 +501,7 @@ // IOs - .io_in ('h0) , + .io_in (io_in ) , .io_out (io_out) , .io_oeb (io_oeb) , @@ -353,6 +509,7 @@ ); + `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin @@ -361,6 +518,57 @@ end `endif +task clock_monitor2; +input [3:0] cpu_cfg; +input [3:0] wbs_cfg; +real exp_cpu_period; // ns +real exp_wbs_period; // ns +begin + force clock_mon = u_top.u_wb_host.cpu_clk; + case(cpu_cfg) + 4'b0000: exp_cpu_period = CLK1_PERIOD; + 4'b0001: exp_cpu_period = CLK2_PERIOD; + 4'b0010: exp_cpu_period = IPLL_PERIOD; + 4'b0011: exp_cpu_period = XTAL_PERIOD; + 4'b0100: exp_cpu_period = CLK1_PERIOD*2; + 4'b0101: exp_cpu_period = CLK2_PERIOD*2; + 4'b0110: exp_cpu_period = IPLL_PERIOD*2; + 4'b0111: exp_cpu_period = XTAL_PERIOD*2; + 4'b1000: exp_cpu_period = CLK1_PERIOD*4; + 4'b1001: exp_cpu_period = CLK2_PERIOD*4; + 4'b1010: exp_cpu_period = IPLL_PERIOD*4; + 4'b1011: exp_cpu_period = XTAL_PERIOD*4; + 4'b1100: exp_cpu_period = CLK1_PERIOD*8; + 4'b1101: exp_cpu_period = CLK2_PERIOD*8; + 4'b1110: exp_cpu_period = IPLL_PERIOD*8; + 4'b1111: exp_cpu_period = XTAL_PERIOD*8; + endcase + check_clock_period("CPU CLock",exp_cpu_period); + release clock_mon; + + force clock_mon = u_top.u_wb_host.wbs_clk_out; + case(wbs_cfg) + 4'b0000: exp_wbs_period = CLK1_PERIOD; + 4'b0001: exp_wbs_period = CLK2_PERIOD; + 4'b0010: exp_wbs_period = IPLL_PERIOD; + 4'b0011: exp_wbs_period = XTAL_PERIOD; + 4'b0100: exp_wbs_period = CLK1_PERIOD*2; + 4'b0101: exp_wbs_period = CLK2_PERIOD*2; + 4'b0110: exp_wbs_period = IPLL_PERIOD*2; + 4'b0111: exp_wbs_period = XTAL_PERIOD*2; + 4'b1000: exp_wbs_period = CLK1_PERIOD*4; + 4'b1001: exp_wbs_period = CLK2_PERIOD*4; + 4'b1010: exp_wbs_period = IPLL_PERIOD*4; + 4'b1011: exp_wbs_period = XTAL_PERIOD*4; + 4'b1100: exp_wbs_period = CLK1_PERIOD*8; + 4'b1101: exp_wbs_period = CLK2_PERIOD*8; + 4'b1110: exp_wbs_period = IPLL_PERIOD*8; + 4'b1111: exp_wbs_period = XTAL_PERIOD*8; + endcase + check_clock_period("WBS Clock",exp_wbs_period); + release clock_mon; +end +endtask task clock_monitor; input [15:0] exp_cpu_period; @@ -372,11 +580,11 @@ check_clock_period("CPU CLock",exp_cpu_period); release clock_mon; - force clock_mon = u_top.u_wb_host.usb_clk; + force clock_mon = u_top.u_pinmux.usb_clk; check_clock_period("USB Clock",exp_usb_period); release clock_mon; - force clock_mon = u_top.u_wb_host.rtc_clk; + force clock_mon = u_top.u_pinmux.rtc_clk; check_clock_period("RTC Clock",exp_rtc_period); release clock_mon; @@ -387,7 +595,7 @@ endtask task pll_clock_monitor; -input [15:0] exp_period; +input real exp_period; begin //force clock_mon = u_top.u_wb_host.pll_clk_out[0]; `ifdef GL @@ -400,6 +608,15 @@ end endtask +task uartm_clock_monitor; +input real exp_period; +begin + force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x; + check_clock_period("UART CLock",exp_period); + release clock_mon; +end +endtask + wire dbg_clk_mon = io_out[33]; @@ -439,22 +656,32 @@ //---------------------------------- task check_clock_period; input [127:0] clk_name; -input [15:0] clk_period; // in NS -time prev_t, next_t, periodd; +input real period; +real edge2, edge1, clock_period; +real tolerance,min_period,max_period; begin - $timeformat(-12,3,"ns",10); + + tolerance = 0.01; + + min_period = period * (1-tolerance); + max_period = period * (1+tolerance); + + //$timeformat(-12,2,"ps",10); repeat(1) @(posedge clock_mon); repeat(1) @(posedge clock_mon); - prev_t = $realtime; + edge1 = $realtime; repeat(100) @(posedge clock_mon); - next_t = $realtime; - periodd = (next_t-prev_t)/100; - //periodd = (periodd)/1e9; - if(clk_period != periodd) begin - $display("STATUS: FAIL => %s Exp Period: %d Rxd: %d",clk_name,clk_period,periodd); + edge2 = $realtime; + clock_period = (edge2-edge1)/100; + + if ( clock_period > max_period ) begin + $display("STATUS: FAIL => %s clock is too fast => Exp: %.3fns Rxd: %.3fns",clk_name,clock_period,max_period); + test_fail = 1; + end else if ( clock_period < min_period ) begin + $display("STATUS: FAIL => %s clock is too slow => Exp: %.3fns Rxd: %.3fns",clk_name,clock_period,min_period); test_fail = 1; end else begin - $display("STATUS: PASS => %s Period: %d ",clk_name,clk_period); + $display("STATUS: PASS => %s Period: %.3fns ",clk_name,period); end end endtask @@ -593,5 +820,6 @@ `endif **/ +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_gpio/Makefile b/verilog/dv/user_gpio/Makefile index c5090ee..28bcc52 100644 --- a/verilog/dv/user_gpio/Makefile +++ b/verilog/dv/user_gpio/Makefile
@@ -78,7 +78,7 @@ endif %.vcd: %.vvp - vvp $< + vvp $< +risc_core_id=$(RISC_CORE) # ---- Clean ----
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v index 490a3a5..a0ab607 100644 --- a/verilog/dv/user_gpio/user_gpio_tb.v +++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -103,9 +103,11 @@ wire [7:0] mprj_io_0; reg test_fail; reg [31:0] read_data; - integer test_step; - wire clock_mon; + reg test_start; + integer test_step; + wire clock_mon; + integer d_risc_id; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -115,109 +117,129 @@ /************* Port-A Mapping ********************************** + * PA0 digital_io[0] + * PA1 digital_io[1] + * PA2 digital_io[2] + * PA3 digital_io[3] + * PA4 digital_io[4] * ********************************************************/ reg [7:0] port_a_out; - wire [7:0] port_a_in = 8'h0; + wire [7:0] port_a_in = { 3'b0, + io_out[4], + io_out[3], + io_out[2], + io_out[1], + io_out[0] + }; + + + assign { io_in[4], + io_in[3], + io_in[2], + io_in[1], + io_in[0] + } = (test_start) ? port_a_out[4:0]: 5'hZ; + /************* Port-B Mapping ********************************** - * Pin-14 PB0/CLKO/ICP1 digital_io[11] - * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[12] - * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] - * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] - * Pin-18 PB4/MISO digital_io[15] - * Pin-19 PB5/SCK digital_io[16] - * Pin-9 PB6/XTAL1/TOSC1 digital_io[6] - * Pin-10 PB7/XTAL2/TOSC2 digital_io[7] + * Pin-14 8 PB0/WS[2]/CLKO/ICP1 strap[3] digital_io[16] + * Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) strap[4] digital_io[17] + * Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) strap[5] digital_io[18] + * Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) strap[6] digital_io[19] + * Pin-18 12 PB4/WS[3]/MISO strap[7] digital_io[20] + * Pin-19 13 PB5/SCK digital_io[21] + * Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[11] + * Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[12] * ********************************************************/ reg [7:0] port_b_out; - wire [7:0] port_b_in = { io_out[7], - io_out[6], - io_out[16], - io_out[15], - io_out[14], - io_out[13], - io_out[12], - io_out[11] + wire [7:0] port_b_in = { io_out[12], + io_out[11], + io_out[21], + io_out[20], + io_out[19], + io_out[18], + io_out[17], + io_out[16] }; - assign { io_in[7], - io_in[6], - io_in[16], - io_in[15], - io_in[14], - io_in[13], - io_in[12], - io_in[11] - } = port_b_out; + assign { io_in[12], + io_in[11], + io_in[21], + io_in[20], + io_in[19], + io_in[18], + io_in[17], + io_in[16] + } = (test_start) ? port_b_out: 8'hZ; /************* Port-C Mapping ********************************** - * Pin-1 PC6/RESET* digital_io[0] - * Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] - * Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] - * Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] - * Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] - * Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] - * Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] + * Pin-23 14 PC0/uartm_rxd/ADC0 digital_io[22]/analog_io[11] + * Pin-24 15 PC1/uartm_txd/ADC1 digital_io[23]/analog_io[12] + * Pin-25 16 PC2/usb_dp/ADC2 digital_io[24]/analog_io[13] + * Pin-26 17 PC3/usb_dn/ADC3 digital_io[25]/analog_io[14] + * Pin-27 18 PC4/ADC4/SDA digital_io[26]/analog_io[15] + * Pin-28 19 PC5/ADC5/SCL digital_io[27]/analog_io[16] + * Pin-1 22 PC6/WS[0]/RESET* digital_io[5] * ********************************************************/ reg [7:0] port_c_out; wire [7:0] port_c_in = { 1'b0, - io_out[0], + io_out[5], + io_out[27], + io_out[26], + io_out[25], + io_out[24], io_out[23], - io_out[22], - io_out[21], - io_out[20], - io_out[19], - io_out[18] + io_out[22] }; - assign { io_in[0], - io_in[23], - io_in[22], - io_in[21], - io_in[20], - io_in[19], - io_in[18] - } = port_c_out[6:0]; + assign { io_in[5], + io_in[27], + io_in[26], + io_in[25], + io_in[24], + io_in[23], + io_in[22] + } = (test_start) ? port_c_out[6:0] : 7'hZ; /************* Port-D Mapping ********************************** - * Pin-2 PD0/RXD[0] digital_io[1] - * Pin-3 PD1/TXD[0] digital_io[2] - * Pin-4 PD2/RXD[1]/INT0 digital_io[3] - * Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] - * Pin-6 PD4/TXD[1] digital_io[5] - * Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] - * Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2] - * Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] + * Pin-2 0 PD0/WS[0]/RXD[0] digital_io[6] + * Pin-3 1 PD1/WS[0]/TXD[0] digital_io[7] + * Pin-4 2 PD2/WS[0]/RXD[1]/INT0 digital_io[8] + * Pin-5 3 PD3/WS[1]INT1/OC2B(PWM0) digital_io[9] + * Pin-6 4 PD4/WS[1]TXD[1] digital_io[10] + * Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 strap[0] digital_io[13] + * Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 strap[1] digital_io[14]/analog_io[2] + * Pin-13 7 PD7/WS[2]/A1N1 strap[2] digital_io[15]/analog_io[3] * ********************************************************/ reg [7:0] port_d_out; - wire [7:0] port_d_in = { io_out[10], - io_out[9], - io_out[8], - io_out[5], - io_out[4], - io_out[3], - io_out[2], - io_out[1] + wire [7:0] port_d_in = { io_out[15], + io_out[14], + io_out[13], + io_out[10], + io_out[9], + io_out[8], + io_out[7], + io_out[6] }; - assign { io_in[10], - io_in[9], - io_in[8], - io_in[5], - io_in[4], - io_in[3], - io_in[2], - io_in[1] - } = port_d_out; + assign { io_in[15], + io_in[14], + io_in[13], + io_in[10], + io_in[9], + io_in[8], + io_in[7], + io_in[6] + } = (test_start) ? port_d_out : 8'hz; /*****************************/ - wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines; + wire [31:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines; initial begin clock = 0; @@ -240,27 +262,32 @@ `endif initial begin + test_start = 0; test_fail = 0; + $value$plusargs("risc_core_id=%d", d_risc_id); + + init(); + test_start = 1; #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); - repeat (2) @(posedge clock); + repeat (2) @(posedge clock); #1; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); - // Disable Multi func - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h000); + // Disable Multi func + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h000); /************* GPIO As Output ******************/ $display("#####################################"); $display("Step-1: Testing GPIO As Output "); // Set the Direction as Output - wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'hFFFFFFFF); // Set the GPIO Output data: 0x55555555 - wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h55555555); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h55555555); cmp_gpio_output(8'h55,8'h55,8'h55,8'h55); // Set the GPIO Output data: 0xAAAAAAAA @@ -279,7 +306,7 @@ $display("#####################################"); $display("Step-2: Testing GPIO As Input "); // Set the Direction as Input - wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000); cmp_gpio_input(8'h55,8'h55,8'h55,8'h55); cmp_gpio_input(8'hAA,8'hAA,8'hAA,8'hAA); @@ -290,12 +317,12 @@ $display("#####################################"); $display("Step-3: Testing GPIO As Posedge Interrupt "); // Set the Direction as Input - wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000); // Set GPIO for posedge Interrupt - wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF); - wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'hFFFFFFFF); - wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'h00000000); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFFFF00); // Drive GPIO with 0x55 cmp_gpio_pos_intr(8'h55,8'h55,8'h55,8'h55); @@ -356,11 +383,6 @@ $finish; end - initial begin - wb_rst_i = 1'b1; - #100; - wb_rst_i = 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -399,9 +421,6 @@ .user_irq () ); -// SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -410,32 +429,6 @@ end `endif -//------------------------------------------------------ -// Integrate the Serial flash with qurd support to -// user core using the gpio pads -// ---------------------------------------------------- - wire flash_io1; - wire flash_clk = io_out[16]; - wire spiram_csb = io_out[13]; - tri #1 flash_io0 = io_out[15]; - assign io_in[14] = flash_io1; - - tri #1 flash_io2 = 1'b1; - tri #1 flash_io3 = 1'b1; - - - is62wvs1288 #(.mem_file_name("flash1.hex")) - u_sfram ( - // Data Inputs/Outputs - .io0 (flash_io0), - .io1 (flash_io1), - // Controls - .clk (flash_clk), - .csb (spiram_csb), - .io2 (flash_io2), - .io3 (flash_io3) - ); - //---------------------------------------------------- // Task @@ -460,12 +453,12 @@ // Wait for some cycle to reg to be written through wbbone host repeat (20) @(posedge clock); - if((exp_port_a & 8'h00) != (port_a_in & 8'h00)) + if((exp_port_a & 8'h1F) != (port_a_in & 8'h1F)) begin - $display("ERROR: PORT A Exp: %x Rxd: %x",exp_port_a & 8'h00,port_a_in & 8'h00); + $display("ERROR: PORT A Exp: %x Rxd: %x",exp_port_a & 8'h1F,port_a_in & 8'h1F); `TB_GLBL.test_fail = 1; end else begin - $display("STATYS: PORT A Data: %x Matched ",port_a_in & 8'h00); + $display("STATYS: PORT A Data: %x Matched ",port_a_in & 8'h1F); end if((exp_port_b & 8'hFF) != (port_b_in & 8'hFF)) @@ -509,7 +502,7 @@ port_c_out = port_c; port_d_out = port_d; - wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F}); end endtask @@ -525,13 +518,12 @@ // Drive GPIO with zero cmp_gpio_input(8'h00,8'h00,8'h00,8'h00); - // Clear Global Interrupt - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000); - // Clear all the Interrupt wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF); - wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0); + // Clear Global Interrupt + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data,32'h0); // Drive Ports cmp_gpio_input(port_d,port_c,port_b,port_a); @@ -547,12 +539,12 @@ repeat (20) @(posedge clock); // Check the GPIO Interrupt - wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F}); // Check The Global Interrupt - wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); - if(irq_lines[15] != 1'b1) begin + if(irq_lines[31:8] == 0) begin $display("ERROR: Global GPIO Interrupt not detected"); `TB_GLBL.test_fail = 1; end @@ -560,8 +552,8 @@ // Clear The GPIO Interrupt wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF); - // Clear GPIO Interrupt - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000); + // Clear GLBL Interrupt + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'hFFFFFFFF); // Check Interrupt are cleared @@ -586,12 +578,12 @@ // Drive GPIO with All One's cmp_gpio_input(8'hFF,8'hFF,8'hFF,8'hFF); - // Clear Global Interrupt - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000); - - // Clear all the Interrupt wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF); wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0); + // Clear Global Interrupt + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0); + // Drive Ports cmp_gpio_input(port_d,port_c,port_b,port_a); @@ -606,12 +598,12 @@ repeat (20) @(posedge clock); // Neg edge interrupt is will compliment of input value - wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0}); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,(port_a ^ 8'hFF )& 8'h1F}); // Check The Global Interrupt - wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0}); - if(irq_lines[15] != 1'b1) begin + if(irq_lines[31:8] == 0) begin $display("ERROR: Global GPIO Interrupt not detected"); `TB_GLBL.test_fail = 1; end @@ -620,7 +612,7 @@ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF); // Clear GPIO Interrupt - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'hFFFFFFFF); // Check Interrupt are cleared wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0); @@ -764,5 +756,6 @@ `endif **/ +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index 0814b1c..a343366 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -124,15 +124,11 @@ end `endif - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end initial begin test_fail = 0; - + init(); + #200; // Wait for reset removal repeat (10) @(posedge clock); $display("############################################"); @@ -339,7 +335,6 @@ ); // SSPI Slave I/F assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -353,10 +348,10 @@ // -------------------------- tri scl,sda; -assign sda = (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz; -assign scl = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz; -assign io_in[22] = sda; -assign io_in[23] = scl; +assign sda = (io_oeb[26] == 1'b0) ? io_out[26] : 1'bz; +assign scl = (io_oeb[27] == 1'b0) ? io_out[27]: 1'bz; +assign io_in[26] = sda; +assign io_in[27] = scl; pullup p1(scl); // pullup scl line pullup p2(sda); // pullup sda line @@ -389,7 +384,7 @@ wbd_ext_we_i ='h0; // write wbd_ext_dat_i ='h0; // data output wbd_ext_sel_i ='h0; // byte enable - $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); + $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); repeat (2) @(posedge clock); end endtask @@ -418,7 +413,7 @@ wbd_ext_we_i ='h0; // write wbd_ext_dat_i ='h0; // data output wbd_ext_sel_i ='h0; // byte enable - //$display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); repeat (2) @(posedge clock); end endtask @@ -496,5 +491,6 @@ `endif **/ +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index 584c4c2..32b5b69 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -135,40 +135,41 @@ initial begin $dumpon; + init(); #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); - // Enable PWM Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h03F); + // Enable PWM Multi Functional Ports + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h03F); - repeat (2) @(posedge clock); + repeat (2) @(posedge clock); #1; - // Remove the reset + // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // config 1us based on system clock - 1000/25ns = 40 - wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39); test_fail = 0; - repeat (200) @(posedge clock); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + repeat (200) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 - $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7"); - test_step = 1; - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_0,'h0000_0000); - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_1,'h0000_0001); - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_2,'h0001_0001); - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_3,'h0001_0002); - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_4,'h0002_0002); - wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_5,'h0002_0003); - pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7); + $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7"); + test_step = 1; + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_0,'h0000_0000); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_1,'h0000_0001); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_2,'h0001_0001); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_3,'h0001_0002); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_4,'h0002_0002); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_5,'h0002_0003); + pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7); repeat (100) @(posedge clock); // $display("+1000 cycles"); @@ -190,20 +191,15 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; -wire pwm0 = io_out[4]; -wire pwm1 = io_out[8]; -wire pwm2 = io_out[9]; -wire pwm3 = io_out[12]; -wire pwm4 = io_out[13]; -wire pwm5 = io_out[14]; +wire pwm0 = io_out[9]; +wire pwm1 = io_out[13]; +wire pwm2 = io_out[14]; +wire pwm3 = io_out[17]; +wire pwm4 = io_out[18]; +wire pwm5 = io_out[19]; task pwm_monitor; @@ -302,7 +298,6 @@ ); // SSPI Slave I/F assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -453,5 +448,6 @@ `endif **/ +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v index 89b05bd..e4785b1 100644 --- a/verilog/dv/user_qspi/user_qspi_tb.v +++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -192,9 +192,10 @@ initial begin $dumpon; + init(); #200; // Wait for reset removal - repeat (10) @(posedge clock); + repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset @@ -202,15 +203,23 @@ repeat (2) @(posedge clock); #1; - // Remove only WB and SPI Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h2); + // Enable SPI Reset + wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,read_data); + read_data = read_data | 8'h02; + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,read_data); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 test_fail = 0; - repeat (200) @(posedge clock); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + repeat (200) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + + if(u_top.strap_qspi_sram) begin // if the SRAM STRAP in QUAD Mode, then send reset command to switch to SINGLE PHASE + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'hFF}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); + end // CS#2 SSPI Indirect RAM READ ACCESS- wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); @@ -1152,11 +1161,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -1197,7 +1201,6 @@ // SSPI Slave I/F assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -1211,22 +1214,22 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quad flash @@ -1246,7 +1249,7 @@ ); - wire spiram_csb = io_out[27]; + wire spiram_csb = io_out[31]; is62wvs1288 #(.mem_file_name("flash1.hex")) u_sfram ( @@ -1391,6 +1394,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile index 0417a18..d83adcc 100644 --- a/verilog/dv/user_risc_boot/Makefile +++ b/verilog/dv/user_risc_boot/Makefile
@@ -51,32 +51,32 @@ vvp: ${PATTERN:=.vvp} %.vvp: %_tb.v - ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o + ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o - ${GCC_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_risc_boot.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N - ${GCC_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex - ${GCC_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump - rm crt.o user_risc_boot.o + ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N + ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump + rm crt.o ${PATTERN}.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c index c14c9a7..923dba7 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot.c +++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -16,37 +16,29 @@ // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> // ////////////////////////////////////////////////////////////////////////// #define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long +#include "../c_func/inc/int_reg_map.h" +#include "common_misc.h" +#include "common_bthread.h" -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel -#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 -#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 -#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 -#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 -#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 -#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 int main() { - //volatile long *out_ptr = (volatile long*)SC_SIM_OUTPORT; - //*out_ptr = 0xAABBCCDD; - //*out_ptr = 0xBBCCDDEE; - //*out_ptr = 0xCCDDEEFF; - //*out_ptr = 0xDDEEFF00; + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + + reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main // Write software Write & Read Register - reg_mprj_globl_soft0 = 0x11223344; - reg_mprj_globl_soft1 = 0x22334455; - reg_mprj_globl_soft2 = 0x33445566; - reg_mprj_globl_soft3 = 0x44556677; - reg_mprj_globl_soft4 = 0x55667788; - reg_mprj_globl_soft5 = 0x66778899; + reg_glbl_soft_reg_0 = 0x11223344; + reg_glbl_soft_reg_1 = 0x22334455; + reg_glbl_soft_reg_2 = 0x33445566; + reg_glbl_soft_reg_3 = 0x44556677; + reg_glbl_soft_reg_4 = 0x55667788; + reg_glbl_soft_reg_5 = 0x66778899; //reg_mprj_globl_reg12 = 0x778899AA; //reg_mprj_globl_reg13 = 0x8899AABB; //reg_mprj_globl_reg14 = 0x99AABBCC;
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index 79c705b..fee4a6d 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -75,7 +75,10 @@ `timescale 1 ns / 1 ns `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" -module user_risc_boot_tb; + +`define TB_HEX "user_risc_boot.hex" +`define TB_TOP user_risc_boot_tb +module `TB_TOP; reg clock; reg wb_rst_i; reg power1, power2; @@ -125,39 +128,34 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, user_risc_boot_tb); + $dumpvars(3, `TB_TOP); end `endif initial begin - $value$plusargs("risc_core_id=%d", d_risc_id); + init(); + #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (30) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - + wait_riscv_boot(); $display("Monitor: Reading Back the expected value"); // User RISC core expect to write these value in global @@ -197,11 +195,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -241,8 +234,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf @@ -257,28 +250,30 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; + // Quard flash - s25fl256s #(.mem_file_name("user_risc_boot.hex"), - .otp_file_name("none"), + s25fl256s #(.mem_file_name(`TB_HEX), + .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) - u_spi_flash_256mb ( + u_spi_flash_256mb + ( // Data Inputs/Outputs .SI (flash_io0), .SO (flash_io1), @@ -423,6 +418,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_spi_isp/user_spi_isp_tb.v b/verilog/dv/user_spi_isp/user_spi_isp_tb.v index 0bbca8c..7d78ef2 100644 --- a/verilog/dv/user_spi_isp/user_spi_isp_tb.v +++ b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
@@ -137,16 +137,14 @@ end initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset + init(); $display("Monitor: Standalone User SPI ISP Test Started"); // Remove Wb Reset - u_spim.reg_wr_dword(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //u_spim.reg_wr_dword(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; @@ -230,18 +228,16 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin end `endif -assign io_in[0] = 1'b0; -assign io_in[16] = sclk; -assign io_in[15] = sdi; -assign sdo = io_out[14]; +assign io_in[5] = 1'b0; +assign io_in[21] = sclk; +assign io_in[20] = sdi; +assign sdo = io_out[19]; bfm_spim u_spim ( // SPI @@ -253,5 +249,6 @@ ); +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v index eee28ca..11f2901 100644 --- a/verilog/dv/user_sspi/user_sspi_tb.v +++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -131,38 +131,39 @@ initial begin $dumpon; + init(); #200; // Wait for reset removal - repeat (10) @(posedge clock); + repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); - // Enable SPI Multi Functional Ports - // wire cfg_spim_enb = cfg_multi_func_sel[10]; - // wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11]; - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h7C00); + // Enable SPI Multi Functional Ports + // wire cfg_spim_enb = cfg_multi_func_sel[10]; + // wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11]; + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h7C00); - repeat (2) @(posedge clock); + repeat (2) @(posedge clock); #1; - // Remove the reset + // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); test_fail = 0; sspi_init(); - repeat (200) @(posedge clock); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 - $display("############################################"); - $display(" Testing IS62/65WVS1288GALL SSRAM[0] Read/Write Access "); - $display("############################################"); + repeat (200) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[0] Read/Write Access "); + $display("############################################"); // SSPI Indirect RAM READ ACCESS- // Byte Read Option // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> - spi_chip_no = 2'b00; // Select the Chip Select to zero + spi_chip_no = 2'b00; // Select the Chip Select to zero sspi_dw_read_check(8'h03,24'h0000,32'h03020100); sspi_dw_read_check(8'h03,24'h0004,32'h07060504); sspi_dw_read_check(8'h03,24'h0008,32'h0b0a0908); @@ -209,13 +210,13 @@ sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); - $display("############################################"); - $display(" Testing IS62/65WVS1288GALL SSRAM[1] Read/Write Access "); - $display("############################################"); + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[1] Read/Write Access "); + $display("############################################"); // SSPI Indirect RAM READ ACCESS- // Byte Read Option // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> - spi_chip_no = 2'b01; // Select the Chip Select to zero + spi_chip_no = 2'b01; // Select the Chip Select to zero sspi_dw_read_check(8'h03,24'h0000,32'h13121110); sspi_dw_read_check(8'h03,24'h0004,32'h17161514); sspi_dw_read_check(8'h03,24'h0008,32'h1B1A1918); @@ -268,13 +269,13 @@ sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); - $display("############################################"); - $display(" Testing IS62/65WVS1288GALL SSRAM[2] Read/Write Access "); - $display("############################################"); + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[2] Read/Write Access "); + $display("############################################"); // SSPI Indirect RAM READ ACCESS- // Byte Read Option // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> - spi_chip_no = 2'b10; // Select the Chip Select to zero + spi_chip_no = 2'b10; // Select the Chip Select to zero sspi_dw_read_check(8'h03,24'h0000,32'h23222120); sspi_dw_read_check(8'h03,24'h0004,32'h27262524); sspi_dw_read_check(8'h03,24'h0008,32'h2b2a2928); @@ -332,13 +333,13 @@ sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); - $display("############################################"); - $display(" Testing IS62/65WVS1288GALL SSRAM[3] Read/Write Access "); - $display("############################################"); + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[3] Read/Write Access "); + $display("############################################"); // SSPI Indirect RAM READ ACCESS- // Byte Read Option // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> - spi_chip_no = 2'b11; // Select the Chip Select to zero + spi_chip_no = 2'b11; // Select the Chip Select to zero sspi_dw_read_check(8'h03,24'h0000,32'h33323130); sspi_dw_read_check(8'h03,24'h0004,32'h37363534); sspi_dw_read_check(8'h03,24'h0008,32'h3b3a3938); @@ -386,14 +387,14 @@ sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); repeat (100) @(posedge clock); - // $display("+1000 cycles"); + // $display("+1000 cycles"); - if(test_fail == 0) begin - `ifdef GL - $display("Monitor: SPI Master Mode (GL) Passed"); - `else - $display("Monitor: SPI Master Mode (RTL) Passed"); - `endif + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: SPI Master Mode (GL) Passed"); + `else + $display("Monitor: SPI Master Mode (RTL) Passed"); + `endif end else begin `ifdef GL $display("Monitor: SPI Master Mode (GL) Failed"); @@ -405,11 +406,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -450,7 +446,6 @@ // SSPI Slave I/F assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf @@ -465,15 +460,15 @@ // user core using the gpio pads // ---------------------------------------------------- wire flash_io1; - wire flash_clk = io_out[16]; - tri #1 flash_io0 = io_out[15]; - assign io_in[14] = flash_io1; + wire flash_clk = io_out[21]; + tri #1 flash_io0 = io_out[20]; + assign io_in[19] = flash_io1; tri #1 flash_io2 = 1'b1; tri #1 flash_io3 = 1'b1; - wire spiram_csb0 = io_out[13]; + wire spiram_csb0 = io_out[18]; is62wvs1288 #(.mem_file_name("flash0.hex")) u_sfram_0 ( // Data Inputs/Outputs @@ -486,7 +481,7 @@ .io3 (flash_io3) ); - wire spiram_csb1 = io_out[12]; + wire spiram_csb1 = io_out[17]; is62wvs1288 #(.mem_file_name("flash1.hex")) u_sfram_1 ( // Data Inputs/Outputs @@ -499,7 +494,7 @@ .io3 (flash_io3) ); - wire spiram_csb2 = io_out[9]; + wire spiram_csb2 = io_out[14]; is62wvs1288 #(.mem_file_name("flash2.hex")) u_sfram_2 ( // Data Inputs/Outputs @@ -512,7 +507,7 @@ .io3 (flash_io3) ); - wire spiram_csb3 = io_out[8]; + wire spiram_csb3 = io_out[13]; is62wvs1288 #(.mem_file_name("flash3.hex")) u_sfram_3 ( // Data Inputs/Outputs @@ -665,6 +660,6 @@ `endif **/ `include "sspi_task.v" - +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v index 35c2e05..d39122d 100644 --- a/verilog/dv/user_timer/user_timer_tb.v +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -133,26 +133,27 @@ initial begin $dumpon; + init(); #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // config 1us based on system clock - 1000/25ns = 40 wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39); // Enable Timer Interrupt - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'h700); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'h007); test_fail = 0; repeat (200) @(posedge clock); @@ -174,12 +175,12 @@ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B); wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); - if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin + if((u_top.u_pinmux.irq_lines[2:0] == 3'b111) && (read_data[2:0] == 3'b111)) begin $display("STATUS: Timer Interrupt detected "); // Clearing the Timer Interrupt - wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700); + wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h007); wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); - if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin + if((u_top.u_pinmux.irq_lines[2:0] == 3'b111) && (read_data[2:0] == 3'b000)) begin $display("ERROR: Timer Interrupt not cleared "); test_fail = 1; end else begin @@ -206,12 +207,12 @@ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B); wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); - if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin + if((u_top.u_pinmux.irq_lines[2:0] == 3'b111) && (read_data[2:0] == 3'b111)) begin $display("STATUS: Timer Interrupt detected "); // Clearing the Timer Interrupt - wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700); + wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h007); wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); - if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin + if((u_top.u_pinmux.irq_lines[2:0] == 3'b111) && (read_data[2:0] == 3'b000)) begin $display("ERROR: Timer Interrupt not cleared "); test_fail = 1; end else begin @@ -242,11 +243,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -337,7 +333,6 @@ ); // SSPI Slave I/F assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -488,5 +483,6 @@ `endif **/ +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile index 1ca5cd8..fc9b113 100644 --- a/verilog/dv/user_uart/Makefile +++ b/verilog/dv/user_uart/Makefile
@@ -51,32 +51,32 @@ vvp: ${PATTERN:=.vvp} %.vvp: %_tb.v - ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o + ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o - ${GCC_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N - ${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex - ${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump - rm crt.o user_uart.o + ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N + ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump + rm crt.o ${PATTERN}.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ @@ -92,4 +92,4 @@ clean: rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump -.PHONY: clean all +.PHONY: clean hex all
diff --git a/verilog/dv/user_uart/user_uart.c b/verilog/dv/user_uart/user_uart.c index 4a82878..b19a157 100644 --- a/verilog/dv/user_uart/user_uart.c +++ b/verilog/dv/user_uart/user_uart.c
@@ -16,27 +16,33 @@ // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> // ////////////////////////////////////////////////////////////////////////// #define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long +#include "../c_func/inc/int_reg_map.h" +#include "common_misc.h" +#include "common_bthread.h" -#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010000) -#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010004) -#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010008) -#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001000C) -#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010010) -#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010014) -#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010018) -#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001001C) -#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010020) int main() { + reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART + reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0 + reg_glbl_multi_func |=0x100; // Enable UART Multi func + reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1} + + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + + reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main + while(1) { // Check UART RX fifo has data, if available loop back the data // Also check txfifo is not full - if((reg_mprj_uart_reg8 != 0) && ((reg_mprj_uart_reg4 & 0x1) != 0x1)) { - reg_mprj_uart_reg5 = reg_mprj_uart_reg6; + if((reg_uart0_rxfifo_stat != 0) && ((reg_uart0_status & 0x1) != 0x1)) { + reg_uart0_txdata = reg_uart0_rxdata; } }
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 0096617..8aa66ca 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -76,9 +76,13 @@ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "uart_agent.v" +`include "user_params.svh" -module user_uart_tb; +`define TB_HEX "user_uart.hex" +`define TB_TOP user_uart_tb +module `TB_TOP; + reg clock ; reg wb_rst_i ; @@ -146,18 +150,21 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(1, user_uart_tb); - $dumpvars(1, user_uart_tb.u_top); + $dumpvars(1, `TB_TOP); + $dumpvars(2, `TB_TOP.u_top); + $dumpvars(0, `TB_TOP.u_top.u_wb_host); + $dumpvars(0, `TB_TOP.u_top.u_pinmux); end `endif - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end + initial begin + + $value$plusargs("risc_core_id=%d", d_risc_id); + + init(); + uart_data_bit = 2'b11; uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; uart_stick_parity = 0; // 1: force even parity @@ -174,17 +181,17 @@ $display("Monitor: Standalone User Uart Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable UART Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100); repeat (2) @(posedge clock); #1; // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); @@ -199,11 +206,12 @@ repeat (100) @(posedge clock); // wait for Processor Get Ready tb_uart.uart_init; - wb_user_core_write(`ADDR_SPACE_UART0+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); + //wb_user_core_write(`ADDR_SPACE_UART0+`UART_CTRL,{3'h0,2'b00,1'b1,1'b1,1'b1}); tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (30000) @(posedge clock); // wait for Processor Get Ready + + wait_riscv_boot(); for (i=0; i<40; i=i+1) @@ -301,8 +309,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf @@ -317,26 +325,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("user_uart.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb @@ -359,8 +367,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -424,6 +432,40 @@ end endtask +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + `TB_TOP.test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask `ifdef GL wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; @@ -463,6 +505,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile index c6bc358..280fed2 100644 --- a/verilog/dv/user_uart1/Makefile +++ b/verilog/dv/user_uart1/Makefile
@@ -51,32 +51,32 @@ vvp: ${PATTERN:=.vvp} %.vvp: %_tb.v - ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o + ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o - ${GCC_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N - ${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex - ${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump - rm crt.o user_uart.o + ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N + ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex + ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump + rm crt.o ${PATTERN}.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/user_uart1/user_uart1.c b/verilog/dv/user_uart1/user_uart1.c new file mode 100644 index 0000000..e680062 --- /dev/null +++ b/verilog/dv/user_uart1/user_uart1.c
@@ -0,0 +1,49 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// +#define SC_SIM_OUTPORT (0xf0000000) +#include "../c_func/inc/int_reg_map.h" +#include "common_misc.h" +#include "common_bthread.h" + + + +int main() +{ + + reg_glbl_cfg0 |= 0x43; // Remove Reset for UART + reg_glbl_multi_func |=0x200; // Enable UART Multi func + reg_uart1_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1} + + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + + reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main + + while(1) { + // Check UART RX fifo has data, if available loop back the data + // Also check txfifo is not full + if((reg_uart1_rxfifo_stat != 0) && ((reg_uart1_status & 0x1) != 0x1)) { + reg_uart1_txdata = reg_uart1_rxdata; + } + } + + return 0; +}
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v index 6a2d3c5..8559565 100644 --- a/verilog/dv/user_uart1/user_uart1_tb.v +++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -78,7 +78,9 @@ `include "uart_agent.v" -module user_uart1_tb; +`define TB_HEX "user_uart1.hex" +`define TB_TOP user_uart1_tb +module `TB_TOP; reg clock ; reg wb_rst_i ; @@ -146,17 +148,19 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(0, user_uart1_tb); + $dumpvars(1, `TB_TOP); + $dumpvars(1, `TB_TOP.u_top); + $dumpvars(1, `TB_TOP.u_top.u_wb_host); + $dumpvars(1, `TB_TOP.u_top.u_pinmux); + $dumpvars(1, `TB_TOP.u_top.u_uart_i2c_usb_spi); end `endif - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end initial begin + + init(); + uart_data_bit = 2'b11; uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; uart_stick_parity = 0; // 1: force even parity @@ -173,17 +177,17 @@ $display("Monitor: Standalone User Uart Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable UART Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h200); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h200); repeat (2) @(posedge clock); #1; // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h143); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h143); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h243); @@ -198,11 +202,12 @@ repeat (100) @(posedge clock); // wait for Processor Get Ready tb_uart.uart_init; - wb_user_core_write(`ADDR_SPACE_UART1+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); + //wb_user_core_write(`ADDR_SPACE_UART1+`UART_CTRL,{3'h0,2'b00,1'b1,1'b1,1'b1}); tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (30000) @(posedge clock); // wait for Processor Get Ready + + wait_riscv_boot(); for (i=0; i<40; i=i+1) @@ -300,8 +305,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf @@ -316,26 +321,26 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash - s25fl256s #(.mem_file_name("user_uart.hex"), + s25fl256s #(.mem_file_name(`TB_HEX), .otp_file_name("none"), .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb @@ -358,8 +363,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[5]; -assign io_in[3] = uart_rxd ; +assign uart_txd = io_out[10]; +assign io_in[8] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -423,6 +428,40 @@ end endtask +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + `TB_TOP.test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask `ifdef GL wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; @@ -462,6 +501,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v index 95f2049..2d909f4 100644 --- a/verilog/dv/user_uart_master/user_uart_master_tb.v +++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -68,6 +68,7 @@ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "uart_agent.v" +`include "user_params.svh" module user_uart_master_tb; @@ -100,10 +101,10 @@ // Uart Configuration // --------------------------------- reg [1:0] uart_data_bit ; -reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; -reg uart_stick_parity ; // 1: force even parity -reg uart_parity_en ; // parity enable -reg uart_even_odd_parity ; // 0: odd parity; 1: even parity +reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; +reg uart_stick_parity ; // 1: force even parity +reg uart_parity_en ; // parity enable +reg uart_even_odd_parity ; // 0: odd parity; 1: even parity reg [7:0] uart_data ; reg [15:0] uart_divisor ; // divided by n * 16 @@ -115,7 +116,8 @@ reg uart_fifo_enable ; // fifo mode disable reg [127:0] la_data_in; -reg flag; +reg flag; +reg [15:0] strap_in; integer i,j; @@ -149,7 +151,10 @@ end initial begin - wb_rst_i <= 1'b1; + strap_in = 0; + strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA + apply_strap(strap_in); + uart_data_bit = 2'b11; uart_stop_bits = 1; // 0: 1 stop bit; 1: 2 stop bit; uart_stick_parity = 0; // 1: force even parity @@ -167,7 +172,6 @@ la_data_in[17:16] = 2'b00; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd #100; - wb_rst_i <= 1'b0; // Release reset $display("Monitor: Standalone User Uart master Test Started"); @@ -270,8 +274,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0; // CLOCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -285,8 +289,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[35]; -assign io_in[34] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_master_uart( .mclk (clock ), @@ -297,5 +301,6 @@ `include "uart_master_tasks.sv" +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index 778156e..b63b948 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -166,34 +166,30 @@ initial begin $dumpon; - + init(); #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); - // Remove Wb/PinMux Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); - // Enable SPI Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h400); + // Enable USB Multi Functional Ports + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h10000); repeat (2) @(posedge clock); #1; - // Remove Wb/PinMux Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); - // Set USB clock : 180/3 = 60Mhz - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h61,8'h0,8'h0}); + // Set USB clock : 180/3 = 60Mhz + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CLK_CTRL,{16'h0,8'h61,8'h0}); - // Remove the reset + // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h03F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h03F); test_fail = 0; - repeat (200) @(posedge clock); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10 + repeat (200) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10 //usb_test1; @@ -259,7 +255,7 @@ ); // SSPI Slave I/F assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK + usb_agent u_usb_agent(); @@ -274,11 +270,11 @@ // Drive USB Pads // -tri usbd_txdp = (io_oeb[36] == 1'b0) ? io_out[36] : 1'bz; -tri usbd_txdn = (io_oeb[37] == 1'b0) ? io_out[37] : 1'bz; +tri usbd_txdp = (io_oeb[24] == 1'b0) ? io_out[24] : 1'bz; +tri usbd_txdn = (io_oeb[25] == 1'b0) ? io_out[25] : 1'bz; -assign io_in[36] = usbd_txdp; -assign io_in[37] = usbd_txdn; +assign io_in[24] = usbd_txdp; +assign io_in[25] = usbd_txdn; // Full Speed Device Indication @@ -556,6 +552,6 @@ **/ `include "tests/usb_test1.v" `include "tests/usb_test2.v" - +`include "user_tasks.sv" endmodule `default_nettype wire
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index ef2d0a1..303eb20 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -18,12 +18,9 @@ // This include is relative to $CARAVEL_PATH (see Makefile) #include <defs.h> #include <stub.c> -#include "../c_func/inc/user_reg_map.h" +#include "../c_func/inc/ext_reg_map.h" -// User Project Slaves (0x3000_0000) -#define reg_mprj_slave (*(volatile uint32_t*)0x30000000) -#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30080000) @@ -95,12 +92,12 @@ reg_mprj_datal = 0xAB600000; // Remove Wishbone Reset - reg_mprj_wbhost_reg0 = 0x1; + reg_mprj_wbhost_ctrl = 0x1; // Remove Reset reg_glbl_cfg0 = 0x01f; - if (reg_pinmux_chip_id != 0x82681501) bFail = 1; + if (reg_glbl_chip_id != 0x82681501) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB610000; // write software write & read Register
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index ef76a58..6a450c2 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -99,10 +99,28 @@ ### WB_HOST ################################################## #ifdef WB_HOST_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/clk_skew_adjust/src/clk_skew_adjust.v #-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv +#-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_reset_fsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv +#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv #-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv #-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv #-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v +#-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_if.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/spi2wb.sv #else $(USER_PROJECT_VERILOG)/gl/wb_host.v #endif @@ -111,13 +129,34 @@ ### PINMUX ################################################## #ifdef PINMUX_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv -#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_top.sv #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_reg.sv #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_driver.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/strap_ctrl.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_rst_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv #else -$(USER_PROJECT_VERILOG)/gl/pinmux.v +$(USER_PROJECT_VERILOG)/gl/pinmux_top.v #endif ################################################## @@ -141,6 +180,7 @@ #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_clkgen.sv #-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv #else $(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v @@ -152,6 +192,7 @@ #ifdef WB_INTER_RTL #-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv #-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv #else $(USER_PROJECT_VERILOG)/gl/wb_interconnect.v #endif
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index d58f2aa..2f41858 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -23,8 +23,11 @@ -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_top.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_driver.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_reg.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/strap_ctrl.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_rst_reg.sv -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv +-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv @@ -65,6 +68,7 @@ -v $(USER_PROJECT_VERILOG)/rtl/lib/ser_shift.sv -v $(USER_PROJECT_VERILOG)/rtl/digital_core/src/glbl_cfg.sv -v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv +-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_reset_fsm.sv -v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_top.sv -v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_if.sv -v $(USER_PROJECT_VERILOG)/rtl/sspis/src/spi2wb.sv
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/digital_pll/src/digital_pll.v index f5400d8..a4f189b 100644 --- a/verilog/rtl/digital_pll/src/digital_pll.v +++ b/verilog/rtl/digital_pll/src/digital_pll.v
@@ -13,6 +13,39 @@ // limitations under the License. // SPDX-License-Identifier: Apache-2.0 + +/***************************************************************** + +Offset bcount 4x clock period clock period (ns) clock (Mhz) +1.168 0 1.168 4.672 214.041095890411 +1.168 1 1.18 4.72 211.864406779661 +1.168 2 1.192 4.768 209.731543624161 +1.168 3 1.204 4.816 207.641196013289 +1.168 4 1.216 4.864 205.592105263158 +1.168 5 1.228 4.912 203.583061889251 +1.168 6 1.24 4.96 201.612903225806 +1.168 7 1.252 5.008 199.680511182109 +1.168 8 1.264 5.056 197.784810126582 +1.168 9 1.276 5.104 195.924764890282 +1.168 10 1.288 5.152 194.099378881988 +1.168 11 1.3 5.2 192.307692307692 +1.168 12 1.312 5.248 190.548780487805 +1.168 13 1.324 5.296 188.821752265861 +1.168 14 1.336 5.344 187.125748502994 +1.168 15 1.348 5.392 185.459940652819 +1.168 16 1.36 5.44 183.823529411765 +1.168 17 1.372 5.488 182.215743440233 +1.168 18 1.384 5.536 180.635838150289 +1.168 19 1.396 5.584 179.083094555874 +1.168 20 1.408 5.632 177.556818181818 +1.168 21 1.42 5.68 176.056338028169 +1.168 22 1.432 5.728 174.581005586592 +1.168 23 1.444 5.776 173.130193905817 +1.168 24 1.456 5.824 171.703296703297 +1.168 25 1.468 5.872 170.299727520436 +1.168 26 1.48 5.92 168.918918918919 + +**************************************************/ `default_nettype none // Digital PLL (ring oscillator + controller) // Technically this is a frequency locked loop, not a phase locked loop.
diff --git a/verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v b/verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v index 002b51e..e50d66b 100755 --- a/verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v +++ b/verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v
@@ -95,6 +95,7 @@ output reg cmd_ack, output reg ack_out, output i2c_busy, + output i2c_fsm_busy, output i2c_al, output [7:0] dout, @@ -161,6 +162,9 @@ .sda_oen ( sda_oen ) ); + // Generate I2C FSM Busy + assign i2c_fsm_busy = (c_state !=0); + // generate go-signal assign go = (read | write | stop) & ~cmd_ack;
diff --git a/verilog/rtl/i2cm/src/core/i2cm_top.v b/verilog/rtl/i2cm/src/core/i2cm_top.v index 3b32db9..2fea533 100755 --- a/verilog/rtl/i2cm/src/core/i2cm_top.v +++ b/verilog/rtl/i2cm/src/core/i2cm_top.v
@@ -40,6 +40,8 @@ // 1. Initail version picked from // http://www.opencores.org/projects/i2c/ // 2. renaming of reset signal to aresetn and sresetn +// v0.1 - Dinesh A, 28th Aug 2022 +// Generated i2c_fsm_busy to identify fsm busy state // ////////////////////////////////////////////////////////////////////// //// //// @@ -123,6 +125,7 @@ reg tip; // transfer in progress reg irq_flag; // interrupt pending flag wire i2c_busy; // bus busy (start signal detected) + wire i2c_fsm_busy;// i2C FSM Busy wire i2c_al; // i2c bus arbitration lost reg al; // status register arbitration lost bit @@ -212,28 +215,29 @@ // hookup byte controller block i2cm_byte_ctrl u_byte_ctrl ( - .clk ( wb_clk_i ), - .sresetn ( sresetn ), - .aresetn ( aresetn ), - .ena ( core_en ), - .clk_cnt ( prer ), - .start ( sta ), - .stop ( sto ), - .read ( rd ), - .write ( wr ), - .ack_in ( ack ), - .din ( txr ), - .cmd_ack ( done ), - .ack_out ( irxack ), - .dout ( rxr ), - .i2c_busy ( i2c_busy ), - .i2c_al ( i2c_al ), - .scl_i ( scl_pad_i ), - .scl_o ( scl_pad_o ), - .scl_oen ( scl_padoen_o ), - .sda_i ( sda_pad_i ), - .sda_o ( sda_pad_o ), - .sda_oen ( sda_padoen_o ) + .clk ( wb_clk_i ), + .sresetn ( sresetn ), + .aresetn ( aresetn ), + .ena ( core_en ), + .clk_cnt ( prer ), + .start ( sta ), + .stop ( sto ), + .read ( rd ), + .write ( wr ), + .ack_in ( ack ), + .din ( txr ), + .cmd_ack ( done ), + .ack_out ( irxack ), + .dout ( rxr ), + .i2c_busy ( i2c_busy ), + .i2c_fsm_busy ( i2c_fsm_busy ), + .i2c_al ( i2c_al ), + .scl_i ( scl_pad_i ), + .scl_o ( scl_pad_o ), + .scl_oen ( scl_padoen_o ), + .sda_i ( sda_pad_i ), + .sda_o ( sda_pad_o ), + .sda_oen ( sda_padoen_o ) ); // status register block + interrupt request signal @@ -273,7 +277,8 @@ assign sr[7] = rxack; assign sr[6] = i2c_busy; assign sr[5] = al; - assign sr[4:2] = 3'h0; // reserved + assign sr[4] = i2c_fsm_busy; // I2C FSM Busy + assign sr[3:2] = 2'h0; // reserved assign sr[1] = tip; assign sr[0] = irq_flag;
diff --git a/verilog/rtl/lib/clk_div8.v b/verilog/rtl/lib/clk_div8.v new file mode 100644 index 0000000..d4731b7 --- /dev/null +++ b/verilog/rtl/lib/clk_div8.v
@@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com> +//////////////////////////////////////////////////////////////////////// + +// ################################################################# +// Module: clock div by 2,4,8 supported +// +// +// +// ################################################################# + + +module clk_div8 ( + // Outputs + output logic clk_div_8, + output logic clk_div_4, + output logic clk_div_2, + // Inputs + input logic mclk, + input logic reset_n + ); + + + + +//------------------------------------ +// Clock Divide func is done here +//------------------------------------ +reg [2:0] clk_cnt ; // high level counter + + +assign clk_div_2 = clk_cnt[0]; +assign clk_div_4 = clk_cnt[1]; +assign clk_div_8 = clk_cnt[2]; + +always @ (posedge mclk or negedge reset_n) +begin // { + if(reset_n == 1'b0) + begin + clk_cnt <= 'h0; + end else begin + clk_cnt <= clk_cnt + 1; + end // } +end // } + + +endmodule +
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv index bd34f11..26e5cbb 100644 --- a/verilog/rtl/lib/ctech_cells.sv +++ b/verilog/rtl/lib/ctech_cells.sv
@@ -118,3 +118,22 @@ `endif endmodule + +module ctech_clk_gate ( + input logic GATE , + input logic CLK , + output logic GCLK + ); + +`ifndef SYNTHESIS + assign GCLK = CLK & GATE; +`else + sky130_fd_sc_hd__dlclkp_2 u_gate( + .GATE (GATE ), + .CLK (CLK ), + .GCLK (GCLK ) + ); +`endif + +endmodule +
diff --git a/verilog/rtl/lib/registers.v b/verilog/rtl/lib/registers.v index b9a093e..ef5d356 100755 --- a/verilog/rtl/lib/registers.v +++ b/verilog/rtl/lib/registers.v
@@ -366,3 +366,45 @@ endmodule + +/********************************************************************* + module: generic 32b register +***********************************************************************/ +module gen_32b_reg2 ( + //List of Inputs + rst_in, + cs, + we, + data_in, + reset_n, + clk, + + //List of Outs + data_out + ); + + input [31:0] rst_in; + input [3:0] we; + input cs; + input [31:0] data_in; + input reset_n; + input clk; + output [31:0] data_out; + + + reg [31:0] data_out; + +always @ (posedge clk) begin + if (reset_n == 1'b0) begin + data_out <= rst_in ; + end + else begin + if(cs && we[0]) data_out[7:0] <= data_in[7:0]; + if(cs && we[1]) data_out[15:8] <= data_in[15:8]; + if(cs && we[2]) data_out[23:16] <= data_in[23:16]; + if(cs && we[3]) data_out[31:24] <= data_in[31:24]; + end +end + + +endmodule
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv index 125bc29..4069ff2 100644 --- a/verilog/rtl/pinmux/src/glbl_reg.sv +++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -34,13 +34,34 @@ //// Revision : //// //// 0.1 - 16th Feb 2021, Dinesh A //// //// initial version //// +//// 0.2 - 28th Aug 2022, Dinesh A //// +//// Additional Mail Box Register added at addr 0xF //// ////////////////////////////////////////////////////////////////////// // +`include "user_params.svh" + module glbl_reg ( // System Signals // Inputs input logic mclk , - input logic h_reset_n , + input logic e_reset_n , // external reset + input logic p_reset_n , // power-on reset + input logic s_reset_n , // soft reset + + input logic [15:0] pad_strap_in , // strap from pad + + input logic user_clock1 , + input logic user_clock2 , + input logic int_pll_clock , + input logic xtal_clk , + + output logic usb_clk , + output logic rtc_clk , + + // to/from Global Reset FSM + input logic [31:0] system_strap , + output logic [31:0] strap_sticky , + // Global Reset control output logic [1:0] cpu_core_rst_n , @@ -54,7 +75,7 @@ // Reg Bus Interface Signal input logic reg_cs , input logic reg_wr , - input logic [3:0] reg_addr , + input logic [4:0] reg_addr , input logic [31:0] reg_wdata , input logic [3:0] reg_be , @@ -85,6 +106,7 @@ // Internal Wire Declarations //----------------------------------------------------------------------- +logic [15:0] strap_latch ; logic sw_rd_en ; logic sw_wr_en; logic [4:0] sw_addr; // addressing 16 registers @@ -92,19 +114,39 @@ logic [3:0] wr_be ; logic [31:0] reg_out; -logic [31:0] reg_0; // Chip ID -logic [31:0] reg_1; // Global Reg-0 -logic [31:0] reg_2; // Global Reg-1 -logic [31:0] reg_3; // Global Interrupt Mask -logic [31:0] reg_4; // Global Interrupt Status -logic [31:0] reg_5; // Multi Function Sel -logic [31:0] reg_6; // Software Reg-0 -logic [31:0] reg_7; // Software Reg-1 -logic [31:0] reg_8; // Software Reg-2 -logic [31:0] reg_9; // Software Reg-3 -logic [31:0] reg_10; // Software Reg-4 -logic [31:0] reg_11; // Software Reg-5 +logic [31:0] reg_0; // Chip ID +logic [31:0] reg_1; // Global Reg-0 +logic [31:0] reg_2; // Global Reg-1 +logic [31:0] reg_3; // Global Interrupt Mask +logic [31:0] reg_4; // Global Interrupt Status +logic [31:0] reg_5; // Multi Function Sel +logic [31:0] reg_6; // +logic [31:0] reg_7; // +logic [31:0] reg_8; // +logic [31:0] reg_9; // +logic [31:0] reg_10; // +logic [31:0] reg_11; // +logic [31:0] reg_12; // Latched Strap +logic [31:0] reg_13; // Strap Sticky +logic [31:0] reg_14; // System Strap +logic [31:0] reg_15; // MailBox Reg +logic [31:0] reg_16; // Software Reg-0 - p_reset +logic [31:0] reg_17; // Software Reg-1 - p_reset +logic [31:0] reg_18; // Software Reg-2 - p_reset +logic [31:0] reg_19; // Software Reg-3 - p_reset +logic [31:0] reg_20; // Software Reg-4 - s_reset +logic [31:0] reg_21; // Software Reg-5 - s_reset +logic [31:0] reg_22; // Software Reg-6 - s_reset +logic [31:0] reg_23; // Software Reg-7 - s_reset +logic [31:0] reg_24; // Reserved +logic [31:0] reg_25; // Reserved +logic [31:0] reg_26; // Reserved +logic [31:0] reg_27; // Reserved +logic [31:0] reg_28; // Reserved +logic [31:0] reg_29; // Reserved +logic [31:0] reg_30; // Reserved +logic [31:0] reg_31; // Reserved logic cs_int; @@ -116,9 +158,9 @@ assign sw_reg_wdata = reg_wdata; -always @ (posedge mclk or negedge h_reset_n) +always @ (posedge mclk or negedge s_reset_n) begin : preg_out_Seq - if (h_reset_n == 1'b0) begin + if (s_reset_n == 1'b0) begin reg_rdata <= 'h0; reg_ack <= 1'b0; end else if (reg_cs && !reg_ack) begin @@ -134,32 +176,71 @@ //----------------------------------------------------------------------- // register read enable and write enable decoding logic //----------------------------------------------------------------------- -wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0); -wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1); -wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2); -wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3); -wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4); -wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5); -wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6); -wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7); -wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8); -wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9); -wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA); -wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB); +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 5'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 5'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 5'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 5'h3); +wire sw_wr_en_4 = sw_wr_en & (sw_addr == 5'h4); +wire sw_wr_en_5 = sw_wr_en & (sw_addr == 5'h5); +wire sw_wr_en_6 = sw_wr_en & (sw_addr == 5'h6); +wire sw_wr_en_7 = sw_wr_en & (sw_addr == 5'h7); +wire sw_wr_en_8 = sw_wr_en & (sw_addr == 5'h8); +wire sw_wr_en_9 = sw_wr_en & (sw_addr == 5'h9); +wire sw_wr_en_10 = sw_wr_en & (sw_addr == 5'hA); +wire sw_wr_en_11 = sw_wr_en & (sw_addr == 5'hB); +wire sw_wr_en_12 = sw_wr_en & (sw_addr == 5'hC); +wire sw_wr_en_13 = sw_wr_en & (sw_addr == 5'hD); +wire sw_wr_en_14 = sw_wr_en & (sw_addr == 5'hE); +wire sw_wr_en_15 = sw_wr_en & (sw_addr == 5'hF); +wire sw_wr_en_16 = sw_wr_en & (sw_addr == 5'h10); +wire sw_wr_en_17 = sw_wr_en & (sw_addr == 5'h11); +wire sw_wr_en_18 = sw_wr_en & (sw_addr == 5'h12); +wire sw_wr_en_19 = sw_wr_en & (sw_addr == 5'h13); +wire sw_wr_en_20 = sw_wr_en & (sw_addr == 5'h14); +wire sw_wr_en_21 = sw_wr_en & (sw_addr == 5'h15); +wire sw_wr_en_22 = sw_wr_en & (sw_addr == 5'h16); +wire sw_wr_en_23 = sw_wr_en & (sw_addr == 5'h17); +wire sw_wr_en_24 = sw_wr_en & (sw_addr == 5'h18); +wire sw_wr_en_25 = sw_wr_en & (sw_addr == 5'h19); +wire sw_wr_en_26 = sw_wr_en & (sw_addr == 5'h1A); +wire sw_wr_en_27 = sw_wr_en & (sw_addr == 5'h1B); +wire sw_wr_en_28 = sw_wr_en & (sw_addr == 5'h1C); +wire sw_wr_en_29 = sw_wr_en & (sw_addr == 5'h1D); +wire sw_wr_en_30 = sw_wr_en & (sw_addr == 5'h1E); +wire sw_wr_en_31 = sw_wr_en & (sw_addr == 5'h1F); - -wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0); -wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1); -wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2); -wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3); -wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4); -wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5); -wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6); -wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7); -wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8); -wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9); -wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA); -wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB); +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 5'h0); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 5'h1); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 5'h2); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 5'h3); +wire sw_rd_en_4 = sw_rd_en & (sw_addr == 5'h4); +wire sw_rd_en_5 = sw_rd_en & (sw_addr == 5'h5); +wire sw_rd_en_6 = sw_rd_en & (sw_addr == 5'h6); +wire sw_rd_en_7 = sw_rd_en & (sw_addr == 5'h7); +wire sw_rd_en_8 = sw_rd_en & (sw_addr == 5'h8); +wire sw_rd_en_9 = sw_rd_en & (sw_addr == 5'h9); +wire sw_rd_en_10 = sw_rd_en & (sw_addr == 5'hA); +wire sw_rd_en_11 = sw_rd_en & (sw_addr == 5'hB); +wire sw_rd_en_12 = sw_rd_en & (sw_addr == 5'hC); +wire sw_rd_en_13 = sw_rd_en & (sw_addr == 5'hD); +wire sw_rd_en_14 = sw_rd_en & (sw_addr == 5'hE); +wire sw_rd_en_15 = sw_rd_en & (sw_addr == 5'hF); +wire sw_rd_en_16 = sw_rd_en & (sw_addr == 5'h10); +wire sw_rd_en_17 = sw_rd_en & (sw_addr == 5'h11); +wire sw_rd_en_18 = sw_rd_en & (sw_addr == 5'h12); +wire sw_rd_en_19 = sw_rd_en & (sw_addr == 5'h13); +wire sw_rd_en_20 = sw_rd_en & (sw_addr == 5'h14); +wire sw_rd_en_21 = sw_rd_en & (sw_addr == 5'h15); +wire sw_rd_en_22 = sw_rd_en & (sw_addr == 5'h16); +wire sw_rd_en_23 = sw_rd_en & (sw_addr == 5'h17); +wire sw_rd_en_24 = sw_rd_en & (sw_addr == 5'h18); +wire sw_rd_en_25 = sw_rd_en & (sw_addr == 5'h19); +wire sw_rd_en_26 = sw_rd_en & (sw_addr == 5'h1A); +wire sw_rd_en_27 = sw_rd_en & (sw_addr == 5'h1B); +wire sw_rd_en_28 = sw_rd_en & (sw_addr == 5'h1C); +wire sw_rd_en_29 = sw_rd_en & (sw_addr == 5'h1D); +wire sw_rd_en_30 = sw_rd_en & (sw_addr == 5'h1E); +wire sw_rd_en_31 = sw_rd_en & (sw_addr == 5'h1F); //----------------------------------------------------------------------- // Individual register assignments @@ -187,22 +268,35 @@ //------------------------------------------ // reg-1: GLBL_CFG_0 //------------------------------------------ -wire [31:0] cfg_glb_ctrl = reg_1; +wire [31:0] cfg_rst_ctrl = reg_1; -ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); -ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); -ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); -ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0])); -ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); -ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); -ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1])); +ctech_buf u_buf_cpu_intf_rst (.A(cfg_rst_ctrl[0]),.X(cpu_intf_rst_n)); +ctech_buf u_buf_qspim_rst (.A(cfg_rst_ctrl[1]),.X(qspim_rst_n)); +ctech_buf u_buf_sspim_rst (.A(cfg_rst_ctrl[2]),.X(sspim_rst_n)); +ctech_buf u_buf_uart0_rst (.A(cfg_rst_ctrl[3]),.X(uart_rst_n[0])); +ctech_buf u_buf_i2cm_rst (.A(cfg_rst_ctrl[4]),.X(i2cm_rst_n)); +ctech_buf u_buf_usb_rst (.A(cfg_rst_ctrl[5]),.X(usb_rst_n)); +ctech_buf u_buf_uart1_rst (.A(cfg_rst_ctrl[6]),.X(uart_rst_n[1])); -ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); -ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); +ctech_buf u_buf_cpu0_rst (.A(cfg_rst_ctrl[8]),.X(cpu_core_rst_n[0])); +ctech_buf u_buf_cpu1_rst (.A(cfg_rst_ctrl[9]),.X(cpu_core_rst_n[1])); -gen_32b_reg #(32'h0) u_reg_1 ( +//--------------------------------------------------------- +// Default reset value decided based on riscv boot mode +// +// bit [12] - Riscv Reset control +// 0 - Keep Riscv on Reset +// 1 - Removed Riscv on Power On Reset +// Default cpu_intf_rst_n & qspim_rst_n reset is removed +//--------------------------------------------------------- +wire strap_riscv_bmode = system_strap[`STRAP_RISCV_RESET_MODE]; +wire [31:0] rst_in = (strap_riscv_bmode) ? 32'h103 : 32'h03; + +glbl_rst_reg #(32'h0) u_reg_1 ( //List of Inputs - .reset_n (h_reset_n ), + .e_reset_n (e_reset_n ), + .s_reset_n (s_reset_n ), + .rst_in (rst_in ), .clk (mclk ), .cs (sw_wr_en_1 ), .we (wr_be ), @@ -216,9 +310,21 @@ // reg-2: GLBL_CFG_1 //------------------------------------------ -gen_32b_reg #(32'h0) u_reg_2 ( +wire [31:0] reg_2_rst_val = {4'h0, + system_strap[`STRAP_RISCV_CACHE_BYPASS], + system_strap[`STRAP_RISCV_CACHE_BYPASS], + 2'b0, + 1'b0, + 3'b0, + system_strap[`STRAP_RISCV_SRAM_CLK_EDGE], + system_strap[`STRAP_RISCV_SRAM_CLK_EDGE], + system_strap[`STRAP_RISCV_SRAM_CLK_EDGE], + system_strap[`STRAP_RISCV_SRAM_CLK_EDGE], + 16'h0}; +gen_32b_reg2 u_reg_2 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), + .rst_in (reg_2_rst_val ), .clk (mclk ), .cs (sw_wr_en_2 ), .we (wr_be ), @@ -238,7 +344,7 @@ gen_32b_reg #(32'h0) u_reg_3 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), .clk (mclk ), .cs (sw_wr_en_3 ), .we (wr_be ), @@ -257,10 +363,10 @@ wire [31:0] hware_intr_req = {gpio_intr[31:8], 3'b0,usb_intr, i2cm_intr,timer_intr[2:0]}; generic_intr_stat_reg #(.WD(32), - .RESET_DEFAULT(0)) u_reg4_be1 ( + .RESET_DEFAULT(0)) u_reg4 ( //inputs .clk (mclk ), - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), .reg_we ({{8{sw_wr_en_4 & reg_ack & wr_be[3]}}, {8{sw_wr_en_4 & reg_ack & wr_be[2]}}, {8{sw_wr_en_4 & reg_ack & wr_be[1]}}, @@ -281,10 +387,11 @@ //----------------------------------------------------------------------- assign cfg_multi_func_sel = reg_5[31:0]; // to be used for read +// bit[31] '1' - uart master enable on power up -gen_32b_reg #(32'h0) u_reg_5 ( +gen_32b_reg #(32'h8000_0000) u_reg_5 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), .clk (mclk ), .cs (sw_wr_en_5 ), .we (wr_be ), @@ -294,98 +401,186 @@ .data_out (reg_5 ) ); + //----------------------------------------- -// Software Reg-0 : ASCI Representation of RISC = 32'h8273_8343 +// Reg-6: Clock Control // ---------------------------------------- -gen_32b_reg #(32'h8273_8343) u_reg_6 ( +gen_32b_reg #(32'h0) u_reg_6 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), .clk (mclk ), - .cs (sw_wr_en_6 ), + .cs (sw_wr_en_6 ), .we (wr_be ), .data_in (sw_reg_wdata ), //List of Outs .data_out (reg_6 ) ); +wire [7:0] cfg_rtc_clk_ctrl = reg_6[7:0]; +wire [7:0] cfg_usb_clk_ctrl = reg_6[15:8]; + + +//------------------------------------------------- +// Strap control +//--------------------------------------------- +strap_ctrl u_strap ( + .clk (mclk ), + .e_reset_n (e_reset_n ), // external reset + .p_reset_n (p_reset_n ), // power-on reset + .s_reset_n (s_reset_n ), // soft reset + + .pad_strap_in (pad_strap_in), // strap from pad + //List of Inputs + .cs (sw_wr_en_13 ), + .we (wr_be ), + .data_in (sw_reg_wdata), + + //List of Outs + .strap_latch (strap_latch ), + .strap_sticky (strap_sticky) + ); + + +assign reg_12 = {16'h0,strap_latch}; +assign reg_13 = strap_sticky; +assign reg_14 = system_strap; + +//----------------------------------------- +// MailBox Register +// ---------------------------------------- +gen_32b_reg #(32'h0) u_reg_15 ( + //List of Inputs + .reset_n (s_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_15 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_15 ) + ); + + + +//----------------------------------------- +// Software Reg-0 : ASCI Representation of RISC = 32'h8273_8343 +// ---------------------------------------- +gen_32b_reg #(CHIP_SIGNATURE) u_reg_16 ( + //List of Inputs + .reset_n (p_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_16 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_16 ) + ); //----------------------------------------- // Software Reg-1, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h2408_2022) u_reg_7 ( +gen_32b_reg #(CHIP_RELEASE_DATE) u_reg_17 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (p_reset_n ), .clk (mclk ), - .cs (sw_wr_en_7 ), + .cs (sw_wr_en_17 ), .we (wr_be ), .data_in (sw_reg_wdata ), //List of Outs - .data_out (reg_7 ) + .data_out (reg_17 ) ); //----------------------------------------- -// Software Reg-2: Poject Revison 5.1 = 0005100 +// Software Reg-2: Poject Revison 5.1 = 0005200 // ---------------------------------------- -gen_32b_reg #(32'h0005_1000) u_reg_8 ( +gen_32b_reg #(CHIP_REVISION) u_reg_18 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (p_reset_n ), .clk (mclk ), - .cs (sw_wr_en_8 ), + .cs (sw_wr_en_18 ), .we (wr_be ), .data_in (sw_reg_wdata ), //List of Outs - .data_out (reg_8 ) + .data_out (reg_18 ) ); //----------------------------------------- // Software Reg-3 // ---------------------------------------- -gen_32b_reg #(32'h0) u_reg_9 ( +gen_32b_reg #(32'h0) u_reg_19 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), .clk (mclk ), - .cs (sw_wr_en_9 ), + .cs (sw_wr_en_19 ), .we (wr_be ), .data_in (sw_reg_wdata ), //List of Outs - .data_out (reg_9 ) + .data_out (reg_19 ) ); //----------------------------------------- // Software Reg-4 // ---------------------------------------- -gen_32b_reg #(32'h0) u_reg_10 ( +gen_32b_reg #(32'h0) u_reg_20 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), .clk (mclk ), - .cs (sw_wr_en_10 ), + .cs (sw_wr_en_20 ), .we (wr_be ), .data_in (sw_reg_wdata ), //List of Outs - .data_out (reg_10 ) + .data_out (reg_20 ) ); //----------------------------------------- // Software Reg-5 // ---------------------------------------- -gen_32b_reg #(32'h0) u_reg_11 ( +gen_32b_reg #(32'h0) u_reg_21 ( //List of Inputs - .reset_n (h_reset_n ), + .reset_n (s_reset_n ), .clk (mclk ), - .cs (sw_wr_en_11 ), + .cs (sw_wr_en_21 ), .we (wr_be ), .data_in (sw_reg_wdata ), //List of Outs - .data_out (reg_11 ) + .data_out (reg_21 ) ); +//----------------------------------------- +// Software Reg-6: +// ---------------------------------------- +gen_32b_reg #(32'h0) u_reg_22 ( + //List of Inputs + .reset_n (s_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_22 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_22 ) + ); - +//----------------------------------------- +// Software Reg-7 +// ---------------------------------------- +gen_32b_reg #(32'h0) u_reg_23 ( + //List of Inputs + .reset_n (s_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_23 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_23 ) + ); //----------------------------------------------------------------------- // Register Read Path Multiplexer instantiation //----------------------------------------------------------------------- @@ -394,22 +589,104 @@ begin reg_out [31:0] = 32'h0; - case (sw_addr [3:0]) - 4'b0000 : reg_out [31:0] = reg_0 [31:0]; - 4'b0001 : reg_out [31:0] = reg_1 [31:0]; - 4'b0010 : reg_out [31:0] = reg_2 [31:0]; - 4'b0011 : reg_out [31:0] = reg_3 [31:0]; - 4'b0100 : reg_out [31:0] = reg_4 [31:0]; - 4'b0101 : reg_out [31:0] = reg_5 [31:0]; - 4'b0110 : reg_out [31:0] = reg_6 [31:0]; - 4'b0111 : reg_out [31:0] = reg_7 [31:0]; - 4'b1000 : reg_out [31:0] = reg_8 [31:0]; - 4'b1001 : reg_out [31:0] = reg_9 [31:0]; - 4'b1010 : reg_out [31:0] = reg_10 [31:0]; - 4'b1011 : reg_out [31:0] = reg_11 [31:0]; + case (sw_addr [4:0]) + 5'b00000 : reg_out [31:0] = reg_0 ; + 5'b00001 : reg_out [31:0] = reg_1 ; + 5'b00010 : reg_out [31:0] = reg_2 ; + 5'b00011 : reg_out [31:0] = reg_3 ; + 5'b00100 : reg_out [31:0] = reg_4 ; + 5'b00101 : reg_out [31:0] = reg_5 ; + 5'b00110 : reg_out [31:0] = reg_6 ; + 5'b00111 : reg_out [31:0] = reg_7 ; + 5'b01000 : reg_out [31:0] = reg_8 ; + 5'b01001 : reg_out [31:0] = reg_9 ; + 5'b01010 : reg_out [31:0] = reg_10 ; + 5'b01011 : reg_out [31:0] = reg_11 ; + 5'b01100 : reg_out [31:0] = reg_12 ; + 5'b01101 : reg_out [31:0] = reg_13 ; + 5'b01110 : reg_out [31:0] = reg_14 ; + 5'b01111 : reg_out [31:0] = reg_15 ; + 5'b10000 : reg_out [31:0] = reg_16 ; + 5'b10001 : reg_out [31:0] = reg_17 ; + 5'b10010 : reg_out [31:0] = reg_18 ; + 5'b10011 : reg_out [31:0] = reg_19 ; + 5'b10100 : reg_out [31:0] = reg_20 ; + 5'b10101 : reg_out [31:0] = reg_21 ; + 5'b10110 : reg_out [31:0] = reg_22 ; + 5'b10111 : reg_out [31:0] = reg_23 ; + 5'b11000 : reg_out [31:0] = reg_24 ; + 5'b11001 : reg_out [31:0] = reg_25 ; + 5'b11010 : reg_out [31:0] = reg_26 ; + 5'b11011 : reg_out [31:0] = reg_27 ; + 5'b11100 : reg_out [31:0] = reg_28 ; + 5'b11101 : reg_out [31:0] = reg_29 ; + 5'b11110 : reg_out [31:0] = reg_30 ; + 5'b11111 : reg_out [31:0] = reg_31 ; default : reg_out [31:0] = 32'h0; endcase end +//---------------------------------- +// Generate RTC Clock Generation +//---------------------------------- +wire rtc_clk_div; +wire rtc_ref_clk_int; +wire rtc_ref_clk; +wire rtc_clk_int; + +wire [1:0] cfg_rtc_clk_sel_sel = cfg_rtc_clk_ctrl[7:6]; +wire cfg_rtc_clk_div = cfg_rtc_clk_ctrl[5]; +wire [4:0] cfg_rtc_clk_ratio = cfg_rtc_clk_ctrl[4:0]; + +assign rtc_ref_clk_int = (cfg_rtc_clk_sel_sel ==2'b00) ? user_clock1 : + (cfg_rtc_clk_sel_sel ==2'b01) ? user_clock2 : + (cfg_rtc_clk_sel_sel ==2'b01) ? int_pll_clock : xtal_clk; +ctech_clk_buf u_rtc_ref_clkbuf (.A (rtc_ref_clk_int), . X(rtc_ref_clk)); +//assign rtc_clk_int = (cfg_rtc_clk_div) ? rtc_clk_div : rtc_ref_clk; +ctech_mux2x1 u_rtc_clk_sel (.A0 (rtc_ref_clk), .A1 (rtc_clk_div), .S (cfg_rtc_clk_div), .X (rtc_clk_int)); + + +ctech_clk_buf u_clkbuf_rtc (.A (rtc_clk_int), . X(rtc_clk)); + +clk_ctl #(4) u_rtcclk ( + // Outputs + .clk_o (rtc_clk_div ), + // Inputs + .mclk (rtc_ref_clk ), + .reset_n (s_reset_n ), + .clk_div_ratio (cfg_rtc_clk_ratio) + ); + +//---------------------------------- +// Generate USB Clock Generation +//---------------------------------- +wire usb_clk_div; +wire usb_ref_clk_int; +wire usb_ref_clk; +wire usb_clk_int; + +wire [1:0] cfg_usb_clk_sel_sel = cfg_usb_clk_ctrl[7:6]; +wire cfg_usb_clk_div = cfg_usb_clk_ctrl[5]; +wire [4:0] cfg_usb_clk_ratio = cfg_usb_clk_ctrl[4:0]; + +assign usb_ref_clk_int = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 : + (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 : + (cfg_usb_clk_sel_sel ==2'b01) ? int_pll_clock : xtal_clk; +ctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk)); +//assign usb_clk_int = (cfg_usb_clk_div) ? usb_clk_div : usb_ref_clk; +ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S (cfg_usb_clk_div), .X (usb_clk_int)); + + +ctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk)); + +clk_ctl #(4) u_usbclk ( + // Outputs + .clk_o (usb_clk_div ), + // Inputs + .mclk (usb_ref_clk ), + .reset_n (s_reset_n ), + .clk_div_ratio (cfg_usb_clk_ratio) + ); + endmodule
diff --git a/verilog/rtl/pinmux/src/glbl_rst_reg.sv b/verilog/rtl/pinmux/src/glbl_rst_reg.sv new file mode 100644 index 0000000..cca7d0b --- /dev/null +++ b/verilog/rtl/pinmux/src/glbl_rst_reg.sv
@@ -0,0 +1,63 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// + +/******************************************************************************** + To handle reset removal on power up new logic is created, + One power up data_out will be reset value and one cycle later it will latch the rst_in. + +This will handle case when one of the bit of rst_n high, Still reset will be asserted in dataout +and one cycle latter it will get updated +**********************************************************************************/ + +module glbl_rst_reg ( + input logic e_reset_n, + input logic s_reset_n, + //List of Inputs + input logic [31:0] rst_in, + input logic cs, + input logic [3:0] we, + input logic [31:0] data_in, + input logic clk, + + //List of Outs + output logic [31:0]data_out + ); + + parameter RESET_DEFAULT = 32'h0; + +logic [31:0] data_out_l; + +always @ (posedge clk or negedge e_reset_n) begin + if (e_reset_n == 1'b0) begin + data_out <= RESET_DEFAULT ; + data_out_l <= 'h0 ; + end else if (s_reset_n == 1'b0) begin + data_out <= RESET_DEFAULT ; + data_out_l <= rst_in ; + end else begin + data_out <= data_out_l; + if(cs && we[0]) data_out_l[7:0] <= data_in[7:0]; + if(cs && we[1]) data_out_l[15:8] <= data_in[15:8]; + if(cs && we[2]) data_out_l[23:16] <= data_in[23:16]; + if(cs && we[3]) data_out_l[31:24] <= data_in[31:24]; + end +end + + +endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index caed827..f8143ed 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -36,64 +36,75 @@ //// Seperated the pinmux from pinmux_top module //// //// 0.2 - 21th Aug 2022, Dinesh A //// //// uart_master disable option added //// +//// 0.3 - 28th Aug 2022, Dinesh A //// +//// Due to caravel io[4:0] reserved on power up, we have//// +//// re-arrange the arduino pins from 5 onward //// ////////////////////////////////////////////////////////////////////// /************************************************ * Pin Mapping Arduino ATMGE CONFIG -* ATMEGA328 Port caravel Pin Mapping -* Pin-1 22 PC6/WS[0]/RESET* digital_io[0] -* Pin-2 0 PD0/WS[0]/RXD[0] digital_io[1] -* Pin-3 1 PD1/WS[0]/TXD[0] digital_io[2] -* Pin-4 2 PD2/WS[0]/RXD[1]/INT0 digital_io[3] -* Pin-5 3 PD3/WS[1]INT1/OC2B(PWM0) digital_io[4] -* Pin-6 4 PD4/WS[1]TXD[1] digital_io[5] +* ATMEGA328 Port caravel Pin Mapping +* Pin-1 22 PC6/WS[0]/RESET* digital_io[5] +* Pin-2 0 PD0/WS[0]/MRXD/RXD[0] digital_io[6] +* Pin-3 1 PD1/WS[0]/MRXD/TXD[0] digital_io[7] +* Pin-4 2 PD2/WS[0]/RXD[1]/INT0 digital_io[8] +* Pin-5 3 PD3/WS[1]INT1/OC2B(PWM0) digital_io[9] +* Pin-6 4 PD4/WS[1]TXD[1] digital_io[10] * Pin-7 VCC - * Pin-8 GND - -* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[6] -* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[7] -* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[8] -* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2] -* Pin-13 7 PD7/WS[2]/A1N1 digital_io[10]/analog_io[3] -* Pin-14 8 PB0/WS[2]/CLKO/ICP1 digital_io[11] -* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) digital_io[12] -* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[13] -* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[14] -* Pin-18 12 PB4/WS[3]/MISO digital_io[15] -* Pin-19 13 PB5/SCK digital_io[16] +* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[11] +* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[12] +* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 strap[0] digital_io[13] +* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 strap[1] digital_io[14]/analog_io[2] +* Pin-13 7 PD7/WS[2]/A1N1 strap[2] digital_io[15]/analog_io[3] +* Pin-14 8 PB0/WS[2]/CLKO/ICP1 strap[3] digital_io[16] +* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) strap[4] digital_io[17] +* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) strap[5] digital_io[18] +* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) strap[6] digital_io[19] +* Pin-18 12 PB4/WS[3]/MISO strap[7] digital_io[20] +* Pin-19 13 PB5/SCK digital_io[21] * Pin-20 AVCC - -* Pin-21 AREF analog_io[10] +* Pin-21 AREF analog_io[10] * Pin-22 GND - -* Pin-23 14 PC0/ADC0 digital_io[18]/analog_io[11] -* Pin-24 15 PC1/ADC1 digital_io[19]/analog_io[12] -* Pin-25 16 PC2/ADC2 digital_io[20]/analog_io[13] -* Pin-26 17 PC3/ADC3 digital_io[21]/analog_io[14] -* Pin-27 18 PC4/ADC4/SDA digital_io[22]/analog_io[15] -* Pin-28 19 PC5/ADC5/SCL digital_io[23]/analog_io[16] +* Pin-23 14 PC0/ADC0 digital_io[22]/analog_io[11] +* Pin-24 15 PC1/ADC1 digital_io[23]/analog_io[12] +* Pin-25 16 PC2/usb_dp/ADC2 digital_io[24]/analog_io[13] +* Pin-26 17 PC3/usb_dn/ADC3 digital_io[25]/analog_io[14] +* Pin-27 18 PC4/ADC4/SDA digital_io[26]/analog_io[15] +* Pin-28 19 PC5/ADC5/SCL digital_io[27]/analog_io[16] * * Additional Pad used for Externam ROM/RAM -* sflash_sck digital_io[24] -* sflash_ss[0] digital_io[25] -* sflash_ss[1] digital_io[26] -* sflash_ss[2] digital_io[27] -* sflash_ss[3] digital_io[28] -* sflash_io0 digital_io[29] -* sflash_io1 digital_io[30] -* sflash_io2 digital_io[31] -* sflash_io3 digital_io[32] -* dbg_clk_mon digital_io[33] -* uartm_rxd digital_io[34] -* uartm_txd digital_io[35] -* usb_dp digital_io[36] -* usb_dn digital_io[37] +* sflash_sck digital_io[28] +* sflash_ss[0] strap[8] digital_io[29] +* sflash_ss[1] strap[9] digital_io[30] +* sflash_ss[2] strap[10] digital_io[31] +* sflash_ss[3] strap[11] digital_io[32] +* sflash_io0 strap[12] digital_io[33] +* sflash_io1 strap[13] digital_io[34] +* sflash_io2 strap[14] digital_io[35] +* sflash_io3 strap[15] digital_io[36] +* dbg_clk_mon digital_io[37] +* These port are not available at power up +* PA0 digital_io[0] +* PA1 digital_io[1] +* PA2 digital_io[2] +* PA3 digital_io[3] +* PA4 digital_io[4] **************************************************************** * Pin-1 RESET is not supported as there is no suppport for fuse config + + **************/ module pinmux ( + input logic cfg_strap_pad_ctrl , // 1 - Keep the Pad in input direction + output logic [15:0] pad_strap_in , // Strap value // Digital IO output logic [37:0] digital_io_out , output logic [37:0] digital_io_oen , input logic [37:0] digital_io_in , + output logic xtal_clk , + // Config input logic [31:0] cfg_gpio_out_type ,// GPIO Type, 1 - WS_281X port input logic [31:0] cfg_gpio_dir_sel , @@ -173,6 +184,13 @@ wire [7:0] port_c_out; // PORT C Data Out wire [7:0] port_d_out; // PORT D Data Out +//-------------------------------------------------- +// Strap Pin Mapping +//-------------------------------------------------- +assign pad_strap_in = {digital_io_in[36:29],digital_io_in[20:13] }; + +assign xtal_clk = digital_io_in[11]; + // GPIO to PORT Mapping assign pad_gpio_in[7:0] = port_a_in; assign pad_gpio_in[15:8] = port_b_in; @@ -191,7 +209,8 @@ wire cfg_spim_enb = cfg_multi_func_sel[10]; wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11]; wire cfg_i2cm_enb = cfg_multi_func_sel[15]; -wire cfg_muart_dis = cfg_multi_func_sel[31:8]; // 0 - uart master enable, 1 - disable +wire cfg_usb_enb = cfg_multi_func_sel[16]; +wire cfg_muart_enb = cfg_multi_func_sel[31]; // 1 - uart master enable, wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0]; wire [7:0] cfg_port_b_dir_sel = cfg_gpio_dir_sel[15:8]; @@ -206,7 +225,7 @@ // This logic to create spi slave interface logic pin_resetn,spis_boot; -// On Reset internal SPI Master is disabled, If pin_reset = 0, then we are in +// On Reset internal SPI Master is disabled, If cfg_spim_enb = 0, then we are in // SPIS Boot Mode assign spis_boot = (cfg_spim_enb ) ? 1'b0: !pin_resetn; assign spis_ssn = (spis_boot ) ? pin_resetn : 1'b1; @@ -217,367 +236,395 @@ port_b_in = 'h0; port_c_in = 'h0; port_d_in = 'h0; - uart_rxd = 'h0; + uart_rxd = 'b1; ext_intr_in= 'h0; spim_mosi = 'h0; i2cm_data_i= 'h0; i2cm_clk_i = 'h0; + uartm_rxd = 'b1; - //Pin-1 PC6/RESET* digital_io[0] - port_c_in[6] = digital_io_in[0]; - pin_resetn = digital_io_in[0]; + //Pin-1 PC6/RESET* digital_io[5] + port_c_in[6] = digital_io_in[5]; + pin_resetn = digital_io_in[5]; - //Pin-2 PD0/RXD[0] digital_io[1] - port_d_in[0] = digital_io_in[1]; - if(cfg_uart_enb[0]) uart_rxd[0] = digital_io_in[1]; + //Pin-2 PD0/MRXD/RXD[0] digital_io[6] + port_d_in[0] = digital_io_in[6]; + if (cfg_muart_enb) uartm_rxd = digital_io_in[6]; + else if(cfg_uart_enb[0]) uart_rxd[0] = digital_io_in[6]; - //Pin-3 PD1/TXD[0] digital_io[2] - port_d_in[1] = digital_io_in[2]; + //Pin-3 PD1/MTXD/TXD[0] digital_io[7] + port_d_in[1] = digital_io_in[7]; - //Pin-4 PD2/RXD[1]/INT0 digital_io[3] - port_d_in[2] = digital_io_in[3]; - if(cfg_uart_enb[1]) uart_rxd[1] = digital_io_in[3]; - else if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3]; + //Pin-4 PD2/RXD[1]/INT0 digital_io[8] + port_d_in[2] = digital_io_in[8]; + if(cfg_uart_enb[1]) uart_rxd[1] = digital_io_in[8]; + else if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[8]; - //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] - port_d_in[3] = digital_io_in[4]; - if(cfg_int_enb[1]) ext_intr_in[1] = digital_io_in[4]; + //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[9] + port_d_in[3] = digital_io_in[9]; + if(cfg_int_enb[1]) ext_intr_in[1] = digital_io_in[9]; - //Pin-6 PD4/TXD[1] digital_io[5] - port_d_in[4] = digital_io_in[5]; + //Pin-6 PD4/TXD[1] digital_io[10] + port_d_in[4] = digital_io_in[10]; - //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] - port_b_in[6] = digital_io_in[6]; + //Pin-9 PB6/XTAL1/TOSC1 digital_io[11] + port_b_in[6] = digital_io_in[11]; - // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] - port_b_in[7] = digital_io_in[7]; + // Pin-10 PB7/XTAL2/TOSC2 digital_io[12] + port_b_in[7] = digital_io_in[12]; - //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] - port_d_in[5] = digital_io_in[8]; + //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[13] + port_d_in[5] = digital_io_in[13]; - //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] - port_d_in[6] = digital_io_in[9]; + //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[14] /analog_io[2] + port_d_in[6] = digital_io_in[14]; - //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] - port_d_in[7] = digital_io_in[10]; + //Pin-13 PD7/A1N1 digital_io[15]/analog_io[3] + port_d_in[7] = digital_io_in[15]; - //Pin-14 PB0/CLKO/ICP1 digital_io[11] - port_b_in[0] = digital_io_in[11]; + //Pin-14 PB0/CLKO/ICP1 digital_io[16] + port_b_in[0] = digital_io_in[16]; - //Pin-15 PB1/OC1A(PWM3) digital_io[12] - port_b_in[1] = digital_io_in[12]; + //Pin-15 PB1/OC1A(PWM3) digital_io[17] + port_b_in[1] = digital_io_in[17]; - //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] - port_b_in[2] = digital_io_in[13]; + //Pin-16 PB2/SS/OC1B(PWM4) digital_io[18] + port_b_in[2] = digital_io_in[18]; - //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] - port_b_in[3] = digital_io_in[14]; - if(cfg_spim_enb) spim_mosi = digital_io_in[14]; // SPIM MOSI (Input) = SPIS MISO (Output) + //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[19] + port_b_in[3] = digital_io_in[19]; + if(cfg_spim_enb) spim_mosi = digital_io_in[19]; // SPIM MOSI (Input) = SPIS MISO (Output) - //Pin-18 PB4/MISO digital_io[15] - port_b_in[4] = digital_io_in[15]; - spis_mosi = (spis_boot) ? digital_io_in[15] : 1'b0; // SPIM MISO (Output) = SPIS MOSI (Input) + //Pin-18 PB4/MISO digital_io[20] + port_b_in[4] = digital_io_in[20]; + spis_mosi = (spis_boot) ? digital_io_in[20] : 1'b0; // SPIM MISO (Output) = SPIS MOSI (Input) - //Pin-19 PB5/SCK digital_io[16] - port_b_in[5]= digital_io_in[16]; - spis_sck = (spis_boot) ? digital_io_in[16] : 1'b1; // SPIM SCK (Output) = SPIS SCK (Input) + //Pin-19 PB5/SCK digital_io[21] + port_b_in[5]= digital_io_in[21]; + spis_sck = (spis_boot) ? digital_io_in[21] : 1'b1; // SPIM SCK (Output) = SPIS SCK (Input) - //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] - port_c_in[0] = digital_io_in[18]; + //Pin-23 PC0/ADC0 digital_io[22]/analog_io[11] + port_c_in[0] = digital_io_in[22]; - //Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] - port_c_in[1] = digital_io_in[19]; + //Pin-24 PC1/ADC1 digital_io[23]/analog_io[12] + port_c_in[1] = digital_io_in[23]; - //Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] - port_c_in[2] = digital_io_in[20]; + //Pin-25 PC2/ADC2 digital_io[24]/usb_dp/analog_io[13] + usb_dp_i = (cfg_usb_enb) ? digital_io_in[24] : 1'b1; + port_c_in[2] = digital_io_in[24]; - //Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] - port_c_in[3] = digital_io_in[21]; + //Pin-26 PC3/ADC3 digital_io[25]/usb_dn/analog_io[14] + usb_dn_i = (cfg_usb_enb) ? digital_io_in[25] : 1'b1; + port_c_in[3] = digital_io_in[25]; - //Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] - port_c_in[4] = digital_io_in[22]; - if(cfg_i2cm_enb) i2cm_data_i = digital_io_in[22]; + //Pin-27 PC4/ADC4/SDA digital_io[26]/analog_io[15] + port_c_in[4] = digital_io_in[26]; + if(cfg_i2cm_enb) i2cm_data_i = digital_io_in[26]; - //Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] - port_c_in[5] = digital_io_in[23]; - if(cfg_i2cm_enb) i2cm_clk_i = digital_io_in[23]; + //Pin-28 PC5/ADC5/SCL digital_io[27]/analog_io[16] + port_c_in[5] = digital_io_in[27]; + if(cfg_i2cm_enb) i2cm_clk_i = digital_io_in[27]; - sflash_di[0] = digital_io_in[29]; - sflash_di[1] = digital_io_in[30]; - sflash_di[2] = digital_io_in[31]; - sflash_di[3] = digital_io_in[32]; + sflash_di[0] = digital_io_in[33]; + sflash_di[1] = digital_io_in[34]; + sflash_di[2] = digital_io_in[35]; + sflash_di[3] = digital_io_in[36]; + + port_a_in[0] = digital_io_in[0]; + port_a_in[1] = digital_io_in[1]; + port_a_in[2] = digital_io_in[2]; + port_a_in[3] = digital_io_in[3]; + port_a_in[4] = digital_io_in[4]; - // UAR MASTER I/F - uartm_rxd = (cfg_muart_dis) ? 1'b0 : digital_io_in[34]; - - usb_dp_i = digital_io_in[36]; - usb_dn_i = digital_io_in[37]; end // dataout selection always_comb begin digital_io_out = 'h0; - //Pin-1 PC6/WS[0]/RESET* digital_io[0] - if(cfg_port_c_port_type[6]) digital_io_out[0] = ws_txd[0]; - else if(cfg_port_c_dir_sel[6]) digital_io_out[0] = port_c_out[6]; + //Pin-1 PC6/WS[0]/RESET* digital_io[5] + if(cfg_port_c_port_type[6]) digital_io_out[5] = ws_txd[0]; + else if(cfg_port_c_dir_sel[6]) digital_io_out[5] = port_c_out[6]; - //Pin-2 PD0/WS[0]/RXD[0] digital_io[1] - if(cfg_port_d_port_type[0]) digital_io_out[1] = ws_txd[0]; - else if(cfg_port_d_dir_sel[0]) digital_io_out[1] = port_d_out[0]; + //Pin-2 PD0/WS[0]/MRXD/RXD[0] digital_io[6] + if(cfg_port_d_port_type[0]) digital_io_out[6] = ws_txd[0]; + else if(cfg_port_d_dir_sel[0]) digital_io_out[6] = port_d_out[0]; - //Pin-3 PD1/WS[0]/TXD[0] digital_io[2] - if (cfg_uart_enb[0]) digital_io_out[2] = uart_txd[0]; - else if(cfg_port_d_port_type[1]) digital_io_out[2] = ws_txd[0]; - else if(cfg_port_d_dir_sel[1]) digital_io_out[2] = port_d_out[1]; + //Pin-3 PD1/WS[0]/MTXD/TXD[0] digital_io[7] + if (cfg_muart_enb) digital_io_out[7] = uartm_txd; + else if(cfg_uart_enb[0]) digital_io_out[7] = uart_txd[0]; + else if(cfg_port_d_port_type[1]) digital_io_out[7] = ws_txd[0]; + else if(cfg_port_d_dir_sel[1]) digital_io_out[7] = port_d_out[1]; - //Pin-4 PD2/WS[0]/RXD[1]/INT0 digital_io[3] - if(cfg_port_d_port_type[2]) digital_io_out[3] = ws_txd[0]; - else if(cfg_port_d_dir_sel[2]) digital_io_out[3] = port_d_out[2]; + //Pin-4 PD2/WS[0]/RXD[1]/INT0 digital_io[8] + if(cfg_port_d_port_type[2]) digital_io_out[8] = ws_txd[0]; + else if(cfg_port_d_dir_sel[2]) digital_io_out[8] = port_d_out[2]; - //Pin-5 PD3/WS[1]INT1/OC2B(PWM0) digital_io[4] - if(cfg_pwm_enb[0]) digital_io_out[4] = pwm_wfm[0]; - else if(cfg_port_d_port_type[3])digital_io_out[4] = ws_txd[1]; - else if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3]; + //Pin-5 PD3/WS[1]INT1/OC2B(PWM0) digital_io[9] + if(cfg_pwm_enb[0]) digital_io_out[9] = pwm_wfm[0]; + else if(cfg_port_d_port_type[3])digital_io_out[9] = ws_txd[1]; + else if(cfg_port_d_dir_sel[3]) digital_io_out[9] = port_d_out[3]; - //Pin-6 PD4/WS[1]/TXD[1] digital_io[5] - if (cfg_uart_enb[1]) digital_io_out[5] = uart_txd[1]; - else if(cfg_port_d_port_type[4]) digital_io_out[5] = ws_txd[1]; - else if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4]; + //Pin-6 PD4/WS[1]/TXD[1] digital_io[10] + if (cfg_uart_enb[1]) digital_io_out[10] = uart_txd[1]; + else if(cfg_port_d_port_type[4]) digital_io_out[10] = ws_txd[1]; + else if(cfg_port_d_dir_sel[4]) digital_io_out[10] = port_d_out[4]; - //Pin-9 PB6/XTAL1/WS[1]/TOSC1 digital_io[6] - if(cfg_port_b_port_type[6]) digital_io_out[6] = ws_txd[1]; - else if(cfg_port_b_dir_sel[6]) digital_io_out[6] = port_b_out[6]; + //Pin-9 PB6/XTAL1/WS[1]/TOSC1 digital_io[11] + if(cfg_port_b_port_type[6]) digital_io_out[11] = ws_txd[1]; + else if(cfg_port_b_dir_sel[6]) digital_io_out[11] = port_b_out[6]; - // Pin-10 PB7/XTAL2/WS[1]/TOSC2 digital_io[7] - if(cfg_port_b_port_type[7]) digital_io_out[7] = ws_txd[1]; - else if(cfg_port_b_dir_sel[7]) digital_io_out[7] = port_b_out[7]; + // Pin-10 PB7/XTAL2/WS[1]/TOSC2 digital_io[12] + if(cfg_port_b_port_type[7]) digital_io_out[12] = ws_txd[1]; + else if(cfg_port_b_dir_sel[7]) digital_io_out[12] = port_b_out[7]; - //Pin-11 PD5/SS[3]/WS[2]/OC0B(PWM1)/T1 digital_io[8] - if(cfg_pwm_enb[1]) digital_io_out[8] = pwm_wfm[1]; - else if(cfg_spim_cs_enb[3]) digital_io_out[8] = spim_ssn[3]; - else if(cfg_port_d_port_type[5])digital_io_out[8] = ws_txd[2]; - else if(cfg_port_d_dir_sel[5]) digital_io_out[8] = port_d_out[5]; + //Pin-11 PD5/SS[3]/WS[2]/OC0B(PWM1)/T1 digital_io[13] + if(cfg_pwm_enb[1]) digital_io_out[13] = pwm_wfm[1]; + else if(cfg_spim_cs_enb[3]) digital_io_out[13] = spim_ssn[3]; + else if(cfg_port_d_port_type[5])digital_io_out[13] = ws_txd[2]; + else if(cfg_port_d_dir_sel[5]) digital_io_out[13] = port_d_out[5]; - //Pin-12 PD6/SS[2]/WS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] - if(cfg_pwm_enb[2]) digital_io_out[9] = pwm_wfm[2]; - else if(cfg_spim_cs_enb[2]) digital_io_out[9] = spim_ssn[2]; - else if(cfg_port_d_port_type[6])digital_io_out[9] = ws_txd[2]; - else if(cfg_port_d_dir_sel[6]) digital_io_out[9] = port_d_out[6]; + //Pin-12 PD6/SS[2]/WS[2]/OC0A(PWM2)/AIN0 digital_io[14] /analog_io[2] + if(cfg_pwm_enb[2]) digital_io_out[14] = pwm_wfm[2]; + else if(cfg_spim_cs_enb[2]) digital_io_out[14] = spim_ssn[2]; + else if(cfg_port_d_port_type[6])digital_io_out[14] = ws_txd[2]; + else if(cfg_port_d_dir_sel[6]) digital_io_out[14] = port_d_out[6]; - //Pin-13 PD7/A1N1/WS[2] digital_io[10]/analog_io[3] - if(cfg_port_d_port_type[7]) digital_io_out[10] = ws_txd[2]; - else if(cfg_port_d_dir_sel[7]) digital_io_out[10] = port_d_out[7]; + //Pin-13 PD7/A1N1/WS[2] digital_io[15]/analog_io[3] + if(cfg_port_d_port_type[7]) digital_io_out[15] = ws_txd[2]; + else if(cfg_port_d_dir_sel[7]) digital_io_out[15] = port_d_out[7]; - //Pin-14 PB0/CLKO/WS[2]/ICP1 digital_io[11] - if(cfg_port_b_port_type[0]) digital_io_out[11] = ws_txd[2]; - else if(cfg_port_b_dir_sel[0]) digital_io_out[11] = port_b_out[0]; + //Pin-14 PB0/CLKO/WS[2]/ICP1 digital_io[16] + if(cfg_port_b_port_type[0]) digital_io_out[16] = ws_txd[2]; + else if(cfg_port_b_dir_sel[0]) digital_io_out[16] = port_b_out[0]; - //Pin-15 PB1/SS[1]/WS[3]/OC1A(PWM3) digital_io[12] - if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3]; - else if(cfg_spim_cs_enb[1]) digital_io_out[12] = spim_ssn[1]; - else if(cfg_port_b_port_type[1])digital_io_out[12] = ws_txd[3]; - else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1]; + //Pin-15 PB1/SS[1]/WS[3]/OC1A(PWM3) digital_io[17] + if(cfg_pwm_enb[3]) digital_io_out[17] = pwm_wfm[3]; + else if(cfg_spim_cs_enb[1]) digital_io_out[17] = spim_ssn[1]; + else if(cfg_port_b_port_type[1])digital_io_out[17] = ws_txd[3]; + else if(cfg_port_b_dir_sel[1]) digital_io_out[17] = port_b_out[1]; - //Pin-16 PB2/SS[0]/WS[3]/OC1B(PWM4) digital_io[13] - if(cfg_pwm_enb[4]) digital_io_out[13] = pwm_wfm[4]; - else if(cfg_spim_cs_enb[0]) digital_io_out[13] = spim_ssn[0]; - else if(cfg_port_b_port_type[2])digital_io_out[13] = ws_txd[3]; - else if(cfg_port_b_dir_sel[2]) digital_io_out[13] = port_b_out[2]; + //Pin-16 PB2/SS[0]/WS[3]/OC1B(PWM4) digital_io[18] + if(cfg_pwm_enb[4]) digital_io_out[18] = pwm_wfm[4]; + else if(cfg_spim_cs_enb[0]) digital_io_out[18] = spim_ssn[0]; + else if(cfg_port_b_port_type[2])digital_io_out[18] = ws_txd[3]; + else if(cfg_port_b_dir_sel[2]) digital_io_out[18] = port_b_out[2]; - //Pin-17 PB3/MOSI/WS[3]/OC2A(PWM5) digital_io[14] - if(cfg_pwm_enb[5]) digital_io_out[14] = pwm_wfm[5]; - else if(cfg_port_b_port_type[3]) digital_io_out[14] = ws_txd[3]; - else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3]; - else if(spis_boot) digital_io_out[14] = spis_miso; // SPIM MOSI (Input) = SPIS MISO (Output) + //Pin-17 PB3/MOSI/WS[3]/OC2A(PWM5) digital_io[19] + if(cfg_pwm_enb[5]) digital_io_out[19] = pwm_wfm[5]; + else if(cfg_port_b_port_type[3]) digital_io_out[19] = ws_txd[3]; + else if(cfg_port_b_dir_sel[3]) digital_io_out[19] = port_b_out[3]; + else if(spis_boot) digital_io_out[19] = spis_miso; // SPIM MOSI (Input) = SPIS MISO (Output) - //Pin-18 PB4/WS[3]/MISO digital_io[15] - if(cfg_spim_enb) digital_io_out[15] = spim_miso; // SPIM MISO (Output) = SPIS MOSI (Input) - else if(cfg_port_b_port_type[4])digital_io_out[15] = ws_txd[3]; - else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4]; + //Pin-18 PB4/WS[3]/MISO digital_io[20] + if(cfg_spim_enb) digital_io_out[20] = spim_miso; // SPIM MISO (Output) = SPIS MOSI (Input) + else if(cfg_port_b_port_type[4])digital_io_out[20] = ws_txd[3]; + else if(cfg_port_b_dir_sel[4]) digital_io_out[20] = port_b_out[4]; - //Pin-19 PB5/SCK digital_io[16] - if(cfg_spim_enb) digital_io_out[16] = spim_sck; // SPIM SCK (Output) = SPIS SCK (Input) - else if(cfg_port_b_dir_sel[5]) digital_io_out[16] = port_b_out[5]; + //Pin-19 PB5/SCK digital_io[21] + if(cfg_spim_enb) digital_io_out[21] = spim_sck; // SPIM SCK (Output) = SPIS SCK (Input) + else if(cfg_port_b_dir_sel[5]) digital_io_out[21] = port_b_out[5]; - //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] - if(cfg_port_c_dir_sel[0]) digital_io_out[18] = port_c_out[0]; + //Pin-23 PC0/ADC0 digital_io[22]/analog_io[11] + if(cfg_port_c_dir_sel[0]) digital_io_out[22] = port_c_out[0]; - //Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] - if(cfg_port_c_dir_sel[1]) digital_io_out[19] = port_c_out[1]; + //Pin-24 PC1/ADC1 digital_io[23]/analog_io[12] + if(cfg_port_c_dir_sel[1]) digital_io_out[23] = port_c_out[1]; - //Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] - if(cfg_port_c_dir_sel[2]) digital_io_out[20] = port_c_out[2]; + //Pin-25 PC2/USB_DP/ADC2 digital_io[24]/analog_io[13] + if(cfg_usb_enb) digital_io_out[24] = usb_dp_o; + else if(cfg_port_c_dir_sel[2]) digital_io_out[24] = port_c_out[2]; - //Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] - if(cfg_port_c_dir_sel[3]) digital_io_out[21] = port_c_out[3]; + //Pin-26 PC3/USB_DN/ADC3 digital_io[25]/analog_io[14] + if(cfg_usb_enb) digital_io_out[25] = usb_dn_o; + if(cfg_port_c_dir_sel[3]) digital_io_out[25] = port_c_out[3]; - //Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] - if(cfg_i2cm_enb) digital_io_out[22] = i2cm_data_o; - else if(cfg_port_c_dir_sel[4]) digital_io_out[22] = port_c_out[4]; + //Pin-27 PC4/ADC4/SDA digital_io[26]/analog_io[15] + if(cfg_i2cm_enb) digital_io_out[26] = i2cm_data_o; + else if(cfg_port_c_dir_sel[4]) digital_io_out[26] = port_c_out[4]; - //Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] - if(cfg_i2cm_enb) digital_io_out[23] = i2cm_clk_o; - else if(cfg_port_c_dir_sel[5]) digital_io_out[23] = port_c_out[5]; + //Pin-28 PC5/ADC5/SCL digital_io[27]/analog_io[16] + if(cfg_i2cm_enb) digital_io_out[27] = i2cm_clk_o; + else if(cfg_port_c_dir_sel[5]) digital_io_out[27] = port_c_out[5]; // Serial Flash - digital_io_out[24] = sflash_sck ; - digital_io_out[25] = sflash_ss[0] ; - digital_io_out[26] = sflash_ss[1] ; - digital_io_out[27] = sflash_ss[2] ; - digital_io_out[28] = sflash_ss[3] ; - digital_io_out[29] = sflash_do[0] ; - digital_io_out[30] = sflash_do[1] ; - digital_io_out[31] = sflash_do[2] ; - digital_io_out[32] = sflash_do[3] ; + digital_io_out[28] = sflash_sck ; + digital_io_out[29] = sflash_ss[0] ; + digital_io_out[30] = sflash_ss[1] ; + digital_io_out[31] = sflash_ss[2] ; + digital_io_out[32] = sflash_ss[3] ; + digital_io_out[33] = sflash_do[0] ; + digital_io_out[34] = sflash_do[1] ; + digital_io_out[35] = sflash_do[2] ; + digital_io_out[36] = sflash_do[3] ; // dbg_clk_mon - Pll clock output monitor - digital_io_out[33] = dbg_clk_mon; + digital_io_out[37] = dbg_clk_mon; - // UART MASTER I/f - digital_io_out[34] = 1'b0 ; // RXD - digital_io_out[35] = uartm_txd ; // TXD - - // USB 1.1 - digital_io_out[36] = usb_dp_o ; - digital_io_out[37] = usb_dn_o ; + digital_io_out[0] = port_a_out[0] ; + digital_io_out[1] = port_a_out[1] ; + digital_io_out[2] = port_a_out[2] ; + digital_io_out[3] = port_a_out[3] ; + digital_io_out[4] = port_a_out[4] ; end // dataoen selection always_comb begin digital_io_oen = 38'h3F_FFFF_FFFF; - //Pin-1 PC6/WS[0]/RESET* digital_io[0] - if(cfg_port_c_port_type[6]) digital_io_oen[0] = 1'b1; - else if(cfg_port_c_dir_sel[6]) digital_io_oen[0] = 1'b0; - //Pin-2 PD0/WS[0]/RXD[0] digital_io[1] - if (cfg_uart_enb[0]) digital_io_oen[1] = 1'b1; - else if(cfg_port_d_port_type[0])digital_io_oen[1] = 1'b1; - else if(cfg_port_d_dir_sel[0]) digital_io_oen[1] = 1'b0; + //Pin-1 PC6/WS[0]/RESET* digital_io[5] + if(cfg_port_c_port_type[6]) digital_io_oen[5] = 1'b1; + else if(cfg_port_c_dir_sel[6]) digital_io_oen[5] = 1'b0; - //Pin-3 PD1/WS[0]/TXD[0] digital_io[2] - if (cfg_uart_enb[0]) digital_io_oen[2] = 1'b0; - else if(cfg_port_d_port_type[1])digital_io_oen[2] = 1'b1; - else if(cfg_port_d_dir_sel[1]) digital_io_oen[2] = 1'b0; + //Pin-2 PD0/WS[0]/MRXD/RXD[0] digital_io[6] + if (cfg_muart_enb) digital_io_oen[6] = 1'b1; + else if(cfg_uart_enb[0]) digital_io_oen[6] = 1'b1; + else if(cfg_port_d_port_type[0])digital_io_oen[6] = 1'b1; + else if(cfg_port_d_dir_sel[0]) digital_io_oen[6] = 1'b0; - //Pin-4 PD2/WS[0]/RXD[1]/INT0 digital_io[3] - if (cfg_uart_enb[1]) digital_io_oen[3] = 1'b1; - else if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1; - else if(cfg_port_d_port_type[2])digital_io_oen[3] = 1'b1; - else if(cfg_port_d_dir_sel[2]) digital_io_oen[3] = 1'b0; + //Pin-3 PD1/WS[0]/MTXD/TXD[0] digital_io[7] + if (cfg_muart_enb) digital_io_oen[7] = 1'b0; + else if(cfg_uart_enb[0]) digital_io_oen[7] = 1'b0; + else if(cfg_port_d_port_type[1])digital_io_oen[7] = 1'b1; + else if(cfg_port_d_dir_sel[1]) digital_io_oen[7] = 1'b0; - //Pin-5 PD3/WS[1]/INT1/OC2B(PWM0) digital_io[4] - if(cfg_pwm_enb[0]) digital_io_oen[4] = 1'b0; - else if(cfg_int_enb[1]) digital_io_oen[4] = 1'b1; - else if(cfg_port_d_port_type[3])digital_io_oen[4] = 1'b1; - else if(cfg_port_d_dir_sel[3]) digital_io_oen[4] = 1'b0; + //Pin-4 PD2/WS[0]/RXD[1]/INT0 digital_io[8] + if(cfg_int_enb[0]) digital_io_oen[8] = 1'b1; + else if(cfg_port_d_port_type[2])digital_io_oen[8] = 1'b1; + else if(cfg_port_d_dir_sel[2]) digital_io_oen[8] = 1'b0; - //Pin-6 PD4/WS[1]/TXD[1] digital_io[5] - if (cfg_uart_enb[1]) digital_io_oen[5] = 1'b0; - else if(cfg_port_d_port_type[4])digital_io_oen[5] = 1'b1; - else if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0; + //Pin-5 PD3/WS[1]/INT1/OC2B(PWM0) digital_io[9] + if(cfg_pwm_enb[0]) digital_io_oen[9] = 1'b0; + else if(cfg_int_enb[1]) digital_io_oen[9] = 1'b1; + else if(cfg_port_d_port_type[3])digital_io_oen[9] = 1'b1; + else if(cfg_port_d_dir_sel[3]) digital_io_oen[9] = 1'b0; - //Pin-9 PB6/WS[1]/XTAL1/TOSC1 digital_io[6] - if(cfg_port_b_port_type[6]) digital_io_oen[6] = 1'b1; - else if(cfg_port_b_dir_sel[6]) digital_io_oen[6] = 1'b0; + //Pin-6 PD4/WS[1]/TXD[1] digital_io[10] + if (cfg_uart_enb[1]) digital_io_oen[10] = 1'b0; + else if(cfg_port_d_port_type[4])digital_io_oen[10] = 1'b1; + else if(cfg_port_d_dir_sel[4]) digital_io_oen[10] = 1'b0; - // Pin-10 PB7/WS[1]/XTAL2/TOSC2 digital_io[7] - if(cfg_port_b_port_type[7]) digital_io_oen[7] = 1'b1; - else if(cfg_port_b_dir_sel[7]) digital_io_oen[7] = 1'b0; + //Pin-9 PB6/WS[1]/XTAL1/TOSC1 digital_io[11] + if (cfg_uart_enb[1]) digital_io_oen[11] = 1'b1; + else if(cfg_port_b_port_type[6]) digital_io_oen[11] = 1'b1; + else if(cfg_port_b_dir_sel[6]) digital_io_oen[11] = 1'b0; - //Pin-11 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[8] - if(cfg_pwm_enb[1]) digital_io_oen[8] = 1'b0; - else if(cfg_spim_cs_enb[3]) digital_io_oen[8] = 1'b0; - else if(cfg_port_d_port_type[5])digital_io_oen[8] = 1'b1; - else if(cfg_port_d_dir_sel[5]) digital_io_oen[8] = 1'b0; + // Pin-10 PB7/WS[1]/XTAL2/TOSC2 digital_io[12] + if(cfg_port_b_port_type[7]) digital_io_oen[12] = 1'b1; + else if(cfg_port_b_dir_sel[7]) digital_io_oen[12] = 1'b0; - //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] - if(cfg_pwm_enb[2]) digital_io_oen[9] = 1'b0; - else if(cfg_spim_cs_enb[2]) digital_io_oen[9] = 1'b0; - else if(cfg_port_d_port_type[6])digital_io_oen[9] = 1'b1; - else if(cfg_port_d_dir_sel[6]) digital_io_oen[9] = 1'b0; + //Pin-11 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[13] + if(cfg_strap_pad_ctrl) digital_io_oen[13] = 1'b1; + else if(cfg_pwm_enb[1]) digital_io_oen[13] = 1'b0; + else if(cfg_spim_cs_enb[3]) digital_io_oen[13] = 1'b0; + else if(cfg_port_d_port_type[5])digital_io_oen[13] = 1'b1; + else if(cfg_port_d_dir_sel[5]) digital_io_oen[13] = 1'b0; - //Pin-13 PD7/WS[2]/A1N1 digital_io[10]/analog_io[3] - if(cfg_port_d_port_type[7]) digital_io_oen[10] = 1'b1; - else if(cfg_port_d_dir_sel[7]) digital_io_oen[10] = 1'b0; + //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[14] /analog_io[2] + if(cfg_strap_pad_ctrl) digital_io_oen[14] = 1'b1; + else if(cfg_pwm_enb[2]) digital_io_oen[14] = 1'b0; + else if(cfg_spim_cs_enb[2]) digital_io_oen[14] = 1'b0; + else if(cfg_port_d_port_type[6])digital_io_oen[14] = 1'b1; + else if(cfg_port_d_dir_sel[6]) digital_io_oen[14] = 1'b0; + + //Pin-13 PD7/WS[2]/A1N1 digital_io[15]/analog_io[3] + if(cfg_strap_pad_ctrl) digital_io_oen[15] = 1'b1; + else if(cfg_port_d_port_type[7])digital_io_oen[15] = 1'b1; + else if(cfg_port_d_dir_sel[7]) digital_io_oen[15] = 1'b0; - //Pin-14 PB0/WS[2]/CLKO/ICP1 digital_io[11] - if(cfg_port_b_port_type[0]) digital_io_oen[11] = 1'b1; - else if(cfg_port_b_dir_sel[0]) digital_io_oen[11] = 1'b0; + //Pin-14 PB0/WS[2]/CLKO/ICP1 digital_io[16] + if(cfg_strap_pad_ctrl) digital_io_oen[16] = 1'b1; + else if(cfg_port_b_port_type[0])digital_io_oen[16] = 1'b1; + else if(cfg_port_b_dir_sel[0]) digital_io_oen[16] = 1'b0; - //Pin-15 PB1/WS[3]/SS[1]/OC1A(PWM3) digital_io[12] - if(cfg_pwm_enb[3]) digital_io_oen[12] = 1'b0; - else if(cfg_spim_cs_enb[1]) digital_io_oen[12] = 1'b0; - else if(cfg_port_b_port_type[1])digital_io_oen[12] = 1'b1; - else if(cfg_port_b_dir_sel[1]) digital_io_oen[12] = 1'b0; + //Pin-15 PB1/WS[3]/SS[1]/OC1A(PWM3) digital_io[17] + if(cfg_strap_pad_ctrl) digital_io_oen[17] = 1'b1; + else if(cfg_pwm_enb[3]) digital_io_oen[17] = 1'b0; + else if(cfg_spim_cs_enb[1]) digital_io_oen[17] = 1'b0; + else if(cfg_port_b_port_type[1])digital_io_oen[17] = 1'b1; + else if(cfg_port_b_dir_sel[1]) digital_io_oen[17] = 1'b0; - //Pin-16 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[13] - if(cfg_pwm_enb[4]) digital_io_oen[13] = 1'b0; - else if(cfg_spim_cs_enb[0]) digital_io_oen[13] = 1'b0; - else if(cfg_port_b_port_type[2])digital_io_oen[13] = 1'b1; - else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0; + //Pin-16 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[18] + if(cfg_strap_pad_ctrl) digital_io_oen[18] = 1'b1; + else if(cfg_pwm_enb[4]) digital_io_oen[18] = 1'b0; + else if(cfg_spim_cs_enb[0]) digital_io_oen[18] = 1'b0; + else if(cfg_port_b_port_type[2])digital_io_oen[18] = 1'b1; + else if(cfg_port_b_dir_sel[2]) digital_io_oen[18] = 1'b0; - //Pin-17 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[14] - if(cfg_spim_enb) digital_io_oen[14] = 1'b1; // SPIM MOSI (Input) - else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0; - else if(cfg_port_b_port_type[3])digital_io_oen[14] = 1'b1; - else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0; - else if(spis_boot) digital_io_oen[14] = 1'b0; // SPIS MISO (Output) + //Pin-17 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[19] + if(cfg_strap_pad_ctrl) digital_io_oen[19] = 1'b1; + else if(cfg_spim_enb) digital_io_oen[19] = 1'b1; // SPIM MOSI (Input) + else if(cfg_pwm_enb[5]) digital_io_oen[19] = 1'b0; + else if(cfg_port_b_port_type[3])digital_io_oen[19] = 1'b1; + else if(cfg_port_b_dir_sel[3]) digital_io_oen[19] = 1'b0; + else if(spis_boot) digital_io_oen[19] = 1'b0; // SPIS MISO (Output) - //Pin-18 PB4/WS[3]/MISO digital_io[15] - if(cfg_spim_enb) digital_io_oen[15] = 1'b0; // SPIM MISO (Output) - else if(cfg_port_b_port_type[4])digital_io_oen[15] = 1'b1; - else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0; - else if(spis_boot) digital_io_oen[15] = 1'b1; // SPIS MOSI (Input) + //Pin-18 PB4/WS[3]/MISO digital_io[20] + if(cfg_strap_pad_ctrl) digital_io_oen[20] = 1'b1; + else if(cfg_spim_enb) digital_io_oen[20] = 1'b0; // SPIM MISO (Output) + else if(cfg_port_b_port_type[4])digital_io_oen[20] = 1'b1; + else if(cfg_port_b_dir_sel[4]) digital_io_oen[20] = 1'b0; + else if(spis_boot) digital_io_oen[20] = 1'b1; // SPIS MOSI (Input) - //Pin-19 PB5/SCK digital_io[16] - if(cfg_spim_enb) digital_io_oen[16] = 1'b0; // SPIM SCK (Output) - else if(cfg_port_b_dir_sel[5]) digital_io_oen[16] = 1'b0; - else if(spis_boot) digital_io_oen[16] = 1'b1; // SPIS SCK (Input) + //Pin-19 PB5/SCK digital_io[21] + if(cfg_spim_enb) digital_io_oen[21] = 1'b0; // SPIM SCK (Output) + else if(cfg_port_b_dir_sel[5]) digital_io_oen[21] = 1'b0; + else if(spis_boot) digital_io_oen[21] = 1'b1; // SPIS SCK (Input) - //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] - if(cfg_port_c_dir_sel[0]) digital_io_oen[18] = 1'b0; + //Pin-23 PC0/ADC0 digital_io[22]/analog_io[11] + if(cfg_port_c_dir_sel[0]) digital_io_oen[22] = 1'b0; - //Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] - if(cfg_port_c_dir_sel[1]) digital_io_oen[19] = 1'b0; + //Pin-24 PC1/ADC1 digital_io[23]/analog_io[12] + if(cfg_port_c_dir_sel[1]) digital_io_oen[23] = 1'b0; - //Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] - if(cfg_port_c_dir_sel[2]) digital_io_oen[20] = 1'b0; + //Pin-25 PC2/USB_DP/ADC2 digital_io[24]/analog_io[13] + if(cfg_usb_enb) digital_io_oen[24] = usb_oen; + else if(cfg_port_c_dir_sel[2]) digital_io_oen[24] = 1'b0; - //Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] - if(cfg_port_c_dir_sel[3]) digital_io_oen[21] = 1'b0; + //Pin-26 PC3/USB_DN/ADC3 digital_io[25]/analog_io[14] + if(cfg_usb_enb) digital_io_oen[25] = usb_oen; + else if(cfg_port_c_dir_sel[3]) digital_io_oen[25] = 1'b0; - //Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] - if(cfg_i2cm_enb) digital_io_oen[22] = i2cm_data_oen; - else if(cfg_port_c_dir_sel[4]) digital_io_oen[22] = 1'b0; + //Pin-27 PC4/ADC4/SDA digital_io[26]/analog_io[15] + if(cfg_i2cm_enb) digital_io_oen[26] = i2cm_data_oen; + else if(cfg_port_c_dir_sel[4]) digital_io_oen[26] = 1'b0; - //Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] - if(cfg_i2cm_enb) digital_io_oen[23] = i2cm_clk_oen; - else if(cfg_port_c_dir_sel[5]) digital_io_oen[23] = 1'b0; + //Pin-28 PC5/ADC5/SCL digital_io[27]/analog_io[16] + if(cfg_i2cm_enb) digital_io_oen[27] = i2cm_clk_oen; + else if(cfg_port_c_dir_sel[5]) digital_io_oen[27] = 1'b0; // Serial Flash - digital_io_oen[24] = 1'b0 ; - digital_io_oen[25] = 1'b0 ; - digital_io_oen[26] = 1'b0 ; - digital_io_oen[27] = 1'b0 ; - digital_io_oen[28] = 1'b0 ; - digital_io_oen[29] = sflash_oen[0]; - digital_io_oen[30] = sflash_oen[1]; - digital_io_oen[31] = sflash_oen[2]; - digital_io_oen[32] = sflash_oen[3]; + if(cfg_strap_pad_ctrl) digital_io_oen[28] = 1'b1; + else digital_io_oen[28] = 1'b0; + if(cfg_strap_pad_ctrl) digital_io_oen[29] = 1'b1; + else digital_io_oen[29] = 1'b0; + if(cfg_strap_pad_ctrl) digital_io_oen[30] = 1'b1; + else digital_io_oen[30] = 1'b0; + if(cfg_strap_pad_ctrl) digital_io_oen[31] = 1'b1; + else digital_io_oen[31] = 1'b0; + if(cfg_strap_pad_ctrl) digital_io_oen[32] = 1'b1; + else digital_io_oen[32] = 1'b0; + if(cfg_strap_pad_ctrl) digital_io_oen[33] = 1'b1; + else digital_io_oen[33] = sflash_oen[0]; + if(cfg_strap_pad_ctrl) digital_io_oen[34] = 1'b1; + else digital_io_oen[34] = sflash_oen[1]; + if(cfg_strap_pad_ctrl) digital_io_oen[35] = 1'b1; + else digital_io_oen[35] = sflash_oen[2]; + if(cfg_strap_pad_ctrl) digital_io_oen[36] = 1'b1; + else digital_io_oen[36] = sflash_oen[3]; // dbg_clk_mon - digital_io_oen[33] = 1'b0 ; - // UART MASTER - digital_io_oen[34] = 1'b1; // RXD - digital_io_oen[35] = cfg_muart_dis; // TXD + if(cfg_strap_pad_ctrl) digital_io_oen[37] = 1'b1; + else digital_io_oen[37] = 1'b0 ; - // USB 1.1 - digital_io_oen[36] = usb_oen; - digital_io_oen[37] = usb_oen; + if(cfg_port_a_dir_sel[0]) digital_io_oen[0] = 1'b0; + if(cfg_port_a_dir_sel[1]) digital_io_oen[1] = 1'b0; + if(cfg_port_a_dir_sel[2]) digital_io_oen[2] = 1'b0; + if(cfg_port_a_dir_sel[3]) digital_io_oen[3] = 1'b0; + if(cfg_port_a_dir_sel[4]) digital_io_oen[4] = 1'b0; end
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv index 7638688..d253eea 100755 --- a/verilog/rtl/pinmux/src/pinmux_top.sv +++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -17,7 +17,7 @@ // ////////////////////////////////////////////////////////////////////// //// //// -//// Pinmux //// +//// Pinmux //// //// //// //// This file is part of the riscduino cores project //// //// https://github.com/dineshannayya/riscduino.git //// @@ -58,21 +58,50 @@ //// D. 4x ws281x driver logic added //// //// E. 4x ws281x driver are mux with 16x gpio //// //// F. gpio type select the normal gpio vs ws281x //// +//// 0.7 - 26th Aug 2022, Dinesh A //// +//// As digitial-io[0-4] reserved at power up. //// +//// A. to keep at least one uart access, //// +//// we have moved UART_RXD[1] from io[3] to io[6] //// +//// B. SPI Slave SSN move from io[0] to [7] //// +//// C. Additional Mail Box Register added at addr 0xF //// +//// D. Due to power on digitalio[0-4] access issue,we //// +//// have moved arduino pin mapping from io 5 onward //// +//// 0.8 - 1 Sept 2022, Dinesh A //// +//// A. System strap implementation //// +//// B. glbl address space increased from 16 to 32 //// +//// C. software register address moved, 4 register will //// +//// reset under power-on reset, 4 register will reset//// +//// system reset //// ////////////////////////////////////////////////////////////////////// - +`include "user_params.svh" module pinmux_top ( `ifdef USE_POWER_PINS - input logic vccd1,// User area 1 1.8V supply - input logic vssd1,// User area 1 digital ground + input logic vccd1,// User area 1 1.8V supply + input logic vssd1,// User area 1 digital ground `endif // clock skew adjust - input logic [3:0] cfg_cska_pinmux, - input logic wbd_clk_int, - output logic wbd_clk_pinmux, + input logic [3:0] cfg_cska_pinmux, + input logic wbd_clk_int, + output logic wbd_clk_pinmux, // System Signals // Inputs input logic mclk, - input logic h_reset_n, + input logic e_reset_n , // external reset + input logic p_reset_n , // power-on reset + input logic s_reset_n , // soft reset + + // to/from Global Reset FSM + input logic cfg_strap_pad_ctrl , + input logic [31:0] system_strap , + output logic [31:0] strap_sticky , + + input logic user_clock1 , + input logic user_clock2 , + input logic int_pll_clock , + output logic xtal_clk , + + output logic usb_clk , + output logic rtc_clk , // Global Reset control output logic [1:0] cpu_core_rst_n , @@ -88,7 +117,7 @@ // Reg Bus Interface Signal input logic reg_cs, input logic reg_wr, - input logic [8:0] reg_addr, + input logic [9:0] reg_addr, input logic [31:0] reg_wdata, input logic [3:0] reg_be, @@ -157,16 +186,18 @@ output logic uartm_rxd , input logic uartm_txd , - output logic pulse1m_mclk, - output logic [31:0] pinmux_debug, + output logic pulse1m_mclk, + output logic [31:0] pinmux_debug, - input logic dbg_clk_mon + input logic dbg_clk_mon ); -logic sreset_n; // Sync Reset +logic s_reset_ssn; // Sync Reset +logic p_reset_ssn; // Sync Reset +logic [15:0] pad_strap_in; /* clock pulse */ //******************************************************** @@ -242,26 +273,26 @@ logic [31:0] reg_ws_rdata; logic reg_ws_ack; -assign reg_rdata = (reg_addr[8:6] == `SEL_GLBL) ? {reg_glbl_rdata} : - (reg_addr[8:6] == `SEL_GPIO) ? {reg_gpio_rdata} : - (reg_addr[8:6] == `SEL_PWM) ? {reg_pwm_rdata} : - (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_rdata : - (reg_addr[8:6] == `SEL_SEMA) ? {16'h0,reg_sema_rdata} : - (reg_addr[8:6] == `SEL_WS) ? reg_ws_rdata : 'h0; +assign reg_rdata = (reg_addr[9:7] == `SEL_GLBL) ? {reg_glbl_rdata} : + (reg_addr[9:7] == `SEL_GPIO) ? {reg_gpio_rdata} : + (reg_addr[9:7] == `SEL_PWM) ? {reg_pwm_rdata} : + (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_rdata : + (reg_addr[9:7] == `SEL_SEMA) ? {16'h0,reg_sema_rdata} : + (reg_addr[9:7] == `SEL_WS) ? reg_ws_rdata : 'h0; -assign reg_ack = (reg_addr[8:6] == `SEL_GLBL) ? reg_glbl_ack : - (reg_addr[8:6] == `SEL_GPIO) ? reg_gpio_ack : - (reg_addr[8:6] == `SEL_PWM) ? reg_pwm_ack : - (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_ack : - (reg_addr[8:6] == `SEL_SEMA) ? reg_sema_ack : - (reg_addr[8:6] == `SEL_WS) ? reg_ws_ack : 1'b0; +assign reg_ack = (reg_addr[9:7] == `SEL_GLBL) ? reg_glbl_ack : + (reg_addr[9:7] == `SEL_GPIO) ? reg_gpio_ack : + (reg_addr[9:7] == `SEL_PWM) ? reg_pwm_ack : + (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_ack : + (reg_addr[9:7] == `SEL_SEMA) ? reg_sema_ack : + (reg_addr[9:7] == `SEL_WS) ? reg_ws_ack : 1'b0; -wire reg_glbl_cs = (reg_addr[8:6] == `SEL_GLBL) ? reg_cs : 1'b0; -wire reg_gpio_cs = (reg_addr[8:6] == `SEL_GPIO) ? reg_cs : 1'b0; -wire reg_pwm_cs = (reg_addr[8:6] == `SEL_PWM) ? reg_cs : 1'b0; -wire reg_timer_cs = (reg_addr[8:6] == `SEL_TIMER)? reg_cs : 1'b0; -wire reg_sema_cs = (reg_addr[8:6] == `SEL_SEMA) ? reg_cs : 1'b0; -wire reg_ws_cs = (reg_addr[8:6] == `SEL_WS) ? reg_cs : 1'b0; +wire reg_glbl_cs = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0; +wire reg_gpio_cs = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0; +wire reg_pwm_cs = (reg_addr[9:7] == `SEL_PWM) ? reg_cs : 1'b0; +wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0; +wire reg_sema_cs = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0; +wire reg_ws_cs = (reg_addr[9:7] == `SEL_WS) ? reg_cs : 1'b0; //--------------------------------------------------------------------- @@ -285,12 +316,20 @@ ); reset_sync u_rst_sync ( - .scan_mode (1'b0 ), - .dclk (mclk ), // Destination clock domain - .arst_n (h_reset_n ), // active low async reset - .srst_n (sreset_n ) + .scan_mode (1'b0 ), + .dclk (mclk ), // Destination clock domain + .arst_n (s_reset_n ), // active low async reset + .srst_n (s_reset_ssn ) ); +reset_sync u_prst_sync ( + .scan_mode (1'b0 ), + .dclk (mclk ), // Destination clock domain + .arst_n (p_reset_n ), // active low async reset + .srst_n (p_reset_ssn ) + ); + + //------------------------------------------------------------------ // Global Register //------------------------------------------------------------------ @@ -298,7 +337,22 @@ // System Signals // Inputs .mclk (mclk ), - .h_reset_n (sreset_n ), + .e_reset_n (e_reset_n ), // external reset + .p_reset_n (p_reset_ssn ), // power-on reset + .s_reset_n (s_reset_ssn ), + + .pad_strap_in (pad_strap_in ), + .system_strap (system_strap ), + .strap_sticky (strap_sticky ), + + .user_clock1 (user_clock1 ), + .user_clock2 (user_clock2 ), + .int_pll_clock (int_pll_clock ), + .xtal_clk (xtal_clk ), + + .usb_clk (usb_clk ), + .rtc_clk (rtc_clk ), + .cpu_core_rst_n (cpu_core_rst_n ), .cpu_intf_rst_n (cpu_intf_rst_n ), @@ -315,7 +369,7 @@ // Reg read/write Interface Inputs .reg_cs (reg_glbl_cs ), .reg_wr (reg_wr ), - .reg_addr (reg_addr[5:2] ), + .reg_addr (reg_addr[6:2] ), .reg_wdata (reg_wdata ), .reg_be (reg_be ), @@ -345,7 +399,7 @@ // System Signals // Inputs .mclk ( mclk ), - .h_reset_n (h_reset_n ), + .h_reset_n (s_reset_ssn ), // Reg Bus Interface Signal .reg_cs (reg_gpio_cs ), @@ -376,7 +430,7 @@ // System Signals // Inputs .mclk ( mclk ), - .h_reset_n (h_reset_n ), + .h_reset_n (s_reset_ssn ), // Reg Bus Interface Signal .reg_cs (reg_pwm_cs ), @@ -400,8 +454,8 @@ timer_top u_timer( // System Signals // Inputs - .mclk ( mclk ), - .h_reset_n (h_reset_n ), + .mclk (mclk ), + .h_reset_n (s_reset_ssn ), // Reg Bus Interface Signal .reg_cs (reg_timer_cs ), @@ -425,7 +479,7 @@ // System Signals // Inputs .mclk ( mclk ), - .h_reset_n (h_reset_n ), + .h_reset_n (s_reset_ssn ), // Reg Bus Interface Signal .reg_cs (reg_sema_cs ), @@ -445,7 +499,7 @@ ws281x_top u_ws281x( .mclk (mclk ), - .h_reset_n (h_reset_n ), + .h_reset_n (s_reset_ssn ), .reg_cs (reg_ws_cs ), .reg_wr (reg_wr ), @@ -467,11 +521,15 @@ //---------------------------------------------------------------------- pinmux u_pinmux ( + .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ), + .pad_strap_in (pad_strap_in ), // Digital IO .digital_io_out (digital_io_out ), .digital_io_oen (digital_io_oen ), .digital_io_in (digital_io_in ), + .xtal_clk (xtal_clk ), + // Config .cfg_gpio_out_type (cfg_gpio_out_type ), .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), @@ -529,6 +587,7 @@ .dbg_clk_mon (dbg_clk_mon ) + ); endmodule
diff --git a/verilog/rtl/pinmux/src/strap_ctrl.sv b/verilog/rtl/pinmux/src/strap_ctrl.sv new file mode 100644 index 0000000..643a6de --- /dev/null +++ b/verilog/rtl/pinmux/src/strap_ctrl.sv
@@ -0,0 +1,235 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// strap control //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// Manages all the strap related func //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 29th Aug 2022, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// + +/************************************************************************* + This block control the system/soft/sticky strap generation + +expected Reset removal sequence + + _________ __________________________________________________ + | | +e_reset_n |________________| + + ________ ________________________________________ + XXXXXXXXX | +p_reset_n XXXXXXXXX__________________________| + + ____________ + XXXXXXXXX | +clk_enb XXXXXXXXX_____________________________________________| + + ____________ + XXXXXXXXX | +s_reset_n XXXXXXXXX________________________________________________________| + +pad_strap_in decoding + bit[1:0] - System Clock Source Selection for wbs/riscv + 00 - User clock1 (Default) + 01 - User clock2 + 10 - Internal PLL + 11 - Xtal + bit[3:2] - Clock Division for wbs/riscv + 00 - 0 Div (Default) + 01 - 2 Div + 10 - 4 Div + 11 - 8 Div + bit [4] - uart master config control + 0 - load from LA + 1 - constant value based on system clock selection (Default) + bit [5] - QSPI SRAM Mode Selection + 1'b0 - Single (Default) + 1'b1 - Quad + bit [7:6] - QSPI Fash Mode Selection + 2'b00 - Single (Default) + 2'b01 - Double + 2'b10 - Quad + 2'b11 - QDDR + bit [8] - Riscv Reset control + 0 - Keep Riscv on Reset + 1 - Removed Riscv on Power On Reset (Default) + bit [9] - Riscv Cache Bypass + 0 - Cache Enable + 1 - Bypass cache (Default + bit [10] - Riscv SRAM clock edge selection + 0 - Normal + 1 - Invert (Default) + bit [12:11] - Skew selection + 2'b00 - Default value (Default + 2'b01 - Default value + 2 + 2'b10 - Default value + 4 + 2'b11 - Default value - 4 + bit [14:13] - Reserved + bit [15] - Strap Mode + 0 - Normal + 1 - Pick Default Value + +system strap decoding + bit[1:0] - System Clock Source Selection for wbs + 00 - User clock1 + 01 - User clock2 + 10 - Internal PLL + 11 - Xtal + bit[3:2] - Clock Division for wbs + 00 - 0 Div + 01 - 2 Div + 10 - 4 Div + 11 - 8 Div + bit[5:4] - System Clock Source Selection for riscv + 00 - User clock1 + 01 - User clock2 + 10 - Internal PLL + 11 - Xtal + bit[7:6] - Clock Division for riscv + 00 - 0 Div + 01 - 2 Div + 10 - 4 Div + 11 - 8 Div + bit [8] - uart master config control + 0 - load from LA + 1 - constant value based on system clock selection + bit [9] - QSPI SRAM Mode Selection CS#2 + 1'b0 - Single + 1'b1 - Quad + bit [11:10] - QSPI FLASH Mode Selection CS#0 + 2'b00 - Single + 2'b01 - Double + 2'b10 - Quad + 2'b11 - QDDR + bit [12] - Riscv Reset control + 0 - Keep Riscv on Reset + 1 - Removed Riscv on Power On Reset + bit [13] - Riscv Cache Bypass + 1 - Cache Enable + 0 - Bypass cache + bit [14] - Riscv SRAM clock edge selection + 0 - Normal + 1 - Invert + + bit [15] - Soft Reboot Request + bit [17:16] - cfg_cska_wi Skew selection + bit [19:18] - cfg_cska_wh Skew selection + bit [21:20] - cfg_cska_riscv Skew selection + bit [23:22] - cfg_cska_qspi Skew selection + bit [25:24] - cfg_cska_uart Skew selection + bit [27:26] - cfg_cska_pinmux Skew selection + bit [29:28] - cfg_cska_qspi_co Skew selection + +**************************************************************************/ +module strap_ctrl ( + + input logic clk , + input logic e_reset_n , // external reset + input logic p_reset_n , // power-on reset + input logic s_reset_n , // soft reset + + input logic [15:0] pad_strap_in , // strap from pad + //List of Inputs + input logic cs , + input logic [3:0] we , + input logic [31:0] data_in , + + //List of Outs + output logic [15:0] strap_latch , + output logic [31:0] strap_sticky + + ); + + +//--------------------------------------------- +// Strap Mapping +//---------------------------------------------- +logic [31:0] strap_map; +logic [14:0] pstrap_select; + +// Pad Strap selection based on strap mode +assign pstrap_select = (strap_latch[15] == 1'b1) ? PSTRAP_DEFAULT_VALUE : strap_latch[14:0]; + +assign strap_map = { + 1'b0 , // bit[31] - Soft Reboot Request - Need to double sync to local clock + 1'b0 , // bit[30] - reserved + pstrap_select[12:11] , // bit[29:28] - cfg_cska_qspi_co Skew selection + pstrap_select[12:11] , // bit[27:26] - cfg_cska_pinmux Skew selection + pstrap_select[12:11] , // bit[25:24] - cfg_cska_uart Skew selection + pstrap_select[12:11] , // bit[23:22] - cfg_cska_qspi Skew selection + pstrap_select[12:11] , // bit[21:20] - cfg_cska_riscv Skew selection + pstrap_select[12:11] , // bit[19:18] - cfg_cska_wh Skew selection + pstrap_select[12:11] , // bit[17:16] - cfg_cska_wi Skew selection + 1'b0 , // bit[15] - Reserved + pstrap_select[10] , // bit[14] - Riscv SRAM clock edge selection + pstrap_select[9] , // bit[13] - Riscv Cache Bypass + pstrap_select[8] , // bit[12] - Riscv Reset control + pstrap_select[7:6] , // bit[11:10] - QSPI FLASH Mode Selection CS#0 + pstrap_select[5] , // bit[9] - QSPI SRAM Mode Selection CS#2 + pstrap_select[4] , // bit[8] - uart master config control + pstrap_select[3:2] , // bit[7:6] - riscv clock div + pstrap_select[1:0] , // bit[5:4] - riscv clock source sel + pstrap_select[3:2] , // bit[3:2] - wbs clock division + pstrap_select[1:0] // bit[1:0] - wbs clock source sel + }; + +//------------------------------------ +// Generating strap latch +//------------------------------------ +always_latch begin + if ( ~e_reset_n ) + begin + strap_latch = pad_strap_in[15:0]; + end +end + +//-------------------------------------------- +// Software controller Strap Register +//-------------------------------------------- + + +always @ (posedge clk or negedge e_reset_n) begin + if(e_reset_n == 1'b0) begin + strap_sticky <= 'h0 ; + end else if (p_reset_n == 1'b0) begin + strap_sticky <= strap_map ; + end else if(s_reset_n == 1'b0) begin + strap_sticky[`STRAP_SOFT_REBOOT_REQ] <= 1'b0; + end else begin + if(cs && we[0]) strap_sticky[7:0] <= data_in[7:0]; + if(cs && we[1]) strap_sticky[15:8] <= data_in[15:8]; + if(cs && we[2]) strap_sticky[23:16] <= data_in[23:16]; + if(cs && we[3]) strap_sticky[31:24] <= data_in[31:24]; + end +end + +endmodule
diff --git a/verilog/rtl/pinmux/src/ws281x_reg.sv b/verilog/rtl/pinmux/src/ws281x_reg.sv index 2b43097..31f25c1 100644 --- a/verilog/rtl/pinmux/src/ws281x_reg.sv +++ b/verilog/rtl/pinmux/src/ws281x_reg.sv
@@ -37,7 +37,7 @@ ////////////////////////////////////////////////////////////////////// -module ws281x_reg #( parameter NP = 4, // Number of PORT +module ws281x_reg #( parameter NP = 2, // Number of PORT parameter DW = 32, // DATA WIDTH parameter AW = 4, // ADDRESS WIDTH parameter BW = 4 // BYTE WIDTH @@ -64,28 +64,28 @@ output logic [9:0] cfg_th1_period , // bit-1 drive low period // wd281x port-0 data - input logic port0_enb , + output logic port0_enb , input logic port0_rd , output logic [23:0] port0_data , output logic port0_dval , // wd281x port-1 data - input logic port1_enb , + output logic port1_enb , input logic port1_rd , output logic [23:0] port1_data , - output logic port1_dval , + output logic port1_dval - // wd281x port-2 data - input logic port2_enb , - input logic port2_rd , - output logic [23:0] port2_data , - output logic port2_dval , + //// wd281x port-2 data + //output logic port2_enb , + //input logic port2_rd , + //output logic [23:0] port2_data , + //output logic port2_dval , - // wd281x port-3 data - input logic port3_enb , - input logic port3_rd , - output logic [23:0] port3_data , - output logic port3_dval + //// wd281x port-3 data + //output logic port3_enb , + //input logic port3_rd , + //output logic [23:0] port3_data , + //output logic port3_dval ); @@ -158,12 +158,12 @@ assign port0_enb = reg_0[0]; assign port1_enb = reg_0[1]; -assign port2_enb = reg_0[2]; -assign port3_enb = reg_0[3]; +//assign port2_enb = reg_0[2]; +//assign port3_enb = reg_0[3]; generic_register #(.WD(4)) u_reg_0( //List of Inputs - .we ({8{sw_wr_en_0 & + .we ({4{sw_wr_en_0 & sw_be[0] }}), .data_in (sw_reg_wdata[3:0]), .reset_n (h_reset_n ), @@ -209,13 +209,11 @@ assign port0_dval =!fifo_empty[0]; assign port1_dval =!fifo_empty[1]; -assign port2_dval =!fifo_empty[2]; -assign port3_dval =!fifo_empty[3]; +//assign port2_dval =!fifo_empty[2]; +//assign port3_dval =!fifo_empty[3]; -assign reg_3 = {2'b00,fifo_empty[3],fifo_full[3], - 2'b00,fifo_empty[2],fifo_full[2], - 2'b00,fifo_empty[1],fifo_full[1], - 2'b00,fifo_empty[0],fifo_full[0]}; +assign reg_3 = { 2'b00,fifo_empty[1],fifo_full[1], + 2'b00,fifo_empty[0],fifo_full[0]}; //---------------------------------------------------- @@ -224,18 +222,18 @@ assign fifo_wr[0] = sw_wr_en_4 & reg_ack; assign fifo_wr[1] = sw_wr_en_5 & reg_ack; -assign fifo_wr[2] = sw_wr_en_6 & reg_ack; -assign fifo_wr[3] = sw_wr_en_7 & reg_ack; +//assign fifo_wr[2] = sw_wr_en_6 & reg_ack; +//assign fifo_wr[3] = sw_wr_en_7 & reg_ack; assign fifo_rd[0] = port0_rd; assign fifo_rd[1] = port1_rd; -assign fifo_rd[2] = port2_rd; -assign fifo_rd[3] = port3_rd; +//assign fifo_rd[2] = port2_rd; +//assign fifo_rd[3] = port3_rd; assign port0_data = fifo_rdata[0]; assign port1_data = fifo_rdata[1]; -assign port2_data = fifo_rdata[2]; -assign port3_data = fifo_rdata[3]; +//assign port2_data = fifo_rdata[2]; +//assign port3_data = fifo_rdata[3]; genvar port; generate @@ -272,8 +270,8 @@ 4'b0011 : reg_out [31:0] = reg_3 [31:0]; 4'b0100 : reg_out [31:0] = port0_data; 4'b0101 : reg_out [31:0] = port1_data; - 4'b0110 : reg_out [31:0] = port2_data; - 4'b0111 : reg_out [31:0] = port3_data; +// 4'b0110 : reg_out [31:0] = port2_data; +// 4'b0111 : reg_out [31:0] = port3_data; default : reg_out [31:0] = 32'h0; endcase end
diff --git a/verilog/rtl/pinmux/src/ws281x_top.sv b/verilog/rtl/pinmux/src/ws281x_top.sv index a048967..6ab06fa 100644 --- a/verilog/rtl/pinmux/src/ws281x_top.sv +++ b/verilog/rtl/pinmux/src/ws281x_top.sv
@@ -56,15 +56,18 @@ ); +assign txd[2] = txd[0]; +assign txd[3] = txd[1]; + logic[15:0] cfg_reset_period ; // Reset period interm of clk logic [9:0] cfg_clk_period ; // Total bit clock period -logic [9:0] cfg_th0_period ; // bit-0 drive low period -logic [9:0] cfg_th1_period ; // bit-1 drive low period +logic [9:0] cfg_th0_period ; // bit-0 drive low period +logic [9:0] cfg_th1_period ; // bit-1 drive low period logic [23:0] port0_data ; logic [23:0] port1_data ; -logic [23:0] port2_data ; -logic [23:0] port3_data ; +//logic [23:0] port2_data ; +//logic [23:0] port3_data ; ws281x_reg u_reg ( .mclk ( mclk ), @@ -92,17 +95,17 @@ .port1_enb ( port1_enb ), .port1_rd ( port1_rd ), .port1_data ( port1_data ), - .port1_dval ( port1_dval ), + .port1_dval ( port1_dval ) - .port2_enb ( port2_enb ), - .port2_rd ( port2_rd ), - .port2_data ( port2_data ), - .port2_dval ( port2_dval ), + //.port2_enb ( port2_enb ), + //.port2_rd ( port2_rd ), + //.port2_data ( port2_data ), + //.port2_dval ( port2_dval ), - .port3_enb ( port3_enb ), - .port3_rd ( port3_rd ), - .port3_data ( port3_data ), - .port3_dval ( port3_dval ) + //.port3_enb ( port3_enb ), + //.port3_rd ( port3_rd ), + //.port3_data ( port3_data ), + //.port3_dval ( port3_dval ) ); @@ -147,6 +150,7 @@ .txd (txd[1] ) // Signal to send to WS2811 chain. ); +/*** //wx281x port-2 ws281x_driver u_txd_2( .clk (mclk ), // Clock input. @@ -186,4 +190,5 @@ .txd (txd[3] ) // Signal to send to WS2811 chain. ); +***/ endmodule
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim index 201a604..ee4d23b 160000 --- a/verilog/rtl/qspim +++ b/verilog/rtl/qspim
@@ -1 +1 @@ -Subproject commit 201a6047f18db8ec792d948a52327b070013ab53 +Subproject commit ee4d23bb8a6edf84545f1aa0ba5db083d12440d7
diff --git a/verilog/rtl/uart/src/uart_rxfsm.sv b/verilog/rtl/uart/src/uart_rxfsm.sv index 58916e6..7129b9c 100644 --- a/verilog/rtl/uart/src/uart_rxfsm.sv +++ b/verilog/rtl/uart/src/uart_rxfsm.sv
@@ -36,6 +36,8 @@ //// 1. initial version picked from //// //// http://www.opencores.org/cores/oms8051mini //// //// //// +//// 0.2 - 1st Sept 2022, Dinesh A //// +//// 1. Moved the Fifo Write to last stop phase //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -140,6 +142,7 @@ offset <= offset + 1; case(rxstate) idle_st : begin + fifo_wr <= 0; if(!si) begin // Start indication if(fifo_aval && cfg_rx_enable) begin rxstate <= xfr_start; @@ -171,7 +174,6 @@ fifo_data[cnt] <= si; cnt <= cnt+1; if(cnt == 7) begin - fifo_wr <= 1; if(cfg_pri_mod == 2'b00) // No Priority rxstate <= xfr_stop_st1; else rxstate <= xfr_pri_st; @@ -179,7 +181,6 @@ end end xfr_pri_st : begin - fifo_wr <= 0; if(rxpos == offset) begin if(cfg_pri_mod == 2'b10) // even priority if( si != ^fifo_data) error_ind <= 2'b10; @@ -189,21 +190,24 @@ end end xfr_stop_st1 : begin - fifo_wr <= 0; if(rxpos == offset) begin if(si) begin if(cfg_stop_bit) // Two Stop bit rxstate <= xfr_stop_st2; - else + else begin + fifo_wr <= 1; rxstate <= idle_st; + end end else begin // Framing error error_ind <= 2'b01; + fifo_wr <= 1; rxstate <= idle_st; end end end xfr_stop_st2 : begin if(rxpos == offset) begin + fifo_wr <= 1; if(si) begin rxstate <= idle_st; end else begin // Framing error
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v new file mode 100644 index 0000000..1e2cb90 --- /dev/null +++ b/verilog/rtl/user_defines.v
@@ -0,0 +1,87 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`ifndef __USER_DEFINES_H +// User GPIO initial configuration parameters +`define __USER_DEFINES_H + +// Useful GPIO mode values. These match the names used in defs.h. +`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 13'h0403 +`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 13'h0803 +`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 13'h0c03 +`define GPIO_MODE_MGMT_STD_OUTPUT 13'h1809 +`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 13'h1801 +`define GPIO_MODE_MGMT_STD_ANALOG 13'h000b + +`define GPIO_MODE_USER_STD_INPUT_NOPULL 13'h0402 +`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 13'h0802 +`define GPIO_MODE_USER_STD_INPUT_PULLUP 13'h0c02 +`define GPIO_MODE_USER_STD_OUTPUT 13'h1808 +`define GPIO_MODE_USER_STD_BIDIRECTIONAL 13'h1800 +`define GPIO_MODE_USER_STD_OUT_MONITORED 13'h1802 +`define GPIO_MODE_USER_STD_ANALOG 13'h000a + +// The power-on configuration for GPIO 0 to 4 is fixed and cannot be +// modified (allowing the SPI and debug to always be accessible unless +// overridden by a flash program). + +// The values below can be any of the standard types defined above, +// or they can be any 13-bit value if the user wants a non-standard +// startup state for the GPIO. By default, every GPIO from 5 to 37 +// is set to power up as an input controlled by the management SoC. +// Users may want to redefine these so that the user project powers +// up in a state that can be used immediately without depending on +// the management SoC to run a startup program to configure the GPIOs. + +`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL // UART_TXD[1] +`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL // UART_RXD[1] +`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL + +// Configurations of GPIO 15 to 25 are used on caravel but not caravan. +`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL + +`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL + +`endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh new file mode 100644 index 0000000..7664338 --- /dev/null +++ b/verilog/rtl/user_params.svh
@@ -0,0 +1,150 @@ +`ifndef USER_PARMS +`define USER_PARMS + +// ASCI Representation of RISC = 32'h8273_8343 +parameter CHIP_SIGNATURE = 32'h8273_8343; +// Software Reg-1, Release date: <DAY><MONTH><YEAR> +parameter CHIP_RELEASE_DATE = 32'h0309_2022; +// Software Reg-2: Poject Revison 5.1 = 0005200 +parameter CHIP_REVISION = 32'h0005_3000; + +parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_1000; + +parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1011_0000; + +/***************************************************** +pad_strap_in decoding + bit[1:0] - System Clock Source Selection for wbs/riscv + 00 - User clock1 (Default) + 01 - User clock2 + 10 - Internal PLL + 11 - Xtal + bit[3:2] - Clock Division for wbs/riscv + 00 - 0 Div (Default) + 01 - 2 Div + 10 - 4 Div + 11 - 8 Div + bit [4] - uart master config control + 0 - load from LA + 1 - constant value based + on system clock selection (Default) + bit [5] - QSPI SRAM Mode Selection + 1'b0 - Single + 1'b1 - Quad (Default) + bit [7:6] - QSPI Fash Mode Selection + 2'b00 - Single + 2'b01 - Double + 2'b10 - Quad (Default + 2'b11 - QDDR + bit [8] - Riscv Reset control + 0 - Keep Riscv on Reset + 1 - Removed Riscv on Power On Reset (Default) + bit [9] - Riscv Cache Bypass + 0 - Cache Enable + 1 - Bypass cache (Default) + bit [10] - Riscv SRAM clock edge selection + 0 - Normal + 1 - Invert (Default) + bit [12:11] - Skew selection + 2'b00 - Default value (Default) + 2'b01 - Default value + 2 + 2'b10 - Default value + 4 + 2'b11 - Default value - 4 + + bit[15] - Strap Mode + 0 - [14:0] loaded from pad + 1 - Default reset value loaded + PSTRAP_DEFAULT_VALUE +****************************************************/ + +`define PSTRAP_CLK_SRC 1:0 +`define PSTRAP_CLK_DIV 3:2 +`define PSTRAP_UARTM_CFG 4 +`define PSTRAP_QSPI_SRAM 5 +`define PSTRAP_QSPI_FLASH 7:6 +`define PSTRAP_RISCV_RESET_MODE 8 +`define PSTRAP_RISCV_CACHE_BYPASS 9 +`define PSTRAP_RISCV_SRAM_CLK_EDGE 10 +`define PSTRAP_CLK_SKEW 12:11 + +`define PSTRAP_DEFAULT_VALUE 15 + +/************************************************************ +system strap decoding + bit[1:0] - System Clock Source Selection for wbs + 00 - User clock1 + 01 - User clock2 + 10 - Internal PLL + 11 - Xtal + bit[3:2] - Clock Division for wbs + 00 - 0 Div + 01 - 2 Div + 10 - 4 Div + 11 - 8 Div + bit[5:4] - System Clock Source Selection for riscv + 00 - User clock1 + 01 - User clock2 + 10 - Internal PLL + 11 - Xtal + bit[7:6] - Clock Division for riscv + 00 - 0 Div + 01 - 2 Div + 10 - 4 Div + 11 - 8 Div + bit [8] - uart master config control + 0 - load from LA + 1 - constant value based on system clock selection + bit [9] - QSPI SRAM Mode Selection CS#2 + 1'b0 - Single + 1'b1 - Quad + bit [11:10] - QSPI FLASH Mode Selection CS#0 + 2'b00 - Single + 2'b01 - Double + 2'b10 - Quad + 2'b11 - QDDR + bit [12] - Riscv Reset control + 0 - Keep Riscv on Reset + 1 - Removed Riscv on Power On Reset + bit [13] - Riscv Cache Bypass + 1 - Cache Enable + 0 - Bypass cache + bit [14] - Riscv SRAM clock edge selection + 0 - Normal + 1 - Invert + + bit [15] - Soft Reboot Request + bit [17:16] - cfg_cska_wi Skew selection + bit [19:18] - cfg_cska_wh Skew selection + bit [21:20] - cfg_cska_riscv Skew selection + bit [23:22] - cfg_cska_qspi Skew selection + bit [25:24] - cfg_cska_uart Skew selection + bit [27:26] - cfg_cska_pinmux Skew selection + bit [29:28] - cfg_cska_qspi_co Skew selection + + +********************************************************/ +// Stikcy Strap +`define STRAP_WB_CLK_SRC 1:0 +`define STRAP_WB_CLK_DIV 3:2 +`define STRAP_RISCV_CLK_SRC 5:4 +`define STRAP_RISCV_CLK_DIV 7:6 +`define STRAP_UARTM_CFG 8 +`define STRAP_QSPI_SRAM 9 +`define STRAP_QSPI_FLASH 11:10 +`define STRAP_RISCV_RESET_MODE 12 +`define STRAP_RISCV_CACHE_BYPASS 13 +`define STRAP_RISCV_SRAM_CLK_EDGE 14 +`define STRAP_QSPI_PRE_SRAM 15 // Previous SRAM Strap Status +`define STRAP_CLK_SKEW_WI 17:16 +`define STRAP_CLK_SKEW_WH 19:18 +`define STRAP_CLK_SKEW_RISCV 21:20 +`define STRAP_CLK_SKEW_QSPI 23:22 +`define STRAP_CLK_SKEW_UART 25:24 +`define STRAP_CLK_SKEW_PINMUX 27:26 +`define STRAP_CLK_SKEW_QSPI_CO 29:28 +`define STRAP_QSPI_INIT_BYPASS 30 +`define STRAP_SOFT_REBOOT_REQ 31 + + +`endif // USER_PARMS +
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 882d9ba..4d5ebb0 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -247,6 +247,23 @@ //// E. 4x ws281x driver logic added //// //// F. 4x ws281x driver are mux with 16x gpio //// //// G. gpio type select the normal gpio vs ws281x //// +//// 5.2 Aug 26 2022, Dinesh A //// +//// A. We have copied the user_defines.h from caravel //// +//// and configured all the GPIO from 5 onwards as //// +//// GPIO_MODE_USER_STD_BIDIRECTIONAL //// +//// //// +//// As digitial-io[0-5] reserved at power up. //// +//// B. to keep at least one uart access, //// +//// we have moved UART_RXD[1] from io[3] to io[6] //// +//// C. SPI Slave SSN move from io[0] to [7] //// +//// 5.3 Sept 2 2022, Dinesh A //// +//// A. System Strap implementation //// +//// B. Arduino pins are moved to take care of caravel //// +//// digital-io[0-4] resevred //// +//// C. global register space increased from 16 to 32 //// +//// D. reset fsm is implementation with soft reboot //// +//// option //// +//// E. strap based booting option added for qspi //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -346,6 +363,8 @@ ************************************************************************/ +`include "user_params.svh" + module user_project_wrapper ( `ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply @@ -520,7 +539,7 @@ // Global Register Wishbone Interface //--------------------------------------------------------------------- wire wbd_glbl_stb_o ; // strobe/request -wire [8:0] wbd_glbl_adr_o ; // address +wire [9:0] wbd_glbl_adr_o ; // address wire wbd_glbl_we_o ; // write wire [WB_WIDTH-1:0] wbd_glbl_dat_o ; // data output wire [3:0] wbd_glbl_sel_o ; // byte enable @@ -722,6 +741,17 @@ wire [3:0] spi_csn ; +//--------------------------------------------------------------------- +// Strap +//--------------------------------------------------------------------- +wire [31:0] system_strap ; +wire [31:0] strap_sticky ; +wire [1:0] strap_qspi_flash = system_strap[`STRAP_QSPI_FLASH]; +wire strap_qspi_sram = system_strap[`STRAP_QSPI_SRAM]; +wire strap_qspi_pre_sram = system_strap[`STRAP_QSPI_PRE_SRAM]; +wire strap_qspi_init_bypass = system_strap[`STRAP_QSPI_INIT_BYPASS]; + + //-------------------------------------------------------------------------- // Pinmux Risc core config // ------------------------------------------------------------------------- @@ -755,10 +785,18 @@ `endif .user_clock1 (wb_clk_i ), .user_clock2 (user_clock2 ), + .int_pll_clock (int_pll_clock ), .cpu_clk (cpu_clk ), - .rtc_clk (rtc_clk ), - .usb_clk (usb_clk ), + + // to/from Pinmux + .xtal_clk (xtal_clk ), + .e_reset_n (e_reset_n ), // external reset + .p_reset_n (p_reset_n ), // power-on reset + .s_reset_n (s_reset_n ), // soft reset + .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ), + .system_strap (system_strap ), + .strap_sticky (strap_sticky ), .wbd_int_rst_n (wbd_int_rst_n ), .wbd_pll_rst_n (wbd_pll_rst_n ), @@ -1083,6 +1121,11 @@ .mclk (wbd_clk_spi ), .rst_n (qspim_rst_n ), + .strap_flash (strap_qspi_flash ), + .strap_pre_sram (strap_qspi_pre_sram ), + .strap_sram (strap_qspi_sram ), + .cfg_init_bypass (strap_qspi_init_bypass ), + // Clock Skew Adjust .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), .cfg_cska_spi (cfg_cska_qspi_rp ), @@ -1271,7 +1314,7 @@ .usb_rstn (usb_rst_n ), // USB reset .spi_rstn (sspim_rst_n ), // SPI reset .app_clk (wbd_clk_uart_skew ), - .usb_clk (usb_clk ), + .usb_clk (usb_clk ), // Reg Bus Interface Signal .reg_cs (wbd_uart_stb_o ), @@ -1328,8 +1371,22 @@ // System Signals // Inputs .mclk (wbd_clk_pinmux_skew ), - .h_reset_n (wbd_int_rst_n ), + .e_reset_n (e_reset_n ), + .p_reset_n (p_reset_n ), + .s_reset_n (wbd_int_rst_n ), + .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ), + .system_strap (system_strap ), + .strap_sticky (strap_sticky ), + + .user_clock1 (wb_clk_i ), + .user_clock2 (user_clock2 ), + .int_pll_clock (int_pll_clock ), + .xtal_clk (xtal_clk ), + + + .rtc_clk (rtc_clk ), + .usb_clk (usb_clk ), // Reset Control .cpu_core_rst_n (cpu_core_rst_n ), .cpu_intf_rst_n (cpu_intf_rst_n ), @@ -1339,7 +1396,7 @@ .i2cm_rst_n (i2c_rst_n ), .usb_rst_n (usb_rst_n ), - .cfg_riscv_ctrl (cfg_riscv_ctrl ), + .cfg_riscv_ctrl (cfg_riscv_ctrl ), // Reg Bus Interface Signal .reg_cs (wbd_glbl_stb_o ),
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v index 53d8331..80de782 100644 --- a/verilog/rtl/user_reg_map.v +++ b/verilog/rtl/user_reg_map.v
@@ -10,10 +10,10 @@ `define ADDR_SPACE_UART1 32'h3001_0100 `define ADDR_SPACE_PINMUX 32'h3002_0000 `define ADDR_SPACE_GLBL 32'h3002_0000 -`define ADDR_SPACE_GPIO 32'h3002_0040 -`define ADDR_SPACE_PWM 32'h3002_0080 -`define ADDR_SPACE_TIMER 32'h3002_00C0 -`define ADDR_SPACE_SEMA 32'h3002_0100 +`define ADDR_SPACE_GPIO 32'h3002_0080 +`define ADDR_SPACE_PWM 32'h3002_0100 +`define ADDR_SPACE_TIMER 32'h3002_0180 +`define ADDR_SPACE_SEMA 32'h3002_0200 `define ADDR_SPACE_WBHOST 32'h3008_0000 //-------------------------------------------------- @@ -34,12 +34,19 @@ `define GLBL_CFG_INTR_MSK 8'h0C // reg_3 - Global Interrupt Mask `define GLBL_CFG_INTR_STAT 8'h10 // reg_4 - Global Interrupt `define GLBL_CFG_MUTI_FUNC 8'h14 // reg_5 - Multi functional sel -`define GLBL_CFG_SOFT_REG_0 8'h18 // reg_6 - Sof Register -`define GLBL_CFG_SOFT_REG_1 8'h1C // reg_7 - Sof Register -`define GLBL_CFG_SOFT_REG_2 8'h20 // reg_8 - Sof Register -`define GLBL_CFG_SOFT_REG_3 8'h24 // reg_9 - Sof Register -`define GLBL_CFG_SOFT_REG_4 8'h28 // reg_10 - Sof Register -`define GLBL_CFG_SOFT_REG_5 8'h2C // reg_11 - Sof Register +`define GLBL_CFG_CLK_CTRL 8'h18 // reg_6 - RTC/USB CLK CTRL +`define GLBL_CFG_PAD_STRAP 8'h30 // Strap as seen in Pad +`define GLBL_CFG_STRAP_STICKY 8'h34 // Sticky Strap used in next soft boot +`define GLBL_CFG_SYSTEM_STRAP 8'h38 // Current System Strap +`define GLBL_CFG_MAIL_BOX 8'h3C // reg_15 - Mail Box +`define GLBL_CFG_SOFT_REG_0 8'h40 // reg_16 - Sof Register +`define GLBL_CFG_SOFT_REG_1 8'h44 // reg_17 - Sof Register +`define GLBL_CFG_SOFT_REG_2 8'h48 // reg_18 - Sof Register +`define GLBL_CFG_SOFT_REG_3 8'h4C // reg_19 - Sof Register +`define GLBL_CFG_SOFT_REG_4 8'h50 // reg_20 - Sof Register +`define GLBL_CFG_SOFT_REG_5 8'h54 // reg_21 - Sof Register +`define GLBL_CFG_SOFT_REG_6 8'h58 // reg_22 - Sof Register +`define GLBL_CFG_SOFT_REG_7 8'h5C // reg_23 - Sof Register //-------------------------------------------------- // GPIO Register
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index d3d85cc..df3c656 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -50,6 +50,9 @@ //// indirect Map {Bank_Sel[15:3], wbm_adr_i[18:0]} //// //// 2.wbm_cyc_i need to qualified with wbm_stb_i //// //// //// +//// 0.5 - Aug 30 2022, Dinesh A //// +//// A. System strap related changes, reset_fsm added //// +//// B. rtc and usb clock moved to pinmux //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -78,6 +81,8 @@ //// //// ////////////////////////////////////////////////////////////////////// +`include "user_params.svh" + module wb_host ( `ifdef USE_POWER_PINS @@ -88,12 +93,23 @@ input logic user_clock2 , output logic cpu_clk , - output logic rtc_clk , - output logic usb_clk , + // Global Reset control output logic wbd_int_rst_n , output logic wbd_pll_rst_n , + + // to/from Pinmux + output logic int_pll_clock , + input logic xtal_clk , + output logic e_reset_n , // external reset + output logic p_reset_n , // power-on reset + output logic s_reset_n , // soft reset + output logic cfg_strap_pad_ctrl, + output logic [31:0] system_strap , + input logic [31:0] strap_sticky , + + // Master Port input logic wbm_rst_i , // Regular Reset signal input logic wbm_clk_i , // System clock @@ -173,13 +189,11 @@ logic sw_wr_en_3; logic [15:0] cfg_bank_sel; logic [31:0] reg_0; // Software_Reg_0 -logic [31:0] cfg_clk_ctrl2; +logic [8:0] cfg_clk_ctrl2; logic [31:0] cfg_pll_ctrl; -logic [7:0] cfg_wb_clk_ctrl; -logic [7:0] cfg_cpu_clk_ctrl; -logic [7:0] cfg_rtc_clk_ctrl; -logic [7:0] cfg_usb_clk_ctrl; +logic [3:0] cfg_wb_clk_ctrl; +logic [3:0] cfg_cpu_clk_ctrl; logic [31:0] cfg_glb_ctrl; @@ -222,19 +236,25 @@ logic wb_err_int ; // error logic [3:0] cfg_mon_sel ; -logic int_pll_clock ; logic pll_clk_div16 ; logic pll_clk_div16_buf ; logic [2:0] cfg_ref_pll_div ; +logic arst_n ; +logic soft_reboot ; +logic clk_enb ; + +assign e_reset_n = wbm_rst_n ; // sync external reset +assign cfg_strap_pad_ctrl = !p_reset_n; + +wire soft_boot_req = strap_sticky[`STRAP_SOFT_REBOOT_REQ]; -assign cfg_pll_enb = cfg_glb_ctrl[15]; -assign cfg_ref_pll_div = cfg_glb_ctrl[14:12]; -assign cfg_mon_sel = cfg_glb_ctrl[11:8]; - -assign cfg_dco_mode = cfg_pll_ctrl[31]; -assign cfg_pll_fed_div = cfg_pll_ctrl[30:26]; -assign cfg_dc_trim = cfg_pll_ctrl[25:0]; +//------------------------------------------ +// PLL Trim Value +//----------------------------------------- +assign cfg_dco_mode = cfg_pll_ctrl[31]; +assign cfg_pll_fed_div = cfg_pll_ctrl[30:26]; +assign cfg_dc_trim = cfg_pll_ctrl[25:0]; //assign int_pll_clock = pll_clk_out[0]; ctech_clk_buf u_clkbuf_pll (.A (pll_clk_out[0]), . X(int_pll_clock)); @@ -243,48 +263,81 @@ // Debug clock monitor optin assign dbg_clk_mon = (cfg_mon_sel == 4'b000) ? pll_clk_div16_buf: - (cfg_mon_sel == 4'b001) ? pll_ref_clk : - (cfg_mon_sel == 4'b010) ? wbs_clk_out : - (cfg_mon_sel == 4'b011) ? cpu_clk_int : - (cfg_mon_sel == 4'b100) ? rtc_clk_div : - (cfg_mon_sel == 4'b101) ? usb_clk_int : 1'b0; + (cfg_mon_sel == 4'b001) ? pll_ref_clk : + (cfg_mon_sel == 4'b010) ? wbs_clk_out : + (cfg_mon_sel == 4'b011) ? cpu_clk_int : 1'b0; -// Reset control -ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n)); -ctech_buf u_buf_pll_rst (.A(cfg_glb_ctrl[1]),.X(wbd_pll_rst_n)); //-------------------------------------------------------------------------------- // Look like wishbone reset removed early than user Power up sequence // To control the reset phase, we have added additional control through la[0] // ------------------------------------------------------------------------------ -wire arst_n = !wbm_rst_i & la_data_in[0]; +assign arst_n = !wbm_rst_i; reset_sync u_wbm_rst ( - .scan_mode (1'b0 ), + .scan_mode (1'b0 ), .dclk (wbm_clk_i ), // Destination clock domain - .arst_n (arst_n ), // active low async reset + .arst_n (arst_n ), // active low async reset .srst_n (wbm_rst_n ) ); reset_sync u_wbs_rst ( - .scan_mode (1'b0 ), + .scan_mode (1'b0 ), .dclk (wbs_clk_i ), // Destination clock domain - .arst_n (arst_n ), // active low async reset + .arst_n (s_reset_n ), // active low async reset .srst_n (wbs_rst_n ) ); +//------------------------------------------ +// Reset FSM +//------------------------------------------ +// Keep WBS in Ref clock during initial boot to strap loading +logic force_refclk; +wb_reset_fsm u_reset_fsm ( + .clk (wbm_clk_i ), + .e_reset_n (e_reset_n ), // external reset + .cfg_fast_sim (cfg_fast_sim), + .soft_boot_req (soft_boot_req), + + .p_reset_n (p_reset_n ), // power-on reset + .s_reset_n (s_reset_n ), // soft reset + .clk_enb (clk_enb ), + .soft_reboot (soft_reboot ), + .force_refclk (force_refclk) + +); + + +//------------------------------------------------- +// UART2WB HOST +// Uart Baud-16x computation +// Assumption is default wb clock is 40Mhz +// For 9600 Baud +// 40,000,000/(9600*16) = 260; +// Configured Value = 260-1 = 259 +//------------------------------------------------- + +wire strap_uart_cfg_mode = system_strap[`STRAP_UARTM_CFG]; + +wire cfg_uartm_tx_enable = (strap_uart_cfg_mode==0) ? la_data_in[1] : 1'b1; +wire cfg_uartm_rx_enable = (strap_uart_cfg_mode==0) ? la_data_in[2] : 1'b1; +wire cfg_uartm_stop_bit = (strap_uart_cfg_mode==0) ? la_data_in[3] : 1'b1; +wire [11:0]cfg_uart_baud_16x = (strap_uart_cfg_mode==0) ? la_data_in[15:4] : 258; +wire [1:0] cfg_uartm_cfg_pri_mod = (strap_uart_cfg_mode==0) ? la_data_in[17:16] : 2'b0; + + // UART Master uart2wb u_uart2wb ( - .arst_n (wbm_rst_n ), // sync reset - .app_clk (wbm_clk_i ), // sys clock + .arst_n (s_reset_n ), // sync reset + .app_clk (wbm_clk_i ), // sys clock // configuration control - .cfg_tx_enable (la_data_in[1] ), // Enable Transmit Path - .cfg_rx_enable (la_data_in[2] ), // Enable Received Path - .cfg_stop_bit (la_data_in[3] ), // 0 -> 1 Start , 1 -> 2 Stop Bits - .cfg_baud_16x (la_data_in[15:4] ), // 16x Baud clock generation - .cfg_pri_mod (la_data_in[17:16] ), // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd + .cfg_tx_enable (cfg_uartm_tx_enable ), // Enable Transmit Path + .cfg_rx_enable (cfg_uartm_rx_enable ), // Enable Received Path + .cfg_stop_bit (cfg_uartm_stop_bit ), // 0 -> 1 Start , 1 -> 2 Stop Bits + .cfg_baud_16x (cfg_uart_baud_16x ), // 16x Baud clock generation + .cfg_pri_mod (cfg_uartm_cfg_pri_mod ), // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd // Master Port .wbm_cyc_o (wbm_uart_cyc_i ), // strobe/request @@ -309,34 +362,40 @@ ); +//---------------------------------------- +// SPI as ISP +//---------------------------------------- + sspis_top u_spi2wb( .sys_clk (wbm_clk_i ), - .rst_n (wbm_rst_n ), + .rst_n (e_reset_n ), - .sclk (sclk ), - .ssn (ssn ), - .sdin (sdin ), - .sdout (sdout ), - .sdout_oen (sdout_oen ), + .sclk (sclk ), + .ssn (ssn ), + .sdin (sdin ), + .sdout (sdout ), + .sdout_oen (sdout_oen ), // WB Master Port - .wbm_cyc_o (wbm_spi_cyc_i ), // strobe/request - .wbm_stb_o (wbm_spi_stb_i ), // strobe/request - .wbm_adr_o (wbm_spi_adr_i ), // address - .wbm_we_o (wbm_spi_we_i ), // write - .wbm_dat_o (wbm_spi_dat_i ), // data output - .wbm_sel_o (wbm_spi_sel_i ), // byte enable - .wbm_dat_i (wbm_spi_dat_o ), // data input - .wbm_ack_i (wbm_spi_ack_o ), // acknowlegement - .wbm_err_i (wbm_spi_err_o ) // error + .wbm_cyc_o (wbm_spi_cyc_i ), // strobe/request + .wbm_stb_o (wbm_spi_stb_i ), // strobe/request + .wbm_adr_o (wbm_spi_adr_i ), // address + .wbm_we_o (wbm_spi_we_i ), // write + .wbm_dat_o (wbm_spi_dat_i ), // data output + .wbm_sel_o (wbm_spi_sel_i ), // byte enable + .wbm_dat_i (wbm_spi_dat_o ), // data input + .wbm_ack_i (wbm_spi_ack_o ), // acknowlegement + .wbm_err_i (wbm_spi_err_o ) // error ); -// Arbitor to select between external wb vs uart wb +//-------------------------------------------------- +// Arbitor to select between external wb vs uart wb vs spi +//--------------------------------------------------- wire [1:0] grnt; wb_arb u_arb( .clk (wbm_clk_i), - .rstn (wbm_rst_n), + .rstn (s_reset_n), .req ({1'b0,wbm_spi_stb_i,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), .gnt (grnt) ); @@ -389,8 +448,8 @@ ctech_delay_buf u_delay1_stb0 (.X(wb_stb_d1),.A(wb_stb_i)); ctech_delay_buf u_delay2_stb1 (.X(wb_stb_d2),.A(wb_stb_d1)); ctech_delay_buf u_delay2_stb2 (.X(wb_stb_d3),.A(wb_stb_d2)); -always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin - if ( wbm_rst_n == 1'b0 ) begin +always_ff @(negedge s_reset_n or posedge wbm_clk_i) begin + if ( s_reset_n == 1'b0 ) begin wb_req <= '0; wb_dat_o <= '0; wb_ack_o <= '0; @@ -431,9 +490,9 @@ assign sw_wr_en_4 = sw_wr_en && (sw_addr==4); assign sw_wr_en_5 = sw_wr_en && (sw_addr==5); -always @ (posedge wbm_clk_i or negedge wbm_rst_n) +always @ (posedge wbm_clk_i or negedge s_reset_n) begin : preg_out_Seq - if (wbm_rst_n == 1'b0) + if (s_reset_n == 1'b0) begin reg_rdata <= 'h0; reg_ack <= 1'b0; @@ -455,11 +514,22 @@ //------------------------------------- // Global + Clock Control // ------------------------------------- -assign cfg_glb_ctrl = reg_0[31:0]; -assign cfg_wb_clk_ctrl = cfg_clk_ctrl2[7:0]; -assign cfg_rtc_clk_ctrl = cfg_clk_ctrl2[15:8]; -assign cfg_usb_clk_ctrl = cfg_clk_ctrl2[23:16]; -assign cfg_cpu_clk_ctrl = cfg_clk_ctrl2[31:24]; +assign cfg_glb_ctrl = reg_0[31:0]; +// Reset control +// On Power-up wb & pll power default enabled +ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0] & s_reset_n),.X(wbd_int_rst_n)); +ctech_buf u_buf_pll_rst (.A(cfg_glb_ctrl[1] & s_reset_n),.X(wbd_pll_rst_n)); + +//assign cfg_fast_sim = cfg_glb_ctrl[8]; +ctech_clk_buf u_fastsim_buf (.A (cfg_glb_ctrl[8]), . X(cfg_fast_sim)); // To Bypass Reset FSM initial wait time + +assign cfg_pll_enb = cfg_glb_ctrl[15]; +assign cfg_ref_pll_div = cfg_glb_ctrl[14:12]; +assign cfg_mon_sel = cfg_glb_ctrl[11:8]; + + +assign cfg_wb_clk_ctrl = cfg_clk_ctrl2[3:0]; +assign cfg_cpu_clk_ctrl = cfg_clk_ctrl2[7:4]; always @( *) @@ -470,18 +540,19 @@ 3'b000 : reg_out [31:0] = reg_0; 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]}; 3'b010 : reg_out [31:0] = cfg_clk_ctrl1 [31:0]; - 3'b011 : reg_out [31:0] = cfg_clk_ctrl2 [31:0]; + 3'b011 : reg_out [31:0] = {24'h0,cfg_clk_ctrl2 [7:0]}; 3'b100 : reg_out [31:0] = cfg_pll_ctrl [31:0]; + 3'b101 : reg_out [31:0] = system_strap [31:0]; default : reg_out [31:0] = 'h0; endcase end -generic_register #(32,0 ) u_glb_ctrl ( +generic_register #(32,32'h8003 ) u_glb_ctrl ( .we ({32{sw_wr_en_0}} ), .data_in (wb_dat_i[31:0] ), - .reset_n (wbm_rst_n ), + .reset_n (e_reset_n ), .clk (wbm_clk_i ), //List of Outs @@ -491,37 +562,84 @@ generic_register #(16,16'h1000 ) u_bank_sel ( .we ({16{sw_wr_en_1}} ), .data_in (wb_dat_i[15:0] ), - .reset_n (wbm_rst_n ), + .reset_n (e_reset_n ), .clk (wbm_clk_i ), //List of Outs .data_out (cfg_bank_sel[15:0] ) ); +//----------------------------------------------- +// clock control-1 +//---------------------------------------------- -generic_register #(32,0 ) u_clk_ctrl1 ( - .we ({32{sw_wr_en_2}} ), - .data_in (wb_dat_i[31:0] ), - .reset_n (wbm_rst_n ), - .clk (wbm_clk_i ), - - //List of Outs - .data_out (cfg_clk_ctrl1[31:0]) - ); +wire [31:0] rst_clk_ctrl1; -generic_register #(32,0 ) u_clk_ctrl2 ( - .we ({32{sw_wr_en_3}} ), - .data_in (wb_dat_i[31:0] ), - .reset_n (wbm_rst_n ), - .clk (wbm_clk_i ), - - //List of Outs - .data_out (cfg_clk_ctrl2[31:0]) - ); -generic_register #(32,0 ) u_pll_ctrl ( +assign rst_clk_ctrl1[3:0] = (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b00) ? SKEW_RESET_VAL[3:0] : + (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 : + (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4; + +assign rst_clk_ctrl1[7:4] = (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b00) ? SKEW_RESET_VAL[7:4] : + (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 : + (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4; + +assign rst_clk_ctrl1[11:8] = (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b00) ? SKEW_RESET_VAL[11:8] : + (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 : + (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4; + +assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b00) ? SKEW_RESET_VAL[15:12] : + (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 : + (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4; + +assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b00) ? SKEW_RESET_VAL[19:16] : + (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 : + (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4; + +assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b00) ? SKEW_RESET_VAL[23:20] : + (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 : + (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4; + +assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b00) ? SKEW_RESET_VAL[27:24] : + (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 : + (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4; + +assign rst_clk_ctrl1[31:28] = 4'b0; + + +always @ (posedge wbm_clk_i ) begin + if (p_reset_n == 1'b0) begin + cfg_clk_ctrl1 <= rst_clk_ctrl1 ; + end + else begin + if(sw_wr_en_2 ) + cfg_clk_ctrl1 <= wb_dat_i[31:0]; + end +end + +//-------------------------------- +// clock control-2 +//-------------------------------- +always @ (posedge wbm_clk_i) begin + if (p_reset_n == 1'b0) begin + cfg_clk_ctrl2 <= strap_sticky[7:0] ; + end + else begin + if(sw_wr_en_3 ) + cfg_clk_ctrl2 <= wb_dat_i[7:0]; + end +end +//-------------------------------- +// Pll Control +//-------------------------------- +// PLL clock : 199.680 Mhz Period: 5.008 & bcount: 7, period +// cfg_dc_trim = 26'b0000000000000_1010101101001 +// cfg_pll_fed_div = 5'b00000 +// cfg_dco_mode = 1'b1 + +generic_register #(32,{1'b1,5'b00000,26'b0000000000000_1010101101001} ) u_pll_ctrl ( .we ({32{sw_wr_en_4}} ), .data_in (wb_dat_i[31:0] ), - .reset_n (wbm_rst_n ), + .reset_n (e_reset_n ), .clk (wbm_clk_i ), //List of Outs @@ -529,6 +647,32 @@ ); +always @ (posedge wbm_clk_i ) begin + if (p_reset_n == 1'b0) begin + cfg_clk_ctrl2 <= strap_sticky[7:0] ; + end + else begin + if(sw_wr_en_3 ) + cfg_clk_ctrl2 <= wb_dat_i[7:0]; + end +end +//------------------------------------------------------------- +// Note: system_strap reset (p_reset_n) will be released +// eariler than s_reset_n to take care of strap loading +//-------------------------------------------------------------- +always @ (posedge wbm_clk_i) begin + if (s_reset_n == 1'b0) begin + system_strap <= {soft_reboot,strap_sticky[30:0]}; + end + else if(sw_wr_en_5 ) begin + system_strap <= wb_dat_i; + end +end + + +//--------------------- End of Register Bank ------------------------ + + assign wb_stb_int = wb_req & !reg_sel; // Since design need more than 16MB address space, we have implemented @@ -537,7 +681,7 @@ async_wb u_async_wb( // Master Port - .wbm_rst_n (wbm_rst_n ), + .wbm_rst_n (s_reset_n ), .wbm_clk_i (wbm_clk_i ), .wbm_cyc_i (wb_cyc_i ), .wbm_stb_i (wb_stb_int ), @@ -571,7 +715,7 @@ .clk_o (pll_ref_clk ), // Inputs .mclk (user_clock1 ), - .reset_n (wbm_rst_n ), + .reset_n (e_reset_n ), .clk_div_ratio (cfg_ref_pll_div ) ); @@ -582,39 +726,41 @@ .clk_o (pll_clk_div16 ), // Inputs .mclk (int_pll_clock ), - .reset_n (wbm_rst_n ), + .reset_n (e_reset_n ), .clk_div_ratio (4'hF ) ); //---------------------------------- // Generate Internal WishBone Clock //---------------------------------- -logic wb_clk_div; -logic wbs_ref_clk_int; -logic wbs_ref_clk; +logic wb_clk_div; +logic wbs_ref_clk_int; +logic wbs_ref_clk; -wire [1:0] cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[7:6]; -wire cfg_wb_clk_div = cfg_wb_clk_ctrl[5]; -wire [4:0] cfg_wb_clk_ratio = cfg_wb_clk_ctrl[4:0]; +wire [1:0] cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[1:0]; +wire [1:0] cfg_wb_clk_ratio = cfg_wb_clk_ctrl[3:2]; - + // Keep WBS in Ref clock during initial boot to strap loading assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 : (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 : - int_pll_clock; + (cfg_wb_clk_src_sel ==2'b10) ? int_pll_clock : xtal_clk; ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk)); +ctech_clk_gate u_clkgate_wbs (.GATE (clk_enb), . CLK(wbs_clk_div), .GCLK(wbs_clk_out)); -//assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i; -ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk_out)); +assign wbs_clk_div =(force_refclk) ? user_clock1 : + (cfg_wb_clk_ratio == 2'b00) ? wbs_ref_clk : + (cfg_wb_clk_ratio == 2'b01) ? wbs_ref_clk_div_2 : + (cfg_wb_clk_ratio == 2'b10) ? wbs_ref_clk_div_4 : wbs_ref_clk_div_8; - -clk_ctl #(4) u_wbclk ( +clk_div8 u_wbclk ( // Outputs - .clk_o (wb_clk_div ), + .clk_div_8 (wbs_ref_clk_div_8 ), + .clk_div_4 (wbs_ref_clk_div_4 ), + .clk_div_2 (wbs_ref_clk_div_2 ), // Inputs - .mclk (wbs_ref_clk ), - .reset_n (wbm_rst_n ), - .clk_div_ratio (cfg_wb_clk_ratio ) + .mclk (wbs_ref_clk ), + .reset_n (p_reset_n ) ); @@ -626,78 +772,29 @@ wire cpu_ref_clk; wire cpu_clk_int; -wire [1:0] cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[7:6]; -wire cfg_cpu_clk_div = cfg_cpu_clk_ctrl[5]; -wire [4:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[4:0]; +wire [1:0] cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[1:0]; +wire [1:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[3:2]; assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 : (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 : - int_pll_clock; + (cfg_cpu_clk_src_sel ==2'b10) ? int_pll_clock : xtal_clk; ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk)); -//assign cpu_clk_int = (cfg_cpu_clk_div) ? cpu_clk_div : cpu_ref_clk; -ctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S (cfg_cpu_clk_div), .X (cpu_clk_int)); +ctech_clk_gate u_clkgate_cpu (.GATE (clk_enb), . CLK(cpu_clk_div), .GCLK(cpu_clk)); -ctech_clk_buf u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk)); +assign cpu_clk_div = (cfg_wb_clk_ratio == 2'b00) ? cpu_ref_clk : + (cfg_wb_clk_ratio == 2'b01) ? cpu_ref_clk_div_2 : + (cfg_wb_clk_ratio == 2'b10) ? cpu_ref_clk_div_4 : cpu_ref_clk_div_8; -clk_ctl #(4) u_cpuclk ( + +clk_div8 u_cpuclk ( // Outputs - .clk_o (cpu_clk_div ), + .clk_div_8 (cpu_ref_clk_div_8 ), + .clk_div_4 (cpu_ref_clk_div_4 ), + .clk_div_2 (cpu_ref_clk_div_2 ), // Inputs - .mclk (cpu_ref_clk ), - .reset_n (wbm_rst_n ), - .clk_div_ratio (cfg_cpu_clk_ratio) + .mclk (cpu_ref_clk ), + .reset_n (p_reset_n ) ); - -//---------------------------------- -// Generate RTC Clock Generation -//---------------------------------- -wire rtc_clk_div; -wire [7:0] cfg_rtc_clk_ratio = cfg_rtc_clk_ctrl[7:0]; - - -ctech_clk_buf u_clkbuf_rtc (.A (rtc_clk_div), . X(rtc_clk)); - -clk_ctl #(7) u_rtcclk ( - // Outputs - .clk_o (rtc_clk_div ), - // Inputs - .mclk (user_clock2 ), - .reset_n (wbm_rst_n ), - .clk_div_ratio (cfg_rtc_clk_ratio) - ); - - -//---------------------------------- -// Generate USB Clock Generation -//---------------------------------- -wire usb_clk_div; -wire usb_ref_clk_int; -wire usb_ref_clk; -wire usb_clk_int; - -wire [1:0] cfg_usb_clk_sel_sel = cfg_usb_clk_ctrl[7:6]; -wire cfg_usb_clk_div = cfg_usb_clk_ctrl[5]; -wire [4:0] cfg_usb_clk_ratio = cfg_usb_clk_ctrl[4:0]; - -assign usb_ref_clk_int = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 : - (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 : - int_pll_clock; -ctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk)); -//assign usb_clk_int = (cfg_usb_clk_div) ? usb_clk_div : usb_ref_clk; -ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S (cfg_usb_clk_div), .X (usb_clk_int)); - - -ctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk)); - -clk_ctl #(4) u_usbclk ( - // Outputs - .clk_o (usb_clk_div ), - // Inputs - .mclk (usb_ref_clk ), - .reset_n (wbm_rst_n ), - .clk_div_ratio (cfg_usb_clk_ratio) - ); - endmodule
diff --git a/verilog/rtl/wb_host/src/wb_reset_fsm.sv b/verilog/rtl/wb_host/src/wb_reset_fsm.sv new file mode 100644 index 0000000..23fd015 --- /dev/null +++ b/verilog/rtl/wb_host/src/wb_reset_fsm.sv
@@ -0,0 +1,146 @@ + +/************************************************************************* + This block control the reset sequence + +expected Reset removal sequence + + _________ __________________________________________________ + | | +e_reset_n |________________| + + ________ ________________________________________ + XXXXXXXXX | +p_reset_n XXXXXXXXX__________________________| + + + ____________ + XXXXXXXXX | +clk_enb XXXXXXXXX_____________________________________________________| + + ____________ + XXXXXXXXX | +s_reset_n XXXXXXXXX________________________________________________________________| + +************************************************************************************************************/ + +module wb_reset_fsm ( + input logic clk , + input logic e_reset_n , // external reset + input logic cfg_fast_sim , + input logic soft_boot_req , + + output logic p_reset_n , // power-on reset + output logic s_reset_n , // soft reset + output logic clk_enb , + output logic soft_reboot , // Indicate Soft Reboot + output logic force_refclk // Keep WBS in Ref clock during initial boot to strap loading + +); + +logic [2:0] state; +logic [15:0] clk_cnt; + +parameter FSM_POWER_UP = 3'b000; +parameter FSM_POWERON_RESET = 3'b001; +parameter FSM_STRAP_LOAD = 3'b010; +parameter FSM_STRAP_CLK_ENB = 3'b011; +parameter FSM_DEASSERT_FORCE = 3'b100; +parameter FSM_SOFT_RESET = 3'b101; +parameter FSM_SOFT_BOOT_REQ = 3'b110; +parameter FSM_CLK_EN_DEASSERT = 3'b111; + +logic boot_req_s,boot_req_ss; + +wire [15:0] clk_exit_cnt = (cfg_fast_sim) ? 100 : 60000; + +always @ (posedge clk or negedge e_reset_n) begin + if (e_reset_n == 1'b0) begin + boot_req_s <= 1'b0; + boot_req_ss <= 1'b0; + state <= FSM_POWER_UP; + s_reset_n <= 0; + p_reset_n <= 0; + clk_cnt <= 0; + soft_reboot <= 0; + clk_enb <= 0; + force_refclk <= 1; + end else begin + // Double Sync the incoming signal + boot_req_s <= soft_boot_req; + boot_req_ss <= boot_req_s; + case(state) + FSM_POWER_UP : begin + if(clk_cnt == clk_exit_cnt) begin + clk_cnt <= 0; + state <= FSM_STRAP_CLK_ENB; + end else begin + clk_cnt <= clk_cnt + 1; + end + end + FSM_STRAP_CLK_ENB : begin + if(clk_cnt == 15) begin + clk_enb <= 1; + clk_cnt <= 0; + state <= FSM_POWERON_RESET; + end else begin + clk_cnt <= clk_cnt + 1; + end + end + FSM_POWERON_RESET : begin + if(clk_cnt == 15) begin + p_reset_n <= 1; + clk_cnt <= 0; + state <= FSM_DEASSERT_FORCE; + end else begin + clk_cnt <= clk_cnt + 1; + end + end + + FSM_DEASSERT_FORCE : begin + if(clk_cnt == 15) begin + force_refclk <= 0; + clk_cnt <= 0; + state <= FSM_SOFT_RESET; + end else begin + clk_cnt <= clk_cnt + 1; + end + end + + FSM_SOFT_RESET : begin + if(clk_cnt == 15) begin + s_reset_n <= 1; + clk_cnt <= 0; + state <= FSM_SOFT_BOOT_REQ; + end else begin + clk_cnt <= clk_cnt + 1; + end + end + FSM_SOFT_BOOT_REQ : begin + if(boot_req_ss) begin + soft_reboot <= 1; + clk_cnt <= 0; + force_refclk <= 1; + clk_enb <= 0; + state <= FSM_CLK_EN_DEASSERT; + end + end + // Disable clock to avoid to block all transation + FSM_CLK_EN_DEASSERT : begin + if(clk_cnt == 15) begin + s_reset_n <= 0; + clk_enb <= 1; + clk_cnt <= 0; + state <= FSM_SOFT_RESET; + end else begin + clk_cnt <= clk_cnt + 1; + end + end + + endcase + + end +end + + + +endmodule
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 7e348fc..e595919 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -203,7 +203,7 @@ input logic s2_wbd_ack_i, // input logic s2_wbd_err_i, - unused output logic [31:0] s2_wbd_dat_o, - output logic [8:0] s2_wbd_adr_o, // glbl reg need only 9 bits + output logic [9:0] s2_wbd_adr_o, // glbl reg need only 9 bits output logic [3:0] s2_wbd_sel_o, output logic s2_wbd_we_o, output logic s2_wbd_cyc_o, @@ -677,7 +677,7 @@ assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ; assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ; - assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[8:0] ; // Global Reg Need 8 bit + assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ; assign s2_wbd_we_o = s2_wb_wr.wbd_we ; assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;