mpw7 timing clean database
diff --git a/README.md b/README.md index 6f3c17d..7ee8651 100644 --- a/README.md +++ b/README.md
@@ -570,6 +570,67 @@ make user_project_wrapper ``` +#Timing Analysis +## Timing Analysis setup + +``` sh + make setup-timing-scripts + make install + make install_mcw +``` +his will update Caravel design files and install the scripts for running timing. + +## Running Timing Analysis + +``` sh +make extract-parasitics +make create-spef-mapping +make caravel-sta +``` +#Other Miscellaneous Targets +The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane’s flow. + +Run make help to display available targets. + +Run lvs on the mag view, + +``` sh +make lvs-<macro_name> +``` + +Run lvs on the gds, + +``` sh +make lvs-gds-<macro_name> +``` + +Run lvs on the maglef, + +``` sh +make lvs-maglef-<macro_name> +``` + +Run drc using magic, + +``` sh +make drc-<macro_name> +``` + +Run antenna check using magic, + +``` sh +make antenna-<macro_name> +``` + +Run XOR check, + +``` sh +make xor-wrapper +``` + + + + # Tool Sets Riscduino Soc flow uses Openlane tool sets.
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 3d0d18f..9aa0565 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index 658a653..3ea7c80 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl index 960f746..3900d26 100755 --- a/openlane/pinmux_top/config.tcl +++ b/openlane/pinmux_top/config.tcl
@@ -41,7 +41,7 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv \
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg index a8e15ef..811a5cf 100644 --- a/openlane/pinmux_top/pin_order.cfg +++ b/openlane/pinmux_top/pin_order.cfg
@@ -104,7 +104,6 @@ pinmux_debug\[29\] pinmux_debug\[30\] pinmux_debug\[31\] -cpu_clk #W strap_sticky\[31\] 000 0 2 @@ -306,6 +305,7 @@ reg_rdata\[0\] reg_ack +cpu_clk #N
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 7576c81..358a009 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -41,7 +41,7 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_core.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_cfg.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index 407a338..006cdfe 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -42,7 +42,7 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reset_fsm.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reg.sv \
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 8b7baf5..38f2c70 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -30,6 +30,8 @@ set ::env(CLOCK_NET) "clk_i" set ::env(SYNTH_MAX_FANOUT) 4 +set ::env(SYNTH_BUFFERING) {0} + ## CTS BUFFER set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" @@ -41,7 +43,8 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_wbb.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo2.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \ @@ -51,8 +54,8 @@ set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\ - CH_DATA_WD=146 \ +set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=7\ + CH_DATA_WD=154 \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 @@ -71,7 +74,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 300 1725" +set ::env(DIE_AREA) "0 0 300 1800" #set ::env(GRT_OBS) "met4 0 0 300 1725" @@ -101,22 +104,20 @@ ## Placement set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 - -set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 2 set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2 +set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500" +set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0" +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1" ## Routing set ::env(GRT_ADJUSTMENT) 0.1 set ::env(DPL_CELL_PADDING) 1 +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1" set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5} -set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5} - set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25} -set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25} - set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500} -set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500} #LVS Issue - DEF Base looks to having issue set ::env(MAGIC_EXT_USE_GDS) {1} @@ -128,20 +129,16 @@ set ::env(MAGIC_GENERATE_LEF) {1} set ::env(MAGIC_WRITE_FULL_LEF) {0} +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2 + +set ::env(ECO_ENABLE) {0} +#set ::env(CURRENT_STEP) "synthesis" +#set ::env(LAST_STEP) "parasitics_sta" set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" set ::env(QUIT_ON_LVS_ERROR) "1" set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" - -set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" -set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" -set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1" -set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000" -set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0" -set ::env(PL_RESIZER_MAX_CAP_MARGIN) "5" - -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 6.2 -set ::env(FP_PDN_HWIDTH) 6.2
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 46750ad..5d9f81e 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,7 +3,12 @@ #MANUAL_PLACE #S -rst_n 000 0 2 +ch_clk_in\[6\] 000 0 2 +ch_clk_in\[5\] +ch_clk_in\[4\] + + +rst_n 020 0 2 ch_data_in\[43\] ch_data_in\[42\] ch_data_in\[41\] @@ -170,7 +175,17 @@ m0_wbd_err_o m0_wbd_cyc_i -ch_data_out\[145\] 225 0 2 +ch_data_in\[153\] 225 0 2 +ch_data_in\[152\] +ch_data_in\[151\] +ch_data_in\[150\] + +ch_data_in\[149\] +ch_data_in\[148\] +ch_data_in\[147\] +ch_data_in\[146\] + +ch_data_out\[145\] ch_data_out\[144\] ch_data_out\[143\] ch_data_out\[142\] @@ -250,6 +265,7 @@ ch_data_out\[22\] ch_data_out\[21\] ch_data_out\[20\] +ch_clk_out\[4\] ch_data_out\[3\] 050 0 2 ch_data_out\[2\] @@ -577,19 +593,30 @@ ch_data_out\[42\] ch_data_out\[41\] ch_data_out\[40\] + ch_data_out\[39\] ch_data_out\[38\] ch_data_out\[37\] ch_data_out\[36\] + ch_data_out\[35\] ch_data_out\[34\] ch_data_out\[33\] ch_data_out\[32\] + + ch_data_out\[31\] ch_data_out\[30\] ch_data_out\[29\] ch_data_out\[28\] + +ch_data_out\[27\] 750 0 2 +ch_data_out\[26\] +ch_data_out\[25\] +ch_data_out\[24\] +ch_clk_out\[5\] + ch_data_out\[76\] 1600 0 2 ch_data_out\[75\] ch_data_out\[74\] @@ -624,10 +651,15 @@ ch_data_out\[45\] ch_data_out\[44\] -ch_data_out\[27\] -ch_data_out\[26\] -ch_data_out\[25\] -ch_data_out\[24\] +ch_data_out\[149\] 1700 0 2 +ch_data_out\[148\] +ch_data_out\[147\] +ch_data_out\[146\] + +ch_data_out\[153\] 1750 0 2 +ch_data_out\[152\] +ch_data_out\[151\] +ch_data_out\[150\] #E ch_data_out\[19\] 0000 0 2 @@ -1044,4 +1076,5 @@ s2_wbd_ack_i s2_wbd_cyc_o +ch_clk_out\[6\]
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl index e10ab74..63ccd07 100644 --- a/openlane/ycr4_iconnect/config.tcl +++ b/openlane/ycr4_iconnect/config.tcl
@@ -23,7 +23,7 @@ # Timing configuration set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "core_clk rtc_clk" +set ::env(CLOCK_PORT) "u_cclk_cts.genblk1.u_mux/X rtc_clk" set ::env(SYNTH_MAX_FANOUT) 4 @@ -34,7 +34,7 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_router.sv \ @@ -44,7 +44,7 @@ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_timer.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_arb.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \ "
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg index 2b289e1..eed55ba 100644 --- a/openlane/ycr4_iconnect/pin_order.cfg +++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -128,7 +128,8 @@ sram0_dout1\[1\] sram0_dout1\[0\] -core0_uid\[1\] 0200 00 2 +core0_clk 0200 00 2 +core0_uid\[1\] core0_uid\[0\] core0_imem_req_ack core0_imem_req @@ -457,7 +458,8 @@ core0_irq_lines\[0\] core0_irq_soft -core2_uid\[1\] 1250 00 2 +core2_clk 1250 00 2 +core2_uid\[1\] core2_uid\[0\] core2_imem_req_ack core2_imem_req @@ -786,663 +788,6 @@ core2_irq_lines\[0\] core2_irq_soft -#E -core1_uid\[1\] 0200 00 2 -core1_uid\[0\] -core1_imem_req_ack -core1_imem_req -core1_imem_cmd -core1_imem_addr\[31\] -core1_imem_addr\[30\] -core1_imem_addr\[29\] -core1_imem_addr\[28\] -core1_imem_addr\[27\] -core1_imem_addr\[26\] -core1_imem_addr\[25\] -core1_imem_addr\[24\] -core1_imem_addr\[23\] -core1_imem_addr\[22\] -core1_imem_addr\[21\] -core1_imem_addr\[20\] -core1_imem_addr\[19\] -core1_imem_addr\[18\] -core1_imem_addr\[17\] -core1_imem_addr\[16\] -core1_imem_addr\[15\] -core1_imem_addr\[14\] -core1_imem_addr\[13\] -core1_imem_addr\[12\] -core1_imem_addr\[11\] -core1_imem_addr\[10\] -core1_imem_addr\[9\] -core1_imem_addr\[8\] -core1_imem_addr\[7\] -core1_imem_addr\[6\] -core1_imem_addr\[5\] -core1_imem_addr\[4\] -core1_imem_addr\[3\] -core1_imem_addr\[2\] -core1_imem_addr\[1\] -core1_imem_addr\[0\] -core1_imem_bl\[2\] -core1_imem_bl\[1\] -core1_imem_bl\[0\] -core1_imem_rdata\[31\] -core1_imem_rdata\[30\] -core1_imem_rdata\[29\] -core1_imem_rdata\[28\] -core1_imem_rdata\[27\] -core1_imem_rdata\[26\] -core1_imem_rdata\[25\] -core1_imem_rdata\[24\] -core1_imem_rdata\[23\] -core1_imem_rdata\[22\] -core1_imem_rdata\[21\] -core1_imem_rdata\[20\] -core1_imem_rdata\[19\] -core1_imem_rdata\[18\] -core1_imem_rdata\[17\] -core1_imem_rdata\[16\] -core1_imem_rdata\[15\] -core1_imem_rdata\[14\] -core1_imem_rdata\[13\] -core1_imem_rdata\[12\] -core1_imem_rdata\[11\] -core1_imem_rdata\[10\] -core1_imem_rdata\[9\] -core1_imem_rdata\[8\] -core1_imem_rdata\[7\] -core1_imem_rdata\[6\] -core1_imem_rdata\[5\] -core1_imem_rdata\[4\] -core1_imem_rdata\[3\] -core1_imem_rdata\[2\] -core1_imem_rdata\[1\] -core1_imem_rdata\[0\] -core1_imem_resp\[1\] -core1_imem_resp\[0\] - -core1_dmem_req_ack 0350 0 2 -core1_dmem_req -core1_dmem_cmd -core1_dmem_width\[1\] -core1_dmem_width\[0\] -core1_dmem_addr\[31\] -core1_dmem_addr\[30\] -core1_dmem_addr\[29\] -core1_dmem_addr\[28\] -core1_dmem_addr\[27\] -core1_dmem_addr\[26\] -core1_dmem_addr\[25\] -core1_dmem_addr\[24\] -core1_dmem_addr\[23\] -core1_dmem_addr\[22\] -core1_dmem_addr\[21\] -core1_dmem_addr\[20\] -core1_dmem_addr\[19\] -core1_dmem_addr\[18\] -core1_dmem_addr\[17\] -core1_dmem_addr\[16\] -core1_dmem_addr\[15\] -core1_dmem_addr\[14\] -core1_dmem_addr\[13\] -core1_dmem_addr\[12\] -core1_dmem_addr\[11\] -core1_dmem_addr\[10\] -core1_dmem_addr\[9\] -core1_dmem_addr\[8\] -core1_dmem_addr\[7\] -core1_dmem_addr\[6\] -core1_dmem_addr\[5\] -core1_dmem_addr\[4\] -core1_dmem_addr\[3\] -core1_dmem_addr\[2\] -core1_dmem_addr\[1\] -core1_dmem_addr\[0\] -core1_dmem_wdata\[31\] -core1_dmem_wdata\[30\] -core1_dmem_wdata\[29\] -core1_dmem_wdata\[28\] -core1_dmem_wdata\[27\] -core1_dmem_wdata\[26\] -core1_dmem_wdata\[25\] -core1_dmem_wdata\[24\] -core1_dmem_wdata\[23\] -core1_dmem_wdata\[22\] -core1_dmem_wdata\[21\] -core1_dmem_wdata\[20\] -core1_dmem_wdata\[19\] -core1_dmem_wdata\[18\] -core1_dmem_wdata\[17\] -core1_dmem_wdata\[16\] -core1_dmem_wdata\[15\] -core1_dmem_wdata\[14\] -core1_dmem_wdata\[13\] -core1_dmem_wdata\[12\] -core1_dmem_wdata\[11\] -core1_dmem_wdata\[10\] -core1_dmem_wdata\[9\] -core1_dmem_wdata\[8\] -core1_dmem_wdata\[7\] -core1_dmem_wdata\[6\] -core1_dmem_wdata\[5\] -core1_dmem_wdata\[4\] -core1_dmem_wdata\[3\] -core1_dmem_wdata\[2\] -core1_dmem_wdata\[1\] -core1_dmem_wdata\[0\] -core1_dmem_rdata\[31\] -core1_dmem_rdata\[30\] -core1_dmem_rdata\[29\] -core1_dmem_rdata\[28\] -core1_dmem_rdata\[27\] -core1_dmem_rdata\[26\] -core1_dmem_rdata\[25\] -core1_dmem_rdata\[24\] -core1_dmem_rdata\[23\] -core1_dmem_rdata\[22\] -core1_dmem_rdata\[21\] -core1_dmem_rdata\[20\] -core1_dmem_rdata\[19\] -core1_dmem_rdata\[18\] -core1_dmem_rdata\[17\] -core1_dmem_rdata\[16\] -core1_dmem_rdata\[15\] -core1_dmem_rdata\[14\] -core1_dmem_rdata\[13\] -core1_dmem_rdata\[12\] -core1_dmem_rdata\[11\] -core1_dmem_rdata\[10\] -core1_dmem_rdata\[9\] -core1_dmem_rdata\[8\] -core1_dmem_rdata\[7\] -core1_dmem_rdata\[6\] -core1_dmem_rdata\[5\] -core1_dmem_rdata\[4\] -core1_dmem_rdata\[3\] -core1_dmem_rdata\[2\] -core1_dmem_rdata\[1\] -core1_dmem_rdata\[0\] -core1_dmem_resp\[1\] -core1_dmem_resp\[0\] - -core1_debug\[48\] 0500 0 2 -core1_debug\[47\] -core1_debug\[46\] -core1_debug\[45\] -core1_debug\[44\] -core1_debug\[43\] -core1_debug\[42\] -core1_debug\[41\] -core1_debug\[40\] -core1_debug\[39\] -core1_debug\[38\] -core1_debug\[37\] -core1_debug\[36\] -core1_debug\[35\] -core1_debug\[34\] -core1_debug\[33\] -core1_debug\[32\] -core1_debug\[31\] -core1_debug\[30\] -core1_debug\[29\] -core1_debug\[28\] -core1_debug\[27\] -core1_debug\[26\] -core1_debug\[25\] -core1_debug\[24\] -core1_debug\[23\] -core1_debug\[22\] -core1_debug\[21\] -core1_debug\[20\] -core1_debug\[19\] -core1_debug\[18\] -core1_debug\[17\] -core1_debug\[16\] -core1_debug\[15\] -core1_debug\[14\] -core1_debug\[13\] -core1_debug\[12\] -core1_debug\[11\] -core1_debug\[10\] -core1_debug\[9\] -core1_debug\[8\] -core1_debug\[7\] -core1_debug\[6\] -core1_debug\[5\] -core1_debug\[4\] -core1_debug\[3\] -core1_debug\[2\] -core1_debug\[1\] -core1_debug\[0\] - -core1_timer_irq 600 0 2 -core1_timer_val\[63\] -core1_timer_val\[62\] -core1_timer_val\[61\] -core1_timer_val\[60\] -core1_timer_val\[59\] -core1_timer_val\[58\] -core1_timer_val\[57\] -core1_timer_val\[56\] -core1_timer_val\[55\] -core1_timer_val\[54\] -core1_timer_val\[53\] -core1_timer_val\[52\] -core1_timer_val\[51\] -core1_timer_val\[50\] -core1_timer_val\[49\] -core1_timer_val\[48\] -core1_timer_val\[47\] -core1_timer_val\[46\] -core1_timer_val\[45\] -core1_timer_val\[44\] -core1_timer_val\[43\] -core1_timer_val\[42\] -core1_timer_val\[41\] -core1_timer_val\[40\] -core1_timer_val\[39\] -core1_timer_val\[38\] -core1_timer_val\[37\] -core1_timer_val\[36\] -core1_timer_val\[35\] -core1_timer_val\[34\] -core1_timer_val\[33\] -core1_timer_val\[32\] -core1_timer_val\[31\] -core1_timer_val\[30\] -core1_timer_val\[29\] -core1_timer_val\[28\] -core1_timer_val\[27\] -core1_timer_val\[26\] -core1_timer_val\[25\] -core1_timer_val\[24\] -core1_timer_val\[23\] -core1_timer_val\[22\] -core1_timer_val\[21\] -core1_timer_val\[20\] -core1_timer_val\[19\] -core1_timer_val\[18\] -core1_timer_val\[17\] -core1_timer_val\[16\] -core1_timer_val\[15\] -core1_timer_val\[14\] -core1_timer_val\[13\] -core1_timer_val\[12\] -core1_timer_val\[11\] -core1_timer_val\[10\] -core1_timer_val\[9\] -core1_timer_val\[8\] -core1_timer_val\[7\] -core1_timer_val\[6\] -core1_timer_val\[5\] -core1_timer_val\[4\] -core1_timer_val\[3\] -core1_timer_val\[2\] -core1_timer_val\[1\] -core1_timer_val\[0\] -core1_irq_lines\[31\] -core1_irq_lines\[30\] -core1_irq_lines\[29\] -core1_irq_lines\[28\] -core1_irq_lines\[27\] -core1_irq_lines\[26\] -core1_irq_lines\[25\] -core1_irq_lines\[24\] -core1_irq_lines\[23\] -core1_irq_lines\[22\] -core1_irq_lines\[21\] -core1_irq_lines\[20\] -core1_irq_lines\[19\] -core1_irq_lines\[18\] -core1_irq_lines\[17\] -core1_irq_lines\[16\] -core1_irq_lines\[15\] -core1_irq_lines\[14\] -core1_irq_lines\[13\] -core1_irq_lines\[12\] -core1_irq_lines\[11\] -core1_irq_lines\[10\] -core1_irq_lines\[9\] -core1_irq_lines\[8\] -core1_irq_lines\[7\] -core1_irq_lines\[6\] -core1_irq_lines\[5\] -core1_irq_lines\[4\] -core1_irq_lines\[3\] -core1_irq_lines\[2\] -core1_irq_lines\[1\] -core1_irq_lines\[0\] -core1_irq_soft - -core3_uid\[1\] 1250 00 2 -core3_uid\[0\] -core3_imem_req_ack -core3_imem_req -core3_imem_cmd -core3_imem_addr\[31\] -core3_imem_addr\[30\] -core3_imem_addr\[29\] -core3_imem_addr\[28\] -core3_imem_addr\[27\] -core3_imem_addr\[26\] -core3_imem_addr\[25\] -core3_imem_addr\[24\] -core3_imem_addr\[23\] -core3_imem_addr\[22\] -core3_imem_addr\[21\] -core3_imem_addr\[20\] -core3_imem_addr\[19\] -core3_imem_addr\[18\] -core3_imem_addr\[17\] -core3_imem_addr\[16\] -core3_imem_addr\[15\] -core3_imem_addr\[14\] -core3_imem_addr\[13\] -core3_imem_addr\[12\] -core3_imem_addr\[11\] -core3_imem_addr\[10\] -core3_imem_addr\[9\] -core3_imem_addr\[8\] -core3_imem_addr\[7\] -core3_imem_addr\[6\] -core3_imem_addr\[5\] -core3_imem_addr\[4\] -core3_imem_addr\[3\] -core3_imem_addr\[2\] -core3_imem_addr\[1\] -core3_imem_addr\[0\] -core3_imem_bl\[2\] -core3_imem_bl\[1\] -core3_imem_bl\[0\] -core3_imem_rdata\[31\] -core3_imem_rdata\[30\] -core3_imem_rdata\[29\] -core3_imem_rdata\[28\] -core3_imem_rdata\[27\] -core3_imem_rdata\[26\] -core3_imem_rdata\[25\] -core3_imem_rdata\[24\] -core3_imem_rdata\[23\] -core3_imem_rdata\[22\] -core3_imem_rdata\[21\] -core3_imem_rdata\[20\] -core3_imem_rdata\[19\] -core3_imem_rdata\[18\] -core3_imem_rdata\[17\] -core3_imem_rdata\[16\] -core3_imem_rdata\[15\] -core3_imem_rdata\[14\] -core3_imem_rdata\[13\] -core3_imem_rdata\[12\] -core3_imem_rdata\[11\] -core3_imem_rdata\[10\] -core3_imem_rdata\[9\] -core3_imem_rdata\[8\] -core3_imem_rdata\[7\] -core3_imem_rdata\[6\] -core3_imem_rdata\[5\] -core3_imem_rdata\[4\] -core3_imem_rdata\[3\] -core3_imem_rdata\[2\] -core3_imem_rdata\[1\] -core3_imem_rdata\[0\] -core3_imem_resp\[1\] -core3_imem_resp\[0\] - -core3_dmem_req_ack 1400 0 2 -core3_dmem_req -core3_dmem_cmd -core3_dmem_width\[1\] -core3_dmem_width\[0\] -core3_dmem_addr\[31\] -core3_dmem_addr\[30\] -core3_dmem_addr\[29\] -core3_dmem_addr\[28\] -core3_dmem_addr\[27\] -core3_dmem_addr\[26\] -core3_dmem_addr\[25\] -core3_dmem_addr\[24\] -core3_dmem_addr\[23\] -core3_dmem_addr\[22\] -core3_dmem_addr\[21\] -core3_dmem_addr\[20\] -core3_dmem_addr\[19\] -core3_dmem_addr\[18\] -core3_dmem_addr\[17\] -core3_dmem_addr\[16\] -core3_dmem_addr\[15\] -core3_dmem_addr\[14\] -core3_dmem_addr\[13\] -core3_dmem_addr\[12\] -core3_dmem_addr\[11\] -core3_dmem_addr\[10\] -core3_dmem_addr\[9\] -core3_dmem_addr\[8\] -core3_dmem_addr\[7\] -core3_dmem_addr\[6\] -core3_dmem_addr\[5\] -core3_dmem_addr\[4\] -core3_dmem_addr\[3\] -core3_dmem_addr\[2\] -core3_dmem_addr\[1\] -core3_dmem_addr\[0\] -core3_dmem_wdata\[31\] -core3_dmem_wdata\[30\] -core3_dmem_wdata\[29\] -core3_dmem_wdata\[28\] -core3_dmem_wdata\[27\] -core3_dmem_wdata\[26\] -core3_dmem_wdata\[25\] -core3_dmem_wdata\[24\] -core3_dmem_wdata\[23\] -core3_dmem_wdata\[22\] -core3_dmem_wdata\[21\] -core3_dmem_wdata\[20\] -core3_dmem_wdata\[19\] -core3_dmem_wdata\[18\] -core3_dmem_wdata\[17\] -core3_dmem_wdata\[16\] -core3_dmem_wdata\[15\] -core3_dmem_wdata\[14\] -core3_dmem_wdata\[13\] -core3_dmem_wdata\[12\] -core3_dmem_wdata\[11\] -core3_dmem_wdata\[10\] -core3_dmem_wdata\[9\] -core3_dmem_wdata\[8\] -core3_dmem_wdata\[7\] -core3_dmem_wdata\[6\] -core3_dmem_wdata\[5\] -core3_dmem_wdata\[4\] -core3_dmem_wdata\[3\] -core3_dmem_wdata\[2\] -core3_dmem_wdata\[1\] -core3_dmem_wdata\[0\] -core3_dmem_rdata\[31\] -core3_dmem_rdata\[30\] -core3_dmem_rdata\[29\] -core3_dmem_rdata\[28\] -core3_dmem_rdata\[27\] -core3_dmem_rdata\[26\] -core3_dmem_rdata\[25\] -core3_dmem_rdata\[24\] -core3_dmem_rdata\[23\] -core3_dmem_rdata\[22\] -core3_dmem_rdata\[21\] -core3_dmem_rdata\[20\] -core3_dmem_rdata\[19\] -core3_dmem_rdata\[18\] -core3_dmem_rdata\[17\] -core3_dmem_rdata\[16\] -core3_dmem_rdata\[15\] -core3_dmem_rdata\[14\] -core3_dmem_rdata\[13\] -core3_dmem_rdata\[12\] -core3_dmem_rdata\[11\] -core3_dmem_rdata\[10\] -core3_dmem_rdata\[9\] -core3_dmem_rdata\[8\] -core3_dmem_rdata\[7\] -core3_dmem_rdata\[6\] -core3_dmem_rdata\[5\] -core3_dmem_rdata\[4\] -core3_dmem_rdata\[3\] -core3_dmem_rdata\[2\] -core3_dmem_rdata\[1\] -core3_dmem_rdata\[0\] -core3_dmem_resp\[1\] -core3_dmem_resp\[0\] - -core3_debug\[48\] 1550 0 2 -core3_debug\[47\] -core3_debug\[46\] -core3_debug\[45\] -core3_debug\[44\] -core3_debug\[43\] -core3_debug\[42\] -core3_debug\[41\] -core3_debug\[40\] -core3_debug\[39\] -core3_debug\[38\] -core3_debug\[37\] -core3_debug\[36\] -core3_debug\[35\] -core3_debug\[34\] -core3_debug\[33\] -core3_debug\[32\] -core3_debug\[31\] -core3_debug\[30\] -core3_debug\[29\] -core3_debug\[28\] -core3_debug\[27\] -core3_debug\[26\] -core3_debug\[25\] -core3_debug\[24\] -core3_debug\[23\] -core3_debug\[22\] -core3_debug\[21\] -core3_debug\[20\] -core3_debug\[19\] -core3_debug\[18\] -core3_debug\[17\] -core3_debug\[16\] -core3_debug\[15\] -core3_debug\[14\] -core3_debug\[13\] -core3_debug\[12\] -core3_debug\[11\] -core3_debug\[10\] -core3_debug\[9\] -core3_debug\[8\] -core3_debug\[7\] -core3_debug\[6\] -core3_debug\[5\] -core3_debug\[4\] -core3_debug\[3\] -core3_debug\[2\] -core3_debug\[1\] -core3_debug\[0\] - -core3_timer_irq 1650 0 2 -core3_timer_val\[63\] -core3_timer_val\[62\] -core3_timer_val\[61\] -core3_timer_val\[60\] -core3_timer_val\[59\] -core3_timer_val\[58\] -core3_timer_val\[57\] -core3_timer_val\[56\] -core3_timer_val\[55\] -core3_timer_val\[54\] -core3_timer_val\[53\] -core3_timer_val\[52\] -core3_timer_val\[51\] -core3_timer_val\[50\] -core3_timer_val\[49\] -core3_timer_val\[48\] -core3_timer_val\[47\] -core3_timer_val\[46\] -core3_timer_val\[45\] -core3_timer_val\[44\] -core3_timer_val\[43\] -core3_timer_val\[42\] -core3_timer_val\[41\] -core3_timer_val\[40\] -core3_timer_val\[39\] -core3_timer_val\[38\] -core3_timer_val\[37\] -core3_timer_val\[36\] -core3_timer_val\[35\] -core3_timer_val\[34\] -core3_timer_val\[33\] -core3_timer_val\[32\] -core3_timer_val\[31\] -core3_timer_val\[30\] -core3_timer_val\[29\] -core3_timer_val\[28\] -core3_timer_val\[27\] -core3_timer_val\[26\] -core3_timer_val\[25\] -core3_timer_val\[24\] -core3_timer_val\[23\] -core3_timer_val\[22\] -core3_timer_val\[21\] -core3_timer_val\[20\] -core3_timer_val\[19\] -core3_timer_val\[18\] -core3_timer_val\[17\] -core3_timer_val\[16\] -core3_timer_val\[15\] -core3_timer_val\[14\] -core3_timer_val\[13\] -core3_timer_val\[12\] -core3_timer_val\[11\] -core3_timer_val\[10\] -core3_timer_val\[9\] -core3_timer_val\[8\] -core3_timer_val\[7\] -core3_timer_val\[6\] -core3_timer_val\[5\] -core3_timer_val\[4\] -core3_timer_val\[3\] -core3_timer_val\[2\] -core3_timer_val\[1\] -core3_timer_val\[0\] - -core3_irq_lines\[31\] -core3_irq_lines\[30\] -core3_irq_lines\[29\] -core3_irq_lines\[28\] -core3_irq_lines\[27\] -core3_irq_lines\[26\] -core3_irq_lines\[25\] -core3_irq_lines\[24\] -core3_irq_lines\[23\] -core3_irq_lines\[22\] -core3_irq_lines\[21\] -core3_irq_lines\[20\] -core3_irq_lines\[19\] -core3_irq_lines\[18\] -core3_irq_lines\[17\] -core3_irq_lines\[16\] -core3_irq_lines\[15\] -core3_irq_lines\[14\] -core3_irq_lines\[13\] -core3_irq_lines\[12\] -core3_irq_lines\[11\] -core3_irq_lines\[10\] -core3_irq_lines\[9\] -core3_irq_lines\[8\] -core3_irq_lines\[7\] -core3_irq_lines\[6\] -core3_irq_lines\[5\] -core3_irq_lines\[4\] -core3_irq_lines\[3\] -core3_irq_lines\[2\] -core3_irq_lines\[1\] -core3_irq_lines\[0\] -core3_irq_soft #S core_icache_req_ack 000 0 2 @@ -1804,6 +1149,674 @@ riscv_debug\[1\] riscv_debug\[0\] +#E +cfg_ccska\[3\] +cfg_ccska\[2\] +cfg_ccska\[1\] +cfg_ccska\[0\] +core_clk_int +core_clk_skew +core_clk + +core1_clk 0200 00 2 +core1_uid\[1\] +core1_uid\[0\] +core1_imem_req_ack +core1_imem_req +core1_imem_cmd +core1_imem_addr\[31\] +core1_imem_addr\[30\] +core1_imem_addr\[29\] +core1_imem_addr\[28\] +core1_imem_addr\[27\] +core1_imem_addr\[26\] +core1_imem_addr\[25\] +core1_imem_addr\[24\] +core1_imem_addr\[23\] +core1_imem_addr\[22\] +core1_imem_addr\[21\] +core1_imem_addr\[20\] +core1_imem_addr\[19\] +core1_imem_addr\[18\] +core1_imem_addr\[17\] +core1_imem_addr\[16\] +core1_imem_addr\[15\] +core1_imem_addr\[14\] +core1_imem_addr\[13\] +core1_imem_addr\[12\] +core1_imem_addr\[11\] +core1_imem_addr\[10\] +core1_imem_addr\[9\] +core1_imem_addr\[8\] +core1_imem_addr\[7\] +core1_imem_addr\[6\] +core1_imem_addr\[5\] +core1_imem_addr\[4\] +core1_imem_addr\[3\] +core1_imem_addr\[2\] +core1_imem_addr\[1\] +core1_imem_addr\[0\] +core1_imem_bl\[2\] +core1_imem_bl\[1\] +core1_imem_bl\[0\] +core1_imem_rdata\[31\] +core1_imem_rdata\[30\] +core1_imem_rdata\[29\] +core1_imem_rdata\[28\] +core1_imem_rdata\[27\] +core1_imem_rdata\[26\] +core1_imem_rdata\[25\] +core1_imem_rdata\[24\] +core1_imem_rdata\[23\] +core1_imem_rdata\[22\] +core1_imem_rdata\[21\] +core1_imem_rdata\[20\] +core1_imem_rdata\[19\] +core1_imem_rdata\[18\] +core1_imem_rdata\[17\] +core1_imem_rdata\[16\] +core1_imem_rdata\[15\] +core1_imem_rdata\[14\] +core1_imem_rdata\[13\] +core1_imem_rdata\[12\] +core1_imem_rdata\[11\] +core1_imem_rdata\[10\] +core1_imem_rdata\[9\] +core1_imem_rdata\[8\] +core1_imem_rdata\[7\] +core1_imem_rdata\[6\] +core1_imem_rdata\[5\] +core1_imem_rdata\[4\] +core1_imem_rdata\[3\] +core1_imem_rdata\[2\] +core1_imem_rdata\[1\] +core1_imem_rdata\[0\] +core1_imem_resp\[1\] +core1_imem_resp\[0\] + +core1_dmem_req_ack 0350 0 2 +core1_dmem_req +core1_dmem_cmd +core1_dmem_width\[1\] +core1_dmem_width\[0\] +core1_dmem_addr\[31\] +core1_dmem_addr\[30\] +core1_dmem_addr\[29\] +core1_dmem_addr\[28\] +core1_dmem_addr\[27\] +core1_dmem_addr\[26\] +core1_dmem_addr\[25\] +core1_dmem_addr\[24\] +core1_dmem_addr\[23\] +core1_dmem_addr\[22\] +core1_dmem_addr\[21\] +core1_dmem_addr\[20\] +core1_dmem_addr\[19\] +core1_dmem_addr\[18\] +core1_dmem_addr\[17\] +core1_dmem_addr\[16\] +core1_dmem_addr\[15\] +core1_dmem_addr\[14\] +core1_dmem_addr\[13\] +core1_dmem_addr\[12\] +core1_dmem_addr\[11\] +core1_dmem_addr\[10\] +core1_dmem_addr\[9\] +core1_dmem_addr\[8\] +core1_dmem_addr\[7\] +core1_dmem_addr\[6\] +core1_dmem_addr\[5\] +core1_dmem_addr\[4\] +core1_dmem_addr\[3\] +core1_dmem_addr\[2\] +core1_dmem_addr\[1\] +core1_dmem_addr\[0\] +core1_dmem_wdata\[31\] +core1_dmem_wdata\[30\] +core1_dmem_wdata\[29\] +core1_dmem_wdata\[28\] +core1_dmem_wdata\[27\] +core1_dmem_wdata\[26\] +core1_dmem_wdata\[25\] +core1_dmem_wdata\[24\] +core1_dmem_wdata\[23\] +core1_dmem_wdata\[22\] +core1_dmem_wdata\[21\] +core1_dmem_wdata\[20\] +core1_dmem_wdata\[19\] +core1_dmem_wdata\[18\] +core1_dmem_wdata\[17\] +core1_dmem_wdata\[16\] +core1_dmem_wdata\[15\] +core1_dmem_wdata\[14\] +core1_dmem_wdata\[13\] +core1_dmem_wdata\[12\] +core1_dmem_wdata\[11\] +core1_dmem_wdata\[10\] +core1_dmem_wdata\[9\] +core1_dmem_wdata\[8\] +core1_dmem_wdata\[7\] +core1_dmem_wdata\[6\] +core1_dmem_wdata\[5\] +core1_dmem_wdata\[4\] +core1_dmem_wdata\[3\] +core1_dmem_wdata\[2\] +core1_dmem_wdata\[1\] +core1_dmem_wdata\[0\] +core1_dmem_rdata\[31\] +core1_dmem_rdata\[30\] +core1_dmem_rdata\[29\] +core1_dmem_rdata\[28\] +core1_dmem_rdata\[27\] +core1_dmem_rdata\[26\] +core1_dmem_rdata\[25\] +core1_dmem_rdata\[24\] +core1_dmem_rdata\[23\] +core1_dmem_rdata\[22\] +core1_dmem_rdata\[21\] +core1_dmem_rdata\[20\] +core1_dmem_rdata\[19\] +core1_dmem_rdata\[18\] +core1_dmem_rdata\[17\] +core1_dmem_rdata\[16\] +core1_dmem_rdata\[15\] +core1_dmem_rdata\[14\] +core1_dmem_rdata\[13\] +core1_dmem_rdata\[12\] +core1_dmem_rdata\[11\] +core1_dmem_rdata\[10\] +core1_dmem_rdata\[9\] +core1_dmem_rdata\[8\] +core1_dmem_rdata\[7\] +core1_dmem_rdata\[6\] +core1_dmem_rdata\[5\] +core1_dmem_rdata\[4\] +core1_dmem_rdata\[3\] +core1_dmem_rdata\[2\] +core1_dmem_rdata\[1\] +core1_dmem_rdata\[0\] +core1_dmem_resp\[1\] +core1_dmem_resp\[0\] + +core1_debug\[48\] 0500 0 2 +core1_debug\[47\] +core1_debug\[46\] +core1_debug\[45\] +core1_debug\[44\] +core1_debug\[43\] +core1_debug\[42\] +core1_debug\[41\] +core1_debug\[40\] +core1_debug\[39\] +core1_debug\[38\] +core1_debug\[37\] +core1_debug\[36\] +core1_debug\[35\] +core1_debug\[34\] +core1_debug\[33\] +core1_debug\[32\] +core1_debug\[31\] +core1_debug\[30\] +core1_debug\[29\] +core1_debug\[28\] +core1_debug\[27\] +core1_debug\[26\] +core1_debug\[25\] +core1_debug\[24\] +core1_debug\[23\] +core1_debug\[22\] +core1_debug\[21\] +core1_debug\[20\] +core1_debug\[19\] +core1_debug\[18\] +core1_debug\[17\] +core1_debug\[16\] +core1_debug\[15\] +core1_debug\[14\] +core1_debug\[13\] +core1_debug\[12\] +core1_debug\[11\] +core1_debug\[10\] +core1_debug\[9\] +core1_debug\[8\] +core1_debug\[7\] +core1_debug\[6\] +core1_debug\[5\] +core1_debug\[4\] +core1_debug\[3\] +core1_debug\[2\] +core1_debug\[1\] +core1_debug\[0\] + +core1_timer_irq 600 0 2 +core1_timer_val\[63\] +core1_timer_val\[62\] +core1_timer_val\[61\] +core1_timer_val\[60\] +core1_timer_val\[59\] +core1_timer_val\[58\] +core1_timer_val\[57\] +core1_timer_val\[56\] +core1_timer_val\[55\] +core1_timer_val\[54\] +core1_timer_val\[53\] +core1_timer_val\[52\] +core1_timer_val\[51\] +core1_timer_val\[50\] +core1_timer_val\[49\] +core1_timer_val\[48\] +core1_timer_val\[47\] +core1_timer_val\[46\] +core1_timer_val\[45\] +core1_timer_val\[44\] +core1_timer_val\[43\] +core1_timer_val\[42\] +core1_timer_val\[41\] +core1_timer_val\[40\] +core1_timer_val\[39\] +core1_timer_val\[38\] +core1_timer_val\[37\] +core1_timer_val\[36\] +core1_timer_val\[35\] +core1_timer_val\[34\] +core1_timer_val\[33\] +core1_timer_val\[32\] +core1_timer_val\[31\] +core1_timer_val\[30\] +core1_timer_val\[29\] +core1_timer_val\[28\] +core1_timer_val\[27\] +core1_timer_val\[26\] +core1_timer_val\[25\] +core1_timer_val\[24\] +core1_timer_val\[23\] +core1_timer_val\[22\] +core1_timer_val\[21\] +core1_timer_val\[20\] +core1_timer_val\[19\] +core1_timer_val\[18\] +core1_timer_val\[17\] +core1_timer_val\[16\] +core1_timer_val\[15\] +core1_timer_val\[14\] +core1_timer_val\[13\] +core1_timer_val\[12\] +core1_timer_val\[11\] +core1_timer_val\[10\] +core1_timer_val\[9\] +core1_timer_val\[8\] +core1_timer_val\[7\] +core1_timer_val\[6\] +core1_timer_val\[5\] +core1_timer_val\[4\] +core1_timer_val\[3\] +core1_timer_val\[2\] +core1_timer_val\[1\] +core1_timer_val\[0\] +core1_irq_lines\[31\] +core1_irq_lines\[30\] +core1_irq_lines\[29\] +core1_irq_lines\[28\] +core1_irq_lines\[27\] +core1_irq_lines\[26\] +core1_irq_lines\[25\] +core1_irq_lines\[24\] +core1_irq_lines\[23\] +core1_irq_lines\[22\] +core1_irq_lines\[21\] +core1_irq_lines\[20\] +core1_irq_lines\[19\] +core1_irq_lines\[18\] +core1_irq_lines\[17\] +core1_irq_lines\[16\] +core1_irq_lines\[15\] +core1_irq_lines\[14\] +core1_irq_lines\[13\] +core1_irq_lines\[12\] +core1_irq_lines\[11\] +core1_irq_lines\[10\] +core1_irq_lines\[9\] +core1_irq_lines\[8\] +core1_irq_lines\[7\] +core1_irq_lines\[6\] +core1_irq_lines\[5\] +core1_irq_lines\[4\] +core1_irq_lines\[3\] +core1_irq_lines\[2\] +core1_irq_lines\[1\] +core1_irq_lines\[0\] +core1_irq_soft + +core3_clk 1250 00 2 +core3_uid\[1\] +core3_uid\[0\] +core3_imem_req_ack +core3_imem_req +core3_imem_cmd +core3_imem_addr\[31\] +core3_imem_addr\[30\] +core3_imem_addr\[29\] +core3_imem_addr\[28\] +core3_imem_addr\[27\] +core3_imem_addr\[26\] +core3_imem_addr\[25\] +core3_imem_addr\[24\] +core3_imem_addr\[23\] +core3_imem_addr\[22\] +core3_imem_addr\[21\] +core3_imem_addr\[20\] +core3_imem_addr\[19\] +core3_imem_addr\[18\] +core3_imem_addr\[17\] +core3_imem_addr\[16\] +core3_imem_addr\[15\] +core3_imem_addr\[14\] +core3_imem_addr\[13\] +core3_imem_addr\[12\] +core3_imem_addr\[11\] +core3_imem_addr\[10\] +core3_imem_addr\[9\] +core3_imem_addr\[8\] +core3_imem_addr\[7\] +core3_imem_addr\[6\] +core3_imem_addr\[5\] +core3_imem_addr\[4\] +core3_imem_addr\[3\] +core3_imem_addr\[2\] +core3_imem_addr\[1\] +core3_imem_addr\[0\] +core3_imem_bl\[2\] +core3_imem_bl\[1\] +core3_imem_bl\[0\] +core3_imem_rdata\[31\] +core3_imem_rdata\[30\] +core3_imem_rdata\[29\] +core3_imem_rdata\[28\] +core3_imem_rdata\[27\] +core3_imem_rdata\[26\] +core3_imem_rdata\[25\] +core3_imem_rdata\[24\] +core3_imem_rdata\[23\] +core3_imem_rdata\[22\] +core3_imem_rdata\[21\] +core3_imem_rdata\[20\] +core3_imem_rdata\[19\] +core3_imem_rdata\[18\] +core3_imem_rdata\[17\] +core3_imem_rdata\[16\] +core3_imem_rdata\[15\] +core3_imem_rdata\[14\] +core3_imem_rdata\[13\] +core3_imem_rdata\[12\] +core3_imem_rdata\[11\] +core3_imem_rdata\[10\] +core3_imem_rdata\[9\] +core3_imem_rdata\[8\] +core3_imem_rdata\[7\] +core3_imem_rdata\[6\] +core3_imem_rdata\[5\] +core3_imem_rdata\[4\] +core3_imem_rdata\[3\] +core3_imem_rdata\[2\] +core3_imem_rdata\[1\] +core3_imem_rdata\[0\] +core3_imem_resp\[1\] +core3_imem_resp\[0\] + +core3_dmem_req_ack 1400 0 2 +core3_dmem_req +core3_dmem_cmd +core3_dmem_width\[1\] +core3_dmem_width\[0\] +core3_dmem_addr\[31\] +core3_dmem_addr\[30\] +core3_dmem_addr\[29\] +core3_dmem_addr\[28\] +core3_dmem_addr\[27\] +core3_dmem_addr\[26\] +core3_dmem_addr\[25\] +core3_dmem_addr\[24\] +core3_dmem_addr\[23\] +core3_dmem_addr\[22\] +core3_dmem_addr\[21\] +core3_dmem_addr\[20\] +core3_dmem_addr\[19\] +core3_dmem_addr\[18\] +core3_dmem_addr\[17\] +core3_dmem_addr\[16\] +core3_dmem_addr\[15\] +core3_dmem_addr\[14\] +core3_dmem_addr\[13\] +core3_dmem_addr\[12\] +core3_dmem_addr\[11\] +core3_dmem_addr\[10\] +core3_dmem_addr\[9\] +core3_dmem_addr\[8\] +core3_dmem_addr\[7\] +core3_dmem_addr\[6\] +core3_dmem_addr\[5\] +core3_dmem_addr\[4\] +core3_dmem_addr\[3\] +core3_dmem_addr\[2\] +core3_dmem_addr\[1\] +core3_dmem_addr\[0\] +core3_dmem_wdata\[31\] +core3_dmem_wdata\[30\] +core3_dmem_wdata\[29\] +core3_dmem_wdata\[28\] +core3_dmem_wdata\[27\] +core3_dmem_wdata\[26\] +core3_dmem_wdata\[25\] +core3_dmem_wdata\[24\] +core3_dmem_wdata\[23\] +core3_dmem_wdata\[22\] +core3_dmem_wdata\[21\] +core3_dmem_wdata\[20\] +core3_dmem_wdata\[19\] +core3_dmem_wdata\[18\] +core3_dmem_wdata\[17\] +core3_dmem_wdata\[16\] +core3_dmem_wdata\[15\] +core3_dmem_wdata\[14\] +core3_dmem_wdata\[13\] +core3_dmem_wdata\[12\] +core3_dmem_wdata\[11\] +core3_dmem_wdata\[10\] +core3_dmem_wdata\[9\] +core3_dmem_wdata\[8\] +core3_dmem_wdata\[7\] +core3_dmem_wdata\[6\] +core3_dmem_wdata\[5\] +core3_dmem_wdata\[4\] +core3_dmem_wdata\[3\] +core3_dmem_wdata\[2\] +core3_dmem_wdata\[1\] +core3_dmem_wdata\[0\] +core3_dmem_rdata\[31\] +core3_dmem_rdata\[30\] +core3_dmem_rdata\[29\] +core3_dmem_rdata\[28\] +core3_dmem_rdata\[27\] +core3_dmem_rdata\[26\] +core3_dmem_rdata\[25\] +core3_dmem_rdata\[24\] +core3_dmem_rdata\[23\] +core3_dmem_rdata\[22\] +core3_dmem_rdata\[21\] +core3_dmem_rdata\[20\] +core3_dmem_rdata\[19\] +core3_dmem_rdata\[18\] +core3_dmem_rdata\[17\] +core3_dmem_rdata\[16\] +core3_dmem_rdata\[15\] +core3_dmem_rdata\[14\] +core3_dmem_rdata\[13\] +core3_dmem_rdata\[12\] +core3_dmem_rdata\[11\] +core3_dmem_rdata\[10\] +core3_dmem_rdata\[9\] +core3_dmem_rdata\[8\] +core3_dmem_rdata\[7\] +core3_dmem_rdata\[6\] +core3_dmem_rdata\[5\] +core3_dmem_rdata\[4\] +core3_dmem_rdata\[3\] +core3_dmem_rdata\[2\] +core3_dmem_rdata\[1\] +core3_dmem_rdata\[0\] +core3_dmem_resp\[1\] +core3_dmem_resp\[0\] + +core3_debug\[48\] 1550 0 2 +core3_debug\[47\] +core3_debug\[46\] +core3_debug\[45\] +core3_debug\[44\] +core3_debug\[43\] +core3_debug\[42\] +core3_debug\[41\] +core3_debug\[40\] +core3_debug\[39\] +core3_debug\[38\] +core3_debug\[37\] +core3_debug\[36\] +core3_debug\[35\] +core3_debug\[34\] +core3_debug\[33\] +core3_debug\[32\] +core3_debug\[31\] +core3_debug\[30\] +core3_debug\[29\] +core3_debug\[28\] +core3_debug\[27\] +core3_debug\[26\] +core3_debug\[25\] +core3_debug\[24\] +core3_debug\[23\] +core3_debug\[22\] +core3_debug\[21\] +core3_debug\[20\] +core3_debug\[19\] +core3_debug\[18\] +core3_debug\[17\] +core3_debug\[16\] +core3_debug\[15\] +core3_debug\[14\] +core3_debug\[13\] +core3_debug\[12\] +core3_debug\[11\] +core3_debug\[10\] +core3_debug\[9\] +core3_debug\[8\] +core3_debug\[7\] +core3_debug\[6\] +core3_debug\[5\] +core3_debug\[4\] +core3_debug\[3\] +core3_debug\[2\] +core3_debug\[1\] +core3_debug\[0\] + +core3_timer_irq 1650 0 2 +core3_timer_val\[63\] +core3_timer_val\[62\] +core3_timer_val\[61\] +core3_timer_val\[60\] +core3_timer_val\[59\] +core3_timer_val\[58\] +core3_timer_val\[57\] +core3_timer_val\[56\] +core3_timer_val\[55\] +core3_timer_val\[54\] +core3_timer_val\[53\] +core3_timer_val\[52\] +core3_timer_val\[51\] +core3_timer_val\[50\] +core3_timer_val\[49\] +core3_timer_val\[48\] +core3_timer_val\[47\] +core3_timer_val\[46\] +core3_timer_val\[45\] +core3_timer_val\[44\] +core3_timer_val\[43\] +core3_timer_val\[42\] +core3_timer_val\[41\] +core3_timer_val\[40\] +core3_timer_val\[39\] +core3_timer_val\[38\] +core3_timer_val\[37\] +core3_timer_val\[36\] +core3_timer_val\[35\] +core3_timer_val\[34\] +core3_timer_val\[33\] +core3_timer_val\[32\] +core3_timer_val\[31\] +core3_timer_val\[30\] +core3_timer_val\[29\] +core3_timer_val\[28\] +core3_timer_val\[27\] +core3_timer_val\[26\] +core3_timer_val\[25\] +core3_timer_val\[24\] +core3_timer_val\[23\] +core3_timer_val\[22\] +core3_timer_val\[21\] +core3_timer_val\[20\] +core3_timer_val\[19\] +core3_timer_val\[18\] +core3_timer_val\[17\] +core3_timer_val\[16\] +core3_timer_val\[15\] +core3_timer_val\[14\] +core3_timer_val\[13\] +core3_timer_val\[12\] +core3_timer_val\[11\] +core3_timer_val\[10\] +core3_timer_val\[9\] +core3_timer_val\[8\] +core3_timer_val\[7\] +core3_timer_val\[6\] +core3_timer_val\[5\] +core3_timer_val\[4\] +core3_timer_val\[3\] +core3_timer_val\[2\] +core3_timer_val\[1\] +core3_timer_val\[0\] + +core3_irq_lines\[31\] +core3_irq_lines\[30\] +core3_irq_lines\[29\] +core3_irq_lines\[28\] +core3_irq_lines\[27\] +core3_irq_lines\[26\] +core3_irq_lines\[25\] +core3_irq_lines\[24\] +core3_irq_lines\[23\] +core3_irq_lines\[22\] +core3_irq_lines\[21\] +core3_irq_lines\[20\] +core3_irq_lines\[19\] +core3_irq_lines\[18\] +core3_irq_lines\[17\] +core3_irq_lines\[16\] +core3_irq_lines\[15\] +core3_irq_lines\[14\] +core3_irq_lines\[13\] +core3_irq_lines\[12\] +core3_irq_lines\[11\] +core3_irq_lines\[10\] +core3_irq_lines\[9\] +core3_irq_lines\[8\] +core3_irq_lines\[7\] +core3_irq_lines\[6\] +core3_irq_lines\[5\] +core3_irq_lines\[4\] +core3_irq_lines\[3\] +core3_irq_lines\[2\] +core3_irq_lines\[1\] +core3_irq_lines\[0\] +core3_irq_soft + #N core_irq_lines_i\[31\] core_irq_lines_i\[30\] @@ -1839,13 +1852,6 @@ core_irq_lines_i\[0\] core_irq_soft_i -cfg_ccska\[3\] -cfg_ccska\[2\] -cfg_ccska\[1\] -cfg_ccska\[0\] -core_clk_int -core_clk_skew -core_clk rtc_clk pwrup_rst_n cpu_intf_rst_n
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index d9b5dd5..b364acb 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -25,6 +25,7 @@ set ::env(CLOCK_PORT) "clk" set ::env(SYNTH_MAX_FANOUT) 4 +set ::env(SYNTH_BUFFERING) {0} ## CTS BUFFER set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" @@ -33,8 +34,8 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv \ - $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_core_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_dm.sv \ @@ -79,10 +80,10 @@ set ::env(DIE_AREA) "0 0 540 950 " set ::env(PL_TARGET_DENSITY) 0.45 -#set ::env(CELL_PAD) "8" +set ::env(CELL_PAD) "8" ## Routing -set ::env(GRT_ADJUSTMENT) 0.2 +#set ::env(GRT_ADJUSTMENT) 0.2 set ::env(PL_TIME_DRIVEN) "1" @@ -100,8 +101,8 @@ set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25} set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25} -set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500} -set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500} +set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {1000} +set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {1000} set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg index f3daaa8..54bb33f 100644 --- a/openlane/ycr_core_top/pin_order.cfg +++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,22 +1,21 @@ #BUS_SORT #MANUAL_PLACE #E -pwrup_rst_n +pwrup_rst_n 0000 00 2 rst_n - -cfg_ccska\[3\] -cfg_ccska\[2\] -cfg_ccska\[1\] -cfg_ccska\[0\] -core_clk_int -core_clk_skew - -clk -clk_o core_rst_n_o core_rdc_qlfy_o -core_uid\[1\] 0200 00 2 +cfg_ccska\[3\] 0180 00 2 +cfg_ccska\[2\] +cfg_ccska\[1\] +cfg_ccska\[0\] +core_clk_skew +clk +clk_o + +core_clk_int 0200 00 2 +core_uid\[1\] core_uid\[0\] imem2core_req_ack_i core2imem_req_o
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc index f8eb2c5..163eb2b 100644 --- a/openlane/ycr_intf/base.sdc +++ b/openlane/ycr_intf/base.sdc
@@ -24,15 +24,24 @@ -group [get_clocks {rtc_clk}]\ -group [get_clocks {wb_clk}] -comment {Async Clock group} +# Set case analysis +set_case_analysis 0 [get_ports {cfg_ccska[3]}] +set_case_analysis 0 [get_ports {cfg_ccska[2]}] +set_case_analysis 0 [get_ports {cfg_ccska[1]}] +set_case_analysis 0 [get_ports {cfg_ccska[0]}] + +set_case_analysis 0 [get_ports {cfg_wcska[3]}] +set_case_analysis 0 [get_ports {cfg_wcska[2]}] +set_case_analysis 0 [get_ports {cfg_wcska[1]}] +set_case_analysis 0 [get_ports {cfg_wcska[0]}] + #Assumed config are static set_false_path -from [get_ports {cfg_dcache_force_flush}] set_false_path -from [get_ports {cfg_dcache_pfet_dis}] set_false_path -from [get_ports {cfg_icache_ntag_pfet_dis}] set_false_path -from [get_ports {cfg_icache_pfet_dis}] -set_false_path -from [get_ports {cfg_cska_riscv[3]}] -set_false_path -from [get_ports {cfg_cska_riscv[2]}] -set_false_path -from [get_ports {cfg_cska_riscv[1]}] -set_false_path -from [get_ports {cfg_cska_riscv[0]}] + + set_false_path -from [get_ports {cfg_sram_lphase[1]}] set_false_path -from [get_ports {cfg_sram_lphase[0]}] @@ -51,19 +60,19 @@ set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_resp[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}] #Wishbone ICACHE I/F set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}] @@ -102,17 +111,17 @@ set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_rdata[*]}] set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_resp[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}] +set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}] # Data memory interface from router to WB bridge @@ -160,21 +169,21 @@ ## ICACHE PORT-0 SRAM Memory I/F -set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] -set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] -set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] +set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] +set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] -set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] -set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] -set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] -set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] -set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] +set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] +set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] +set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] +set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] +set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] ## ICACHE PORT-1 SRAM Memory I/F -set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] -set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] +set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] @@ -199,39 +208,39 @@ set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}] set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}] -set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}] -set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}] -set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}] -set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}] +set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}] +set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}] +set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}] +set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}] ## DCACHE PORT-0 SRAM I/F -set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] -set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] -set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] +set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] +set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] +set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] +set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] +set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] -set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] -set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] -set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] -set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] -set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] +set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] +set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] +set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] +set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] +set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] set_input_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] ## DCACHE PORT-1 SRAM I/F -set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] -set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] +set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] +set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] -set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] -set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] +set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] +set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] set_input_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}] set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}]
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index 72878b2..61647d9 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -34,8 +34,8 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv \ - $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_tag_fifo.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_tag_fifo.sv \
diff --git a/signoff/clk_buf/OPENLANE_VERSION b/signoff/clk_buf/OPENLANE_VERSION deleted file mode 100644 index a2633b1..0000000 --- a/signoff/clk_buf/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane rc7
diff --git a/signoff/clk_buf/PDK_SOURCES b/signoff/clk_buf/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/clk_buf/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/clk_buf/final_summary_report.csv b/signoff/clk_buf/final_summary_report.csv deleted file mode 100644 index f6ee716..0000000 --- a/signoff/clk_buf/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/clk_buf,clk_buf,clk_buf,Flow_completed,0h1m2s,0h0m26s,925.925925925926,0.0018,555.5555555555555,3,382.24,1,0,0,0,0,0,0,0,0,0,0,0,45,4,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,49267,0.0,0.58,0.26,0.0,-1,-1,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,14,13,0,27,90.9090909090909,11,10,AREA 0,5,60,1,30,30,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/clk_skew_adjust/OPENLANE_VERSION b/signoff/clk_skew_adjust/OPENLANE_VERSION deleted file mode 100644 index ad796aa..0000000 --- a/signoff/clk_skew_adjust/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane v0.21-6-gbc3b032
diff --git a/signoff/clk_skew_adjust/PDK_SOURCES b/signoff/clk_skew_adjust/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/clk_skew_adjust/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/clk_skew_adjust/final_summary_report.csv b/signoff/clk_skew_adjust/final_summary_report.csv deleted file mode 100644 index 6c84744..0000000 --- a/signoff/clk_skew_adjust/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m15s,0h0m36s,7500.0,0.01,3000.0,5,391.95,30,0,0,0,0,0,0,0,0,0,0,0,2812,197,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,6.42,6.62,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,64,102,0,166,90.9090909090909,11,10,AREA 0,5,40,1,20,20,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/digital_pll/OPENLANE_VERSION b/signoff/digital_pll/OPENLANE_VERSION deleted file mode 100644 index b5bf449..0000000 --- a/signoff/digital_pll/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
diff --git a/signoff/digital_pll/PDK_SOURCES b/signoff/digital_pll/PDK_SOURCES deleted file mode 100644 index f9d0f46..0000000 --- a/signoff/digital_pll/PDK_SOURCES +++ /dev/null
@@ -1 +0,0 @@ -open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
diff --git a/signoff/glbl_cfg/OPENLANE_VERSION b/signoff/glbl_cfg/OPENLANE_VERSION deleted file mode 100644 index ad796aa..0000000 --- a/signoff/glbl_cfg/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane v0.21-6-gbc3b032
diff --git a/signoff/glbl_cfg/PDK_SOURCES b/signoff/glbl_cfg/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/glbl_cfg/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv deleted file mode 100644 index 68bccb3..0000000 --- a/signoff/glbl_cfg/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h15m36s,0h9m28s,45883.33333333334,0.12,22941.66666666667,40,569.11,2753,0,0,0,0,0,0,0,0,0,-1,0,131923,23407,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,25.3,27.26,0.31,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/mbist/OPENLANE_VERSION b/signoff/mbist/OPENLANE_VERSION deleted file mode 100644 index 80c7664..0000000 --- a/signoff/mbist/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane N/A
diff --git a/signoff/mbist/PDK_SOURCES b/signoff/mbist/PDK_SOURCES deleted file mode 100644 index ca3684a..0000000 --- a/signoff/mbist/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b --ne skywater-pdk -c094b6e83a4f9298e47f696ec5a7fd53535ec5eb --ne open_pdks -14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist/final_summary_report.csv b/signoff/mbist/final_summary_report.csv deleted file mode 100644 index 78824ce..0000000 --- a/signoff/mbist/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/mbist,mbist_top,mbist,flow_completed,0h11m2s,-1,20833.333333333336,0.3,10416.666666666668,13.1,663.13,3125,0,0,0,0,0,0,0,10,0,0,-1,458568,43437,-0.67,-6.26,-1,-1.39,-1,-0.67,-3033.14,-1,-1.39,-1,372704250.0,1.47,48.85,12.24,20.92,0.0,-1,2382,6613,753,4936,0,0,0,2339,0,0,0,0,0,0,0,4,849,672,17,130,3852,0,3982,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/mbist_wrapper/OPENLANE_VERSION b/signoff/mbist_wrapper/OPENLANE_VERSION deleted file mode 100644 index 80c7664..0000000 --- a/signoff/mbist_wrapper/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane N/A
diff --git a/signoff/mbist_wrapper/PDK_SOURCES b/signoff/mbist_wrapper/PDK_SOURCES deleted file mode 100644 index ca3684a..0000000 --- a/signoff/mbist_wrapper/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b --ne skywater-pdk -c094b6e83a4f9298e47f696ec5a7fd53535ec5eb --ne open_pdks -14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist_wrapper/final_summary_report.csv b/signoff/mbist_wrapper/final_summary_report.csv deleted file mode 100644 index b6c97f9..0000000 --- a/signoff/mbist_wrapper/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/mbist_wrapper,mbist_wrapper,mbist_wrapper,flow_completed,0h14m13s,-1,26073.260073260073,0.273,13036.630036630037,16.48,695.21,3559,0,0,0,0,0,0,-1,16,0,0,-1,445806,47865,-0.67,-5.91,-1,-1.78,-1,-0.67,-2737.45,-1,-1.78,-1,357342288.0,5.91,47.85,15.03,24.02,0.01,-1,2596,7282,753,5382,0,0,0,2664,0,0,0,0,0,0,0,4,1049,798,17,138,3514,0,3652,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/pinmux_top/OPENLANE_VERSION +++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/pinmux_top/PDK_SOURCES +++ b/signoff/pinmux_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/qspim_top/OPENLANE_VERSION +++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/qspim_top/PDK_SOURCES +++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/sdram/OPENLANE_VERSION b/signoff/sdram/OPENLANE_VERSION deleted file mode 100644 index bab6e84..0000000 --- a/signoff/sdram/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane v0.21-9-g94fe743
diff --git a/signoff/sdram/PDK_SOURCES b/signoff/sdram/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/sdram/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv deleted file mode 100644 index 24acce0..0000000 --- a/signoff/sdram/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h17m16s,0h6m17s,40708.57142857143,0.35,20354.285714285714,30,662.62,7124,0,0,0,0,0,0,0,0,0,-1,0,316920,56671,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,242866426,0.0,25.86,16.86,2.54,-1,-1,7028,7287,1219,1478,0,0,0,7124,196,107,83,98,352,210,34,2240,1267,1186,23,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/spi_master/OPENLANE_VERSION b/signoff/spi_master/OPENLANE_VERSION deleted file mode 100644 index bab6e84..0000000 --- a/signoff/spi_master/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane v0.21-9-g94fe743
diff --git a/signoff/spi_master/PDK_SOURCES b/signoff/spi_master/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/spi_master/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv deleted file mode 100644 index 8e28748..0000000 --- a/signoff/spi_master/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h20m39s,0h10m39s,58438.46153846153,0.26,29219.230769230766,47,664.71,7597,0,0,0,0,0,0,0,0,3,-1,0,384228,67124,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,294776771,0.0,31.33,39.79,0.04,-1,-1,7537,7673,1268,1404,0,0,0,7597,245,0,169,100,1051,210,32,2443,1353,1292,24,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/syntacore/OPENLANE_VERSION b/signoff/syntacore/OPENLANE_VERSION deleted file mode 100644 index 80c7664..0000000 --- a/signoff/syntacore/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane N/A
diff --git a/signoff/syntacore/PDK_SOURCES b/signoff/syntacore/PDK_SOURCES deleted file mode 100644 index ca3684a..0000000 --- a/signoff/syntacore/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b --ne skywater-pdk -c094b6e83a4f9298e47f696ec5a7fd53535ec5eb --ne open_pdks -14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv deleted file mode 100644 index 04c97bd..0000000 --- a/signoff/syntacore/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h41m48s,-1,53830.971659919036,0.7904,26915.485829959518,30.93,1195.5,21274,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1674760,240681,-2.04,-17.8,-1,0.0,-1,-2459.49,-21655.63,-1,0.0,-1,1322263875.0,0.0,62.03,24.69,26.16,0.01,-1,18597,30067,1067,12430,0,0,0,21980,0,0,0,0,0,0,0,4,5240,5924,49,366,10822,0,11188,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.32,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart/OPENLANE_VERSION b/signoff/uart/OPENLANE_VERSION deleted file mode 100644 index a2633b1..0000000 --- a/signoff/uart/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane rc7
diff --git a/signoff/uart/PDK_SOURCES b/signoff/uart/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/uart/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv deleted file mode 100644 index 5d02b7b..0000000 --- a/signoff/uart/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart,uart_core,uart,Flow_completed,0h6m24s,0h4m13s,46166.66666666667,0.12,23083.333333333336,35,545.14,2770,0,0,0,0,0,0,0,0,0,-1,0,93784,20982,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.71,19.11,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm/OPENLANE_VERSION b/signoff/uart_i2cm/OPENLANE_VERSION deleted file mode 100644 index a2633b1..0000000 --- a/signoff/uart_i2cm/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane rc7
diff --git a/signoff/uart_i2cm/PDK_SOURCES b/signoff/uart_i2cm/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/uart_i2cm/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart_i2cm/final_summary_report.csv b/signoff/uart_i2cm/final_summary_report.csv deleted file mode 100644 index 6a4c74e..0000000 --- a/signoff/uart_i2cm/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart_i2cm,uart_i2c_top,uart_i2cm,Flow_completed,0h5m42s,0h3m37s,59350.0,0.12,29675.0,47,561.56,3561,0,0,0,0,0,0,0,0,0,-1,0,124117,27523,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,81974377,0.0,25.57,25.46,0.33,-1,-1,3562,3582,623,643,0,0,0,3561,98,10,58,70,423,155,27,836,589,556,17,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb/OPENLANE_VERSION b/signoff/uart_i2cm_usb/OPENLANE_VERSION deleted file mode 100644 index bab6e84..0000000 --- a/signoff/uart_i2cm_usb/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane v0.21-9-g94fe743
diff --git a/signoff/uart_i2cm_usb/PDK_SOURCES b/signoff/uart_i2cm_usb/PDK_SOURCES deleted file mode 100644 index 8b58bd5..0000000 --- a/signoff/uart_i2cm_usb/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -a68c95289612a361870acedb7f6478fcfae32e49 --ne skywater-pdk -f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7 --ne open_pdks -522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart_i2cm_usb/final_summary_report.csv b/signoff/uart_i2cm_usb/final_summary_report.csv deleted file mode 100644 index 2c0683d..0000000 --- a/signoff/uart_i2cm_usb/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h25m24s,0h9m59s,59157.14285714286,0.42,29578.57142857143,45,758.68,12423,0,0,0,0,0,0,0,0,0,-1,0,522443,99881,-3.16,-3.16,-3.07,-3.07,-3.11,-91.08,-91.08,-91.67,-91.67,-91.56,390283627,0.0,31.24,29.46,0.31,-1,-1,12407,12476,2262,2331,0,0,0,12423,364,10,202,244,2118,325,79,2692,2224,2170,26,498,5146,0,5644,76.27765064836004,13.11,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION deleted file mode 100644 index 80c7664..0000000 --- a/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane N/A
diff --git a/signoff/uart_i2cm_usb_spi/PDK_SOURCES b/signoff/uart_i2cm_usb_spi/PDK_SOURCES deleted file mode 100644 index 22e7dc1..0000000 --- a/signoff/uart_i2cm_usb_spi/PDK_SOURCES +++ /dev/null
@@ -1,3 +0,0 @@ -openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f -skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv deleted file mode 100644 index ab09edd..0000000 --- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow completed,0h21m12s0ms,0h16m10s0ms,69377.14285714286,0.35,34688.57142857143,39.46,1340.21,12141,0,0,0,0,0,0,0,-1,0,-1,-1,562021,101968,-3.48,-3.71,-1,-3.61,-3.64,-107.08,-112.91,-1,-117.02,-116.69,361088707.0,0.0,49.42,49.35,17.1,19.4,-1,8563,12956,1538,5867,0,0,0,9739,384,231,256,254,2189,356,86,774,2441,2349,19,498,4643,0,5141,73.31378299120234,13.64,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION +++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES +++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION index b5bf449..1234be5 100644 --- a/signoff/user_project_wrapper/OPENLANE_VERSION +++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@ -openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES index f9d0f46..f8d3b3a 100644 --- a/signoff/user_project_wrapper/PDK_SOURCES +++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/wb_host/OPENLANE_VERSION +++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/wb_host/PDK_SOURCES +++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/wb_interconnect/OPENLANE_VERSION +++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/wb_interconnect/PDK_SOURCES +++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/ycr2_mintf/OPENLANE_VERSION b/signoff/ycr2_mintf/OPENLANE_VERSION deleted file mode 100644 index 80c7664..0000000 --- a/signoff/ycr2_mintf/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane N/A
diff --git a/signoff/ycr2_mintf/PDK_SOURCES b/signoff/ycr2_mintf/PDK_SOURCES deleted file mode 100644 index ca3684a..0000000 --- a/signoff/ycr2_mintf/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b --ne skywater-pdk -c094b6e83a4f9298e47f696ec5a7fd53535ec5eb --ne open_pdks -14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/ycr2_mintf/final_summary_report.csv b/signoff/ycr2_mintf/final_summary_report.csv deleted file mode 100644 index 3115988..0000000 --- a/signoff/ycr2_mintf/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/ycr2_mintf,ycr2_mintf,ycr2_mintf,flow_completed,0h48m5s,-1,57793.4595524957,0.581,28896.72977624785,33.36,1340.78,16789,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1408277,195540,-10.62,-28.88,-1,0.0,-1,-17949.18,-47210.0,-1,0.0,-1,1013309764.0,10.14,57.98,47.13,16.49,2.06,-1,12552,26416,1453,14955,0,0,0,15245,0,0,0,0,0,0,0,4,4400,4298,34,498,7906,0,8404,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.36,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/ycr4_iconnect/OPENLANE_VERSION b/signoff/ycr4_iconnect/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/ycr4_iconnect/OPENLANE_VERSION +++ b/signoff/ycr4_iconnect/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/ycr4_iconnect/PDK_SOURCES b/signoff/ycr4_iconnect/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/ycr4_iconnect/PDK_SOURCES +++ b/signoff/ycr4_iconnect/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/ycr_core/OPENLANE_VERSION b/signoff/ycr_core/OPENLANE_VERSION deleted file mode 100644 index 80c7664..0000000 --- a/signoff/ycr_core/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane N/A
diff --git a/signoff/ycr_core/PDK_SOURCES b/signoff/ycr_core/PDK_SOURCES deleted file mode 100644 index 22e7dc1..0000000 --- a/signoff/ycr_core/PDK_SOURCES +++ /dev/null
@@ -1,3 +0,0 @@ -openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f -skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/ycr_core/final_summary_report.csv b/signoff/ycr_core/final_summary_report.csv deleted file mode 100644 index 2521873..0000000 --- a/signoff/ycr_core/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/ycr_core,ycr_core_top,ycr_core,flow completed,0h26m15s0ms,0h13m46s0ms,71291.22807017545,0.57,35645.614035087725,35.55,2265.47,20318,0,0,0,0,0,0,0,50,0,0,-1,1367930,192575,0.0,-6.73,-1,0.0,0.0,0.0,-6500.44,-1,0.0,0.0,1018911064.0,0.0,60.43,70.65,30.63,55.95,-1,16388,22628,537,6677,0,0,0,19143,686,261,526,603,2869,894,266,4810,2496,2403,42,682,7717,0,8399,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.36,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/ycr_core_top/OPENLANE_VERSION +++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/ycr_core_top/PDK_SOURCES +++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION index fabca1a..1234be5 100644 --- a/signoff/ycr_intf/OPENLANE_VERSION +++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 +OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES index ef91c87..f8d3b3a 100644 --- a/signoff/ycr_intf/PDK_SOURCES +++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c +open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/yifive/OPENLANE_VERSION b/signoff/yifive/OPENLANE_VERSION deleted file mode 100644 index 80c7664..0000000 --- a/signoff/yifive/OPENLANE_VERSION +++ /dev/null
@@ -1 +0,0 @@ -openlane N/A
diff --git a/signoff/yifive/PDK_SOURCES b/signoff/yifive/PDK_SOURCES deleted file mode 100644 index ca3684a..0000000 --- a/signoff/yifive/PDK_SOURCES +++ /dev/null
@@ -1,6 +0,0 @@ --ne openlane -8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b --ne skywater-pdk -c094b6e83a4f9298e47f696ec5a7fd53535ec5eb --ne open_pdks -14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv deleted file mode 100644 index 1468984..0000000 --- a/signoff/yifive/final_summary_report.csv +++ /dev/null
@@ -1,2 +0,0 @@ -,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h15m29s,-1,60431.59065628477,1.12375,30215.795328142383,34.22,1576.42,33955,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,2627806,392238,-14.85,-43.3,-1,-1.42,-1,-32507.17,-16836.69,-1,-10.35,-1,1924632372.0,11.2,42.7,59.54,6.88,11.31,0.0,28631,47773,1744,20479,0,0,0,34029,0,0,0,0,0,0,0,4,8317,8690,56,1122,15482,0,16604,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv index 6bda236..75cd3e9 100644 --- a/verilog/dv/common/agents/user_tasks.sv +++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,7 @@ begin // Run in Fast Sim Mode `ifdef GL - force u_top.u_wb_host._10673_.Q= 1'b1; + force u_top.u_wb_host._10252_.Q= 1'b1; `else force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1; `endif
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v index ef56ee4..75ec36d 100644 --- a/verilog/dv/risc_boot/risc_boot_tb.v +++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -135,6 +135,9 @@ $dumpvars(1,risc_boot_tb.u_top.mprj); $dumpvars(0,risc_boot_tb.u_top.mprj.u_wb_host); $dumpvars(0,risc_boot_tb.u_top.mprj.u_pinmux); + //$dumpvars(0,risc_boot_tb.u_top.mprj.u_qspi_master); + $dumpvars(1,risc_boot_tb.u_top.mprj.u_riscv_top); + $dumpvars(0,risc_boot_tb.u_top.mprj.u_riscv_top.i_core_top_0); //$dumpvars(0,risc_boot_tb.tb_uart); //$dumpvars(0,risc_boot_tb.u_user_spiflash); $display("Waveform Dump started"); @@ -143,6 +146,14 @@ initial begin + $display("################# NOTE:#####################################"); + $display("This test assumes Caravel GPIO are pre-programmed with user_define.v value"); + $display("If you see RTL simulation fails, cross check mgmt_core_wrapper/verilog/includes/includes.rtl.caravel "); + $display(" From: -v $(CARAVEL_PATH)/rtl/user_defines.v "); + $display(" To: -v $(USER_PROJECT_VERILOG)/rtl/user_defines.v "); + $display(" Gate Sim expect to fail as caravel gate netlist have not generated based on user_define.v in user project"); + $display("#####################################################################################"); + // Repeat cycles of 1000 clock edges as needed to complete testbench repeat (80) begin repeat (2000) @(posedge clock);
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz index c1bd055..aa9d785 100644 --- a/verilog/gl/user_project_wrapper.v.gz +++ b/verilog/gl/user_project_wrapper.v.gz Binary files differ
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index a5097ab..9693486 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -4,9 +4,9 @@ +incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes -+incdir+$(USER_PROJECT_VERILOG)/dv/bfm -+incdir+$(USER_PROJECT_VERILOG)/dv/model -+incdir+$(USER_PROJECT_VERILOG)/dv/agents ++incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm ++incdir+$(USER_PROJECT_VERILOG)/dv/common/model ++incdir+$(USER_PROJECT_VERILOG)/dv/common/agents $(USER_PROJECT_VERILOG)/rtl/user_reg_map.v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v $(USER_PROJECT_VERILOG)/gl/ycr_intf.v
diff --git a/verilog/includes/includes.gl.lib b/verilog/includes/includes.gl.lib index d82a5c2..a047636 100644 --- a/verilog/includes/includes.gl.lib +++ b/verilog/includes/includes.gl.lib
@@ -1,11 +1,13 @@ ########################################################### # STD CELLS - they need to be below the defines.v files ########################################################### --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v -$(USER_PROJECT_VERILOG)/gl/digital_pll.v +#$(USER_PROJECT_VERILOG)/gl/digital_pll.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv index 26e5cbb..a9c6693 100644 --- a/verilog/rtl/lib/ctech_cells.sv +++ b/verilog/rtl/lib/ctech_cells.sv
@@ -111,10 +111,12 @@ input logic A, output logic X); +wire X1; `ifndef SYNTHESIS assign X = A; `else - sky130_fd_sc_hd__clkdlybuf4s15_2 u_dly (.X(X),.A(A)); + sky130_fd_sc_hd__clkbuf_1 u_dly0 (.X(X1),.A(A)); + sky130_fd_sc_hd__clkbuf_1 u_dly1 (.X(X),.A(X1)); `endif endmodule
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh index d4ae6a0..4b6012a 100644 --- a/verilog/rtl/user_params.svh +++ b/verilog/rtl/user_params.svh
@@ -4,12 +4,12 @@ // ASCI Representation of RISC = 32'h8273_8343 parameter CHIP_SIGNATURE = 32'h8273_8343; // Software Reg-1, Release date: <DAY><MONTH><YEAR> -parameter CHIP_RELEASE_DATE = 32'h2011_2022; +parameter CHIP_RELEASE_DATE = 32'h2711_2022; // Software Reg-2: Poject Revison 5.1 = 0005200 -parameter CHIP_REVISION = 32'h0005_8000; +parameter CHIP_REVISION = 32'h0006_0000; -parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_1100_1010_1010_1001_0011; -parameter CLK_SKEW2_RESET_VAL = 32'b0000_0000_0000_0000_0000_0000_0000_0111; +parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_1101_1010_1010_1000_0011; +parameter CLK_SKEW2_RESET_VAL = 32'b0000_0000_0100_0100_0100_0100_0011_1101; parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 3fcb96f..bc47afd 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -282,6 +282,11 @@ //// B. clock skew control added for core clock //// //// 5.8 Nov 20, 2022, Dinesh A //// //// A. Pinmux - Double Sync added for usb & i2c inter //// +//// 5.9 Nov 25, 2022, Dinesh A //// +//// cpu_clk will be feed through wb_interconnect for //// +//// buffering purpose //// +//// 6.0 Nov 27, 2022, Dinesh A //// +//// MPW-7 Timing clean setup ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -741,6 +746,36 @@ wire usb_intr_o ; wire i2cm_intr_o ; +//------------------------------------------------------------ +// AES Integration local decleration +//------------------------------------------------------------ +wire cpu_clk_aes ; +wire [3:0] cfg_ccska_aes ; +wire [3:0] cfg_ccska_aes_rp ; +wire aes_dmem_req ; +wire aes_dmem_cmd ; +wire [1:0] aes_dmem_width ; +wire [6:0] aes_dmem_addr ; +wire [31:0] aes_dmem_wdata ; +wire aes_dmem_req_ack ; +wire [31:0] aes_dmem_rdata ; +wire [1:0] aes_dmem_resp ; + +//------------------------------------------------------------ +// FPU Integration local decleration +//------------------------------------------------------------ +wire cpu_clk_fpu ; +wire [3:0] cfg_ccska_fpu ; +wire [3:0] cfg_ccska_fpu_rp ; +wire fpu_dmem_req ; +wire fpu_dmem_cmd ; +wire [1:0] fpu_dmem_width ; +wire [4:0] fpu_dmem_addr ; +wire [31:0] fpu_dmem_wdata ; +wire fpu_dmem_req_ack ; +wire [31:0] fpu_dmem_rdata ; +wire [1:0] fpu_dmem_resp ; + //---------------------------------------------------------------- // UART Master I/F // ------------------------------------------------------------- @@ -825,17 +860,33 @@ wire [3:0] cfg_ccska_riscv_core2_rp ; wire [3:0] cfg_ccska_riscv_core3_rp ; -wire [3:0] cfg_ccska_riscv_intf = cfg_clk_skew_ctrl2[3:0]; -wire [3:0] cfg_ccska_riscv_icon = cfg_clk_skew_ctrl2[7:4]; -wire [3:0] cfg_ccska_riscv_core0 = cfg_clk_skew_ctrl2[11:8]; -wire [3:0] cfg_ccska_riscv_core1 = cfg_clk_skew_ctrl2[15:12]; -wire [3:0] cfg_ccska_riscv_core2 = cfg_clk_skew_ctrl2[19:16]; -wire [3:0] cfg_ccska_riscv_core3 = cfg_clk_skew_ctrl2[23:20]; +wire [3:0] cfg_ccska_riscv_intf = cfg_clk_skew_ctrl2[3:0]; +wire [3:0] cfg_ccska_riscv_icon = cfg_clk_skew_ctrl2[7:4]; +wire [3:0] cfg_ccska_riscv_core0 = cfg_clk_skew_ctrl2[11:8]; +wire [3:0] cfg_ccska_riscv_core1 = cfg_clk_skew_ctrl2[15:12]; +wire [3:0] cfg_ccska_riscv_core2 = cfg_clk_skew_ctrl2[19:16]; +wire [3:0] cfg_ccska_riscv_core3 = cfg_clk_skew_ctrl2[23:20]; +assign cfg_ccska_aes = cfg_clk_skew_ctrl2[27:24]; +assign cfg_ccska_fpu = cfg_clk_skew_ctrl2[31:28]; assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug}; wire int_pll_clock = pll_clk_out[0]; +//------------------------------------- +// cpu clock repeater mapping +//------------------------------------- +wire [2:0] cpu_clk_rp; + +wire [1:0] cpu_clk_rp_risc = cpu_clk_rp[1:0]; +wire cpu_clk_rp_pinmux = cpu_clk_rp[2]; + + + + +/*********************************************** + Wishbone HOST +*************************************************/ wb_host u_wb_host( `ifdef USE_POWER_PINS @@ -910,6 +961,9 @@ ); +/**************************************************************** + Digital PLL +*****************************************************************/ // This rtl/gds picked from efabless caravel project dg_pll u_pll( @@ -953,7 +1007,7 @@ .cfg_bypass_dcache (cfg_bypass_dcache ), // Clock - .core_clk_int (cpu_clk ), + .core_clk_int (cpu_clk_rp_risc ), .cfg_ccska_riscv_intf (cfg_ccska_riscv_intf_rp ), .cfg_ccska_riscv_icon (cfg_ccska_riscv_icon_rp ), .cfg_ccska_riscv_core0 (cfg_ccska_riscv_core0_rp ), @@ -1220,8 +1274,8 @@ wb_interconnect #( `ifndef SYNTHESIS - .CH_CLK_WD (4 ), - .CH_DATA_WD (146 ) + .CH_CLK_WD (7 ), + .CH_DATA_WD (154 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS @@ -1229,16 +1283,22 @@ .vssd1 (vssd1 ),// User area 1 digital ground `endif .ch_clk_in ({ + cpu_clk, + cpu_clk, + cpu_clk, wbd_clk_int, wbd_clk_int, wbd_clk_int, wbd_clk_int} ), .ch_clk_out ({ + cpu_clk_rp, wbd_clk_pinmux_rp, wbd_clk_uart_rp, wbd_clk_qspi_rp, wbd_clk_risc_rp} ), .ch_data_in ({ + cfg_ccska_fpu[3:0], + cfg_ccska_aes[3:0], strap_sticky[31:0], strap_uartm[1:0], system_strap[31:0], @@ -1263,6 +1323,8 @@ cfg_wcska_riscv[3:0] } ), .ch_data_out ({ + cfg_ccska_fpu_rp[3:0], + cfg_ccska_aes_rp[3:0], strap_sticky_rp[31:0], strap_uartm_rp[1:0], system_strap_rp[31:0], @@ -1471,7 +1533,7 @@ .user_clock2 (user_clock2 ), .int_pll_clock (int_pll_clock ), .xtal_clk (xtal_clk ), - .cpu_clk (cpu_clk ), + .cpu_clk (cpu_clk_rp_pinmux ), .rtc_clk (rtc_clk ), @@ -1574,6 +1636,8 @@ ); + + dac_top u_4x8bit_dac( `ifdef USE_POWER_PINS .vccd1 (vdda1 ), @@ -1589,4 +1653,7 @@ .Vout2(analog_io[17] ), .Vout3(analog_io[18] ) ); + + + endmodule : user_project_wrapper
diff --git a/verilog/rtl/yifive/ycr4c b/verilog/rtl/yifive/ycr4c index 8f82bfb..98c7e4c 160000 --- a/verilog/rtl/yifive/ycr4c +++ b/verilog/rtl/yifive/ycr4c
@@ -1 +1 @@ -Subproject commit 8f82bfb0df287990c9eb5e951c5afde4b3249589 +Subproject commit 98c7e4cee08f0572d66007aed782c893c6d92147