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foss-eda-tools/third_party/shuttle/sky130/mpw-007/slot-006/d1cb6916e50664803a9b52521807b5799dbe471d^!/.
commit
d1cb6916e50664803a9b52521807b5799dbe471d
[log]
author
dineshannayya <dinesh.annayya@gmail.com>
Sun Mar 20 13:46:04 2022 +0530
committer
dineshannayya <dinesh.annayya@gmail.com>
Sun Mar 20 13:46:04 2022 +0530
tree
129e4cc6ed96d25f848c81e3cfb985e72eaef47e
parent
11a641834d557d83635d78e223d5216ee803c8e3 [diff]
read me and verify update

diff --git a/README.md b/README.md
index acfd916..74a7875 100644
--- a/README.md
+++ b/README.md

@@ -47,7 +47,7 @@
 # Key features
 ```
     * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
-    * Dual Core  32 Bit RISC-V core
+    * Dual 32 Bit RISC-V core
     * 2KB SRAM for instruction cache 
     * 2KB SRAM for data cache
     * 2KB SRAM for Tightly coupled memory - For Data Memory
@@ -59,6 +59,7 @@
     * Simple SPI Master
     * 6 Channel ADC (in Progress)
     * 6 PWM
+    * 3 Timer (16 Bit), 1us/1ms/1second resolution
     * Pin Compatbible to arudino uno
     * Wishbone compatible design
     * Written in System Verilog
@@ -110,14 +111,14 @@
   <tr align="center"> <td> Pin-28          </td> <td> PC5/ADC5/SCL           </td> <td>  A5             </td> <td> digital_io[23]/analog_io[16]         </td></tr>
   <tr align="center"> <td colspan="4">   Additional Pad used for Externam ROM/RAM/USB </td></tr>
   <tr align="center"> <td> Sflash          </td> <td> sflash_sck             </td> <td>                 </td> <td> digital_io[24]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss              </td> <td>                 </td> <td> digital_io[25]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[26]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[27]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[28]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io3             </td> <td>                 </td> <td> digital_io[29]                       </td></tr>
-  <tr align="center"> <td> SSRAM           </td> <td> Reserved               </td> <td>                 </td> <td> digital_io[30]                       </td></tr>
-  <tr align="center"> <td> SSRAM           </td> <td> Reserved               </td> <td>                 </td> <td> digital_io[31]                       </td></tr>
-  <tr align="center"> <td> SSRAM           </td> <td> Reserved               </td> <td>                 </td> <td> digital_io[32]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss0             </td> <td>                 </td> <td> digital_io[25]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss1             </td> <td>                 </td> <td> digital_io[26]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss2             </td> <td>                 </td> <td> digital_io[27]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss3             </td> <td>                 </td> <td> digital_io[28]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[29]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[30]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[31]                       </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io3             </td> <td>                 </td> <td> digital_io[32]                       </td></tr>
   <tr align="center"> <td> SSRAM           </td> <td> Reserved               </td> <td>                 </td> <td> digital_io[33]                       </td></tr>
   <tr align="center"> <td> SSRAM           </td> <td> uartm rxd              </td> <td>                 </td> <td> digital_io[34]                       </td></tr>
   <tr align="center"> <td> SSRAM           </td> <td> uartm txd              </td> <td>                 </td> <td> digital_io[35]                       </td></tr>
@@ -134,8 +135,8 @@
 Following Design changes are done on the basic version of syntacore RISC core
 ```
    * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
-   * local Instruction Memory is increased from 4 to 8 location
-   * Instruction Request are changed from Single word to 4 Word Burst
+   * local Instruction Memory depth increased from 4 to 8 location
+   * Instruction Mem Request are changed from Single word to 4 Word Burst
    * Multiplication and Divsion are changed to improve timing
    * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
    * 2KB instruction cache 
@@ -539,10 +540,18 @@
 ``` sh
     make verify-wb_port  
     make verify-risc_boot
+    make verify-uart_master
+    make verify-user_basic
     make verify-user_uart
     make verify-user_spi
     make verify-user_i2cm
     make verify-user_risc_boot
+    make verify-user_pwm
+    make verify-user_timer
+    make verify-user_sspi
+    make verify-user_qspi
+    make verify-user_usb
+    make verify-user_uart_master
     make verify-wb_port SIM=RTL DUMP=OFF
     make verify-wb_port SIM=RTL DUMP=ON
     make verify-riscv_regress
@@ -586,11 +595,7 @@
 
 ## Contacts
 
-Report an issue: <https://github.com/dineshannayya/riscduino/issues>
+Report an issue: <https://github.com/dineshannayya/riscduino_dcore/issues>
 
 # Documentation
 * **Syntacore Link** - https://github.com/syntacore/scr1
-
-
-
-

diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index e534f3b..6ef2620 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile

@@ -48,6 +48,10 @@
 SIM?=RTL
 DUMP?=OFF
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_basic

diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 6f0b848..a0aac1a 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile

@@ -48,6 +48,10 @@
 SIM?=RTL
 DUMP?=OFF
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_i2cm

diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile
index 220c33c..80c35a0 100644
--- a/verilog/dv/user_pwm/Makefile
+++ b/verilog/dv/user_pwm/Makefile

@@ -46,6 +46,10 @@
 SIM?=RTL
 DUMP?=OFF
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_pwm

diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile
index 250d502..4447c1c 100644
--- a/verilog/dv/user_qspi/Makefile
+++ b/verilog/dv/user_qspi/Makefile

@@ -48,6 +48,10 @@
 SIM?=RTL
 DUMP?=OFF
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_qspi

diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 46c4437..7476457 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile

@@ -49,6 +49,10 @@
 DUMP?=OFF
 RISC_CORE?=0
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_risc_boot

diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile
index 0f8d1a7..db60fd3 100644
--- a/verilog/dv/user_sspi/Makefile
+++ b/verilog/dv/user_sspi/Makefile

@@ -48,6 +48,10 @@
 SIM?=RTL
 DUMP?=OFF
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_sspi

diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile
index cda351b..9e7660a 100644
--- a/verilog/dv/user_timer/Makefile
+++ b/verilog/dv/user_timer/Makefile

@@ -46,6 +46,10 @@
 SIM?=RTL
 DUMP?=OFF
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_timer

diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 320f113..7d5a495 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile

@@ -49,6 +49,10 @@
 DUMP?=OFF
 RISC_CORE?=0
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_uart

diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index 4e61e77..eca6304 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile

@@ -43,6 +43,10 @@
 SIM?=RTL
 DUMP?=OFF
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_uart_master

diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile
index 3e082d3..2a70c4c 100644
--- a/verilog/dv/user_usb/Makefile
+++ b/verilog/dv/user_usb/Makefile

@@ -50,6 +50,10 @@
 DUMP?=OFF
 RISC_CORE?=0
 
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
 .SUFFIXES:
 
 PATTERN = user_usb