All the marco lvs has done with gds
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl index f5360ec..b1bce35 100755 --- a/openlane/pinmux_top/config.tcl +++ b/openlane/pinmux_top/config.tcl
@@ -106,8 +106,6 @@ ###################################################################################### # Metal-2/3 Signal are Routed near to block boundary is creating DRC violation at Top-level # during pad connectivity -#set ::env(FP_IO_HEXTEND) {1} -#set ::env(FP_IO_VEXTEND) {1} #set ::env(GRT_OBS) " \ # met2 0 2 500 3, \ @@ -133,11 +131,13 @@ set ::env(DIODE_INSERTION_STRATEGY) 4 - #LVS Issue - DEF Base looks to having issue set ::env(MAGIC_EXT_USE_GDS) {1} - +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1" +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1" +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) "1" set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" set ::env(QUIT_ON_LVS_ERROR) "1"
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg index 724e4f3..fcf8cf6 100644 --- a/openlane/pinmux_top/pin_order.cfg +++ b/openlane/pinmux_top/pin_order.cfg
@@ -70,7 +70,6 @@ e_reset_n p_reset_n s_reset_n -rtc_clk usb_clk strap_sticky\[31\] strap_sticky\[30\] @@ -301,7 +300,8 @@ #N -digital_io_oen\[37\] 000 0 2 +rtc_clk 000 0 2 +digital_io_oen\[37\] digital_io_out\[37\] digital_io_in\[37\] digital_io_oen\[36\]
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl index f715632..06d3dd2 100755 --- a/openlane/qspim_top/config.tcl +++ b/openlane/qspim_top/config.tcl
@@ -85,6 +85,9 @@ # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0" +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + #set ::env(FP_IO_VEXTEND) 4 #set ::env(FP_IO_HEXTEND) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index b317ba7..0415b67 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -105,6 +105,9 @@ set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.42" +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0" @@ -125,7 +128,7 @@ set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1} #set ::env(GLB_RT_ADJUSTMENT) {0.25} -set ::env(GRT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0} +#set ::env(GRT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0} set ::env(CELL_PAD) {8} set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index cf8883d..b8c8715 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -2,10 +2,10 @@ u_uart_i2c_usb_spi 2250 1350 N u_pinmux 2250 2250 N -u_riscv_top.i_core_top_0 50 1400 N -u_riscv_top.i_core_top_1 1200 1400 FN -u_riscv_top.u_connect 735 1400 N -u_riscv_top.u_intf 950 650 N +u_riscv_top.i_core_top_0 75 1400 N +u_riscv_top.i_core_top_1 1200 1400 FN +u_riscv_top.u_connect 735 1400 N +u_riscv_top.u_intf 950 650 N u_dcache_2kb 150 130 N u_icache_2kb 950 130 N u_tsram0_2kb 150 750 N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index f69b2c4..2f1eeb6 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -85,7 +85,7 @@ # If you're going to use multiple power domains, then keep this disabled. -set ::env(RUN_CVC) 1 +set ::env(RUN_CVC) 0 #set ::env(PDN_CFG) $script_dir/pdn.tcl @@ -109,6 +109,9 @@ set ::env(DIODE_INSERTION_STRATEGY) 4 +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1" set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index de21996..51f3ba1 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -107,14 +107,9 @@ set ::env(GRT_ADJUSTMENT) 0.1 set ::env(DPL_CELL_PADDING) 1 -#set ::env(GLB_RT_ADJUSTMENT) 0 -#set ::env(GLB_RT_L2_ADJUSTMENT) 0.21 -#set ::env(GLB_RT_L3_ADJUSTMENT) 0.21 -#set ::env(GLB_RT_L4_ADJUSTMENT) 0.1 -#set ::env(GLB_RT_L5_ADJUSTMENT) 0.1 -#set ::env(GLB_RT_L6_ADJUSTMENT) 0.1 -#set ::env(GLB_RT_ALLOW_CONGESTION) 0 -#set ::env(GLB_RT_OVERFLOW_ITERS) 200 + +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl index 76ec7e5..1542431 100644 --- a/openlane/ycr2_iconnect/config.tcl +++ b/openlane/ycr2_iconnect/config.tcl
@@ -63,36 +63,34 @@ set ::env(DIE_AREA) "0 0 390 1200" set ::env(PL_TARGET_DENSITY) 0.20 -set ::env(CELL_PAD) 2 -set ::env(GRT_ADJUSTMENT) {0.2} +#set ::env(CELL_PAD) 2 +#set ::env(GRT_ADJUSTMENT) {0.2} #set ::env(GLB_RT_ADJUSTMENT) {0.2} #set ::env(PL_ROUTABILITY_DRIVEN) "1" set ::env(PL_TIME_DRIVEN) "1" -set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1} -set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1} -set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1} -set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1} -set ::env(GLB_OPTIMIZE_MIRRORING) {1} -set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1} - -### PDN -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 6.2 -set ::env(FP_PDN_HWIDTH) 6.2 - #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20 -set ::env(DIODE_INSERTION_STRATEGY) 3 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +set ::env(DIODE_INSERTION_STRATEGY) 4 +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1" +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1" +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) "1" set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" set ::env(QUIT_ON_LVS_ERROR) "1" set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index c4a2de6..016305e 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -82,11 +82,16 @@ ## Routing set ::env(GRT_ADJUSTMENT) 0.2 +set ::env(PL_TIME_DRIVEN) "1" + #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 3 +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" @@ -96,6 +101,7 @@ #Need to cross-check why global timing opimization creating setup vio with hugh hold fix set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" +#PDN set ::env(FP_PDN_VPITCH) 100 set ::env(FP_PDN_HPITCH) 100 set ::env(FP_PDN_VWIDTH) 6.2
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index ab60789..a66d6ae 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -69,8 +69,11 @@ set ::env(PL_TARGET_DENSITY) 0.37 -#set ::env(FP_IO_VEXTEND) {6} -#set ::env(FP_IO_HEXTEND) {6} +set ::env(FP_IO_VEXTEND) {4} +set ::env(FP_IO_HEXTEND) {4} + +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAXLAYER) "5"
diff --git a/signoff/ycr2_iconnect/OPENLANE_VERSION b/signoff/ycr2_iconnect/OPENLANE_VERSION index d5588cd..b5bf449 100644 --- a/signoff/ycr2_iconnect/OPENLANE_VERSION +++ b/signoff/ycr2_iconnect/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8 +openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
diff --git a/signoff/ycr2_iconnect/PDK_SOURCES b/signoff/ycr2_iconnect/PDK_SOURCES index e8e14ea..f9d0f46 100644 --- a/signoff/ycr2_iconnect/PDK_SOURCES +++ b/signoff/ycr2_iconnect/PDK_SOURCES
@@ -1 +1 @@ -open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066 +open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION index d5588cd..b5bf449 100644 --- a/signoff/ycr_core_top/OPENLANE_VERSION +++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8 +openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES index e8e14ea..f9d0f46 100644 --- a/signoff/ycr_core_top/PDK_SOURCES +++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066 +open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION index d5588cd..b5bf449 100644 --- a/signoff/ycr_intf/OPENLANE_VERSION +++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8 +openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES index e8e14ea..f9d0f46 100644 --- a/signoff/ycr_intf/PDK_SOURCES +++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@ -open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066 +open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index e8fb7d2..6fca945 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -187,4 +187,29 @@ echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin >> wb.min.rpt } - + + echo "SRAM Interface Timing.................." > sram.min.rpt + echo "SRAM Interface Timing.................." > sram.min.summary.rpt + set sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/din0[*]}] + set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/addr0[*]}]] + set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/addr1[*]}]] + set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/csb0[*]}]] + set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/csb1[*]}]] + set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/web0[*]}]] + set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/wmask0[*]}]] + + set sram_oport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/dout0[*]}] + set sram_oport [concat $sram_oport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/dout1[*]}]] + + foreach pin $sram_iport { + echo "SRAM Interface Timing for : [get_full_name $pin]" >> sram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin >> sram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt + } + + foreach pin $sram_oport { + echo "SRAM Interface Timing for : [get_full_name $pin]" >> sram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin >> sram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt + } +
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 141381b..f1f0d68 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema user_mcore_test1 user_mcore_test2 +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema arduino_timer_intr user_mcore_test1 user_mcore_test2 arduino_gpio_intr arduino_i2c_scaner all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/agents/caravel_task.sv b/verilog/dv/agents/caravel_task.sv new file mode 100644 index 0000000..8ce81ef --- /dev/null +++ b/verilog/dv/agents/caravel_task.sv
@@ -0,0 +1,172 @@ + +/******************** +parameter bit [15:0] PAD_STRAP = (2'b00 << `PSTRAP_CLK_SRC ) | + (2'b00 << `PSTRAP_CLK_DIV ) | + (1'b1 << `PSTRAP_UARTM_CFG ) | + (1'b1 << `PSTRAP_QSPI_SRAM ) | + (2'b10 << `PSTRAP_QSPI_FLASH ) | + (1'b1 << `PSTRAP_RISCV_RESET_MODE ) | + (1'b1 << `PSTRAP_RISCV_CACHE_BYPASS ) | + (1'b1 << `PSTRAP_RISCV_SRAM_CLK_EDGE ) | + (2'b00 << `PSTRAP_CLK_SKEW ) | + (1'b0 << `PSTRAP_DEFAULT_VALUE ) ; +****/ + +`ifdef RISC_BOOT // RISCV Based Test case +parameter bit [15:0] PAD_STRAP = 16'b0000_0001_1011_0000; +`else +parameter bit [15:0] PAD_STRAP = 16'b0000_0000_1011_0000; +`endif + +/*********************************************** + +wire [15:0] strap_in; +assign strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1 +assign strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div +assign strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection +assign strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad +assign strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad +assign strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset +assign strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable +assign strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal +assign strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value + +assign strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal +***/ + +initial +begin + // Run in Fast Sim Mode + `ifdef GL + force u_top.mprj.u_wb_host._8654_.Q= 1'b1; + `else + force u_top.mprj.u_wb_host.u_fastsim_buf.X = 1'b1; + `endif + +end +task init; +begin + //#1 - Apply Reset + #1000 RSTB = 1; + repeat (10) @(posedge clock); + #1000 RSTB = 0; + + //#3 - Remove Reset + #1000 RSTB = 1; + repeat (10) @(posedge clock); + //#4 - Wait for Power on reset removal + wait(u_top.mprj.p_reset_n == 1); + + // #5 - Wait for system reset removal + wait(u_top.mprj.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +/**** + //#2 - Apply Strap + strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1 + strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div + strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection + strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad + strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad + strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset + strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable + strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal + strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value + + strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal + + force u_top.io_in[36:29] = strap_in[15:8]; + force u_top.io_in[20:13] = strap_in[7:0]; + repeat (10) @(posedge clock); + + //#3 - Remove Reset + wb_rst_i = 0; // Remove Reset + repeat (10) @(posedge clock); + //#4 - Wait for Power on reset removal + wait(u_top.p_reset_n == 1); + + // #5 - Release the Strap + release u_top.io_in[36:29]; + release u_top.io_in[20:13]; + + // #6 - Wait for system reset removal + wait(u_top.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +***/ + end +endtask + +task apply_strap; +input [15:0] strap; +begin + + repeat (10) @(posedge clock); + //#1 - Apply Reset + RSTB = 0; + //#2 - Apply Strap + force u_top.mprj_io[36:29] = strap[15:8]; + force u_top.mprj_io[20:13] = strap[7:0]; + repeat (10) @(posedge clock); + + //#3 - Remove Reset + RSTB = 1; // Remove Reset + + //#4 - Wait for Power on reset removal + wait(u_top.mprj.p_reset_n == 1); + + // #5 - Release the Strap + release u_top.mprj_io[36:29]; + release u_top.mprj_io[20:13]; + + // #6 - Wait for system reset removal + wait(u_top.mprj.s_reset_n == 1); // Wait for system reset removal + repeat (10) @(posedge clock); + +end +endtask + +//--------------------------------------------------------- +// Create Pull Up/Down Based on Reset Strap Parameter +//--------------------------------------------------------- + +genvar gCnt; +generate + for(gCnt=0; gCnt<16; gCnt++) begin : g_strap + if(gCnt < 8) begin + if(PAD_STRAP[gCnt]) begin + pullup(mprj_io[13+gCnt]); + end else begin + pulldown(mprj_io[13+gCnt]); + end + end else begin + if(PAD_STRAP[gCnt]) begin + pullup(mprj_io[29+gCnt-8]); + end else begin + pulldown(mprj_io[29+gCnt-8]); + end + end + end + +`ifdef RISC_BOOT // RISCV Based Test case +//------------------------------------------- +task wait_riscv_boot; +begin + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + $display("Status: Waiting for RISCV Core Boot ... "); + + wait(u_top.mprj.u_pinmux.u_glbl_reg.reg_15 == 8'h1); + $display("Status: RISCV Core is Booted "); + +end +endtask + +`endif + + +endgenerate +
diff --git a/verilog/dv/agents/user_tasks.sv b/verilog/dv/agents/user_tasks.sv index 2cbdfc6..a6dedb0 100644 --- a/verilog/dv/agents/user_tasks.sv +++ b/verilog/dv/agents/user_tasks.sv
@@ -97,6 +97,10 @@ end endtask +//----------------------------------------------- +// Apply user defined strap at power-on +//----------------------------------------------- + task apply_strap; input [15:0] strap; begin @@ -126,6 +130,9 @@ end endtask +//--------------------------------------------------------- +// Create Pull Up/Down Based on Reset Strap Parameter +//--------------------------------------------------------- genvar gCnt; generate for(gCnt=0; gCnt<16; gCnt++) begin : g_strap @@ -147,6 +154,7 @@ `ifdef RISC_BOOT // RISCV Based Test case //------------------------------------------- task wait_riscv_boot; +input [7:0] id; begin // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit // bit[7:0] - core-0 @@ -155,9 +163,9 @@ // bit[31:24] - core-3 $display("Status: Waiting for RISCV Core Boot ... "); read_data = 0; - while((read_data >> (d_risc_id*8)) != 8'h1) begin + while((read_data >> (id*8)) != 8'h1) begin + repeat (200) @(posedge clock); wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,read_data); - repeat (1000) @(posedge clock); end $display("Status: RISCV Core is Booted "); @@ -165,6 +173,27 @@ end endtask + +task wait_riscv_exit; +input [7:0] id; +begin + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + $display("Status: Waiting for RISCV Core Boot ... "); + read_data = 0; + while((read_data >> (id*8)) != 8'hFF) begin + repeat (200) @(posedge clock); + wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,read_data); + end + + $display("Status: RISCV Core is Exited "); + +end +endtask + `endif
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v index 8f8b4ae..cd671e2 100644 --- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v +++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -192,7 +192,7 @@ $display("Monitor: Standalone User Risc Boot Test Started"); init(); - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); // Remove Wb Reset //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v index 699f433..b93e319 100644 --- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v +++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -227,7 +227,7 @@ $display("Monitor: Standalone User Risc Boot Test Started"); init(); - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); // Remove Wb Reset //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v index e91855d..edd4444 100644 --- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v +++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -173,7 +173,7 @@ $display("Monitor: Standalone User Risc Boot Test Started"); init(); - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); // Remove Wb Reset //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v index 608d120..035faac 100644 --- a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v +++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
@@ -286,7 +286,7 @@ $value$plusargs("risc_core_id=%d", d_risc_id); init(); - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); #200; // Wait for reset removal repeat (10) @(posedge clock);
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v index 8fc236c..8fac63c 100644 --- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v +++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -199,7 +199,7 @@ $display("Monitor: Standalone User Risc Boot Test Started"); init(); - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); // Remove Wb Reset //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
diff --git a/verilog/dv/arduino_multi_serial/Makefile b/verilog/dv/arduino_multi_serial/Makefile index d0899fd..2c7cd0d 100644 --- a/verilog/dv/arduino_multi_serial/Makefile +++ b/verilog/dv/arduino_multi_serial/Makefile
@@ -104,24 +104,24 @@ rm *.o *.a ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp b/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp index c857650..21cfce6 100644 --- a/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp +++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp
@@ -24,11 +24,8 @@ */ -#line 25 "/tmp/.arduinoIDE-unsaved202266-51666-8e7jjt.yj22m/MultiSerial/MultiSerial.ino" void setup(); -#line 31 "/tmp/.arduinoIDE-unsaved202266-51666-8e7jjt.yj22m/MultiSerial/MultiSerial.ino" void loop(); -#line 25 "/tmp/.arduinoIDE-unsaved202266-51666-8e7jjt.yj22m/MultiSerial/MultiSerial.ino" void setup() { // initialize both serial ports: Serial.begin(288000);
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v index 8cfeed9..8a969ad 100644 --- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v +++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -71,6 +71,7 @@ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "is62wvs1288.v" `include "uart_agent.v" +`include "user_params.svh" `define TB_HEX "arduino_multi_serial.hex" `define TB_TOP arduino_multi_serial_tb @@ -187,108 +188,111 @@ initial begin - uart_data_bit = 2'b11; - uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; - uart_stick_parity = 0; // 1: force even parity - uart_parity_en = 0; // parity enable - uart_even_odd_parity = 1; // 0: odd parity; 1: even parity - tb_set_uart_baud(50000000,288000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 - uart_timeout = 2000;// wait time limit - uart_fifo_enable = 0; // fifo mode disable + uart_data_bit = 2'b11; + uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; + uart_stick_parity = 0; // 1: force even parity + uart_parity_en = 0; // parity enable + uart_even_odd_parity = 1; // 0: odd parity; 1: even parity + tb_set_uart_baud(50000000,288000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 + uart_timeout = 2000;// wait time limit + uart_fifo_enable = 0; // fifo mode disable $value$plusargs("risc_core_id=%d", d_risc_id); + init(); + wait_riscv_boot(d_risc_id); + #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; - // Remove all the reset - if(d_risc_id == 0) begin - $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); - end else if(d_risc_id == 1) begin - $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); - end else if(d_risc_id == 2) begin - $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); - end else if(d_risc_id == 3) begin - $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); - end + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 3"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); + end - repeat (100) @(posedge clock); // wait for Processor Get Ready + repeat (100) @(posedge clock); // wait for Processor Get Ready - tb_uart0.debug_mode = 1; // enable debug display - tb_uart0.uart_init; - tb_uart0.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, + tb_uart0.debug_mode = 1; // enable debug display + tb_uart0.uart_init; + tb_uart0.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); tb_uart1.debug_mode = 1; // enable debug display - tb_uart1.uart_init; - tb_uart1.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, + tb_uart1.uart_init; + tb_uart1.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (60000) @(posedge clock); // wait for Processor Get Ready - flag = 0; + repeat (5000) @(posedge clock); // wait for Processor Get Ready + flag = 0; check_sum = 0; - for (i=0; i<40; i=i+1) - uart0_write_data[i] = $random; + for (i=0; i<40; i=i+1) + uart0_write_data[i] = $random; - for (i=0; i<40; i=i+1) - uart1_write_data[i] = $random; + for (i=0; i<40; i=i+1) + uart1_write_data[i] = $random; - fork - //Drive UART-0 - begin - for (i=0; i<40; i=i+1) - begin - $display ("\n... UART-0 Agent Writing char %x ...", uart0_write_data[i]); - tb_uart0.write_char (uart0_write_data[i]); - end - end + fork + //Drive UART-0 + begin + for (i=0; i<40; i=i+1) + begin + $display ("\n... UART-0 Agent Writing char %x ...", uart0_write_data[i]); + tb_uart0.write_char (uart0_write_data[i]); + end + end - //Drive UART-1 - begin - for (j=0; j<40; j=j+1) - begin - $display ("\n... UART-1 Agent Writing char %x ...", uart1_write_data[j]); - tb_uart1.write_char (uart1_write_data[j]); - end - end + //Drive UART-1 + begin + for (j=0; j<40; j=j+1) + begin + $display ("\n... UART-1 Agent Writing char %x ...", uart1_write_data[j]); + tb_uart1.write_char (uart1_write_data[j]); + end + end - //Receive UART-0 - begin - for (k=0; k<40; k=k+1) - begin - tb_uart0.read_char_chk(uart1_write_data[k]); - end - end + //Receive UART-0 + begin + for (k=0; k<40; k=k+1) + begin + tb_uart0.read_char_chk(uart1_write_data[k]); + end + end - //Receive UART-1 - begin - for (l=0; l<40; l=l+1) - begin - tb_uart1.read_char_chk(uart0_write_data[l]); - end - end - join + //Receive UART-1 + begin + for (l=0; l<40; l=l+1) + begin + tb_uart1.read_char_chk(uart0_write_data[l]); + end + end + join - test_fail = 0; - #100 - tb_uart0.report_status(uart_rx_nu, uart_tx_nu); - if(uart_tx_nu != 40) test_fail = 1; - if(uart_rx_nu != 40) test_fail = 1; + test_fail = 0; + #100 + tb_uart0.report_status(uart_rx_nu, uart_tx_nu); + if(uart_tx_nu != 40) test_fail = 1; + if(uart_rx_nu != 40) test_fail = 1; - tb_uart1.report_status(uart_rx_nu, uart_tx_nu); - if(uart_tx_nu != 40) test_fail = 1; - if(uart_rx_nu != 40) test_fail = 1; + tb_uart1.report_status(uart_rx_nu, uart_tx_nu); + if(uart_tx_nu != 40) test_fail = 1; + if(uart_rx_nu != 40) test_fail = 1; $display("###################################################"); @@ -309,11 +313,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -352,8 +351,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -571,6 +570,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index 2601fc5..f9bb9f4 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -113,6 +113,7 @@ # RTL/GL/GL_SDF SIM?=RTL DUMP?=OFF +RISC_CORE?=0 .SUFFIXES: @@ -164,11 +165,11 @@ ## RTL ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif @@ -177,11 +178,11 @@ ##GL ifeq ($(SIM),GL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DGL -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + iverilog -g2005-sv -Ttyp -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< endif @@ -205,7 +206,7 @@ endif %.vcd: %.vvp - vvp $< + vvp $< +risc_core_id=$(RISC_CORE) # twinwave: RTL-%.vcd GL-%.vcd # twinwave RTL-$@ * + GL-$@ * @@ -229,7 +230,7 @@ # ---- Clean ---- clean: - \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe + \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe *.dump .PHONY: clean hex all
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index 8ff48ff..d7c3275 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -18,155 +18,11 @@ // This include is relative to $CARAVEL_PATH (see Makefile) #include <defs.h> #include <stub.c> -#include "../c_func/inc/user_reg_map.h" - -// User Project Slaves (0x3000_0000) - -#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30080000) - -#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000) -#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004) -#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008) -#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C) -#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010) -#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014) -#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018) -#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C) -#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020) - -#define GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP 0x1C00 -/* - RiscV Hello World test. - - Wake up the Risc V - - Boot from SPI Flash - - Riscv Write Hello World to SDRAM, - - External Wishbone read back validation the data -*/ -int i = 0; -int clk = 0; void main() { - int bFail = 0; - /* - IO Control Registers - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | - Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - */ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spi_enable = 1; - reg_wb_enable = 1; - // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] - - // Flag start of the test - reg_mprj_datal = 0xAB600000; - - //----------------------------------------------------- - // Start of User Functionality and take over the GPIO Pins - // ------------------------------------------------------ - // User block decide on the GPIO function - reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - //reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - reg_la0_data = 0x001; // Remove Soft Reset - reg_la0_data = 0x000; - reg_la0_data = 0x001; // Remove Soft Reset - - - // Remove Wishbone Reset - reg_mprj_wbhost_reg0 = 0x1; - - - // Remove All Reset - reg_glbl_cfg0 = 0x11F; - - // Enable UART Multi Functional Ports - - reg_glbl_multi_func = 0x100; - - // configure the user uart - reg_mprj_uart_reg0 = 0x7; }
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v index e9865d9..ee52d59 100644 --- a/verilog/dv/risc_boot/risc_boot_tb.v +++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -72,6 +72,7 @@ `timescale 1 ns / 1 ps `include "uart_agent.v" +`include "user_params.svh" module risc_boot_tb; reg clock; @@ -103,6 +104,7 @@ reg [7:0] uart_write_data [0:39]; reg uart_fifo_enable ; // fifo mode disable reg test_fail ; + integer d_risc_id; integer i,j; //--------------------------------- @@ -130,9 +132,9 @@ $dumpfile("simx.vcd"); $dumpvars(1,risc_boot_tb); //$dumpvars(1,risc_boot_tb.u_spi_flash_256mb); - //$dumpvars(2,risc_boot_tb.uut); - $dumpvars(1,risc_boot_tb.uut.mprj); - $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host); + //$dumpvars(2,risc_boot_tb.u_top); + $dumpvars(1,risc_boot_tb.u_top.mprj); + $dumpvars(0,risc_boot_tb.u_top.mprj.u_wb_host); //$dumpvars(0,risc_boot_tb.tb_uart); //$dumpvars(0,risc_boot_tb.u_user_spiflash); $display("Waveform Dump started"); @@ -160,6 +162,11 @@ initial begin + + $value$plusargs("risc_core_id=%d", d_risc_id); + + init(); + uart_data_bit = 2'b11; uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; uart_stick_parity = 0; // 1: force even parity @@ -172,15 +179,16 @@ #200; // Wait for reset removal // Wait for Managment core to boot up - wait(checkbits == 16'h AB60); - $display("Monitor: Test User Risc Boot Started"); // Wait for user risc core to boot up - repeat (50000) @(posedge clock); tb_uart.uart_init; tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); + + wait_riscv_boot(d_risc_id); + repeat (50000) @(posedge clock); + for (i=0; i<40; i=i+1) uart_write_data[i] = $random; @@ -238,10 +246,8 @@ initial begin - RSTB <= 1'b0; CSB <= 1'b1; // Force CSB high #2000; - RSTB <= 1'b1; // Release reset #170000; CSB = 1'b0; // CSB can be released end @@ -276,7 +282,7 @@ wire USER_VDD1V8 = power4; wire VSS = 1'b0; - caravel uut ( + caravel u_top ( .vddio (VDD3V3), .vssio (VSS), .vdda (VDD3V3), @@ -316,8 +322,8 @@ // Connect Quad Flash to for usr Risc Core //----------------------------------------- - wire user_flash_clk = mprj_io[24]; - wire user_flash_csb = mprj_io[25]; + wire user_flash_clk = mprj_io[28]; + wire user_flash_csb = mprj_io[29]; //tri user_flash_io0 = mprj_io[26]; //tri user_flash_io1 = mprj_io[27]; //tri user_flash_io2 = mprj_io[28]; @@ -330,13 +336,13 @@ .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs - .SI (mprj_io[29]), - .SO (mprj_io[30]), + .SI (mprj_io[33]), + .SO (mprj_io[34]), // Controls .SCK (user_flash_clk), .CSNeg (user_flash_csb), - .WPNeg (mprj_io[31]), - .HOLDNeg (mprj_io[32]), + .WPNeg (mprj_io[35]), + .HOLDNeg (mprj_io[36]), .RSTNeg (RSTB) ); @@ -346,8 +352,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = mprj_io[2]; -assign mprj_io[1] = uart_rxd ; +assign uart_txd = mprj_io[7]; +assign mprj_io[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -361,6 +367,7 @@ initial begin end `endif +`include "caravel_task.sv" endmodule // SSFLASH has 1ps/1ps time scale `include "s25fl256s.sv"
diff --git a/verilog/dv/risc_boot/user_uart.c b/verilog/dv/risc_boot/user_uart.c index 29805f7..b19a157 100644 --- a/verilog/dv/risc_boot/user_uart.c +++ b/verilog/dv/risc_boot/user_uart.c
@@ -16,42 +16,33 @@ // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> // ////////////////////////////////////////////////////////////////////////// #define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long +#include "../c_func/inc/int_reg_map.h" +#include "common_misc.h" +#include "common_bthread.h" -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C) -#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010000) -#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010004) -#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010008) -#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001000C) -#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010010) -#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010014) -#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010018) -#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001001C) -#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010020) int main() { + reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART + reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0 + reg_glbl_multi_func |=0x100; // Enable UART Multi func + reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1} + + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + + reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main + while(1) { // Check UART RX fifo has data, if available loop back the data - if(reg_mprj_uart_reg8 != 0) { - reg_mprj_uart_reg5 = reg_mprj_uart_reg6; + // Also check txfifo is not full + if((reg_uart0_rxfifo_stat != 0) && ((reg_uart0_status & 0x1) != 0x1)) { + reg_uart0_txdata = reg_uart0_rxdata; } }
diff --git a/verilog/dv/user_mcore_test1/Makefile b/verilog/dv/user_mcore_test1/Makefile index 9aa71f1..376195f 100644 --- a/verilog/dv/user_mcore_test1/Makefile +++ b/verilog/dv/user_mcore_test1/Makefile
@@ -60,24 +60,24 @@ rm crt.o ${PATTERN}.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/user_mcore_test1/user_mcore_test1.c b/verilog/dv/user_mcore_test1/user_mcore_test1.c index a77f439..36eb98a 100644 --- a/verilog/dv/user_mcore_test1/user_mcore_test1.c +++ b/verilog/dv/user_mcore_test1/user_mcore_test1.c
@@ -16,6 +16,7 @@ */ +#include "../c_func/inc/int_reg_map.h" #include "common_misc.h" #include "common_bthread.h" @@ -24,18 +25,6 @@ #define uint16_t int #define size 10 -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel -#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 -#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 -#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 -#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 -#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 -#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 // ------------------------------------------------------------------------- // Multi-core test, Two Array is filled with below data, destination hold sum // source result remark @@ -97,6 +86,15 @@ int src0[buf_size]; int src1[buf_size]; char test_pass = 0x1; + if ( bthread_get_core_id() == 0 ) { + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main + + } for ( int i = 0; i < buf_size; i++ ) { src0[i] = 0x1111 * (i); @@ -121,18 +119,18 @@ // Spawn work onto core 1 bthread_spawn( 1, &vvadd_mt, &arg1 ); - reg_mprj_globl_soft2 = 0x33445566; // Sig-2 + reg_glbl_soft_reg_2 = 0x33445566; // Sig-2 // Have core 0 also do some work. vvadd_mt(&arg0); - reg_mprj_globl_soft3 = 0x44556677; // Sig-3 + reg_glbl_soft_reg_3 = 0x44556677; // Sig-3 // Wait for core 1 to finish. bthread_join(1); // Stop counting stats //test_stats_off(); - reg_mprj_globl_soft4 = 0x55667788; // sig-4 + reg_glbl_soft_reg_4 = 0x55667788; // sig-4 // Core 0 will verify the results. if ( bthread_get_core_id() == 0 ) { @@ -143,10 +141,19 @@ test_pass &= 0; } if(test_pass == 0x1) { - reg_mprj_globl_soft5 = 0x66778899; // sig-5 + reg_glbl_soft_reg_5 = 0x66778899; // sig-5 } } + if ( bthread_get_core_id() == 0 ) { + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + reg_glbl_mail_box = 0xff << (bthread_get_core_id() * 8); // Start of Main + + } return 0; }
diff --git a/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v index 1d75851..f22daef 100644 --- a/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v +++ b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
@@ -128,13 +128,14 @@ initial begin $value$plusargs("risc_core_id=%d", d_risc_id); + init(); #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; @@ -143,12 +144,9 @@ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F); - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (23) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end + wait_riscv_boot(0); + wait_riscv_exit(0); $display("Monitor: Reading Back the expected value"); // User RISC core expect to write these value in global @@ -188,11 +186,7 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end + wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -231,8 +225,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -246,22 +240,22 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash s25fl256s #(.mem_file_name(`TB_HEX_FILE), @@ -412,6 +406,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_mcore_test2/Makefile b/verilog/dv/user_mcore_test2/Makefile index 1c301e2..8054ca6 100644 --- a/verilog/dv/user_mcore_test2/Makefile +++ b/verilog/dv/user_mcore_test2/Makefile
@@ -60,24 +60,24 @@ rm crt.o ${PATTERN}.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) - iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@
diff --git a/verilog/dv/user_mcore_test2/user_mcore_test2.c b/verilog/dv/user_mcore_test2/user_mcore_test2.c index 4ba53eb..b2a53c8 100644 --- a/verilog/dv/user_mcore_test2/user_mcore_test2.c +++ b/verilog/dv/user_mcore_test2/user_mcore_test2.c
@@ -55,17 +55,22 @@ // Common Sub-Routine if ( bthread_get_core_id() == 0 ) { - // Enable the GPIO UART I/F reg_glbl_multi_func = 0x100; - // Enable the UART TX/RX & STOP=2 - reg_uart0_ctrl = 0x7; // 1152000 Baud at 50Mhz System clock reg_uart0_baud_ctrl1 = 0x0; reg_uart0_baud_ctrl2 = 0x0; + // Enable the UART TX/RX & STOP=2 + reg_uart0_ctrl = 0x7; - reg_glbl_soft_reg_5 = 0x1; // Test Start Indication + // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit + // bit[7:0] - core-0 + // bit[15:8] - core-1 + // bit[23:16] - core-2 + // bit[31:24] - core-3 + reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main + } // Core 0 thread if ( bthread_get_core_id() == 0 ) { @@ -78,7 +83,7 @@ // Core 1 thread if ( bthread_get_core_id() == 1 ) { - while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start + while((reg_glbl_mail_box & 0x1) == 0x0); // wait for test start print_message("UART command-0 from core-1\n"); print_message("UART command-1 from core-1\n"); print_message("UART command-2 from core-1\n"); @@ -87,7 +92,7 @@ } // Core 2 thread if ( bthread_get_core_id() == 2 ) { - while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start + while((reg_glbl_mail_box & 0x1) == 0x0); // wait for test start print_message("UART command-0 from core-2\n"); print_message("UART command-1 from core-2\n"); print_message("UART command-2 from core-2\n"); @@ -96,7 +101,7 @@ } // Core 3 thread if ( bthread_get_core_id() == 3 ) { - while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start + while((reg_glbl_mail_box & 0x1) == 0x0); // wait for test start print_message("UART command-0 from core-3\n"); print_message("UART command-1 from core-3\n"); print_message("UART command-2 from core-3\n");
diff --git a/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v index 18f5cf0..63ca219 100644 --- a/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v +++ b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
@@ -192,17 +192,21 @@ uart_parity_en = 0; // parity enable uart_even_odd_parity = 1; // 0: odd parity; 1: even parity tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 - uart_timeout = 200;// wait time limit + uart_timeout = 2000;// wait time limit uart_fifo_enable = 0; // fifo mode disable $value$plusargs("risc_core_id=%d", d_risc_id); + init(); + + #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); + // Remove Wb Reset - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; @@ -210,16 +214,14 @@ $display("STATUS: Working with Both core Risc core 0 & 1 "); wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F); - read_data = 0; - // Wait for Software Reg-5 = 1 Set by the RiscV core - while (read_data !== 32'h1) begin - wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data); - end tb_uart.debug_mode = 0; // disable debug display tb_uart.uart_init; tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); + wait_riscv_boot(0); + + flag = 0; check_sum = 0; test_start = 1; @@ -236,7 +238,7 @@ end end begin - repeat (300000) @(posedge clock); // wait for Processor Get Ready + repeat (600000) @(posedge clock); // wait for Processor Get Ready end join_any @@ -272,11 +274,6 @@ $finish; end - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end wire USER_VDD1V8 = 1'b1; wire VSS = 1'b0; @@ -315,8 +312,8 @@ ); // SSPI Slave I/F -assign io_in[0] = 1'b1; // RESET -assign io_in[16] = 1'b0 ; // SPIS SCK +assign io_in[5] = 1'b1; // RESET +assign io_in[21] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -330,22 +327,22 @@ // user core using the gpio pads // ---------------------------------------------------- - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_clk = io_out[28]; + wire flash_csb = io_out[29]; // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + wire #1 io_oeb_29 = io_oeb[33]; + wire #1 io_oeb_30 = io_oeb[34]; + wire #1 io_oeb_31 = io_oeb[35]; + wire #1 io_oeb_32 = io_oeb[36]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz; - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; + assign io_in[33] = flash_io0; + assign io_in[34] = flash_io1; + assign io_in[35] = flash_io2; + assign io_in[36] = flash_io3; // Quard flash s25fl256s #(.mem_file_name(`TB_HEX_FILE), @@ -370,8 +367,8 @@ // -------------------------- wire uart_txd,uart_rxd; -assign uart_txd = io_out[2]; -assign io_in[1] = uart_rxd ; +assign uart_txd = io_out[7]; +assign io_in[6] = uart_rxd ; uart_agent tb_uart( .mclk (clock ), @@ -430,7 +427,7 @@ wbd_ext_we_i ='h0; // write wbd_ext_dat_i ='h0; // data output wbd_ext_sel_i ='h0; // byte enable - //$display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); repeat (2) @(posedge clock); end endtask @@ -509,6 +506,7 @@ `endif **/ +`include "user_tasks.sv" endmodule `include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index cf5b14d..62a6c21 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -133,9 +133,9 @@ `endif initial begin + $value$plusargs("risc_core_id=%d", d_risc_id); init(); - $value$plusargs("risc_core_id=%d", d_risc_id); #200; // Wait for reset removal repeat (10) @(posedge clock); @@ -155,7 +155,7 @@ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); $display("Monitor: Reading Back the expected value"); // User RISC core expect to write these value in global
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index a4e25f8..e1db54f 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -161,6 +161,8 @@ initial begin + $value$plusargs("risc_core_id=%d", d_risc_id); + init(); uart_data_bit = 2'b11; @@ -209,7 +211,7 @@ uart_stick_parity, uart_timeout, uart_divisor); - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); for (i=0; i<40; i=i+1)
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v index 8559565..cab2731 100644 --- a/verilog/dv/user_uart1/user_uart1_tb.v +++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -207,7 +207,7 @@ uart_stick_parity, uart_timeout, uart_divisor); - wait_riscv_boot(); + wait_riscv_boot(d_risc_id); for (i=0; i<40; i=i+1)
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/digital_pll/src/digital_pll.v index a4f189b..79cb52e 100644 --- a/verilog/rtl/digital_pll/src/digital_pll.v +++ b/verilog/rtl/digital_pll/src/digital_pll.v
@@ -15,8 +15,12 @@ /***************************************************************** +Formula clock period: 1.168 + (bcount * 0.012) -Offset bcount 4x clock period clock period (ns) clock (Mhz) +Example for bcount: 10 + clock period = 1.168 + (10 *0.012) = 1.288 + +Offset bcount clock period 4xclock period (ns) clock (Mhz) 1.168 0 1.168 4.672 214.041095890411 1.168 1 1.18 4.72 211.864406779661 1.168 2 1.192 4.768 209.731543624161