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foss-eda-tools/third_party/shuttle/sky130/mpw-007/slot-006/a966daa9a9d190c1f620acfe52784d6c6dc15a61^!/.
commit
a966daa9a9d190c1f620acfe52784d6c6dc15a61
[log]
author
dineshannayya <dinesh.annayya@gmail.com>
Sun Nov 27 21:53:22 2022 +0530
committer
dineshannayya <dinesh.annayya@gmail.com>
Sun Nov 27 21:53:22 2022 +0530
tree
40bed1c228a11aee3d98a5e0a6b9a3b9df404ad9
parent
1f4edd077d15d05c2ba81137e8d35d10580fb5e0 [diff]
Timing Min clean database

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 1334cec..fe93390 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index fc30bce..e55e3c3 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ

diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 960f746..3900d26 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl

@@ -41,7 +41,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-     $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
      $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv     \
      $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv     \
      $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv  \

diff --git a/openlane/uart_i2c_usb_spi_top/config.tcl b/openlane/uart_i2c_usb_spi_top/config.tcl
index 7576c81..358a009 100644
--- a/openlane/uart_i2c_usb_spi_top/config.tcl
+++ b/openlane/uart_i2c_usb_spi_top/config.tcl

@@ -41,7 +41,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-    $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+    $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
     $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_core.sv  \
     $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_cfg.sv   \
     $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \

diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 1f6639d..c464041 100755
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl

@@ -258,7 +258,7 @@
     set steps [dict create \
         "synthesis" "run_synthesis" \
         "floorplan" "run_floorplan" \
-        "placement" "run_placement_step" \
+        "placement" "run_placement_step"\
         "cts" "run_cts_step" \
         "routing" "run_routing_step" \
         "parasitics_sta" "run_parasitics_sta_step" \

diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index c654abd..48a791b 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl

@@ -42,7 +42,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-     $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
      $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reset_fsm.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reg.sv \

diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index f169b0e..a87255c 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl

@@ -43,7 +43,8 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-        $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv     \
         $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_wbb.sv                \
         $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo2.sv                \
         $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv     \

diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index e2344a5..51bfa57 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg

@@ -622,6 +622,12 @@
 
 ch_clk_out\[6\]
 
+ch_data_out\[27\]  750 0 2
+ch_data_out\[26\] 
+ch_data_out\[25\] 
+ch_data_out\[24\] 
+ch_clk_out\[5\]
+
 ch_data_out\[76\]   1600 0 2
 ch_data_out\[75\] 
 ch_data_out\[74\] 
@@ -656,12 +662,6 @@
 ch_data_out\[45\] 
 ch_data_out\[44\] 
 
-ch_data_out\[27\] 
-ch_data_out\[26\] 
-ch_data_out\[25\] 
-ch_data_out\[24\] 
-ch_clk_out\[5\]
-
 ch_data_out\[149\]  1700 0 2
 ch_data_out\[148\]  
 ch_data_out\[147\]  

diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg
index 7c607cd..e23aca7 100644
--- a/openlane/ycr2_iconnect/pin_order.cfg
+++ b/openlane/ycr2_iconnect/pin_order.cfg

@@ -819,6 +819,14 @@
 riscv_debug\[0\]
 
 #E
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
+core_clk          
+
 core1_uid\[1\]      0200 00 2
 core1_uid\[0\]   
 core1_imem_req_ack
@@ -1182,13 +1190,6 @@
 core_irq_lines_i\[0\]
 core_irq_soft_i
 
-cfg_ccska\[3\]
-cfg_ccska\[2\]
-cfg_ccska\[1\]
-cfg_ccska\[0\]
-core_clk_int
-core_clk_skew
-core_clk          
 rtc_clk
 pwrup_rst_n
 cpu_intf_rst_n

diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index b03c508..cc73165 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc

@@ -217,7 +217,7 @@
 set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
 
 ## DCACHE PORT-0 SRAM I/F
-set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
 set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
 set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
 set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]

diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/pinmux_top/OPENLANE_VERSION
+++ b/signoff/pinmux_top/OPENLANE_VERSION

@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483

diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/pinmux_top/PDK_SOURCES
+++ b/signoff/pinmux_top/PDK_SOURCES

@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93

diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION

@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483

diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES

@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93

diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION

@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483

diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES

@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93

diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION

@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483

diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES

@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93

diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION

@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483

diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES

@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93

diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 3dab8e7..69088cd 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ

diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index 26e5cbb..a9c6693 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv

@@ -111,10 +111,12 @@
 	input  logic A,
 	output logic X);
 
+wire X1;
 `ifndef SYNTHESIS
     assign X = A;
 `else
-     sky130_fd_sc_hd__clkdlybuf4s15_2 u_dly (.X(X),.A(A));
+     sky130_fd_sc_hd__clkbuf_1 u_dly0 (.X(X1),.A(A));
+     sky130_fd_sc_hd__clkbuf_1 u_dly1 (.X(X),.A(X1));
 `endif
 
 endmodule

diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index ba50ccf..adb39ff 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh

@@ -4,12 +4,12 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2511_2022;
+parameter CHIP_RELEASE_DATE = 32'h2711_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0005_9000;
+parameter CHIP_REVISION   = 32'h0006_0000;
 
-parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_1100_1010_1010_1001_0011;
-parameter CLK_SKEW2_RESET_VAL = 32'b0000_0000_0000_0000_0000_0000_0000_0111;
+parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_1000_1000_1110_1000_0100;
+parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_1000_0111_1110;
 
 parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;
 

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 7a38583..f7b53fa 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v

@@ -288,6 +288,8 @@
 ////    5.9  Nov 25, 2022, Dinesh A                               ////
 ////         cpu_clk will be feed through wb_interconnect for     ////
 ////         buffering purpose                                    ////
+////    6.0  Nov 27, 2022, Dinesh A                               ////
+////         MPW-7 Timing clean setup
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////