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foss-eda-tools/third_party/shuttle/sky130/mpw-007/slot-006/8f65930fa51069d75a50e3f23f746954fdd70227^!/.
commit
8f65930fa51069d75a50e3f23f746954fdd70227
[log]
author
dineshannayya <dinesh.annayya@gmail.com>
Mon Nov 14 16:10:24 2022 +0530
committer
dineshannayya <dinesh.annayya@gmail.com>
Mon Nov 14 16:10:24 2022 +0530
tree
820639d09ce503424ab3d134aef3b74e4b380043
parent
47fa18443e2de5dcba7b1a0d0a3816f168989885 [diff]
update

diff --git a/openlane/dg_pll/base.sdc b/openlane/dg_pll/base.sdc
index 062e55d..b10a47b 100644
--- a/openlane/dg_pll/base.sdc
+++ b/openlane/dg_pll/base.sdc

@@ -1,35 +1,27 @@
-
-
-current_design digital_pll
+current_design dg_pll
 
 create_clock [get_pins {"ringosc.ibufp01/Y"} ] -name "pll_control_clock"  -period 6.6666666666667 
 
 set_propagated_clock [get_clocks {pll_control_clock}] 
 
-set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
-set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
-puts "\[INFO\]: Setting output delay to: $output_delay_value"
-puts "\[INFO\]: Setting input delay to: $input_delay_value"
 
-set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs]
-set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
+set ::env(SYNTH_TIMING_DERATE) 0.05
 puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
 set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
 set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 
-puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
-set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_control_clock}]
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
 
-puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
-set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_control_clock}]
 
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
 
 set_max_transition 1.00 [current_design]
 set_max_capacitance 0.2 [current_design]

diff --git a/openlane/dg_pll/config.tcl b/openlane/dg_pll/config.tcl
index ab632d6..0a00de1 100644
--- a/openlane/dg_pll/config.tcl
+++ b/openlane/dg_pll/config.tcl

@@ -48,7 +48,7 @@
 #set ::env(BOTTOM_MARGIN_MULT) 2
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 
 set ::env(CELL_PAD)  0

diff --git a/openlane/dg_pll/interactive.tcl b/openlane/dg_pll/interactive.tcl
index 32e355e..5368378 100755
--- a/openlane/dg_pll/interactive.tcl
+++ b/openlane/dg_pll/interactive.tcl

@@ -13,7 +13,6 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 package require openlane; # provides the utils as well
-
 proc run_placement_step {args} {
     if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
         set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
@@ -24,69 +23,6 @@
     run_placement
 }
 
-proc run_placement {args} {
-    # |----------------------------------------------------|
-    # |----------------   3. PLACEMENT   ------------------|
-    # |----------------------------------------------------|
-    set ::env(CURRENT_STAGE) placement
-
-    if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
-        set old_pl_target_density $::env(PL_TARGET_DENSITY)
-        set ::env(PL_TARGET_DENSITY) $::env(PL_TARGET_DENSITY_CELLS)
-    }
-
-    if { $::env(PL_RANDOM_GLB_PLACEMENT) } {
-        # useful for very tiny designs
-        random_global_placement
-    } else {
-        global_placement_or
-    }
-
-    if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
-        set ::env(PL_TARGET_DENSITY) $old_pl_target_density
-    }
-
-    run_resizer_design
-    remove_buffers_from_nets
-
-    detailed_placement_or -def $::env(placement_results)/$::env(DESIGN_NAME).def -log $::env(placement_logs)/detailed.log
-
-    scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(placement_logs)/screenshot.log
-}
-
-
-proc global_placement_or {args} {
-    increment_index
-    TIMER::timer_start
-    set log [index_file $::env(placement_logs)/global.log]
-    puts_info "Running Global Placement (log: [relpath . $log])..."
-
-    set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/global.def]
-
-    # random initial placement
-    if { $::env(PL_RANDOM_INITIAL_PLACEMENT) } {
-        random_global_placement
-        set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
-    }
-
-    run_openroad_script $::env(SCRIPTS_DIR)/openroad/gpl.tcl -indexed_log $log
-
-    # sometimes replace fails with a ZERO exit code; the following is a workaround
-    # until the cause is found and fixed
-    if { ! [file exists $::env(SAVE_DEF)] } {
-        puts_err "Global placement has failed to produce a DEF file."
-        flow_fail
-    }
-
-    check_replace_divergence
-
-    TIMER::timer_stop
-    exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "global placement - openroad"
-    set_def $::env(SAVE_DEF)
-}
-
-
-
 proc run_cts_step {args} {
     if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
         set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
@@ -96,6 +32,9 @@
 
     run_cts
     run_resizer_timing
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
 }
 
 proc run_routing_step {args} {
@@ -181,6 +120,12 @@
     }
 }
 
+proc run_erc_step {args} {
+    if { $::env(RUN_CVC) } {
+        run_erc
+    }
+}
+
 proc run_eco_step {args} {
     if { $::env(ECO_ENABLE) == 1 } {
         run_eco_flow
@@ -205,90 +150,13 @@
 proc run_post_run_hooks {} {
     if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
         puts_info "Running post run hook"
-        set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+        set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
         puts_info "$result"
     } else {
         puts_info "hooks/post_run.py not found, skipping"
     }
 }
 
-proc run_magic_drc_batch {args} {
-    set options {
-        {-magicrc optional}
-        {-tech optional}
-        {-report required}
-        {-design required}
-        {-gds required}
-    }
-    set flags {}
-    parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
-    if { [info exists arg_values(-magicrc)] } {
-        set magicrc [file normalize $arg_values(-magicrc)]
-    }
-    if { [info exists arg_values(-tech)] } {
-        set ::env(TECH) [file normalize $arg_values(-tech)]
-    }
-    set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
-    set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
-    set ::env(DESIGN_NAME) $arg_values(-design)
-
-    if { [info exists magicrc] } {
-        exec magic \
-            -noconsole \
-            -dnull \
-            -rcfile $magicrc \
-            $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
-            </dev/null |& tee /dev/tty
-    } else {
-        exec magic \
-            -noconsole \
-            -dnull \
-            $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
-            </dev/null |& tee /dev/tty
-    }
-}
-
-proc run_lvs_batch {args} {
-    # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
-    # extracts gds only if EXT_NETLIST does not exist
-    set options {
-        {-design required}
-        {-gds optional}
-        {-net optional}
-    }
-    set flags {}
-    parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
-
-    prep {*}$args
-
-    if { [info exists arg_values(-gds)] } {
-        set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
-    } else {
-        set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
-    }
-    if { [info exists arg_values(-net)] } {
-        set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
-    }
-
-    assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
-
-    set ::env(MAGIC_EXT_USE_GDS) 1
-    set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
-    if { [file exists $::env(EXT_NETLIST)] } {
-        puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
-    } else {
-        run_magic_spice_export
-    }
-
-    run_lvs
-}
-
-
-proc run_file {args} {
-    set ::env(TCLLIBPATH) $::auto_path
-    exec tclsh {*}$args >&@stdout
-}
-
 proc run_floorplan {args} {
     # |----------------------------------------------------|
     # |----------------   2. FLOORPLAN   ------------------|
@@ -330,17 +198,17 @@
 
     apply_def_template
 
-    #if { [info exist ::env(EXTRA_LEFS)] } {
-        if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
-            file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
-            manual_macro_placement -f
-        } else {
-        #    global_placement_or
-        #    basic_macro_placement
-        }
-    #}
+     if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+         file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+         manual_macro_placement -f
+     } else {
+         #global_placement_or
+         #basic_macro_placement
+     }
 
-    tap_decap_or
+    if { $::env(RUN_TAP_DECAP_INSERTION) } {
+        tap_decap_or
+    }
 
     scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
 
@@ -349,7 +217,6 @@
 
 
 
-
 proc run_flow {args} {
     set options {
         {-design optional}

diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 414f142..f30df93 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl

@@ -105,7 +105,7 @@
 set ::env(PL_TIME_DRIVEN) 1
 set ::env(PL_TARGET_DENSITY) "0.38"
 set ::env(CELL_PAD) "8"
-#set ::env(GRT_ADJUSTMENT) {0.2}
+set ::env(GRT_ADJUSTMENT) {0.2}
 
 
 ######################################################################################
@@ -141,7 +141,7 @@
 
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}

diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index 9c49d24..cd08560 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl

@@ -108,7 +108,7 @@
 
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}

diff --git a/openlane/sar_adc/config.tcl b/openlane/sar_adc/config.tcl
index 7b6c845..8accbf0 100644
--- a/openlane/sar_adc/config.tcl
+++ b/openlane/sar_adc/config.tcl

@@ -83,4 +83,4 @@
 set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
 
 ## LVS mismatch is to be solved manually by shorting VDD and VSS pins to the core ring 
-set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_LVS_ERROR) "1"

diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 7576c81..5ee77d2 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl

@@ -131,7 +131,7 @@
 
 set ::env(CELL_PAD) {8}
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index dc103e6..8d822c9 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -76,6 +76,8 @@
 	    $::env(DESIGN_DIR)/../../verilog/gl/dg_pll.v \
 	    $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/aes_top.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/fpu_wrapper.v \
 	    "
 
 set ::env(EXTRA_LEFS) "\
@@ -88,8 +90,10 @@
 	$lef_root/ycr_core_top.lef \
 	$lef_root/ycr2_iconnect.lef \
 	$lef_root/dg_pll.lef \
-	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
 	$lef_root/dac_top.lef \
+	$lef_root/aes_top.lef \
+	$lef_root/fpu_wrapper.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -103,6 +107,8 @@
 	$gds_root/ycr2_iconnect.gds \
 	$gds_root/dg_pll.gds \
 	$gds_root/dac_top.gds \
+	$gds_root/aes_top.gds \
+	$gds_root/fpu_wrapper.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -168,11 +174,13 @@
 	u_dcache_2kb                vccd1 vssd1 vccd1 vssd1,\
 	u_uart_i2c_usb_spi          vccd1 vssd1 vccd1 vssd1,\
 	u_wb_host                   vccd1 vssd1 vccd1 vssd1,\
-	u_riscv_top.i_core_top_0    vccd1 vssd1 vccd1 vssd1, \
-	u_riscv_top.i_core_top_1    vccd1 vssd1 vccd1 vssd1, \
+	u_riscv_top.i_core_top_0    vccd1 vssd1 vccd1 vssd1,\
+	u_riscv_top.i_core_top_1    vccd1 vssd1 vccd1 vssd1,\
 	u_riscv_top.u_connect       vccd1 vssd1 VPWR  VGND, \
-	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1, \
-	u_4x8bit_dac                vdda1 vssa1 vccd1 vssd1
+	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1,\
+	u_4x8bit_dac                vdda1 vssa1 vccd1 vssd1,\
+	u_aes                       vdda1 vssa1 vccd1 vssd1,\
+	u_fpu                       vdda1 vssa1 vccd1 vssd1
       	"
 
 

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 47411c8..f120935 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg

@@ -4,15 +4,16 @@
 u_pinmux                     2250            2000           N
 u_pll                        2500            3028           N
 
-u_riscv_top.i_core_top_0    75	       1400 	        N
-u_riscv_top.i_core_top_1    1200	       1400	        FN
-u_riscv_top.u_connect       733	       1400	        N
-u_riscv_top.u_intf          950 	       650	            N
-u_dcache_2kb                150             130             N
-u_icache_2kb                950             130             N
-u_tsram0_2kb                150             750             N
+u_fpu                       1000            2600           N
+u_aes                       50              2600           N
+u_riscv_top.i_core_top_0    75	     1400 	     N
+u_riscv_top.i_core_top_1    1200	     1400	     FN
+u_riscv_top.u_connect       733	     1400	     N
+u_riscv_top.u_intf          950 	     650	     N
+u_dcache_2kb                150             130            N
+u_icache_2kb                950             130            N
+u_tsram0_2kb                150             750            N
 
 
 u_intercon                  1850            650             N
 u_wb_host                   1750            100             N
-

diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 407a338..b4c0b35 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl

@@ -121,7 +121,7 @@
 
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}

diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 8b7baf5..e83bae6 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl

@@ -52,7 +52,7 @@
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
 set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
-	                 CH_DATA_WD=146 \
+	                 CH_DATA_WD=154 \
 			 "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
@@ -71,7 +71,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 300 1725"
+set ::env(DIE_AREA) "0 0 300 1800"
 
 #set ::env(GRT_OBS) "met4  0 0 300 1725"
 
@@ -101,25 +101,23 @@
 ## Placement
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
-
-set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 2
 set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
 
 ## Routing
 set ::env(GRT_ADJUSTMENT) 0.1
 set ::env(DPL_CELL_PADDING) 1
 
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
-set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
-
 set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
-set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
-
 set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
@@ -128,20 +126,16 @@
 set ::env(MAGIC_GENERATE_LEF) {1}
 set ::env(MAGIC_WRITE_FULL_LEF) {0}
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "1"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
-
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000"
-set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
-set ::env(PL_RESIZER_MAX_CAP_MARGIN) "5"
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 6.2
-set ::env(FP_PDN_HWIDTH) 6.2

diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 46750ad..7038097 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg

@@ -170,7 +170,17 @@
 m0_wbd_err_o        
 m0_wbd_cyc_i        
 
-ch_data_out\[145\]  225 0 2
+ch_data_in\[153\]  225 0 2
+ch_data_in\[152\]  
+ch_data_in\[151\]  
+ch_data_in\[150\]
+
+ch_data_in\[149\]  
+ch_data_in\[148\]  
+ch_data_in\[147\]  
+ch_data_in\[146\]
+  
+ch_data_out\[145\]
 ch_data_out\[144\]  
 ch_data_out\[143\]  
 ch_data_out\[142\]  
@@ -629,6 +639,16 @@
 ch_data_out\[25\] 
 ch_data_out\[24\] 
 
+ch_data_out\[153\]  1700 0 2
+ch_data_out\[152\]  
+ch_data_out\[151\]  
+ch_data_out\[150\]  
+
+ch_data_out\[149\]  
+ch_data_out\[148\]  
+ch_data_out\[147\]  
+ch_data_out\[146\]  
+
 #E
 ch_data_out\[19\]   0000 0  2  
 ch_data_out\[18\]

diff --git a/openlane/ycr2_iconnect/base.sdc b/openlane/ycr2_iconnect/base.sdc
index 2c9946e..fbe6f17 100644
--- a/openlane/ycr2_iconnect/base.sdc
+++ b/openlane/ycr2_iconnect/base.sdc

@@ -3,6 +3,9 @@
 ###############################################################################
 create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
 
+create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm clock0} [get_ports sram0_clk0]
+create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm clock1} [get_ports sram0_clk1]
+
 set_clock_transition 0.1500 [all_clocks]
 set_clock_uncertainty -setup 0.5000 [all_clocks]
 set_clock_uncertainty -hold 0.2500 [all_clocks]
@@ -12,11 +15,14 @@
 set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
 set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 
+set_case_analysis 0 [get_ports {cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_ports {cfg_sram_lphase[1]}]
+
 #CORE-0 IMEM Constraints
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
 
 set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
 set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
@@ -30,11 +36,11 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
 
 #CORE-0 DMEM Constraints
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
 
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
@@ -49,10 +55,10 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
 
 #CORE-1 IMEM Constraints
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
 
 set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
 set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
@@ -66,11 +72,11 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
 
 #CORE-1 DMEM Constraints
-set_input_delay  -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
-set_input_delay  -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
-set_input_delay  -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
-set_input_delay  -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
-set_input_delay  -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
+set_input_delay  -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay  -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
+set_input_delay  -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
+set_input_delay  -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
+set_input_delay  -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
 
 set_input_delay  -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
 set_input_delay  -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
@@ -84,6 +90,33 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
 
+## PORT-0 TCM I/F
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_din0[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_dout0[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_dout0[*]}]
+
+
+## PORT-1 TCM1 I/F
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_addr1[*]}]
+
+set_output_delay -max 1.000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_addr1[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_dout1[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_dout1[*]}]
+
 ###############################################################################
 # Environment
 ###############################################################################

diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl
index 57a5277..f7e8019 100644
--- a/openlane/ycr2_iconnect/config.tcl
+++ b/openlane/ycr2_iconnect/config.tcl

@@ -64,22 +64,25 @@
 set ::env(DIE_AREA) "0 0 390 1200"
 
 set ::env(PL_TARGET_DENSITY) 0.20
-#set ::env(CELL_PAD) 2
-#set ::env(GRT_ADJUSTMENT) {0.2}
+set ::env(CELL_PAD) 8
+set ::env(GRT_ADJUSTMENT) {0.2}
 
-#set ::env(GLB_RT_ADJUSTMENT) {0.2}
 
 #set ::env(PL_ROUTABILITY_DRIVEN) "1"
 set ::env(PL_TIME_DRIVEN) "1"
 
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
-set ::env(DIODE_INSERTION_STRATEGY) 4
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
+set ::env(DIODE_INSERTION_STRATEGY) 3
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}

diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg
index 83e0e23..7c607cd 100644
--- a/openlane/ycr2_iconnect/pin_order.cfg
+++ b/openlane/ycr2_iconnect/pin_order.cfg

@@ -1194,3 +1194,166 @@
 cpu_intf_rst_n
 cfg_bypass_icache
 cfg_bypass_dcache
+
+
+#N
+aes_dmem_req_ack
+aes_dmem_req
+aes_dmem_cmd
+aes_dmem_width\[1\]
+aes_dmem_width\[0\]
+aes_dmem_addr\[6\]
+aes_dmem_addr\[5\]
+aes_dmem_addr\[4\]
+aes_dmem_addr\[3\]
+aes_dmem_addr\[2\]
+aes_dmem_addr\[1\]
+aes_dmem_addr\[0\]
+aes_dmem_wdata\[31\]
+aes_dmem_wdata\[30\]
+aes_dmem_wdata\[29\]
+aes_dmem_wdata\[28\]
+aes_dmem_wdata\[27\]
+aes_dmem_wdata\[26\]
+aes_dmem_wdata\[25\]
+aes_dmem_wdata\[24\]
+aes_dmem_wdata\[23\]
+aes_dmem_wdata\[22\]
+aes_dmem_wdata\[21\]
+aes_dmem_wdata\[20\]
+aes_dmem_wdata\[19\]
+aes_dmem_wdata\[18\]
+aes_dmem_wdata\[17\]
+aes_dmem_wdata\[16\]
+aes_dmem_wdata\[15\]
+aes_dmem_wdata\[14\]
+aes_dmem_wdata\[13\]
+aes_dmem_wdata\[12\]
+aes_dmem_wdata\[11\]
+aes_dmem_wdata\[10\]
+aes_dmem_wdata\[9\]
+aes_dmem_wdata\[8\]
+aes_dmem_wdata\[7\]
+aes_dmem_wdata\[6\]
+aes_dmem_wdata\[5\]
+aes_dmem_wdata\[4\]
+aes_dmem_wdata\[3\]
+aes_dmem_wdata\[2\]
+aes_dmem_wdata\[1\]
+aes_dmem_wdata\[0\]
+aes_dmem_rdata\[31\]
+aes_dmem_rdata\[30\]
+aes_dmem_rdata\[29\]
+aes_dmem_rdata\[28\]
+aes_dmem_rdata\[27\]
+aes_dmem_rdata\[26\]
+aes_dmem_rdata\[25\]
+aes_dmem_rdata\[24\]
+aes_dmem_rdata\[23\]
+aes_dmem_rdata\[22\]
+aes_dmem_rdata\[21\]
+aes_dmem_rdata\[20\]
+aes_dmem_rdata\[19\]
+aes_dmem_rdata\[18\]
+aes_dmem_rdata\[17\]
+aes_dmem_rdata\[16\]
+aes_dmem_rdata\[15\]
+aes_dmem_rdata\[14\]
+aes_dmem_rdata\[13\]
+aes_dmem_rdata\[12\]
+aes_dmem_rdata\[11\]
+aes_dmem_rdata\[10\]
+aes_dmem_rdata\[9\]
+aes_dmem_rdata\[8\]
+aes_dmem_rdata\[7\]
+aes_dmem_rdata\[6\]
+aes_dmem_rdata\[5\]
+aes_dmem_rdata\[4\]
+aes_dmem_rdata\[3\]
+aes_dmem_rdata\[2\]
+aes_dmem_rdata\[1\]
+aes_dmem_rdata\[0\]
+aes_dmem_resp\[1\]
+aes_dmem_resp\[0\]
+
+
+
+fpu_dmem_req_ack 0200 0 2
+fpu_dmem_req
+fpu_dmem_cmd
+fpu_dmem_width\[1\]
+fpu_dmem_width\[0\]
+fpu_dmem_addr\[4\]
+fpu_dmem_addr\[3\]
+fpu_dmem_addr\[2\]
+fpu_dmem_addr\[1\]
+fpu_dmem_addr\[0\]
+fpu_dmem_wdata\[31\]
+fpu_dmem_wdata\[30\]
+fpu_dmem_wdata\[29\]
+fpu_dmem_wdata\[28\]
+fpu_dmem_wdata\[27\]
+fpu_dmem_wdata\[26\]
+fpu_dmem_wdata\[25\]
+fpu_dmem_wdata\[24\]
+fpu_dmem_wdata\[23\]
+fpu_dmem_wdata\[22\]
+fpu_dmem_wdata\[21\]
+fpu_dmem_wdata\[20\]
+fpu_dmem_wdata\[19\]
+fpu_dmem_wdata\[18\]
+fpu_dmem_wdata\[17\]
+fpu_dmem_wdata\[16\]
+fpu_dmem_wdata\[15\]
+fpu_dmem_wdata\[14\]
+fpu_dmem_wdata\[13\]
+fpu_dmem_wdata\[12\]
+fpu_dmem_wdata\[11\]
+fpu_dmem_wdata\[10\]
+fpu_dmem_wdata\[9\]
+fpu_dmem_wdata\[8\]
+fpu_dmem_wdata\[7\]
+fpu_dmem_wdata\[6\]
+fpu_dmem_wdata\[5\]
+fpu_dmem_wdata\[4\]
+fpu_dmem_wdata\[3\]
+fpu_dmem_wdata\[2\]
+fpu_dmem_wdata\[1\]
+fpu_dmem_wdata\[0\]
+fpu_dmem_rdata\[31\]
+fpu_dmem_rdata\[30\]
+fpu_dmem_rdata\[29\]
+fpu_dmem_rdata\[28\]
+fpu_dmem_rdata\[27\]
+fpu_dmem_rdata\[26\]
+fpu_dmem_rdata\[25\]
+fpu_dmem_rdata\[24\]
+fpu_dmem_rdata\[23\]
+fpu_dmem_rdata\[22\]
+fpu_dmem_rdata\[21\]
+fpu_dmem_rdata\[20\]
+fpu_dmem_rdata\[19\]
+fpu_dmem_rdata\[18\]
+fpu_dmem_rdata\[17\]
+fpu_dmem_rdata\[16\]
+fpu_dmem_rdata\[15\]
+fpu_dmem_rdata\[14\]
+fpu_dmem_rdata\[13\]
+fpu_dmem_rdata\[12\]
+fpu_dmem_rdata\[11\]
+fpu_dmem_rdata\[10\]
+fpu_dmem_rdata\[9\]
+fpu_dmem_rdata\[8\]
+fpu_dmem_rdata\[7\]
+fpu_dmem_rdata\[6\]
+fpu_dmem_rdata\[5\]
+fpu_dmem_rdata\[4\]
+fpu_dmem_rdata\[3\]
+fpu_dmem_rdata\[2\]
+fpu_dmem_rdata\[1\]
+fpu_dmem_rdata\[0\]
+fpu_dmem_resp\[1\]
+fpu_dmem_resp\[0\]
+
+
+

diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 873ac0a..679443f 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc

@@ -34,7 +34,7 @@
 #DMEM Constraints
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
 set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
-set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
 

diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index 4056ea0..406c103 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl

@@ -79,7 +79,7 @@
 set ::env(DIE_AREA) "0 0 540 950 "
 
 set ::env(PL_TARGET_DENSITY) 0.45
-set ::env(CELL_PAD) "8"
+#set ::env(CELL_PAD) "8"
 
 ## Routing
 set ::env(GRT_ADJUSTMENT) 0.2
@@ -92,7 +92,7 @@
 set ::env(DIODE_INSERTION_STRATEGY) 3
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
@@ -110,6 +110,10 @@
 
 #Need to cross-check why global timing opimization creating setup vio with hugh hold fix
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
 
 #PDN
 set ::env(FP_PDN_VPITCH) 100

diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index f8eb2c5..b03c508 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc

@@ -2,7 +2,6 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
-create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
 create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
 
 create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
@@ -21,18 +20,26 @@
 
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
- -group [get_clocks {rtc_clk}]\
  -group [get_clocks {wb_clk}] -comment {Async Clock group}
 
+# Set case analysis
+set_case_analysis  0 [get_ports {cfg_ccska[3]}]
+set_case_analysis  0 [get_ports {cfg_ccska[2]}]
+set_case_analysis  0 [get_ports {cfg_ccska[1]}]
+set_case_analysis  0 [get_ports {cfg_ccska[0]}]
+
+set_case_analysis  0 [get_ports {cfg_wcska[3]}]
+set_case_analysis  0 [get_ports {cfg_wcska[2]}]
+set_case_analysis  0 [get_ports {cfg_wcska[1]}]
+set_case_analysis  0 [get_ports {cfg_wcska[0]}]
+
 #Assumed config are static
 set_false_path -from  [get_ports {cfg_dcache_force_flush}]
 set_false_path -from  [get_ports {cfg_dcache_pfet_dis}]
 set_false_path -from  [get_ports {cfg_icache_ntag_pfet_dis}]
 set_false_path -from  [get_ports {cfg_icache_pfet_dis}]
-set_false_path -from  [get_ports {cfg_cska_riscv[3]}]
-set_false_path -from  [get_ports {cfg_cska_riscv[2]}]
-set_false_path -from  [get_ports {cfg_cska_riscv[1]}]
-set_false_path -from  [get_ports {cfg_cska_riscv[0]}]
+
+
 set_false_path -from  [get_ports {cfg_sram_lphase[1]}]
 set_false_path -from  [get_ports {cfg_sram_lphase[0]}]
 
@@ -51,19 +58,19 @@
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
 
 
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
 
 #Wishbone ICACHE I/F
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
@@ -102,17 +109,17 @@
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
 
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
 
 
 # Data memory interface from router to WB bridge
@@ -160,21 +167,21 @@
 
 
 ## ICACHE PORT-0 SRAM Memory I/F
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
 
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
 
 ## ICACHE PORT-1 SRAM Memory I/F
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
 set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
 set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
 
@@ -199,39 +206,39 @@
 set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
 set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
 
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
 
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
 
 ## DCACHE PORT-0 SRAM I/F
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
 
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
 
 set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
 set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
 
 
 ## DCACHE PORT-1 SRAM I/F
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
 
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
 
 set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
 set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]

diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 2d2308c..dad9eb7 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl

@@ -65,7 +65,8 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 set ::env(FP_SIZING) absolute
 set ::env(DIE_AREA) "0 0 810 640 "
-set ::env(CELL_PAD) "6"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) {0.2}
 
 set ::env(PL_TARGET_DENSITY) 0.37
 
@@ -78,7 +79,7 @@
 set ::env(DIODE_INSERTION_STRATEGY) 3
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}

diff --git a/verilog/rtl/pinmux/src/1 b/verilog/rtl/pinmux/src/1
deleted file mode 100644
index e69de29..0000000
--- a/verilog/rtl/pinmux/src/1
+++ /dev/null