aes and fpu integration
diff --git a/.gitmodules b/.gitmodules index 916c6dd..5426bcd 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -7,3 +7,9 @@ [submodule "verilog/dv/common/riscduino_board"] path = verilog/dv/common/riscduino_board url = https://github.com/dineshannayya/riscduino_board.git +[submodule "verilog/rtl/security_core"] + path = verilog/rtl/security_core + url = https://github.com/dineshannayya/security_core +[submodule "verilog/rtl/fpu"] + path = verilog/rtl/fpu + url = https://github.com/dineshannayya/fpu
diff --git a/openlane/digital_pll/base.sdc b/openlane/dg_pll/base.sdc similarity index 100% rename from openlane/digital_pll/base.sdc rename to openlane/dg_pll/base.sdc
diff --git a/openlane/digital_pll/config.tcl b/openlane/dg_pll/config.tcl similarity index 78% rename from openlane/digital_pll/config.tcl rename to openlane/dg_pll/config.tcl index 1cf0b69..ab632d6 100644 --- a/openlane/digital_pll/config.tcl +++ b/openlane/dg_pll/config.tcl
@@ -15,12 +15,12 @@ set script_dir [file dirname [file normalize [info script]]] -set ::env(DESIGN_NAME) digital_pll +set ::env(DESIGN_NAME) dg_pll set ::env(DESIGN_IS_CORE) 0 -set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/digital_pll.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/digital_pll_controller.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/ring_osc2x13.v" +set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/dg_pll.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/digital_pll_controller.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/ring_osc2x13.v" set ::env(CLOCK_PORT) "" set ::env(CLOCK_TREE_SYNTH) 0 @@ -40,29 +40,44 @@ set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 100 90" +set ::env(DIE_AREA) "0 0 90 100" +set ::env(GRT_OBS) "met4 0 0 90 100" + #set ::env(TOP_MARGIN_MULT) 2 #set ::env(BOTTOM_MARGIN_MULT) 2 #LVS Issue - DEF Base looks to having issue -#set ::env(MAGIC_EXT_USE_GDS) {1} +set ::env(MAGIC_EXT_USE_GDS) {1} + set ::env(CELL_PAD) 0 ## PDN set ::env(FP_PDN_VPITCH) 40 set ::env(FP_PDN_HPITCH) 40 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2 +set ::env(FP_PDN_VOFFSET) "5" +set ::env(FP_PDN_HOFFSET) "5" +set ::env(FP_PDN_HSPACING) {13.8} +set ::env(FP_PDN_VSPACING) {13.8} +set ::env(FP_PDN_HORIZONTAL_HALO) "10" +set ::env(FP_PDN_VERTICAL_HALO) "10" ## Placement set ::env(PL_TARGET_DENSITY) 0.82 -## Routing -#set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0 -#set ::env(GLB_RT_ADJUSTMENT) 0 -set ::env(GLB_RT_MINLAYER) 2 -set ::env(GLB_RT_MAXLAYER) 6 +## Routing + +#set ::env(GLB_RT_MAXLAYER) 5 +set ::env(RT_MAX_LAYER) {met4} + +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 @@ -76,11 +91,4 @@ ## Diode Insertion #set ::env(DIODE_INSERTION_STRATEGY) "4" -set ::env(FP_PDN_VOFFSET) "5" -set ::env(FP_PDN_VPITCH) "40" -set ::env(FP_PDN_HOFFSET) "5" -set ::env(FP_PDN_HPITCH) "40" -set ::env(FP_PDN_HWIDTH) {6.2} -set ::env(FP_PDN_VWIDTH) {6.2} -set ::env(FP_PDN_HSPACING) {15} -set ::env(FP_PDN_VSPACING) {15} +
diff --git a/openlane/digital_pll/interactive.tcl b/openlane/dg_pll/interactive.tcl similarity index 99% rename from openlane/digital_pll/interactive.tcl rename to openlane/dg_pll/interactive.tcl index cfc6830..32e355e 100755 --- a/openlane/digital_pll/interactive.tcl +++ b/openlane/dg_pll/interactive.tcl
@@ -373,7 +373,7 @@ } set LVS_ENABLED 1 - set DRC_ENABLED 0 + set DRC_ENABLED 1 set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
diff --git a/openlane/digital_pll/macro.cfg b/openlane/dg_pll/macro.cfg similarity index 100% rename from openlane/digital_pll/macro.cfg rename to openlane/dg_pll/macro.cfg
diff --git a/openlane/digital_pll/pin_order.cfg b/openlane/dg_pll/pin_order.cfg similarity index 100% rename from openlane/digital_pll/pin_order.cfg rename to openlane/dg_pll/pin_order.cfg
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl index 9326c1a..414f142 100755 --- a/openlane/pinmux_top/config.tcl +++ b/openlane/pinmux_top/config.tcl
@@ -64,6 +64,7 @@ $::env(DESIGN_DIR)/../../verilog/rtl/ws281x/src/ws281x_reg.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/strap_ctrl.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_rst_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/dig2ana/src/dig2ana_reg.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \ @@ -92,7 +93,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 500 850" +set ::env(DIE_AREA) "0 0 520 850" # If you're going to use multiple power domains, then keep this disabled. @@ -102,7 +103,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.37" +set ::env(PL_TARGET_DENSITY) "0.38" set ::env(CELL_PAD) "8" #set ::env(GRT_ADJUSTMENT) {0.2} @@ -131,7 +132,10 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 + +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg index 25515be..a8e15ef 100644 --- a/openlane/pinmux_top/pin_order.cfg +++ b/openlane/pinmux_top/pin_order.cfg
@@ -2,7 +2,9 @@ #MANUAL_PLACE #S -cpu_core_rst_n\[1\] 000 0 2 +cpu_core_rst_n\[3\] 000 0 2 +cpu_core_rst_n\[2\] +cpu_core_rst_n\[1\] cpu_core_rst_n\[0\] cpu_intf_rst_n qspim_rst_n @@ -62,82 +64,13 @@ spis_miso spis_mosi -cfg_strap_pad_ctrl 0100 0 4 -user_clock1 +user_clock1 0100 0 4 user_clock2 int_pll_clock xtal_clk -e_reset_n -p_reset_n s_reset_n rtc_clk usb_clk -strap_uartm\[1\] -strap_uartm\[0\] -strap_sticky\[31\] -strap_sticky\[30\] -strap_sticky\[29\] -strap_sticky\[28\] -strap_sticky\[27\] -strap_sticky\[26\] -strap_sticky\[25\] -strap_sticky\[24\] -strap_sticky\[23\] -strap_sticky\[22\] -strap_sticky\[21\] -strap_sticky\[20\] -strap_sticky\[19\] -strap_sticky\[18\] -strap_sticky\[17\] -strap_sticky\[16\] -strap_sticky\[15\] -strap_sticky\[14\] -strap_sticky\[13\] -strap_sticky\[12\] -strap_sticky\[11\] -strap_sticky\[10\] -strap_sticky\[9\] -strap_sticky\[8\] -strap_sticky\[7\] -strap_sticky\[6\] -strap_sticky\[5\] -strap_sticky\[4\] -strap_sticky\[3\] -strap_sticky\[2\] -strap_sticky\[1\] -strap_sticky\[0\] -system_strap\[31\] -system_strap\[30\] -system_strap\[29\] -system_strap\[28\] -system_strap\[27\] -system_strap\[26\] -system_strap\[25\] -system_strap\[24\] -system_strap\[23\] -system_strap\[22\] -system_strap\[21\] -system_strap\[20\] -system_strap\[19\] -system_strap\[18\] -system_strap\[17\] -system_strap\[16\] -system_strap\[15\] -system_strap\[14\] -system_strap\[13\] -system_strap\[12\] -system_strap\[11\] -system_strap\[10\] -system_strap\[9\] -system_strap\[8\] -system_strap\[7\] -system_strap\[6\] -system_strap\[5\] -system_strap\[4\] -system_strap\[3\] -system_strap\[2\] -system_strap\[1\] -system_strap\[0\] pinmux_debug\[0\] 0300 0 2 pinmux_debug\[1\] @@ -174,8 +107,80 @@ cpu_clk #W +strap_sticky\[31\] 000 0 2 +strap_sticky\[30\] +strap_sticky\[29\] +strap_sticky\[28\] +strap_sticky\[27\] +strap_sticky\[26\] +strap_sticky\[25\] +strap_sticky\[24\] +strap_sticky\[23\] +strap_sticky\[22\] +strap_sticky\[21\] +strap_sticky\[20\] +strap_sticky\[19\] +strap_sticky\[18\] +strap_sticky\[17\] +strap_sticky\[16\] +strap_sticky\[15\] +strap_sticky\[14\] +strap_sticky\[13\] +strap_sticky\[12\] +strap_sticky\[11\] +strap_sticky\[10\] +strap_sticky\[9\] +strap_sticky\[8\] +strap_sticky\[7\] +strap_sticky\[6\] +strap_sticky\[5\] +strap_sticky\[4\] +strap_sticky\[3\] +strap_sticky\[2\] +strap_sticky\[1\] +strap_sticky\[0\] -soft_irq +strap_uartm\[1\] +strap_uartm\[0\] + +system_strap\[31\] +system_strap\[30\] +system_strap\[29\] +system_strap\[28\] +system_strap\[27\] +system_strap\[26\] +system_strap\[25\] +system_strap\[24\] +system_strap\[23\] +system_strap\[22\] +system_strap\[21\] +system_strap\[20\] +system_strap\[19\] +system_strap\[18\] +system_strap\[17\] +system_strap\[16\] +system_strap\[15\] +system_strap\[14\] +system_strap\[13\] +system_strap\[12\] +system_strap\[11\] +system_strap\[10\] +system_strap\[9\] +system_strap\[8\] +system_strap\[7\] +system_strap\[6\] +system_strap\[5\] +system_strap\[4\] +system_strap\[3\] +system_strap\[2\] +system_strap\[1\] +system_strap\[0\] + +p_reset_n +e_reset_n +cfg_strap_pad_ctrl + +soft_irq 200 0 2 irq_lines\[31\] irq_lines\[30\] irq_lines\[29\] @@ -219,7 +224,7 @@ -reg_cs 200 0 +reg_cs 260 0 2 reg_wr reg_addr\[9\] reg_addr\[8\] @@ -303,7 +308,44 @@ #N -digital_io_oen\[37\] 000 0 4 + +cfg_dac3_mux_sel\[7\] +cfg_dac3_mux_sel\[6\] +cfg_dac3_mux_sel\[5\] +cfg_dac3_mux_sel\[4\] +cfg_dac3_mux_sel\[3\] +cfg_dac3_mux_sel\[2\] +cfg_dac3_mux_sel\[1\] +cfg_dac3_mux_sel\[0\] + +cfg_dac2_mux_sel\[7\] +cfg_dac2_mux_sel\[6\] +cfg_dac2_mux_sel\[5\] +cfg_dac2_mux_sel\[4\] +cfg_dac2_mux_sel\[3\] +cfg_dac2_mux_sel\[2\] +cfg_dac2_mux_sel\[1\] +cfg_dac2_mux_sel\[0\] + +cfg_dac1_mux_sel\[7\] +cfg_dac1_mux_sel\[6\] +cfg_dac1_mux_sel\[5\] +cfg_dac1_mux_sel\[4\] +cfg_dac1_mux_sel\[3\] +cfg_dac1_mux_sel\[2\] +cfg_dac1_mux_sel\[1\] +cfg_dac1_mux_sel\[0\] + +cfg_dac0_mux_sel\[7\] +cfg_dac0_mux_sel\[6\] +cfg_dac0_mux_sel\[5\] +cfg_dac0_mux_sel\[4\] +cfg_dac0_mux_sel\[3\] +cfg_dac0_mux_sel\[2\] +cfg_dac0_mux_sel\[1\] +cfg_dac0_mux_sel\[0\] + +digital_io_oen\[37\] 100 0 4 digital_io_out\[37\] digital_io_in\[37\] digital_io_oen\[36\]
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl index c376278..9c49d24 100755 --- a/openlane/qspim_top/config.tcl +++ b/openlane/qspim_top/config.tcl
@@ -73,6 +73,9 @@ set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 450 550" +#set ::env(GRT_OBS) " \ +# met4 0 0 450 550" + set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.42" @@ -95,6 +98,11 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} + +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg index 9f93b81..c078759 100644 --- a/openlane/qspim_top/pin_order.cfg +++ b/openlane/qspim_top/pin_order.cfg
@@ -55,7 +55,7 @@ #W -cfg_cska_sp_co\[3\] 0000 0 2 +cfg_cska_sp_co\[3\] 0200 0 2 cfg_cska_sp_co\[2\] cfg_cska_sp_co\[1\] cfg_cska_sp_co\[0\] @@ -67,7 +67,7 @@ wbd_clk_spi mclk -wbd_stb_i 0100 0 2 +wbd_stb_i 0300 0 2 wbd_we_i wbd_adr_i\[31\] wbd_adr_i\[30\]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 9870805..7576c81 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -118,6 +118,11 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} + +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg index aba1684..2801070 100644 --- a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg +++ b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
@@ -2,7 +2,7 @@ #MANUAL_PLACE #W -cfg_cska_uart\[3\] 0000 0 2 +cfg_cska_uart\[3\] 0200 0 2 cfg_cska_uart\[2\] cfg_cska_uart\[1\] cfg_cska_uart\[0\] @@ -10,7 +10,7 @@ wbd_clk_uart app_clk -reg_cs 0100 0 2 +reg_cs 0300 0 2 reg_wr reg_addr\[8\] reg_addr\[7\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 1c58278..dc103e6 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -69,13 +69,14 @@ $::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \ $::env(DESIGN_DIR)/../../verilog/gl/pinmux_top.v \ $::env(DESIGN_DIR)/../../verilog/gl/uart_i2c_usb_spi_top.v \ - $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \ - $::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \ - $::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \ - $::env(DESIGN_DIR)/../../verilog/gl/ycr2_iconnect.v \ - $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \ - $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ - " + $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \ + $::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \ + $::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \ + $::env(DESIGN_DIR)/../../verilog/gl/ycr2_iconnect.v \ + $::env(DESIGN_DIR)/../../verilog/gl/dg_pll.v \ + $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ + $::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \ + " set ::env(EXTRA_LEFS) "\ $lef_root/qspim_top.lef \ @@ -86,8 +87,9 @@ $lef_root/ycr_intf.lef \ $lef_root/ycr_core_top.lef \ $lef_root/ycr2_iconnect.lef \ - $lef_root/digital_pll.lef \ + $lef_root/dg_pll.lef \ $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ + $lef_root/dac_top.lef \ " set ::env(EXTRA_GDS_FILES) "\ @@ -99,8 +101,9 @@ $gds_root/ycr_intf.gds \ $gds_root/ycr_core_top.gds \ $gds_root/ycr2_iconnect.gds \ - $gds_root/digital_pll.gds \ - $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds " + $gds_root/dg_pll.gds \ + $gds_root/dac_top.gds \ + " set ::env(SYNTH_DEFINES) [list SYNTHESIS ] @@ -120,13 +123,13 @@ set ::env(FP_PDN_HORIZONTAL_HALO) "10" set ::env(FP_PDN_VERTICAL_HALO) "10" set ::env(FP_PDN_VOFFSET) "5" -set ::env(FP_PDN_VPITCH) "60" +set ::env(FP_PDN_VPITCH) "80" set ::env(FP_PDN_HOFFSET) "5" -set ::env(FP_PDN_HPITCH) "60" +set ::env(FP_PDN_HPITCH) "80" set ::env(FP_PDN_HWIDTH) {6.2} set ::env(FP_PDN_VWIDTH) {6.2} -set ::env(FP_PDN_HSPACING) {20} -set ::env(FP_PDN_VSPACING) {20} +set ::env(FP_PDN_HSPACING) {13.8} +set ::env(FP_PDN_VSPACING) {13.8} set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2} @@ -135,6 +138,7 @@ set ::env(VDD_PIN) {vccd1} set ::env(GND_PIN) {vssd1} +set ::env(PDN_STRIPE) {vccd1 vdda1 vssd1 vssa1} set ::env(DRT_OPT_ITERS) {32} set ::env(GRT_OBS) " \ @@ -167,7 +171,8 @@ u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1, \ u_riscv_top.i_core_top_1 vccd1 vssd1 vccd1 vssd1, \ u_riscv_top.u_connect vccd1 vssd1 VPWR VGND, \ - u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1 \ + u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1, \ + u_4x8bit_dac vdda1 vssa1 vccd1 vssd1 "
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index ea07b10..47411c8 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,7 +1,8 @@ -u_qspi_master 2250 650 N -u_uart_i2c_usb_spi 2250 1350 N -u_pinmux 2250 2250 N -u_pll 2500 3148 N +u_4x8bit_dac 1850 2500 N +u_qspi_master 2250 450 N +u_uart_i2c_usb_spi 2250 1100 N +u_pinmux 2250 2000 N +u_pll 2500 3028 N u_riscv_top.i_core_top_0 75 1400 N u_riscv_top.i_core_top_1 1200 1400 FN
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl index c1e213d..b2a2b42 100644 --- a/openlane/user_project_wrapper/pdn_cfg.tcl +++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -93,7 +93,7 @@ -pitch $::env(FP_PDN_VPITCH) \ -offset $::env(FP_PDN_VOFFSET) \ -spacing $::env(FP_PDN_VSPACING) \ - -nets "$::env(VDD_NET) $::env(GND_NET)" \ + -nets "$::env(PDN_STRIPE)" \ -starts_with POWER -extend_to_core_ring add_pdn_stripe \ @@ -103,7 +103,7 @@ -pitch $::env(FP_PDN_HPITCH) \ -offset $::env(FP_PDN_HOFFSET) \ -spacing $::env(FP_PDN_HSPACING) \ - -nets "$::env(VDD_NET) $::env(GND_NET)" \ + -nets "$::env(PDN_STRIPE)" \ -starts_with POWER -extend_to_core_ring add_pdn_connect \
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index f2b9028..407a338 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -85,8 +85,10 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 450 425" +set ::env(DIE_AREA) "0 0 400 425" +set ::env(GRT_OBS) " \ + met4 0 0 400 425" # If you're going to use multiple power domains, then keep this disabled. set ::env(RUN_CVC) 0 @@ -111,6 +113,10 @@ set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg index 26c9f8e..8c93e59 100644 --- a/openlane/wb_host/pin_order.cfg +++ b/openlane/wb_host/pin_order.cfg
@@ -158,51 +158,89 @@ #N -wbd_int_rst_n 0100 0 2 -cfg_clk_ctrl1\[31\] -cfg_clk_ctrl1\[30\] -cfg_clk_ctrl1\[29\] -cfg_clk_ctrl1\[28\] -cfg_clk_ctrl1\[27\] -cfg_clk_ctrl1\[26\] -cfg_clk_ctrl1\[25\] -cfg_clk_ctrl1\[24\] -cfg_clk_ctrl1\[23\] -cfg_clk_ctrl1\[22\] -cfg_clk_ctrl1\[21\] -cfg_clk_ctrl1\[20\] -cfg_clk_ctrl1\[19\] -cfg_clk_ctrl1\[18\] -cfg_clk_ctrl1\[17\] -cfg_clk_ctrl1\[16\] -cfg_clk_ctrl1\[15\] -cfg_clk_ctrl1\[14\] -cfg_clk_ctrl1\[13\] -cfg_clk_ctrl1\[12\] -cfg_clk_ctrl1\[11\] -cfg_clk_ctrl1\[10\] -cfg_clk_ctrl1\[9\] -cfg_clk_ctrl1\[8\] -cfg_clk_ctrl1\[3\] -cfg_clk_ctrl1\[2\] -cfg_clk_ctrl1\[1\] -cfg_clk_ctrl1\[0\] +cfg_clk_skew_ctrl2\[31\] 0000 0 2 +cfg_clk_skew_ctrl2\[30\] +cfg_clk_skew_ctrl2\[29\] +cfg_clk_skew_ctrl2\[28\] +cfg_clk_skew_ctrl2\[27\] +cfg_clk_skew_ctrl2\[26\] +cfg_clk_skew_ctrl2\[25\] +cfg_clk_skew_ctrl2\[24\] + +cfg_clk_skew_ctrl1\[31\] +cfg_clk_skew_ctrl1\[30\] +cfg_clk_skew_ctrl1\[29\] +cfg_clk_skew_ctrl1\[28\] + +cfg_clk_skew_ctrl1\[7\] +cfg_cska_wh\[3\] +cfg_clk_skew_ctrl1\[6\] +cfg_cska_wh\[2\] +cfg_clk_skew_ctrl1\[5\] +cfg_cska_wh\[1\] +cfg_clk_skew_ctrl1\[4\] +cfg_cska_wh\[0\] + +wbd_int_rst_n 0100 0 2 +cfg_clk_skew_ctrl2\[23\] +cfg_clk_skew_ctrl2\[22\] +cfg_clk_skew_ctrl2\[21\] +cfg_clk_skew_ctrl2\[20\] +cfg_clk_skew_ctrl2\[19\] +cfg_clk_skew_ctrl2\[18\] +cfg_clk_skew_ctrl2\[17\] +cfg_clk_skew_ctrl2\[16\] +cfg_clk_skew_ctrl2\[15\] +cfg_clk_skew_ctrl2\[14\] +cfg_clk_skew_ctrl2\[13\] +cfg_clk_skew_ctrl2\[12\] +cfg_clk_skew_ctrl2\[11\] +cfg_clk_skew_ctrl2\[10\] +cfg_clk_skew_ctrl2\[9\] +cfg_clk_skew_ctrl2\[8\] +cfg_clk_skew_ctrl2\[7\] +cfg_clk_skew_ctrl2\[6\] +cfg_clk_skew_ctrl2\[5\] +cfg_clk_skew_ctrl2\[4\] +cfg_clk_skew_ctrl2\[3\] +cfg_clk_skew_ctrl2\[2\] +cfg_clk_skew_ctrl2\[1\] +cfg_clk_skew_ctrl2\[0\] + +cfg_clk_skew_ctrl1\[27\] +cfg_clk_skew_ctrl1\[26\] +cfg_clk_skew_ctrl1\[25\] +cfg_clk_skew_ctrl1\[24\] +cfg_clk_skew_ctrl1\[23\] +cfg_clk_skew_ctrl1\[22\] +cfg_clk_skew_ctrl1\[21\] +cfg_clk_skew_ctrl1\[20\] +cfg_clk_skew_ctrl1\[19\] +cfg_clk_skew_ctrl1\[18\] +cfg_clk_skew_ctrl1\[17\] +cfg_clk_skew_ctrl1\[16\] +cfg_clk_skew_ctrl1\[15\] +cfg_clk_skew_ctrl1\[14\] +cfg_clk_skew_ctrl1\[13\] +cfg_clk_skew_ctrl1\[12\] +cfg_clk_skew_ctrl1\[11\] +cfg_clk_skew_ctrl1\[10\] +cfg_clk_skew_ctrl1\[9\] +cfg_clk_skew_ctrl1\[8\] + +cfg_clk_skew_ctrl1\[3\] +cfg_clk_skew_ctrl1\[2\] +cfg_clk_skew_ctrl1\[1\] +cfg_clk_skew_ctrl1\[0\] + wbd_clk_int wbs_clk_out wbs_clk_i wbd_clk_wh -cfg_clk_ctrl1\[7\] -cfg_cska_wh\[3\] -cfg_clk_ctrl1\[6\] -cfg_cska_wh\[2\] -cfg_clk_ctrl1\[5\] -cfg_cska_wh\[1\] -cfg_clk_ctrl1\[4\] -cfg_cska_wh\[0\] -wbs_stb_o 160 0 2 +wbs_stb_o 200 0 2 wbs_we_o wbs_adr_o\[31\] wbs_adr_o\[30\] @@ -309,15 +347,7 @@ wbs_cyc_o -cfg_strap_pad_ctrl -e_reset_n -int_pll_clock -p_reset_n -s_reset_n -xtal_clk -strap_uartm\[1\] -strap_uartm\[0\] -strap_sticky\[31\] +strap_sticky\[31\] 325 0 2 strap_sticky\[30\] strap_sticky\[29\] strap_sticky\[28\] @@ -349,6 +379,10 @@ strap_sticky\[2\] strap_sticky\[1\] strap_sticky\[0\] + +strap_uartm\[1\] +strap_uartm\[0\] + system_strap\[31\] system_strap\[30\] system_strap\[29\] @@ -381,3 +415,11 @@ system_strap\[2\] system_strap\[1\] system_strap\[0\] + +cfg_strap_pad_ctrl +e_reset_n +p_reset_n + +int_pll_clock +xtal_clk +s_reset_n
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 58b9acb..8b7baf5 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -52,7 +52,7 @@ set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\ - CH_DATA_WD=53 \ + CH_DATA_WD=146 \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 @@ -73,6 +73,7 @@ set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 300 1725" +#set ::env(GRT_OBS) "met4 0 0 300 1725" # If you're going to use multiple power domains, then keep this disabled. set ::env(RUN_CVC) 0 @@ -123,6 +124,10 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} +#Lef +set ::env(MAGIC_GENERATE_LEF) {1} +set ::env(MAGIC_WRITE_FULL_LEF) {0} + set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 93ca457..46750ad 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -4,6 +4,30 @@ #S rst_n 000 0 2 +ch_data_in\[43\] +ch_data_in\[42\] +ch_data_in\[41\] +ch_data_in\[40\] +ch_data_in\[39\] +ch_data_in\[38\] +ch_data_in\[37\] +ch_data_in\[36\] +ch_data_in\[35\] +ch_data_in\[34\] +ch_data_in\[33\] +ch_data_in\[32\] +ch_data_in\[31\] +ch_data_in\[30\] +ch_data_in\[29\] +ch_data_in\[28\] +ch_data_in\[27\] +ch_data_in\[26\] +ch_data_in\[25\] +ch_data_in\[24\] +ch_data_in\[23\] +ch_data_in\[22\] +ch_data_in\[21\] +ch_data_in\[20\] ch_data_in\[19\] ch_data_in\[18\] ch_data_in\[17\] @@ -24,10 +48,12 @@ ch_data_in\[2\] ch_data_in\[1\] ch_data_in\[0\] + cfg_cska_wi\[3\] cfg_cska_wi\[2\] cfg_cska_wi\[1\] cfg_cska_wi\[0\] + ch_clk_in\[3\] ch_clk_in\[2\] ch_clk_in\[1\] @@ -37,7 +63,7 @@ clk_i -m0_wbd_stb_i 060 0 2 +m0_wbd_stb_i 100 0 2 m0_wbd_we_i m0_wbd_adr_i\[31\] m0_wbd_adr_i\[30\] @@ -144,44 +170,88 @@ m0_wbd_err_o m0_wbd_cyc_i +ch_data_out\[145\] 225 0 2 +ch_data_out\[144\] +ch_data_out\[143\] +ch_data_out\[142\] +ch_data_out\[141\] +ch_data_out\[140\] +ch_data_out\[139\] +ch_data_out\[138\] +ch_data_out\[137\] +ch_data_out\[136\] +ch_data_out\[135\] +ch_data_out\[134\] +ch_data_out\[133\] +ch_data_out\[132\] +ch_data_out\[131\] +ch_data_out\[130\] +ch_data_out\[129\] +ch_data_out\[128\] +ch_data_out\[127\] +ch_data_out\[126\] +ch_data_out\[125\] +ch_data_out\[124\] +ch_data_out\[123\] +ch_data_out\[122\] +ch_data_out\[121\] +ch_data_out\[120\] +ch_data_out\[119\] +ch_data_out\[118\] +ch_data_out\[117\] +ch_data_out\[116\] +ch_data_out\[115\] +ch_data_out\[114\] + +ch_data_out\[113\] +ch_data_out\[112\] + +ch_data_in\[111\] +ch_data_in\[110\] +ch_data_in\[109\] +ch_data_in\[108\] +ch_data_in\[107\] +ch_data_in\[106\] +ch_data_in\[105\] +ch_data_in\[104\] +ch_data_in\[103\] +ch_data_in\[102\] +ch_data_in\[101\] +ch_data_in\[100\] +ch_data_in\[99\] +ch_data_in\[98\] +ch_data_in\[97\] +ch_data_in\[96\] +ch_data_in\[95\] +ch_data_in\[94\] +ch_data_in\[93\] +ch_data_in\[92\] +ch_data_in\[91\] +ch_data_in\[90\] +ch_data_in\[89\] +ch_data_in\[88\] +ch_data_in\[87\] +ch_data_in\[86\] +ch_data_in\[85\] +ch_data_in\[84\] +ch_data_in\[83\] +ch_data_in\[82\] +ch_data_in\[81\] +ch_data_in\[80\] + +ch_data_in\[79\] +ch_data_in\[78\] +ch_data_in\[77\] + #W -ch_data_out\[52\] 000 0 2 -ch_data_out\[51\] -ch_data_out\[50\] -ch_data_out\[49\] -ch_data_out\[48\] -ch_data_out\[47\] -ch_data_out\[46\] -ch_data_out\[45\] -ch_data_out\[44\] -ch_data_out\[43\] -ch_data_out\[42\] -ch_data_out\[41\] -ch_data_out\[40\] -ch_data_out\[39\] -ch_data_out\[38\] -ch_data_out\[37\] -ch_data_out\[36\] -ch_data_out\[35\] -ch_data_out\[34\] -ch_data_out\[33\] -ch_data_out\[32\] -ch_data_out\[31\] -ch_data_out\[30\] -ch_data_out\[29\] -ch_data_out\[28\] -ch_data_out\[27\] -ch_data_out\[26\] -ch_data_out\[25\] -ch_data_out\[24\] -ch_data_out\[23\] +ch_data_out\[23\] 000 0 2 ch_data_out\[22\] ch_data_out\[21\] ch_data_out\[20\] -ch_data_out\[3\] +ch_data_out\[3\] 050 0 2 ch_data_out\[2\] ch_data_out\[1\] ch_data_out\[0\] @@ -189,6 +259,7 @@ ch_clk_out\[0\] m1_wbd_stb_i 100 0 2 +m1_wbd_cyc_i m1_wbd_we_i m1_wbd_adr_i\[31\] m1_wbd_adr_i\[30\] @@ -294,12 +365,12 @@ m1_wbd_dat_o\[2\] m1_wbd_dat_o\[1\] m1_wbd_dat_o\[0\] -m1_wbd_ack_o m1_wbd_lack_o +m1_wbd_ack_o m1_wbd_err_o -m1_wbd_cyc_i m2_wbd_stb_i 300 0 2 +m2_wbd_cyc_i m2_wbd_we_i m2_wbd_adr_i\[31\] m2_wbd_adr_i\[30\] @@ -415,9 +486,9 @@ m2_wbd_ack_o m2_wbd_lack_o m2_wbd_err_o -m2_wbd_cyc_i m3_wbd_stb_i 500 0 2 +m3_wbd_cyc_i m3_wbd_we_i m3_wbd_adr_i\[31\] m3_wbd_adr_i\[30\] @@ -501,8 +572,62 @@ m3_wbd_ack_o m3_wbd_lack_o m3_wbd_err_o -m3_wbd_cyc_i +ch_data_out\[43\] 650 0 2 +ch_data_out\[42\] +ch_data_out\[41\] +ch_data_out\[40\] +ch_data_out\[39\] +ch_data_out\[38\] +ch_data_out\[37\] +ch_data_out\[36\] +ch_data_out\[35\] +ch_data_out\[34\] +ch_data_out\[33\] +ch_data_out\[32\] +ch_data_out\[31\] +ch_data_out\[30\] +ch_data_out\[29\] +ch_data_out\[28\] + +ch_data_out\[76\] 1600 0 2 +ch_data_out\[75\] +ch_data_out\[74\] +ch_data_out\[73\] +ch_data_out\[72\] +ch_data_out\[71\] +ch_data_out\[70\] +ch_data_out\[69\] +ch_data_out\[68\] +ch_data_out\[67\] +ch_data_out\[66\] +ch_data_out\[65\] +ch_data_out\[64\] +ch_data_out\[63\] +ch_data_out\[62\] +ch_data_out\[61\] +ch_data_out\[60\] +ch_data_out\[59\] +ch_data_out\[58\] +ch_data_out\[57\] +ch_data_out\[56\] +ch_data_out\[55\] +ch_data_out\[54\] +ch_data_out\[53\] +ch_data_out\[52\] +ch_data_out\[51\] +ch_data_out\[50\] +ch_data_out\[49\] +ch_data_out\[48\] +ch_data_out\[47\] +ch_data_out\[46\] +ch_data_out\[45\] +ch_data_out\[44\] + +ch_data_out\[27\] +ch_data_out\[26\] +ch_data_out\[25\] +ch_data_out\[24\] #E ch_data_out\[19\] 0000 0 2 @@ -633,13 +758,13 @@ s0_wbd_cyc_o -ch_data_out\[11\] 0700 0 2 +ch_data_out\[11\] 0650 0 2 ch_data_out\[10\] ch_data_out\[9\] ch_data_out\[8\] ch_clk_out\[2\] -s1_wbd_stb_o 0800 0 2 +s1_wbd_stb_o 0750 0 2 s1_wbd_we_o s1_wbd_adr_o\[8\] s1_wbd_adr_o\[7\] @@ -721,7 +846,106 @@ s1_wbd_ack_i s1_wbd_cyc_o -ch_data_in\[52\] 1500 0 2 + +ch_data_in\[145\] 1350 0 2 +ch_data_in\[144\] +ch_data_in\[143\] +ch_data_in\[142\] +ch_data_in\[141\] +ch_data_in\[140\] +ch_data_in\[139\] +ch_data_in\[138\] +ch_data_in\[137\] +ch_data_in\[136\] +ch_data_in\[135\] +ch_data_in\[134\] +ch_data_in\[133\] +ch_data_in\[132\] +ch_data_in\[131\] +ch_data_in\[130\] +ch_data_in\[129\] +ch_data_in\[128\] +ch_data_in\[127\] +ch_data_in\[126\] +ch_data_in\[125\] +ch_data_in\[124\] +ch_data_in\[123\] +ch_data_in\[122\] +ch_data_in\[121\] +ch_data_in\[120\] +ch_data_in\[119\] +ch_data_in\[118\] +ch_data_in\[117\] +ch_data_in\[116\] +ch_data_in\[115\] +ch_data_in\[114\] + +ch_data_in\[113\] +ch_data_in\[112\] + + +ch_data_out\[111\] +ch_data_out\[110\] +ch_data_out\[109\] +ch_data_out\[108\] +ch_data_out\[107\] +ch_data_out\[106\] +ch_data_out\[105\] +ch_data_out\[104\] +ch_data_out\[103\] +ch_data_out\[102\] +ch_data_out\[101\] +ch_data_out\[100\] +ch_data_out\[99\] +ch_data_out\[98\] +ch_data_out\[97\] +ch_data_out\[96\] +ch_data_out\[95\] +ch_data_out\[94\] +ch_data_out\[93\] +ch_data_out\[92\] +ch_data_out\[91\] +ch_data_out\[90\] +ch_data_out\[89\] +ch_data_out\[88\] +ch_data_out\[87\] +ch_data_out\[86\] +ch_data_out\[85\] +ch_data_out\[84\] +ch_data_out\[83\] +ch_data_out\[82\] +ch_data_out\[81\] +ch_data_out\[80\] + +ch_data_out\[79\] +ch_data_out\[78\] +ch_data_out\[77\] + +ch_data_in\[76\] 1550 0 2 +ch_data_in\[75\] +ch_data_in\[74\] +ch_data_in\[73\] +ch_data_in\[72\] +ch_data_in\[71\] +ch_data_in\[70\] +ch_data_in\[69\] +ch_data_in\[68\] +ch_data_in\[67\] +ch_data_in\[66\] +ch_data_in\[65\] +ch_data_in\[64\] +ch_data_in\[63\] +ch_data_in\[62\] +ch_data_in\[61\] +ch_data_in\[60\] +ch_data_in\[59\] +ch_data_in\[58\] +ch_data_in\[57\] +ch_data_in\[56\] +ch_data_in\[55\] +ch_data_in\[54\] +ch_data_in\[53\] +ch_data_in\[52\] ch_data_in\[51\] ch_data_in\[50\] ch_data_in\[49\] @@ -730,30 +954,6 @@ ch_data_in\[46\] ch_data_in\[45\] ch_data_in\[44\] -ch_data_in\[43\] -ch_data_in\[42\] -ch_data_in\[41\] -ch_data_in\[40\] -ch_data_in\[39\] -ch_data_in\[38\] -ch_data_in\[37\] -ch_data_in\[36\] -ch_data_in\[35\] -ch_data_in\[34\] -ch_data_in\[33\] -ch_data_in\[32\] -ch_data_in\[31\] -ch_data_in\[30\] -ch_data_in\[29\] -ch_data_in\[28\] -ch_data_in\[27\] -ch_data_in\[26\] -ch_data_in\[25\] -ch_data_in\[24\] -ch_data_in\[23\] -ch_data_in\[22\] -ch_data_in\[21\] -ch_data_in\[20\] ch_data_out\[15\] ch_data_out\[14\] @@ -761,7 +961,7 @@ ch_data_out\[12\] ch_clk_out\[3\] -s2_wbd_stb_o 1600 0 2 +s2_wbd_stb_o 1610 0 2 s2_wbd_we_o s2_wbd_adr_o\[9\] s2_wbd_adr_o\[8\] @@ -844,3 +1044,4 @@ s2_wbd_ack_i s2_wbd_cyc_o +
diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl index 5b3dbc2..57a5277 100644 --- a/openlane/ycr2_iconnect/config.tcl +++ b/openlane/ycr2_iconnect/config.tcl
@@ -34,6 +34,7 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_iconnect.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_cross_bar.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_router.sv \
diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg index ab65df8..83e0e23 100644 --- a/openlane/ycr2_iconnect/pin_order.cfg +++ b/openlane/ycr2_iconnect/pin_order.cfg
@@ -457,6 +457,367 @@ core0_irq_lines\[0\] core0_irq_soft + +#S +core_icache_req_ack 000 0 2 +core_icache_req +core_icache_cmd +core_icache_addr\[31\] +core_icache_addr\[30\] +core_icache_addr\[29\] +core_icache_addr\[28\] +core_icache_addr\[27\] +core_icache_addr\[26\] +core_icache_addr\[25\] +core_icache_addr\[24\] +core_icache_addr\[23\] +core_icache_addr\[22\] +core_icache_addr\[21\] +core_icache_addr\[20\] +core_icache_addr\[19\] +core_icache_addr\[18\] +core_icache_addr\[17\] +core_icache_addr\[16\] +core_icache_addr\[15\] +core_icache_addr\[14\] +core_icache_addr\[13\] +core_icache_addr\[12\] +core_icache_addr\[11\] +core_icache_addr\[10\] +core_icache_addr\[9\] +core_icache_addr\[8\] +core_icache_addr\[7\] +core_icache_addr\[6\] +core_icache_addr\[5\] +core_icache_addr\[4\] +core_icache_addr\[3\] +core_icache_addr\[2\] +core_icache_addr\[1\] +core_icache_addr\[0\] +core_icache_bl\[2\] +core_icache_bl\[1\] +core_icache_bl\[0\] +core_icache_width\[1\] +core_icache_width\[0\] +core_icache_rdata\[31\] +core_icache_rdata\[30\] +core_icache_rdata\[29\] +core_icache_rdata\[28\] +core_icache_rdata\[27\] +core_icache_rdata\[26\] +core_icache_rdata\[25\] +core_icache_rdata\[24\] +core_icache_rdata\[23\] +core_icache_rdata\[22\] +core_icache_rdata\[21\] +core_icache_rdata\[20\] +core_icache_rdata\[19\] +core_icache_rdata\[18\] +core_icache_rdata\[17\] +core_icache_rdata\[16\] +core_icache_rdata\[15\] +core_icache_rdata\[14\] +core_icache_rdata\[13\] +core_icache_rdata\[12\] +core_icache_rdata\[11\] +core_icache_rdata\[10\] +core_icache_rdata\[9\] +core_icache_rdata\[8\] +core_icache_rdata\[7\] +core_icache_rdata\[6\] +core_icache_rdata\[5\] +core_icache_rdata\[4\] +core_icache_rdata\[3\] +core_icache_rdata\[2\] +core_icache_rdata\[1\] +core_icache_rdata\[0\] +core_icache_resp\[1\] +core_icache_resp\[0\] + + +core_dcache_req_ack 100 0 2 +core_dcache_req +core_dcache_cmd +core_dcache_width\[1\] +core_dcache_width\[0\] +core_dcache_addr\[31\] +core_dcache_addr\[30\] +core_dcache_addr\[29\] +core_dcache_addr\[28\] +core_dcache_addr\[27\] +core_dcache_addr\[26\] +core_dcache_addr\[25\] +core_dcache_addr\[24\] +core_dcache_addr\[23\] +core_dcache_addr\[22\] +core_dcache_addr\[21\] +core_dcache_addr\[20\] +core_dcache_addr\[19\] +core_dcache_addr\[18\] +core_dcache_addr\[17\] +core_dcache_addr\[16\] +core_dcache_addr\[15\] +core_dcache_addr\[14\] +core_dcache_addr\[13\] +core_dcache_addr\[12\] +core_dcache_addr\[11\] +core_dcache_addr\[10\] +core_dcache_addr\[9\] +core_dcache_addr\[8\] +core_dcache_addr\[7\] +core_dcache_addr\[6\] +core_dcache_addr\[5\] +core_dcache_addr\[4\] +core_dcache_addr\[3\] +core_dcache_addr\[2\] +core_dcache_addr\[1\] +core_dcache_addr\[0\] +core_dcache_wdata\[31\] +core_dcache_wdata\[30\] +core_dcache_wdata\[29\] +core_dcache_wdata\[28\] +core_dcache_wdata\[27\] +core_dcache_wdata\[26\] +core_dcache_wdata\[25\] +core_dcache_wdata\[24\] +core_dcache_wdata\[23\] +core_dcache_wdata\[22\] +core_dcache_wdata\[21\] +core_dcache_wdata\[20\] +core_dcache_wdata\[19\] +core_dcache_wdata\[18\] +core_dcache_wdata\[17\] +core_dcache_wdata\[16\] +core_dcache_wdata\[15\] +core_dcache_wdata\[14\] +core_dcache_wdata\[13\] +core_dcache_wdata\[12\] +core_dcache_wdata\[11\] +core_dcache_wdata\[10\] +core_dcache_wdata\[9\] +core_dcache_wdata\[8\] +core_dcache_wdata\[7\] +core_dcache_wdata\[6\] +core_dcache_wdata\[5\] +core_dcache_wdata\[4\] +core_dcache_wdata\[3\] +core_dcache_wdata\[2\] +core_dcache_wdata\[1\] +core_dcache_wdata\[0\] +core_dcache_rdata\[31\] +core_dcache_rdata\[30\] +core_dcache_rdata\[29\] +core_dcache_rdata\[28\] +core_dcache_rdata\[27\] +core_dcache_rdata\[26\] +core_dcache_rdata\[25\] +core_dcache_rdata\[24\] +core_dcache_rdata\[23\] +core_dcache_rdata\[22\] +core_dcache_rdata\[21\] +core_dcache_rdata\[20\] +core_dcache_rdata\[19\] +core_dcache_rdata\[18\] +core_dcache_rdata\[17\] +core_dcache_rdata\[16\] +core_dcache_rdata\[15\] +core_dcache_rdata\[14\] +core_dcache_rdata\[13\] +core_dcache_rdata\[12\] +core_dcache_rdata\[11\] +core_dcache_rdata\[10\] +core_dcache_rdata\[9\] +core_dcache_rdata\[8\] +core_dcache_rdata\[7\] +core_dcache_rdata\[6\] +core_dcache_rdata\[5\] +core_dcache_rdata\[4\] +core_dcache_rdata\[3\] +core_dcache_rdata\[2\] +core_dcache_rdata\[1\] +core_dcache_rdata\[0\] +core_dcache_resp\[1\] +core_dcache_resp\[0\] + +core_dmem_req_ack 0200 0 2 +core_dmem_req +core_dmem_cmd +core_dmem_bl\[2\] +core_dmem_bl\[1\] +core_dmem_bl\[0\] +core_dmem_width\[1\] +core_dmem_width\[0\] +core_dmem_addr\[31\] +core_dmem_addr\[30\] +core_dmem_addr\[29\] +core_dmem_addr\[28\] +core_dmem_addr\[27\] +core_dmem_addr\[26\] +core_dmem_addr\[25\] +core_dmem_addr\[24\] +core_dmem_addr\[23\] +core_dmem_addr\[22\] +core_dmem_addr\[21\] +core_dmem_addr\[20\] +core_dmem_addr\[19\] +core_dmem_addr\[18\] +core_dmem_addr\[17\] +core_dmem_addr\[16\] +core_dmem_addr\[15\] +core_dmem_addr\[14\] +core_dmem_addr\[13\] +core_dmem_addr\[12\] +core_dmem_addr\[11\] +core_dmem_addr\[10\] +core_dmem_addr\[9\] +core_dmem_addr\[8\] +core_dmem_addr\[7\] +core_dmem_addr\[6\] +core_dmem_addr\[5\] +core_dmem_addr\[4\] +core_dmem_addr\[3\] +core_dmem_addr\[2\] +core_dmem_addr\[1\] +core_dmem_addr\[0\] +core_dmem_wdata\[31\] +core_dmem_wdata\[30\] +core_dmem_wdata\[29\] +core_dmem_wdata\[28\] +core_dmem_wdata\[27\] +core_dmem_wdata\[26\] +core_dmem_wdata\[25\] +core_dmem_wdata\[24\] +core_dmem_wdata\[23\] +core_dmem_wdata\[22\] +core_dmem_wdata\[21\] +core_dmem_wdata\[20\] +core_dmem_wdata\[19\] +core_dmem_wdata\[18\] +core_dmem_wdata\[17\] +core_dmem_wdata\[16\] +core_dmem_wdata\[15\] +core_dmem_wdata\[14\] +core_dmem_wdata\[13\] +core_dmem_wdata\[12\] +core_dmem_wdata\[11\] +core_dmem_wdata\[10\] +core_dmem_wdata\[9\] +core_dmem_wdata\[8\] +core_dmem_wdata\[7\] +core_dmem_wdata\[6\] +core_dmem_wdata\[5\] +core_dmem_wdata\[4\] +core_dmem_wdata\[3\] +core_dmem_wdata\[2\] +core_dmem_wdata\[1\] +core_dmem_wdata\[0\] +core_dmem_rdata\[31\] +core_dmem_rdata\[30\] +core_dmem_rdata\[29\] +core_dmem_rdata\[28\] +core_dmem_rdata\[27\] +core_dmem_rdata\[26\] +core_dmem_rdata\[25\] +core_dmem_rdata\[24\] +core_dmem_rdata\[23\] +core_dmem_rdata\[22\] +core_dmem_rdata\[21\] +core_dmem_rdata\[20\] +core_dmem_rdata\[19\] +core_dmem_rdata\[18\] +core_dmem_rdata\[17\] +core_dmem_rdata\[16\] +core_dmem_rdata\[15\] +core_dmem_rdata\[14\] +core_dmem_rdata\[13\] +core_dmem_rdata\[12\] +core_dmem_rdata\[11\] +core_dmem_rdata\[10\] +core_dmem_rdata\[9\] +core_dmem_rdata\[8\] +core_dmem_rdata\[7\] +core_dmem_rdata\[6\] +core_dmem_rdata\[5\] +core_dmem_rdata\[4\] +core_dmem_rdata\[3\] +core_dmem_rdata\[2\] +core_dmem_rdata\[1\] +core_dmem_rdata\[0\] +core_dmem_resp\[1\] +core_dmem_resp\[0\] + +cfg_dcache_force_flush +cfg_sram_lphase\[1\] +cfg_sram_lphase\[0\] + +core_debug_sel\[1\] 300 0 2 +core_debug_sel\[0\] + +riscv_debug\[63\] +riscv_debug\[62\] +riscv_debug\[61\] +riscv_debug\[60\] +riscv_debug\[59\] +riscv_debug\[58\] +riscv_debug\[57\] +riscv_debug\[56\] +riscv_debug\[55\] +riscv_debug\[54\] +riscv_debug\[53\] +riscv_debug\[52\] +riscv_debug\[51\] +riscv_debug\[50\] +riscv_debug\[49\] +riscv_debug\[48\] +riscv_debug\[47\] +riscv_debug\[46\] +riscv_debug\[45\] +riscv_debug\[44\] +riscv_debug\[43\] +riscv_debug\[42\] +riscv_debug\[41\] +riscv_debug\[40\] +riscv_debug\[39\] +riscv_debug\[38\] +riscv_debug\[37\] +riscv_debug\[36\] +riscv_debug\[35\] +riscv_debug\[34\] +riscv_debug\[33\] +riscv_debug\[32\] +riscv_debug\[31\] +riscv_debug\[30\] +riscv_debug\[29\] +riscv_debug\[28\] +riscv_debug\[27\] +riscv_debug\[26\] +riscv_debug\[25\] +riscv_debug\[24\] +riscv_debug\[23\] +riscv_debug\[22\] +riscv_debug\[21\] +riscv_debug\[20\] +riscv_debug\[19\] +riscv_debug\[18\] +riscv_debug\[17\] +riscv_debug\[16\] +riscv_debug\[15\] +riscv_debug\[14\] +riscv_debug\[13\] +riscv_debug\[12\] +riscv_debug\[11\] +riscv_debug\[10\] +riscv_debug\[9\] +riscv_debug\[8\] +riscv_debug\[7\] +riscv_debug\[6\] +riscv_debug\[5\] +riscv_debug\[4\] +riscv_debug\[3\] +riscv_debug\[2\] +riscv_debug\[1\] +riscv_debug\[0\] + #E core1_uid\[1\] 0200 00 2 core1_uid\[0\] @@ -787,368 +1148,7 @@ core1_irq_soft -#S -core_icache_req_ack 000 0 2 -core_icache_req -core_icache_cmd -core_icache_addr\[31\] -core_icache_addr\[30\] -core_icache_addr\[29\] -core_icache_addr\[28\] -core_icache_addr\[27\] -core_icache_addr\[26\] -core_icache_addr\[25\] -core_icache_addr\[24\] -core_icache_addr\[23\] -core_icache_addr\[22\] -core_icache_addr\[21\] -core_icache_addr\[20\] -core_icache_addr\[19\] -core_icache_addr\[18\] -core_icache_addr\[17\] -core_icache_addr\[16\] -core_icache_addr\[15\] -core_icache_addr\[14\] -core_icache_addr\[13\] -core_icache_addr\[12\] -core_icache_addr\[11\] -core_icache_addr\[10\] -core_icache_addr\[9\] -core_icache_addr\[8\] -core_icache_addr\[7\] -core_icache_addr\[6\] -core_icache_addr\[5\] -core_icache_addr\[4\] -core_icache_addr\[3\] -core_icache_addr\[2\] -core_icache_addr\[1\] -core_icache_addr\[0\] -core_icache_bl\[2\] -core_icache_bl\[1\] -core_icache_bl\[0\] -core_icache_width\[1\] -core_icache_width\[0\] -core_icache_rdata\[31\] -core_icache_rdata\[30\] -core_icache_rdata\[29\] -core_icache_rdata\[28\] -core_icache_rdata\[27\] -core_icache_rdata\[26\] -core_icache_rdata\[25\] -core_icache_rdata\[24\] -core_icache_rdata\[23\] -core_icache_rdata\[22\] -core_icache_rdata\[21\] -core_icache_rdata\[20\] -core_icache_rdata\[19\] -core_icache_rdata\[18\] -core_icache_rdata\[17\] -core_icache_rdata\[16\] -core_icache_rdata\[15\] -core_icache_rdata\[14\] -core_icache_rdata\[13\] -core_icache_rdata\[12\] -core_icache_rdata\[11\] -core_icache_rdata\[10\] -core_icache_rdata\[9\] -core_icache_rdata\[8\] -core_icache_rdata\[7\] -core_icache_rdata\[6\] -core_icache_rdata\[5\] -core_icache_rdata\[4\] -core_icache_rdata\[3\] -core_icache_rdata\[2\] -core_icache_rdata\[1\] -core_icache_rdata\[0\] -core_icache_resp\[1\] -core_icache_resp\[0\] - - -core_dcache_req_ack 100 0 2 -core_dcache_req -core_dcache_cmd -core_dcache_width\[1\] -core_dcache_width\[0\] -core_dcache_addr\[31\] -core_dcache_addr\[30\] -core_dcache_addr\[29\] -core_dcache_addr\[28\] -core_dcache_addr\[27\] -core_dcache_addr\[26\] -core_dcache_addr\[25\] -core_dcache_addr\[24\] -core_dcache_addr\[23\] -core_dcache_addr\[22\] -core_dcache_addr\[21\] -core_dcache_addr\[20\] -core_dcache_addr\[19\] -core_dcache_addr\[18\] -core_dcache_addr\[17\] -core_dcache_addr\[16\] -core_dcache_addr\[15\] -core_dcache_addr\[14\] -core_dcache_addr\[13\] -core_dcache_addr\[12\] -core_dcache_addr\[11\] -core_dcache_addr\[10\] -core_dcache_addr\[9\] -core_dcache_addr\[8\] -core_dcache_addr\[7\] -core_dcache_addr\[6\] -core_dcache_addr\[5\] -core_dcache_addr\[4\] -core_dcache_addr\[3\] -core_dcache_addr\[2\] -core_dcache_addr\[1\] -core_dcache_addr\[0\] -core_dcache_wdata\[31\] -core_dcache_wdata\[30\] -core_dcache_wdata\[29\] -core_dcache_wdata\[28\] -core_dcache_wdata\[27\] -core_dcache_wdata\[26\] -core_dcache_wdata\[25\] -core_dcache_wdata\[24\] -core_dcache_wdata\[23\] -core_dcache_wdata\[22\] -core_dcache_wdata\[21\] -core_dcache_wdata\[20\] -core_dcache_wdata\[19\] -core_dcache_wdata\[18\] -core_dcache_wdata\[17\] -core_dcache_wdata\[16\] -core_dcache_wdata\[15\] -core_dcache_wdata\[14\] -core_dcache_wdata\[13\] -core_dcache_wdata\[12\] -core_dcache_wdata\[11\] -core_dcache_wdata\[10\] -core_dcache_wdata\[9\] -core_dcache_wdata\[8\] -core_dcache_wdata\[7\] -core_dcache_wdata\[6\] -core_dcache_wdata\[5\] -core_dcache_wdata\[4\] -core_dcache_wdata\[3\] -core_dcache_wdata\[2\] -core_dcache_wdata\[1\] -core_dcache_wdata\[0\] -core_dcache_rdata\[31\] -core_dcache_rdata\[30\] -core_dcache_rdata\[29\] -core_dcache_rdata\[28\] -core_dcache_rdata\[27\] -core_dcache_rdata\[26\] -core_dcache_rdata\[25\] -core_dcache_rdata\[24\] -core_dcache_rdata\[23\] -core_dcache_rdata\[22\] -core_dcache_rdata\[21\] -core_dcache_rdata\[20\] -core_dcache_rdata\[19\] -core_dcache_rdata\[18\] -core_dcache_rdata\[17\] -core_dcache_rdata\[16\] -core_dcache_rdata\[15\] -core_dcache_rdata\[14\] -core_dcache_rdata\[13\] -core_dcache_rdata\[12\] -core_dcache_rdata\[11\] -core_dcache_rdata\[10\] -core_dcache_rdata\[9\] -core_dcache_rdata\[8\] -core_dcache_rdata\[7\] -core_dcache_rdata\[6\] -core_dcache_rdata\[5\] -core_dcache_rdata\[4\] -core_dcache_rdata\[3\] -core_dcache_rdata\[2\] -core_dcache_rdata\[1\] -core_dcache_rdata\[0\] -core_dcache_resp\[1\] -core_dcache_resp\[0\] - -core_dmem_req_ack 0200 0 2 -core_dmem_req -core_dmem_cmd -core_dmem_bl\[2\] -core_dmem_bl\[1\] -core_dmem_bl\[0\] -core_dmem_width\[1\] -core_dmem_width\[0\] -core_dmem_addr\[31\] -core_dmem_addr\[30\] -core_dmem_addr\[29\] -core_dmem_addr\[28\] -core_dmem_addr\[27\] -core_dmem_addr\[26\] -core_dmem_addr\[25\] -core_dmem_addr\[24\] -core_dmem_addr\[23\] -core_dmem_addr\[22\] -core_dmem_addr\[21\] -core_dmem_addr\[20\] -core_dmem_addr\[19\] -core_dmem_addr\[18\] -core_dmem_addr\[17\] -core_dmem_addr\[16\] -core_dmem_addr\[15\] -core_dmem_addr\[14\] -core_dmem_addr\[13\] -core_dmem_addr\[12\] -core_dmem_addr\[11\] -core_dmem_addr\[10\] -core_dmem_addr\[9\] -core_dmem_addr\[8\] -core_dmem_addr\[7\] -core_dmem_addr\[6\] -core_dmem_addr\[5\] -core_dmem_addr\[4\] -core_dmem_addr\[3\] -core_dmem_addr\[2\] -core_dmem_addr\[1\] -core_dmem_addr\[0\] -core_dmem_wdata\[31\] -core_dmem_wdata\[30\] -core_dmem_wdata\[29\] -core_dmem_wdata\[28\] -core_dmem_wdata\[27\] -core_dmem_wdata\[26\] -core_dmem_wdata\[25\] -core_dmem_wdata\[24\] -core_dmem_wdata\[23\] -core_dmem_wdata\[22\] -core_dmem_wdata\[21\] -core_dmem_wdata\[20\] -core_dmem_wdata\[19\] -core_dmem_wdata\[18\] -core_dmem_wdata\[17\] -core_dmem_wdata\[16\] -core_dmem_wdata\[15\] -core_dmem_wdata\[14\] -core_dmem_wdata\[13\] -core_dmem_wdata\[12\] -core_dmem_wdata\[11\] -core_dmem_wdata\[10\] -core_dmem_wdata\[9\] -core_dmem_wdata\[8\] -core_dmem_wdata\[7\] -core_dmem_wdata\[6\] -core_dmem_wdata\[5\] -core_dmem_wdata\[4\] -core_dmem_wdata\[3\] -core_dmem_wdata\[2\] -core_dmem_wdata\[1\] -core_dmem_wdata\[0\] -core_dmem_rdata\[31\] -core_dmem_rdata\[30\] -core_dmem_rdata\[29\] -core_dmem_rdata\[28\] -core_dmem_rdata\[27\] -core_dmem_rdata\[26\] -core_dmem_rdata\[25\] -core_dmem_rdata\[24\] -core_dmem_rdata\[23\] -core_dmem_rdata\[22\] -core_dmem_rdata\[21\] -core_dmem_rdata\[20\] -core_dmem_rdata\[19\] -core_dmem_rdata\[18\] -core_dmem_rdata\[17\] -core_dmem_rdata\[16\] -core_dmem_rdata\[15\] -core_dmem_rdata\[14\] -core_dmem_rdata\[13\] -core_dmem_rdata\[12\] -core_dmem_rdata\[11\] -core_dmem_rdata\[10\] -core_dmem_rdata\[9\] -core_dmem_rdata\[8\] -core_dmem_rdata\[7\] -core_dmem_rdata\[6\] -core_dmem_rdata\[5\] -core_dmem_rdata\[4\] -core_dmem_rdata\[3\] -core_dmem_rdata\[2\] -core_dmem_rdata\[1\] -core_dmem_rdata\[0\] -core_dmem_resp\[1\] -core_dmem_resp\[0\] - -cfg_dcache_force_flush -cfg_sram_lphase\[1\] -cfg_sram_lphase\[0\] - -core_debug_sel\[1\] 300 0 2 -core_debug_sel\[0\] - -riscv_debug\[63\] -riscv_debug\[62\] -riscv_debug\[61\] -riscv_debug\[60\] -riscv_debug\[59\] -riscv_debug\[58\] -riscv_debug\[57\] -riscv_debug\[56\] -riscv_debug\[55\] -riscv_debug\[54\] -riscv_debug\[53\] -riscv_debug\[52\] -riscv_debug\[51\] -riscv_debug\[50\] -riscv_debug\[49\] -riscv_debug\[48\] -riscv_debug\[47\] -riscv_debug\[46\] -riscv_debug\[45\] -riscv_debug\[44\] -riscv_debug\[43\] -riscv_debug\[42\] -riscv_debug\[41\] -riscv_debug\[40\] -riscv_debug\[39\] -riscv_debug\[38\] -riscv_debug\[37\] -riscv_debug\[36\] -riscv_debug\[35\] -riscv_debug\[34\] -riscv_debug\[33\] -riscv_debug\[32\] -riscv_debug\[31\] -riscv_debug\[30\] -riscv_debug\[29\] -riscv_debug\[28\] -riscv_debug\[27\] -riscv_debug\[26\] -riscv_debug\[25\] -riscv_debug\[24\] -riscv_debug\[23\] -riscv_debug\[22\] -riscv_debug\[21\] -riscv_debug\[20\] -riscv_debug\[19\] -riscv_debug\[18\] -riscv_debug\[17\] -riscv_debug\[16\] -riscv_debug\[15\] -riscv_debug\[14\] -riscv_debug\[13\] -riscv_debug\[12\] -riscv_debug\[11\] -riscv_debug\[10\] -riscv_debug\[9\] -riscv_debug\[8\] -riscv_debug\[7\] -riscv_debug\[6\] -riscv_debug\[5\] -riscv_debug\[4\] -riscv_debug\[3\] -riscv_debug\[2\] -riscv_debug\[1\] -riscv_debug\[0\] - -#N -core_irq_lines_i\[31\] +core_irq_lines_i\[31\] 850 0 2 core_irq_lines_i\[30\] core_irq_lines_i\[29\] core_irq_lines_i\[28\] @@ -1182,6 +1182,12 @@ core_irq_lines_i\[0\] core_irq_soft_i +cfg_ccska\[3\] +cfg_ccska\[2\] +cfg_ccska\[1\] +cfg_ccska\[0\] +core_clk_int +core_clk_skew core_clk rtc_clk pwrup_rst_n
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc index 874dabb..873ac0a 100644 --- a/openlane/ycr_core_top/base.sdc +++ b/openlane/ycr_core_top/base.sdc
@@ -34,7 +34,7 @@ #DMEM Constraints set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] -set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] +set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index e4947ce..4056ea0 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -33,6 +33,8 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_core_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_dm.sv \
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg index 8fc1648..222f71f 100644 --- a/openlane/ycr_core_top/pin_order.cfg +++ b/openlane/ycr_core_top/pin_order.cfg
@@ -336,6 +336,12 @@ rst_n +cfg_ccska\[3\] +cfg_ccska\[2\] +cfg_ccska\[1\] +cfg_ccska\[0\] +core_clk_int +core_clk_skew clk clk_o
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index 89d85ff..2d2308c 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -69,11 +69,8 @@ set ::env(PL_TARGET_DENSITY) 0.37 -set ::env(FP_IO_VEXTEND) {4} -set ::env(FP_IO_HEXTEND) {4} - -#LVS Issue - DEF Base looks to having issue -set ::env(MAGIC_EXT_USE_GDS) {1} +#set ::env(FP_IO_VEXTEND) {6} +#set ::env(FP_IO_HEXTEND) {6} set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAXLAYER) "5"
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg index 016df72..cbeff2f 100644 --- a/openlane/ycr_intf/pin_order.cfg +++ b/openlane/ycr_intf/pin_order.cfg
@@ -391,7 +391,6 @@ wb_rst_n 500 0 pwrup_rst_n -core_clk cpu_intf_rst_n #W @@ -528,15 +527,24 @@ #E -cfg_cska_riscv\[3\] 0000 0 2 -cfg_cska_riscv\[2\] -cfg_cska_riscv\[1\] -cfg_cska_riscv\[0\] +cfg_ccska\[3\] 0000 0 2 +cfg_ccska\[2\] +cfg_ccska\[1\] +cfg_ccska\[0\] +core_clk_int +core_clk_skew +core_clk + +cfg_wcska\[3\] 0050 0 2 +cfg_wcska\[2\] +cfg_wcska\[1\] +cfg_wcska\[0\] wbd_clk_int -wbd_clk_riscv +wbd_clk_skew wb_clk wbd_dmem_stb_o 0100 0 2 +wbd_dmem_cyc_o wbd_dmem_we_o wbd_dmem_adr_o\[31\] wbd_dmem_adr_o\[30\] @@ -647,6 +655,7 @@ wbd_dmem_err_i wb_dcache_stb_o 0300 0 2 +wb_dcache_cyc_o wb_dcache_we_o wb_dcache_adr_o\[31\] wb_dcache_adr_o\[30\] @@ -762,9 +771,9 @@ wb_dcache_ack_i wb_dcache_lack_i wb_dcache_err_i -wb_dcache_cyc_o wb_icache_stb_o 500 0 2 +wb_icache_cyc_o wb_icache_we_o wb_icache_adr_o\[31\] wb_icache_adr_o\[30\] @@ -848,7 +857,6 @@ wb_icache_ack_i wb_icache_lack_i wb_icache_err_i -wb_icache_cyc_o cfg_icache_pfet_dis cfg_icache_ntag_pfet_dis
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index 9fe343c..bec965e 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -51,6 +51,7 @@ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v + read_verilog $::env(USER_ROOT)/verilog/gl/dg_pll.v read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v @@ -155,7 +156,7 @@ read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef - read_spef -path mprj/u_pll $::env(USER_ROOT)/spef/digital_pll.spef + read_spef -path mprj/u_pll $::env(USER_ROOT)/spef/dg_pll.spef read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
diff --git a/sta/scripts/ycr_core_timing.tcl b/sta/scripts/ycr_core_timing.tcl index 9557046..34a5c68 100644 --- a/sta/scripts/ycr_core_timing.tcl +++ b/sta/scripts/ycr_core_timing.tcl
@@ -36,6 +36,9 @@ read_sdc -echo ./sdc/ycr_core_top.sdc set_propagated_clock [all_clocks] + report_annotated_check -list_annotated + report_annotated_check -list_not_annotated + check_setup -verbose > unconstraints.rpt report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50 report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 327fed6..667b17d 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -62,10 +62,10 @@ set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}] set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}] set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] @@ -77,6 +77,27 @@ set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] +# clock skew cntrl-2 +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}] + +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}] + +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}] + +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[0]}] + #Keept the SRAM clock driving edge at pos edge set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}] set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 75dedef..a1faaf8 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_mcore_test1 user_mcore_test2 +PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_mcore_test1 user_mcore_test2 user_aes_core user_fpu_core all: ${PATTERNS} echo "################# RTL Test case Summary #####################" > regression.rpt @@ -27,11 +27,11 @@ for i in ${PATTERNS}; do \ ( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \ done - echo "################# GL Test case Summary #####################" >> regression.rpt - \rm -rf */*.vvp - for i in ${PATTERNS}; do \ - ( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \ - done + #echo "################# GL Test case Summary #####################" >> regression.rpt + #\rm -rf */*.vvp + #for i in ${PATTERNS}; do \ + # ( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \ + #done echo "################# End of Test case Summary #####################" >> regression.rpt DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v index b618915..368b494 100644 --- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v +++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -168,7 +168,7 @@ tb_uart.uart_init; tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (1000) @(posedge clock); // wait for Processor Get Ready + repeat (10000) @(posedge clock); // wait for Processor Get Ready flag = 0; check_sum = 0;
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v index 7f5b1c0..7cce107 100644 --- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v +++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -205,6 +205,7 @@ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); + repeat (10000) @(posedge clock); // wait for Processor Get Ready flag = 0; check_sum = 0; dCnt = 0;
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v index d1141a8..639e350 100644 --- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v +++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -165,7 +165,7 @@ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (1000) @(posedge clock); // wait for Processor Get Ready + repeat (5000) @(posedge clock); // wait for Processor Get Ready flag = 1;
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v index 72c3fbe..1ae2309 100644 --- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v +++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -117,13 +117,14 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(3, `TB_TOP); - $dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); - $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); - $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); - $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core); - $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm); - $dumpvars(0, `TB_TOP.u_top.u_pinmux); + $dumpvars(1, `TB_TOP); + $dumpvars(0, `TB_TOP.tb_uart); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect); + //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf); + $dumpvars(1, `TB_TOP.u_top.u_uart_i2c_usb_spi); + //$dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm); + //$dumpvars(0, `TB_TOP.u_top.u_pinmux); end `endif @@ -172,13 +173,13 @@ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - u_i2c_slave_0.debug = 0; // disable i2c bfm debug message - u_i2c_slave_1.debug = 0; // disable i2c bfm debug message - u_i2c_slave_2.debug = 0; // disable i2c bfm debug message - u_i2c_slave_3.debug = 0; // disable i2c bfm debug message - u_i2c_slave_4.debug = 0; // disable i2c bfm debug message + u_i2c_slave_0.debug = 0; // disable i2c bfm debug message + u_i2c_slave_1.debug = 0; // disable i2c bfm debug message + u_i2c_slave_2.debug = 0; // disable i2c bfm debug message + u_i2c_slave_3.debug = 0; // disable i2c bfm debug message + u_i2c_slave_4.debug = 0; // disable i2c bfm debug message - repeat (1000) @(posedge clock); // wait for Processor Get Ready + repeat (10000) @(posedge clock); // wait for Processor Get Ready flag = 0; check_sum = 0; compare_start = 1;
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v index 40f9df8..882a549 100644 --- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v +++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -175,7 +175,7 @@ u_i2c_slave_0.debug = 1; // disable i2c bfm debug message u_i2c_slave_1.debug = 1; // disable i2c bfm debug message - repeat (1000) @(posedge clock); // wait for Processor Get Ready + repeat (10000) @(posedge clock); // wait for Processor Get Ready flag = 0; check_sum = 0; compare_start = 1;
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v index abbaa1d..f3f29e1 100644 --- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v +++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -175,7 +175,7 @@ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (1000) @(posedge clock); // wait for Processor Get Ready + repeat (10000) @(posedge clock); // wait for Processor Get Ready flag = 0; check_sum = 0; compare_start = 1;
diff --git a/verilog/dv/common/agents/uart_agent.v b/verilog/dv/common/agents/uart_agent.v index 5ca1813..0aab170 100644 --- a/verilog/dv/common/agents/uart_agent.v +++ b/verilog/dv/common/agents/uart_agent.v
@@ -146,10 +146,9 @@ //////////////////////////////////////////////////////////////////////////////// task read_char_chk; -input expected_data; +input [7:0] expected_data; integer i; -reg [7:0] expected_data; reg [7:0] data; reg parity; @@ -340,7 +339,6 @@ integer i; -reg [7:0] expected_data; reg [7:0] data; reg parity;
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv index 0ea83c8..6bda236 100644 --- a/verilog/dv/common/agents/user_tasks.sv +++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,7 @@ begin // Run in Fast Sim Mode `ifdef GL - force u_top.u_wb_host._09718_.Q= 1'b1; + force u_top.u_wb_host._10673_.Q= 1'b1; `else force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1; `endif @@ -204,6 +204,7 @@ //--------------------------------------------------------- // Create Pull Up/Down Based on Reset Strap Parameter +// System strap are in io_in[13] to [20] and 29 to [36] //--------------------------------------------------------- genvar gCnt; generate @@ -222,6 +223,13 @@ end end end + // Add Non Strap with pull-up to avoid unkown propagation during gate sim + for(gCnt=0; gCnt<13; gCnt++) begin : g_nostrap1 + pullup(io_in[gCnt]); + end + for(gCnt=21; gCnt<29; gCnt++) begin : g_nostrap2 + pullup(io_in[gCnt]); + end endgenerate `ifdef RISC_BOOT // RISCV Based Test case @@ -449,6 +457,32 @@ baud_div = baud_div-1; end endtask + +/************************************************************************* + * This is I2C Prescale value computation logic + * Note: from I2c Logic 3 Prescale value SCL = 0, and 2 Prescale value SCL=1 + * Filtering logic uses two sample of Precale/4-1 period. + * I2C Clock = System Clock / ((5*(Prescale-1)) + (2 * ((Prescale/4)-1))) + * for 50Mhz system clock, 400Khz I2C clock + * 400,000 = 50,000,000 * (5*(Prescale-1) + 2*(Prescale/4+1)+2) + * 5*Prescale -5 + 2*Prescale/4 + 2 + 2= 50,000,000/400,000 + * 5*prescale -5 + Prescale/2 + 4 = 125 + * (10*prescale+Prescale)/2 - 1 = 125 + * (11 *Prescale)/2 = 125+1 + * Prescale = 126*2/11 + + * *************************************************************************/ + task tb_set_i2c_prescale; + input [31:0] ref_clk; + input [31:0] rate; + output [15:0] prescale; + reg [15:0] prescale; + begin + prescale = ref_clk/rate; + prescale = prescale +1; + prescale = (prescale *2)/11; + end + endtask /** `ifdef GL
diff --git a/verilog/dv/common/firmware/int_reg_map.h b/verilog/dv/common/firmware/int_reg_map.h index fa79ec1..4c56c49 100644 --- a/verilog/dv/common/firmware/int_reg_map.h +++ b/verilog/dv/common/firmware/int_reg_map.h
@@ -90,3 +90,50 @@ #define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x1001011C) // Reg-7 #define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x10010120) // Reg-8 +// AES Encription Register +#define reg_aes_enc_ctrl (*(volatile uint32_t*)0x0C490080) // Reg-0 + +#define reg_aes_enc_key_dw0 (*(volatile uint32_t*)0x0C490084) // Reg-1 +#define reg_aes_enc_key_dw1 (*(volatile uint32_t*)0x0C490088) // Reg-2 +#define reg_aes_enc_key_dw2 (*(volatile uint32_t*)0x0C49008C) // Reg-3 +#define reg_aes_enc_key_dw3 (*(volatile uint32_t*)0x0C490090) // Reg-4 +#define reg_aes_enc_key_bptr (*(volatile uint8_t*)0x0C490093) // Last Addr Location + +#define reg_aes_enc_text_in_dw0 (*(volatile uint32_t*)0x0C490094) // Reg-5 +#define reg_aes_enc_text_in_dw1 (*(volatile uint32_t*)0x0C490098) // Reg-6 +#define reg_aes_enc_text_in_dw2 (*(volatile uint32_t*)0x0C49009C) // Reg-7 +#define reg_aes_enc_text_in_dw3 (*(volatile uint32_t*)0x0C4900A0) // Reg-8 +#define reg_aes_enc_text_in_bptr (*(volatile uint8_t*)0x0C4900A3) // Last Addr Location + +#define reg_aes_enc_text_out_dw0 (*(volatile uint32_t*)0x0C4900A4) // Reg-9 +#define reg_aes_enc_text_out_dw1 (*(volatile uint32_t*)0x0C4900A8) // Reg-10 +#define reg_aes_enc_text_out_dw2 (*(volatile uint32_t*)0x0C4900AC) // Reg-11 +#define reg_aes_enc_text_out_dw3 (*(volatile uint32_t*)0x0C4900B0) // Reg-12 +#define reg_aes_enc_text_out_bptr (*(volatile uint8_t*)0x0C4900B3) // Last Addr Location + +// AES Decryption Register +#define reg_aes_dec_ctrl (*(volatile uint32_t*)0x0C4900C0) // Reg-0 +#define reg_aes_dec_key_dw0 (*(volatile uint32_t*)0x0C4900C4) // Reg-1 +#define reg_aes_dec_key_dw1 (*(volatile uint32_t*)0x0C4900C8) // Reg-2 +#define reg_aes_dec_key_dw2 (*(volatile uint32_t*)0x0C4900CC) // Reg-3 +#define reg_aes_dec_key_dw3 (*(volatile uint32_t*)0x0C4900D0) // Reg-4 +#define reg_aes_dec_key_bptr (*(volatile uint8_t*)0x0C4900D3) // Last Addr Location + +#define reg_aes_dec_text_in_dw0 (*(volatile uint32_t*)0x0C4900D4) // Reg-5 +#define reg_aes_dec_text_in_dw1 (*(volatile uint32_t*)0x0C4900D8) // Reg-6 +#define reg_aes_dec_text_in_dw2 (*(volatile uint32_t*)0x0C4900DC) // Reg-7 +#define reg_aes_dec_text_in_dw3 (*(volatile uint32_t*)0x0C4900E0) // Reg-8 +#define reg_aes_dec_text_in_bptr (*(volatile uint8_t*)0x0C4900E3) // Last Addr Location + +#define reg_aes_dec_text_out_dw0 (*(volatile uint32_t*)0x0C4900E4) // Reg-9 +#define reg_aes_dec_text_out_dw1 (*(volatile uint32_t*)0x0C4900E8) // Reg-10 +#define reg_aes_dec_text_out_dw2 (*(volatile uint32_t*)0x0C4900EC) // Reg-11 +#define reg_aes_dec_text_out_dw3 (*(volatile uint32_t*)0x0C4900F0) // Reg-12 +#define reg_aes_dec_text_out_bptr (*(volatile uint8_t*)0x0C4900F3) // Last Addr Location + +// FPU Core +#define reg_fpu_ctrl (*(volatile uint32_t*)0x0C490100) // Reg-0 +#define reg_fpu_din1 (*(volatile uint32_t*)0x0C490104) // Reg-1 +#define reg_fpu_din2 (*(volatile uint32_t*)0x0C490108) // Reg-2 +#define reg_fpu_res (*(volatile uint32_t*)0x0C49010C) // Reg-3 +
diff --git a/verilog/dv/uart_master_test2/uart_master_test2_tb.v b/verilog/dv/uart_master_test2/uart_master_test2_tb.v index ba4fdeb..257363e 100644 --- a/verilog/dv/uart_master_test2/uart_master_test2_tb.v +++ b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
@@ -21,7 +21,6 @@ `define TB_HEX "uart_master.hex" `define TB_TOP uart_master_tb module `TB_TOP; - reg clock; reg RSTB; reg CSB;
diff --git a/verilog/dv/user_aes/user_aes.c b/verilog/dv/user_aes/user_aes.c index 2830ebe..1b7a697 100644 --- a/verilog/dv/user_aes/user_aes.c +++ b/verilog/dv/user_aes/user_aes.c
@@ -60,6 +60,7 @@ reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0 reg_glbl_multi_func |=0x100; // Enable UART Multi func + reg_gpio_dsel =0xFF00; // Enable PORT B As output reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1} // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit // bit[7:0] - core-0
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v index 3d47bd3..55aba10 100644 --- a/verilog/dv/user_aes/user_aes_tb.v +++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -21,9 +21,7 @@ //// This file is part of the Riscduino cores project //// //// //// //// Description //// -//// This is a standalone test bench to validate the //// -//// Digital core with Risc core executing code from TCM/SRAM. //// -//// with icache and dcache bypass mode //// +//// To validate Software AES Encription & Decription //// //// //// //// To Do: //// //// nothing //// @@ -32,7 +30,7 @@ //// - Dinesh Annayya, dinesha@opencores.org //// //// //// //// Revision : //// -//// 0.1 - 16th Feb 2021, Dinesh A //// +//// 0.1 - 7th Nov 2022, Dinesh A //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -98,24 +96,24 @@ /************* Port-B Mapping ********************************** - * Pin-14 PB0/CLKO/ICP1 digital_io[11] - * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[12] - * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] - * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] - * Pin-18 PB4/MISO digital_io[15] - * Pin-19 PB5/SCK digital_io[16] - * Pin-9 PB6/XTAL1/TOSC1 digital_io[6] - * Pin-10 PB7/XTAL2/TOSC2 digital_io[7] + * Pin-14 PB0/CLKO/ICP1 digital_io[16] + * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[17] + * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[18] + * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[19] + * Pin-18 PB4/MISO digital_io[20] + * Pin-19 PB5/SCK digital_io[21] + * Pin-9 PB6/XTAL1/TOSC1 digital_io[11] + * Pin-10 PB7/XTAL2/TOSC2 digital_io[12] * ********************************************************/ - wire [7:0] port_b_in = { io_out[7], - io_out[6], - io_out[16], - io_out[15], - io_out[14], - io_out[13], - io_out[12], - io_out[11] + wire [7:0] port_b_in = { io_out[12], + io_out[11], + io_out[21], + io_out[20], + io_out[19], + io_out[18], + io_out[17], + io_out[16] }; initial begin test_fail = 0; @@ -195,7 +193,7 @@ repeat (1400000) @(posedge clock); end begin - wait(port_b_in == 8'h18); + wait(port_b_in == 8'h18 || port_b_in == 8'hA8); end begin while(1) begin
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index feab774..2865bda 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -145,33 +145,33 @@ reg [1:0] strap_skew; wire [31:0] skew_config; -assign skew_config[3:0] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[3:0] : - (strap_skew == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 : - (strap_skew == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4; +assign skew_config[3:0] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[3:0] : + (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[3:0] + 2 : + (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[3:0] + 4 : CLK_SKEW1_RESET_VAL[3:0]-4; -assign skew_config[7:4] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[7:4] : - (strap_skew == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 : - (strap_skew == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4; +assign skew_config[7:4] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[7:4] : + (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[7:4] + 2 : + (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[7:4] + 4 : CLK_SKEW1_RESET_VAL[7:4]-4; -assign skew_config[11:8] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[11:8] : - (strap_skew == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 : - (strap_skew == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4; +assign skew_config[11:8] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[11:8] : + (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[11:8] + 2 : + (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[11:8] + 4 : CLK_SKEW1_RESET_VAL[11:8]-4; -assign skew_config[15:12] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[15:12] : - (strap_skew == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 : - (strap_skew == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4; +assign skew_config[15:12] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[15:12] : + (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[15:12] + 2 : + (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[15:12] + 4 : CLK_SKEW1_RESET_VAL[15:12]-4; -assign skew_config[19:16] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[19:16] : - (strap_skew == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 : - (strap_skew == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4; +assign skew_config[19:16] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[19:16] : + (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[19:16] + 2 : + (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[19:16] + 4 : CLK_SKEW1_RESET_VAL[19:16]-4; -assign skew_config[23:20] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[23:20] : - (strap_skew == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 : - (strap_skew == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4; +assign skew_config[23:20] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[23:20] : + (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[23:20] + 2 : + (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[23:20] + 4 : CLK_SKEW1_RESET_VAL[23:20]-4; -assign skew_config[27:24] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[27:24] : - (strap_skew == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 : - (strap_skew == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4; +assign skew_config[27:24] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[27:24] : + (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 : + (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4; assign skew_config[31:28] = 4'b0; @@ -194,7 +194,7 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(0, `TB_TOP); + $dumpvars(1, `TB_TOP); $dumpvars(1, `TB_TOP.u_top); $dumpvars(0, `TB_TOP.u_top.u_pll); $dumpvars(0, `TB_TOP.u_top.u_wb_host); @@ -279,7 +279,8 @@ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in); wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,strap_sticky); wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SYSTEM_STRAP,read_data,strap_sticky); - wb_user_core_read_check(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,read_data,clk_ctrl2); + wb_user_core_read(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,read_data); + if(read_data[23:16] != clk_ctrl2) test_fail = 1; clock_monitor2(cpu_clk_cfg,wbs_clk_cfg); end end @@ -479,9 +480,40 @@ `endif $display("##########################################################"); - $display("Step-10,Monitor: Checking the chip signature :"); - $display("###################################################"); + $display("Step-10,Monitor: Analog Config checks "); + $display("##########################################################"); test_id = 10; + test_step = 14; + + // Remove Wb/PinMux Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC0,'h11); + wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC1,'h22); + wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC2,'h33); + wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC3,'h44); + wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC0,read_data,'h11); + wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC1,read_data,'h22); + wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC2,read_data,'h33); + wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC3,read_data,'h44); + repeat (10) @(posedge clock); + if((u_top.u_4x8bit_dac.DIn0 != 'h11) || (u_top.u_4x8bit_dac.DIn1 != 'h22) || + (u_top.u_4x8bit_dac.DIn2 != 'h33) || (u_top.u_4x8bit_dac.DIn3 != 'h44)) begin + test_fail = 1; + end + + if(test_fail == 1) begin + $display("ERROR: Step-10,Monitor: Analog Config check - FAILED"); + end else begin + $display("STATUS: Step-10,Monitor: Ananlog Config check - PASSED"); + + $display("##########################################################"); + + end + $display("##########################################################"); + $display("Step-11,Monitor: Checking the chip signature :"); + $display("###################################################"); + test_id = 11; test_step = 14; // Remove Wb/PinMux Reset wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); @@ -490,9 +522,9 @@ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE); wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION); if(test_fail == 1) begin - $display("ERROR: Step-10,Monitor: Checking the chip signature - FAILED"); + $display("ERROR: Step-11,Monitor: Checking the chip signature - FAILED"); end else begin - $display("STATUS: Step-10,Monitor: Checking the chip signature - PASSED"); + $display("STATUS: Step-11,Monitor: Checking the chip signature - PASSED"); $display("##########################################################"); @@ -636,7 +668,7 @@ input real exp_period; begin `ifdef GL - force clock_mon = u_top.u_wb_host._09314_.Q; + force clock_mon = u_top.u_wb_host._09635_.Q; `else force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x; `endif
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index 0547990..c4b27a9 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -76,6 +76,7 @@ `include "user_tasks.sv" +reg [15:0] prescale; //---------------------------------- // Uart Configuration @@ -119,9 +120,12 @@ @(posedge clock); $display("---------- Initialize I2C Master ----------"); + // Sysclock: 50Mhz, I2C : 400Khz + tb_set_i2c_prescale(50000000,400000,prescale); + //Wrire Prescale registers - wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7); - wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),8'h00); + wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),prescale[7:0]); + wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),prescale[15:8]); // Core Enable wb_user_core_write(`ADDR_SPACE_I2CM+(8'h2<<2),8'h80);
diff --git a/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v index c6f6181..ba2f54e 100644 --- a/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v +++ b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
@@ -117,36 +117,6 @@ end `endif - /************************************************************************* - * This is Baud Rate to clock divider conversion for Test Bench - * Note: DUT uses 16x baud clock, where are test bench uses directly - * baud clock, Due to 16x Baud clock requirement at RTL, there will be - * some resolution loss, we expect at lower baud rate this resolution - * loss will be less. For Quick simulation perpose higher baud rate used - * *************************************************************************/ - task tb_set_uart_baud; - input [31:0] ref_clk; - input [31:0] baud_rate; - output [31:0] baud_div; - reg [31:0] baud_div; - begin - // for 230400 Baud = (50Mhz/230400) = 216.7 - baud_div = ref_clk/baud_rate; // Get the Bit Baud rate - // Baud 16x = 216/16 = 13 - baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench - // Test bench baud clock , 16x of above value - // 13 * 16 = 208, - // (Note if you see original value was 216, now it's 208 ) - baud_div = baud_div * 16; - // Test bench half cycle counter to toggle it - // 208/2 = 104 - baud_div = baud_div/2; - //As counter run's from 0 , substract from 1 - baud_div = baud_div-1; - end - endtask - - initial begin uart_data_bit = 2'b11; uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index b8bce21..3c425ce 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -98,9 +98,11 @@ initial begin $dumpfile("simx.vcd"); $dumpvars(1, `TB_GLBL); - $dumpvars(0, `TB_GLBL.u_top.u_wb_host); + $dumpvars(1, `TB_GLBL.pwm_monitor); + $dumpvars(1, `TB_GLBL.check_clock_period); + $dumpvars(1, `TB_GLBL.u_top.u_wb_host); $dumpvars(0, `TB_GLBL.u_top.u_pinmux); - $dumpvars(0, `TB_GLBL.u_top.u_intercon); + $dumpvars(1, `TB_GLBL.u_top.u_intercon); end `endif @@ -741,7 +743,7 @@ $display("STATUS: Step-10, PWM One Shot + mode:3 + Comparator Center - PASSED"); end $display("Check Sum: %x ",check_sum); - if(check_sum != 16'hc638) test_fail = 1; + if(check_sum != 16'hc692) test_fail = 1; repeat (100) @(posedge clock); // $display("+1000 cycles"); @@ -777,6 +779,16 @@ wire pwm4 = pwm_wfm[4]; wire pwm5 = pwm_wfm[5]; + +reg [2:0] pwm_sel; + +assign clock_mon = (pwm_sel == 0) ? pwm0 : + (pwm_sel == 1) ? pwm1 : + (pwm_sel == 2) ? pwm2 : + (pwm_sel == 3) ? pwm3 : + (pwm_sel == 4) ? pwm4 : pwm5; + + task pwm_monitor; input [31:0] pwm0_period; input [31:0] pwm1_period; @@ -785,29 +797,29 @@ input [31:0] pwm4_period; input [31:0] pwm5_period; begin - force clock_mon = pwm0; + pwm_sel = 3'h0; + repeat (100) @(posedge clock); check_clock_period("PWM0 Clock",pwm0_period); - release clock_mon; - force clock_mon = pwm1; + pwm_sel = 3'h1; + repeat (100) @(posedge clock); check_clock_period("PWM1 Clock",pwm1_period); - release clock_mon; - force clock_mon = pwm2; + pwm_sel = 3'h2; + repeat (100) @(posedge clock); check_clock_period("PWM2 Clock",pwm2_period); - release clock_mon; - force clock_mon = pwm3; + pwm_sel = 3'h3; + repeat (100) @(posedge clock); check_clock_period("PWM3 Clock",pwm3_period); - release clock_mon; - force clock_mon = pwm4; + pwm_sel = 3'h4; + repeat (100) @(posedge clock); check_clock_period("PWM4 Clock",pwm4_period); - release clock_mon; - force clock_mon = pwm5; + pwm_sel = 3'h5; + repeat (100) @(posedge clock); check_clock_period("PWM5 Clock",pwm5_period); - release clock_mon; end endtask @@ -821,7 +833,7 @@ time prev_t, next_t, periodd; begin $timeformat(-12,3,"ns",10); - repeat(1) @(posedge clock_mon); + repeat(2) @(posedge clock_mon); repeat(1) @(posedge clock_mon); prev_t = $realtime; repeat(2) @(posedge clock_mon);
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 8029645..935aa9e 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -118,6 +118,7 @@ $dumpvars(1, `TB_TOP); $dumpvars(2, `TB_TOP.u_top); $dumpvars(0, `TB_TOP.u_top.u_wb_host); + $dumpvars(2, `TB_TOP.u_top.u_riscv_top); $dumpvars(0, `TB_TOP.u_top.u_pinmux); end `endif
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index aa79249..59e8b61 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -221,3 +221,8 @@ #-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv + + +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v + +-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v
diff --git a/verilog/includes/includes.gl.lib b/verilog/includes/includes.gl.lib index 9a0c428..f6100e2 100644 --- a/verilog/includes/includes.gl.lib +++ b/verilog/includes/includes.gl.lib
@@ -9,6 +9,5 @@ -v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v #$(USER_PROJECT_VERILOG)/gl/digital_pll.v --v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v --v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v --v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index e9e4e4e..30634b6 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -3,6 +3,7 @@ +incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl +incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm +incdir+$(USER_PROJECT_VERILOG)/dv/common/model +incdir+$(USER_PROJECT_VERILOG)/dv/common/agents @@ -32,6 +33,11 @@ -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv -v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v + +-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v + +-v $(USER_PROJECT_VERILOG)/rtl/dig2ana/src/dig2ana_reg.sv + -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv @@ -130,6 +136,16 @@ -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_arb.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_sbox.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_rcon.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_key_expand_128.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_cipher_top.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_inv_sbox.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_inv_cipher_top.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/top/aes_top.sv +$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/top/aes_reg.sv + + -v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv -v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv -v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv @@ -139,3 +155,15 @@ -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v -v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv -v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv + +-v $(USER_PROJECT_VERILOG)/rtl/fpu_wrapper/src/fpu_wrapper.sv +-v $(USER_PROJECT_VERILOG)/rtl/fpu_wrapper/src/fpu_reg.sv +-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_top.sv +-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_mul.sv +-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_div.sv +-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_add.sv +-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_f2i.sv +-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_i2f.sv + + +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
diff --git a/verilog/includes/includes.rtl.lib b/verilog/includes/includes.rtl.lib index 5045805..9db7739 100644 --- a/verilog/includes/includes.rtl.lib +++ b/verilog/includes/includes.rtl.lib
@@ -1,3 +1,2 @@ --v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v --v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v --v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/dac/src/dac_top.v b/verilog/rtl/dac/src/dac_top.v new file mode 100644 index 0000000..951076d --- /dev/null +++ b/verilog/rtl/dac/src/dac_top.v
@@ -0,0 +1,24 @@ +module dac_top (Vout0, + Vout1, + Vout2, + Vout3, + Vref, + vccd1, + vssd1, + DIn0, + DIn1, + DIn2, + DIn3); + output Vout0; + output Vout1; + output Vout2; + output Vout3; + input Vref; + input vccd1; + input vssd1; + input [7:0] DIn0; + input [7:0] DIn1; + input [7:0] DIn2; + input [7:0] DIn3; + +endmodule
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/dg_pll/src/dg_pll.v similarity index 98% rename from verilog/rtl/digital_pll/src/digital_pll.v rename to verilog/rtl/dg_pll/src/dg_pll.v index 79cb52e..a364783 100644 --- a/verilog/rtl/digital_pll/src/digital_pll.v +++ b/verilog/rtl/dg_pll/src/dg_pll.v
@@ -54,7 +54,7 @@ // Digital PLL (ring oscillator + controller) // Technically this is a frequency locked loop, not a phase locked loop. -module digital_pll( +module dg_pll( `ifdef USE_POWER_PINS VPWR, VGND,
diff --git a/verilog/rtl/digital_pll/src/digital_pll_controller.v b/verilog/rtl/dg_pll/src/digital_pll_controller.v similarity index 100% rename from verilog/rtl/digital_pll/src/digital_pll_controller.v rename to verilog/rtl/dg_pll/src/digital_pll_controller.v
diff --git a/verilog/rtl/digital_pll/src/ring_osc2x13.v b/verilog/rtl/dg_pll/src/ring_osc2x13.v similarity index 100% rename from verilog/rtl/digital_pll/src/ring_osc2x13.v rename to verilog/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/dig2ana/src/dig2ana_reg.sv b/verilog/rtl/dig2ana/src/dig2ana_reg.sv new file mode 100644 index 0000000..b0ad653 --- /dev/null +++ b/verilog/rtl/dig2ana/src/dig2ana_reg.sv
@@ -0,0 +1,206 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// Digital To Analog Register //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// Manages all the analog related config //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 29rd Sept 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// + + +module dig2ana_reg #( + parameter DW = 32, // DATA WIDTH + parameter AW = 4, // ADDRESS WIDTH + parameter BW = 4 // BYTE WIDTH + ) ( + // System Signals + // Inputs + input logic mclk , + input logic h_reset_n , + + // Reg Bus Interface Signal + input logic reg_cs , + input logic reg_wr , + input logic [AW-1:0] reg_addr , + input logic [DW-1:0] reg_wdata , + input logic [BW-1:0] reg_be , + + // Outputs + output logic [DW-1:0] reg_rdata , + output logic reg_ack , + + output logic [7:0] cfg_dac0_mux_sel , + output logic [7:0] cfg_dac1_mux_sel , + output logic [7:0] cfg_dac2_mux_sel , + output logic [7:0] cfg_dac3_mux_sel + + + + ); + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_rd_en ; +logic sw_wr_en ; +logic [AW-1:0] sw_addr ; +logic [DW-1:0] sw_reg_wdata ; +logic [BW-1:0] sw_be ; + +logic [DW-1:0] reg_out ; +logic [DW-1:0] reg_0 ; +logic [DW-1:0] reg_1 ; +logic [DW-1:0] reg_2 ; +logic [DW-1:0] reg_3 ; + + +assign sw_addr = reg_addr; +assign sw_be = reg_be; +assign sw_rd_en = reg_cs & !reg_wr; +assign sw_wr_en = reg_cs & reg_wr; +assign sw_reg_wdata = reg_wdata; + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3); + + + +always @ (posedge mclk or negedge h_reset_n) +begin : preg_out_Seq + if (h_reset_n == 1'b0) begin + reg_rdata <= 'h0; + reg_ack <= 1'b0; + end else if (reg_cs && !reg_ack) begin + reg_rdata <= reg_out[DW-1:0] ; + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + +//----------------------------------------------------------------------- +// reg-0 +//----------------------------------------------------------------- + +assign cfg_dac0_mux_sel = reg_0[7:0]; +generic_register #(8,8'h0 ) u_reg0_be0 ( + .we ({8{sw_wr_en_0 & + sw_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_0[7:0] ) + ); + +assign reg_0[31:8] = 'h0; + +//----------------------------------------------------------------------- +// reg-1 +//----------------------------------------------------------------- + +assign cfg_dac1_mux_sel = reg_1[7:0]; +generic_register #(8,8'h0 ) u_reg1_be0 ( + .we ({8{sw_wr_en_1 & + sw_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_1[7:0] ) + ); + +assign reg_1[31:8] = 'h0; + +//----------------------------------------------------------------------- +// reg-2 +//----------------------------------------------------------------- + +assign cfg_dac2_mux_sel = reg_2[7:0]; +generic_register #(8,8'h0 ) u_reg2_be0 ( + .we ({8{sw_wr_en_2 & + sw_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_2[7:0] ) + ); + +assign reg_2[31:8] = 'h0; + +//----------------------------------------------------------------------- +// reg-3 +//----------------------------------------------------------------- + +assign cfg_dac3_mux_sel = reg_3[7:0]; +generic_register #(8,8'h0 ) u_reg3_be0 ( + .we ({8{sw_wr_en_3 & + sw_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_3[7:0] ) + ); + +assign reg_3[31:8] = 'h0; + +//----------------------------------------------------------------------- +// Register Read Path Multiplexer instantiation +//----------------------------------------------------------------------- + +always_comb +begin + reg_out [31:0] = 32'h0; + + case (sw_addr [3:0]) + 4'b0000 : reg_out [31:0] = reg_0 ; + 4'b0001 : reg_out [31:0] = reg_1 ; + 4'b0010 : reg_out [31:0] = reg_2 ; + 4'b0011 : reg_out [31:0] = reg_3 ; + default : reg_out [31:0] = 32'h0; + endcase +end + + +endmodule
diff --git a/verilog/rtl/fpu b/verilog/rtl/fpu new file mode 160000 index 0000000..105f901 --- /dev/null +++ b/verilog/rtl/fpu
@@ -0,0 +1 @@ +Subproject commit 105f90130c507523bc6f45ca16431901fdd415c3
diff --git a/verilog/rtl/fpu_wrapper/src/a.out b/verilog/rtl/fpu_wrapper/src/a.out new file mode 100755 index 0000000..fb9ef8c --- /dev/null +++ b/verilog/rtl/fpu_wrapper/src/a.out
@@ -0,0 +1,4684 @@ +#! /usr/local/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1556-g542da1166)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/local/lib/ivl/system.vpi"; +:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/local/lib/ivl/v2005_math.vpi"; +:vpi_module "/usr/local/lib/ivl/va_math.vpi"; +:vpi_module "/usr/local/lib/ivl/v2009.vpi"; +S_0x5570afab39a0 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x5570afab5920 .scope module, "ctech_buf" "ctech_buf" 3 74; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +o0x7f116f7cb018 .functor BUFZ 1, C4<z>; HiZ drive +L_0x5570afad0180 .functor BUFZ 1, o0x7f116f7cb018, C4<0>, C4<0>, C4<0>; +v0x5570afb20990_0 .net "A", 0 0, o0x7f116f7cb018; 0 drivers +v0x5570afb20a30_0 .net "X", 0 0, L_0x5570afad0180; 1 drivers +S_0x5570afab5ca0 .scope module, "ctech_clk_buf" "ctech_clk_buf" 3 86; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +o0x7f116f7cb0d8 .functor BUFZ 1, C4<z>; HiZ drive +L_0x5570afb51eb0 .functor BUFZ 1, o0x7f116f7cb0d8, C4<0>, C4<0>, C4<0>; +v0x5570afb1ced0_0 .net "A", 0 0, o0x7f116f7cb0d8; 0 drivers +v0x5570afb1cf70_0 .net "X", 0 0, L_0x5570afb51eb0; 1 drivers +S_0x5570afab63a0 .scope module, "ctech_clk_gate" "ctech_clk_gate" 3 122; + .timescale 0 0; + .port_info 0 /INPUT 1 "GATE"; + .port_info 1 /INPUT 1 "CLK"; + .port_info 2 /OUTPUT 1 "GCLK"; +o0x7f116f7cb198 .functor BUFZ 1, C4<z>; HiZ drive +o0x7f116f7cb1c8 .functor BUFZ 1, C4<z>; HiZ drive +L_0x5570afb51f80 .functor AND 1, o0x7f116f7cb198, o0x7f116f7cb1c8, C4<1>, C4<1>; +v0x5570afabff50_0 .net "CLK", 0 0, o0x7f116f7cb198; 0 drivers +v0x5570af9b33a0_0 .net "GATE", 0 0, o0x7f116f7cb1c8; 0 drivers +v0x5570af9b3460_0 .net "GCLK", 0 0, L_0x5570afb51f80; 1 drivers +S_0x5570afab3620 .scope module, "ctech_delay_buf" "ctech_delay_buf" 3 98; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +o0x7f116f7cb2b8 .functor BUFZ 1, C4<z>; HiZ drive +L_0x5570afb52080 .functor BUFZ 1, o0x7f116f7cb2b8, C4<0>, C4<0>, C4<0>; +v0x5570af9b3580_0 .net "A", 0 0, o0x7f116f7cb2b8; 0 drivers +v0x5570afb29d80_0 .net "X", 0 0, L_0x5570afb52080; 1 drivers +S_0x5570afab6020 .scope module, "fpu_wrapper" "fpu_wrapper" 4 39; + .timescale 0 0; + .port_info 0 /INPUT 1 "mclk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 4 "cfg_cska"; + .port_info 3 /INPUT 1 "wbd_clk_int"; + .port_info 4 /OUTPUT 1 "wbd_clk_out"; + .port_info 5 /INPUT 1 "dmem_req"; + .port_info 6 /INPUT 1 "dmem_cmd"; + .port_info 7 /INPUT 2 "dmem_width"; + .port_info 8 /INPUT 5 "dmem_addr"; + .port_info 9 /INPUT 32 "dmem_wdata"; + .port_info 10 /OUTPUT 1 "dmem_req_ack"; + .port_info 11 /OUTPUT 32 "dmem_rdata"; + .port_info 12 /OUTPUT 2 "dmem_resp"; +P_0x5570afaae460 .param/l "WB_WIDTH" 0 4 39, +C4<00000000000000000000000000100000>; +L_0x5570afb69190 .functor BUFT 4, v0x5570afb4ef20_0, C4<0000>, C4<0000>, C4<0000>; +o0x7f116f7d1018 .functor BUFZ 4, C4<zzzz>; HiZ drive +v0x5570afb4ee80_0 .net "cfg_cska", 3 0, o0x7f116f7d1018; 0 drivers +v0x5570afb4ef20_0 .var "cfg_fpu_cmd", 3 0; +v0x5570afb4efc0_0 .net "cfg_fpu_din1", 31 0, L_0x5570afb67d50; 1 drivers +v0x5570afb4f060_0 .net "cfg_fpu_din2", 31 0, L_0x5570afb67fd0; 1 drivers +v0x5570afb4f100_0 .net "cfg_fpu_val", 0 0, L_0x5570afb578c0; 1 drivers +o0x7f116f7cec18 .functor BUFZ 5, C4<zzzzz>; HiZ drive +v0x5570afb4f240_0 .net "dmem_addr", 4 0, o0x7f116f7cec18; 0 drivers +o0x7f116f7cec78 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb4f2e0_0 .net "dmem_cmd", 0 0, o0x7f116f7cec78; 0 drivers +v0x5570afb4f380_0 .net "dmem_rdata", 31 0, v0x5570afb3fbe0_0; 1 drivers +o0x7f116f7cecd8 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb4f420_0 .net "dmem_req", 0 0, o0x7f116f7cecd8; 0 drivers +v0x5570afb4f4c0_0 .net "dmem_req_ack", 0 0, v0x5570afb3fd80_0; 1 drivers +v0x5570afb4f560_0 .net "dmem_resp", 1 0, v0x5570afb3fe40_0; 1 drivers +o0x7f116f7ced68 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive +v0x5570afb4f600_0 .net "dmem_wdata", 31 0, o0x7f116f7ced68; 0 drivers +o0x7f116f7ced98 .functor BUFZ 2, C4<zz>; HiZ drive +v0x5570afb4f6a0_0 .net "dmem_width", 1 0, o0x7f116f7ced98; 0 drivers +v0x5570afb4f740_0 .net "fpu_done", 0 0, L_0x5570afb6ad00; 1 drivers +v0x5570afb4f7e0_0 .net "fpu_result", 31 0, L_0x5570afb6be10; 1 drivers +o0x7f116f7cb4f8 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb4f880_0 .net "mclk", 0 0, o0x7f116f7cb4f8; 0 drivers +o0x7f116f7cb3a8 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb4fb30_0 .net "rst_n", 0 0, o0x7f116f7cb3a8; 0 drivers +v0x5570afb4fc20_0 .net "rst_ss_n", 0 0, L_0x5570afb6a800; 1 drivers +o0x7f116f7cf368 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb4fcc0_0 .net "wbd_clk_int", 0 0, o0x7f116f7cf368; 0 drivers +v0x5570afb4fdb0_0 .net "wbd_clk_out", 0 0, L_0x5570afb55560; 1 drivers +S_0x5570afaaf280 .scope module, "u_app_rst" "reset_sync" 4 92, 5 66 0, S_0x5570afab6020; + .timescale 0 0; + .port_info 0 /INPUT 1 "scan_mode"; + .port_info 1 /INPUT 1 "dclk"; + .port_info 2 /INPUT 1 "arst_n"; + .port_info 3 /OUTPUT 1 "srst_n"; +P_0x5570afb29ea0 .param/l "WIDTH" 0 5 73, +C4<00000000000000000000000000000001>; +v0x5570afb2a5a0_0 .net "arst_n", 0 0, o0x7f116f7cb3a8; alias, 0 drivers +v0x5570afb2a660_0 .net "dclk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb2a700_0 .var "in_data_2s", 0 0; +v0x5570afb2a800_0 .var "in_data_s", 0 0; +L_0x7f116f782018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x5570afb2a8a0_0 .net "scan_mode", 0 0, L_0x7f116f782018; 1 drivers +v0x5570afb2a990_0 .net "srst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +E_0x5570afb29f70/0 .event negedge, v0x5570afb2a260_0; +E_0x5570afb29f70/1 .event posedge, v0x5570afb2a660_0; +E_0x5570afb29f70 .event/or E_0x5570afb29f70/0, E_0x5570afb29f70/1; +S_0x5570afab40a0 .scope module, "u_buf" "ctech_mux2x1" 5 99, 3 2 0, S_0x5570afaaf280; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb2a060 .param/l "WB" 0 3 2, +C4<00000000000000000000000000000001>; +L_0x5570afb6a800 .functor BUFT 1, v0x5570afb2a700_0, C4<0>, C4<0>, C4<0>; +v0x5570afb2a160_0 .net "A0", 0 0, v0x5570afb2a700_0; 1 drivers +v0x5570afb2a260_0 .net "A1", 0 0, o0x7f116f7cb3a8; alias, 0 drivers +v0x5570afb2a340_0 .net "S", 0 0, L_0x7f116f782018; alias, 1 drivers +v0x5570afb2a410_0 .net "X", 0 0, L_0x5570afb6a800; alias, 1 drivers +S_0x5570afab4420 .scope module, "u_fpu_core" "fpu_sp_top" 4 129, 6 62 0, S_0x5570afab6020; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 4 "cmd"; + .port_info 3 /INPUT 32 "din1"; + .port_info 4 /INPUT 32 "din2"; + .port_info 5 /INPUT 1 "dval"; + .port_info 6 /OUTPUT 32 "result"; + .port_info 7 /OUTPUT 1 "rdy"; +P_0x5570afb2ab20 .param/l "CMD_FPU_DP_ADD" 0 7 6, C4<1001>; +P_0x5570afb2ab60 .param/l "CMD_FPU_DP_DIV" 0 7 8, C4<1011>; +P_0x5570afb2aba0 .param/l "CMD_FPU_DP_MUL" 0 7 7, C4<1010>; +P_0x5570afb2abe0 .param/l "CMD_FPU_SP_ADD" 0 7 1, C4<0001>; +P_0x5570afb2ac20 .param/l "CMD_FPU_SP_DIV" 0 7 3, C4<0011>; +P_0x5570afb2ac60 .param/l "CMD_FPU_SP_F2I" 0 7 4, C4<0100>; +P_0x5570afb2aca0 .param/l "CMD_FPU_SP_I2F" 0 7 5, C4<0101>; +P_0x5570afb2ace0 .param/l "CMD_FPU_SP_MUL" 0 7 2, C4<0010>; +L_0x5570afb69360 .functor AND 1, L_0x5570afb578c0, L_0x5570afb69290, C4<1>, C4<1>; +L_0x5570afb695e0 .functor AND 1, L_0x5570afb578c0, L_0x5570afb694b0, C4<1>, C4<1>; +L_0x5570afb697e0 .functor AND 1, L_0x5570afb578c0, L_0x5570afb696f0, C4<1>, C4<1>; +L_0x5570afb69a10 .functor AND 1, L_0x5570afb578c0, L_0x5570afb698f0, C4<1>, C4<1>; +L_0x5570afb69c40 .functor AND 1, L_0x5570afb578c0, L_0x5570afb69b50, C4<1>, C4<1>; +L_0x7f116f7822e8 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>; +v0x5570afb338b0_0 .net/2u *"_ivl_0", 3 0, L_0x7f116f7822e8; 1 drivers +L_0x7f116f782378 .functor BUFT 1, C4<0011>, C4<0>, C4<0>, C4<0>; +v0x5570afb339b0_0 .net/2u *"_ivl_12", 3 0, L_0x7f116f782378; 1 drivers +v0x5570afb33a90_0 .net *"_ivl_14", 0 0, L_0x5570afb696f0; 1 drivers +L_0x7f116f7823c0 .functor BUFT 1, C4<0100>, C4<0>, C4<0>, C4<0>; +v0x5570afb33b30_0 .net/2u *"_ivl_18", 3 0, L_0x7f116f7823c0; 1 drivers +v0x5570afb33c10_0 .net *"_ivl_2", 0 0, L_0x5570afb69290; 1 drivers +v0x5570afb33cd0_0 .net *"_ivl_20", 0 0, L_0x5570afb698f0; 1 drivers +L_0x7f116f782408 .functor BUFT 1, C4<0101>, C4<0>, C4<0>, C4<0>; +v0x5570afb33d90_0 .net/2u *"_ivl_24", 3 0, L_0x7f116f782408; 1 drivers +v0x5570afb33e70_0 .net *"_ivl_26", 0 0, L_0x5570afb69b50; 1 drivers +L_0x7f116f782450 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>; +v0x5570afb33f30_0 .net/2u *"_ivl_30", 3 0, L_0x7f116f782450; 1 drivers +v0x5570afb34010_0 .net *"_ivl_32", 0 0, L_0x5570afb69e60; 1 drivers +L_0x7f116f782498 .functor BUFT 1, C4<0010>, C4<0>, C4<0>, C4<0>; +v0x5570afb340d0_0 .net/2u *"_ivl_34", 3 0, L_0x7f116f782498; 1 drivers +v0x5570afb341b0_0 .net *"_ivl_36", 0 0, L_0x5570afb6a1b0; 1 drivers +L_0x7f116f7824e0 .functor BUFT 1, C4<0011>, C4<0>, C4<0>, C4<0>; +v0x5570afb34270_0 .net/2u *"_ivl_38", 3 0, L_0x7f116f7824e0; 1 drivers +v0x5570afb34350_0 .net *"_ivl_40", 0 0, L_0x5570afb6a2a0; 1 drivers +L_0x7f116f782528 .functor BUFT 1, C4<0100>, C4<0>, C4<0>, C4<0>; +v0x5570afb34410_0 .net/2u *"_ivl_42", 3 0, L_0x7f116f782528; 1 drivers +v0x5570afb344f0_0 .net *"_ivl_44", 0 0, L_0x5570afb6a3e0; 1 drivers +L_0x7f116f782570 .functor BUFT 1, C4<0101>, C4<0>, C4<0>, C4<0>; +v0x5570afb345b0_0 .net/2u *"_ivl_46", 3 0, L_0x7f116f782570; 1 drivers +v0x5570afb347a0_0 .net *"_ivl_48", 0 0, L_0x5570afb6a4d0; 1 drivers +L_0x7f116f7825b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x5570afb34860_0 .net/2u *"_ivl_50", 0 0, L_0x7f116f7825b8; 1 drivers +v0x5570afb34940_0 .net *"_ivl_52", 0 0, L_0x5570afb6a620; 1 drivers +v0x5570afb34a20_0 .net *"_ivl_54", 0 0, L_0x5570afb6a760; 1 drivers +v0x5570afb34b00_0 .net *"_ivl_56", 0 0, L_0x5570afb6a960; 1 drivers +v0x5570afb34be0_0 .net *"_ivl_58", 0 0, L_0x5570afb6aaf0; 1 drivers +L_0x7f116f782330 .functor BUFT 1, C4<0010>, C4<0>, C4<0>, C4<0>; +v0x5570afb34cc0_0 .net/2u *"_ivl_6", 3 0, L_0x7f116f782330; 1 drivers +L_0x7f116f782600 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>; +v0x5570afb34da0_0 .net/2u *"_ivl_62", 3 0, L_0x7f116f782600; 1 drivers +v0x5570afb34e80_0 .net *"_ivl_64", 0 0, L_0x5570afb6ae40; 1 drivers +L_0x7f116f782648 .functor BUFT 1, C4<0010>, C4<0>, C4<0>, C4<0>; +v0x5570afb34f40_0 .net/2u *"_ivl_66", 3 0, L_0x7f116f782648; 1 drivers +v0x5570afb35020_0 .net *"_ivl_68", 0 0, L_0x5570afb6afc0; 1 drivers +L_0x7f116f782690 .functor BUFT 1, C4<0011>, C4<0>, C4<0>, C4<0>; +v0x5570afb350e0_0 .net/2u *"_ivl_70", 3 0, L_0x7f116f782690; 1 drivers +v0x5570afb351c0_0 .net *"_ivl_72", 0 0, L_0x5570afb6b0b0; 1 drivers +L_0x7f116f7826d8 .functor BUFT 1, C4<0100>, C4<0>, C4<0>, C4<0>; +v0x5570afb35280_0 .net/2u *"_ivl_74", 3 0, L_0x7f116f7826d8; 1 drivers +v0x5570afb35360_0 .net *"_ivl_76", 0 0, L_0x5570afb6b240; 1 drivers +L_0x7f116f782720 .functor BUFT 1, C4<0101>, C4<0>, C4<0>, C4<0>; +v0x5570afb35420_0 .net/2u *"_ivl_78", 3 0, L_0x7f116f782720; 1 drivers +v0x5570afb35710_0 .net *"_ivl_8", 0 0, L_0x5570afb694b0; 1 drivers +v0x5570afb357d0_0 .net *"_ivl_80", 0 0, L_0x5570afb6b540; 1 drivers +L_0x7f116f782768 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5570afb35890_0 .net/2u *"_ivl_82", 31 0, L_0x7f116f782768; 1 drivers +v0x5570afb35970_0 .net *"_ivl_84", 31 0, L_0x5570afb6b1a0; 1 drivers +v0x5570afb35a50_0 .net *"_ivl_86", 31 0, L_0x5570afb6b7d0; 1 drivers +v0x5570afb35b30_0 .net *"_ivl_88", 31 0, L_0x5570afb6ba20; 1 drivers +v0x5570afb35c10_0 .net *"_ivl_90", 31 0, L_0x5570afb6bbb0; 1 drivers +v0x5570afb35cf0_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb35d90_0 .net "cmd", 3 0, v0x5570afb4ef20_0; 1 drivers +v0x5570afb35e70_0 .net "din1", 31 0, L_0x5570afb67d50; alias, 1 drivers +v0x5570afb35f30_0 .net "din2", 31 0, L_0x5570afb67fd0; alias, 1 drivers +v0x5570afb35ff0_0 .net "dval", 0 0, L_0x5570afb578c0; alias, 1 drivers +v0x5570afb360b0_0 .net "rdy", 0 0, L_0x5570afb6ad00; alias, 1 drivers +v0x5570afb36170_0 .net "result", 31 0, L_0x5570afb6be10; alias, 1 drivers +v0x5570afb36250_0 .net "rst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb362f0_0 .net "sp_add_dval", 0 0, L_0x5570afb69360; 1 drivers +v0x5570afb36390_0 .net "sp_add_rdy", 0 0, v0x5570afb2c6e0_0; 1 drivers +v0x5570afb36430_0 .net "sp_add_result", 31 0, v0x5570afb2c7a0_0; 1 drivers +v0x5570afb364d0_0 .net "sp_div_dval", 0 0, L_0x5570afb697e0; 1 drivers +v0x5570afb36570_0 .net "sp_div_rdy", 0 0, v0x5570afb2eac0_0; 1 drivers +v0x5570afb36640_0 .net "sp_div_result", 31 0, v0x5570afb2ec60_0; 1 drivers +v0x5570afb36710_0 .net "sp_f2i_dval", 0 0, L_0x5570afb69a10; 1 drivers +v0x5570afb367e0_0 .net "sp_f2i_rdy", 0 0, v0x5570afb2ff90_0; 1 drivers +v0x5570afb368b0_0 .net "sp_f2i_result", 31 0, v0x5570afb30050_0; 1 drivers +v0x5570afb36980_0 .net "sp_i2f_dval", 0 0, L_0x5570afb69c40; 1 drivers +v0x5570afb36a50_0 .net "sp_i2f_rdy", 0 0, v0x5570afb30c00_0; 1 drivers +v0x5570afb36b20_0 .net "sp_i2f_result", 31 0, v0x5570afb30cc0_0; 1 drivers +v0x5570afb36bf0_0 .net "sp_mul_dval", 0 0, L_0x5570afb695e0; 1 drivers +v0x5570afb36cc0_0 .net "sp_mul_rdy", 0 0, v0x5570afb32e80_0; 1 drivers +v0x5570afb36d90_0 .net "sp_mul_result", 31 0, v0x5570afb32f40_0; 1 drivers +L_0x5570afb69290 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f7822e8; +L_0x5570afb694b0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782330; +L_0x5570afb696f0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782378; +L_0x5570afb698f0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f7823c0; +L_0x5570afb69b50 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782408; +L_0x5570afb69e60 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782450; +L_0x5570afb6a1b0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782498; +L_0x5570afb6a2a0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f7824e0; +L_0x5570afb6a3e0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782528; +L_0x5570afb6a4d0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782570; +L_0x5570afb6a620 .functor MUXZ 1, L_0x7f116f7825b8, v0x5570afb30c00_0, L_0x5570afb6a4d0, C4<>; +L_0x5570afb6a760 .functor MUXZ 1, L_0x5570afb6a620, v0x5570afb2ff90_0, L_0x5570afb6a3e0, C4<>; +L_0x5570afb6a960 .functor MUXZ 1, L_0x5570afb6a760, v0x5570afb2eac0_0, L_0x5570afb6a2a0, C4<>; +L_0x5570afb6aaf0 .functor MUXZ 1, L_0x5570afb6a960, v0x5570afb32e80_0, L_0x5570afb6a1b0, C4<>; +L_0x5570afb6ad00 .functor MUXZ 1, L_0x5570afb6aaf0, v0x5570afb2c6e0_0, L_0x5570afb69e60, C4<>; +L_0x5570afb6ae40 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782600; +L_0x5570afb6afc0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782648; +L_0x5570afb6b0b0 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782690; +L_0x5570afb6b240 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f7826d8; +L_0x5570afb6b540 .cmp/eq 4, v0x5570afb4ef20_0, L_0x7f116f782720; +L_0x5570afb6b1a0 .functor MUXZ 32, L_0x7f116f782768, v0x5570afb30cc0_0, L_0x5570afb6b540, C4<>; +L_0x5570afb6b7d0 .functor MUXZ 32, L_0x5570afb6b1a0, v0x5570afb30050_0, L_0x5570afb6b240, C4<>; +L_0x5570afb6ba20 .functor MUXZ 32, L_0x5570afb6b7d0, v0x5570afb2ec60_0, L_0x5570afb6b0b0, C4<>; +L_0x5570afb6bbb0 .functor MUXZ 32, L_0x5570afb6ba20, v0x5570afb32f40_0, L_0x5570afb6afc0, C4<>; +L_0x5570afb6be10 .functor MUXZ 32, L_0x5570afb6bbb0, v0x5570afb2c7a0_0, L_0x5570afb6ae40, C4<>; +S_0x5570afab47a0 .scope module, "u_sp_add" "fpu_sp_add" 6 127, 8 41 0, S_0x5570afab4420; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 32 "din1"; + .port_info 3 /INPUT 32 "din2"; + .port_info 4 /INPUT 1 "dval"; + .port_info 5 /OUTPUT 32 "result"; + .port_info 6 /OUTPUT 1 "rdy"; +P_0x5570afb2b220 .param/l "ADD_0" 0 8 58, C4<0100>; +P_0x5570afb2b260 .param/l "ADD_1" 0 8 59, C4<0101>; +P_0x5570afb2b2a0 .param/l "ALIGN" 0 8 57, C4<0011>; +P_0x5570afb2b2e0 .param/l "NORMALISE_1" 0 8 60, C4<0110>; +P_0x5570afb2b320 .param/l "NORMALISE_2" 0 8 61, C4<0111>; +P_0x5570afb2b360 .param/l "OUT_RDY" 0 8 64, C4<1010>; +P_0x5570afb2b3a0 .param/l "PACK" 0 8 63, C4<1001>; +P_0x5570afb2b3e0 .param/l "ROUND" 0 8 62, C4<1000>; +P_0x5570afb2b420 .param/l "SPECIAL_CASES" 0 8 56, C4<0010>; +P_0x5570afb2b460 .param/l "UNPACK" 0 8 55, C4<0001>; +P_0x5570afb2b4a0 .param/l "WAIT_REQ" 0 8 54, C4<0000>; +v0x5570afb2bb30_0 .var "a", 31 0; +v0x5570afb2bc30_0 .var "a_e", 9 0; +v0x5570afb2bd10_0 .var "a_m", 26 0; +v0x5570afb2bdd0_0 .var "a_s", 0 0; +v0x5570afb2be90_0 .var "b", 31 0; +v0x5570afb2bfc0_0 .var "b_e", 9 0; +v0x5570afb2c0a0_0 .var "b_m", 26 0; +v0x5570afb2c180_0 .var "b_s", 0 0; +v0x5570afb2c240_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb2c2e0_0 .net "din1", 31 0, L_0x5570afb67d50; alias, 1 drivers +v0x5570afb2c3a0_0 .net "din2", 31 0, L_0x5570afb67fd0; alias, 1 drivers +v0x5570afb2c480_0 .net "dval", 0 0, L_0x5570afb69360; alias, 1 drivers +v0x5570afb2c540_0 .var "guard", 0 0; +v0x5570afb2c600_0 .var "pre_sum", 27 0; +v0x5570afb2c6e0_0 .var "rdy", 0 0; +v0x5570afb2c7a0_0 .var "result", 31 0; +v0x5570afb2c880_0 .var "round_bit", 0 0; +v0x5570afb2ca50_0 .net "rst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb2caf0_0 .var "state", 3 0; +v0x5570afb2cbd0_0 .var "sticky", 0 0; +v0x5570afb2cc90_0 .var "z", 31 0; +v0x5570afb2cd70_0 .var "z_e", 9 0; +v0x5570afb2ce50_0 .var "z_m", 23 0; +v0x5570afb2cf30_0 .var "z_s", 0 0; +E_0x5570afb2bad0/0 .event negedge, v0x5570afb2a410_0; +E_0x5570afb2bad0/1 .event posedge, v0x5570afb2a660_0; +E_0x5570afb2bad0 .event/or E_0x5570afb2bad0/0, E_0x5570afb2bad0/1; +S_0x5570afab4b20 .scope module, "u_sp_div" "fpu_sp_div" 6 149, 9 39 0, S_0x5570afab4420; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 32 "din1"; + .port_info 3 /INPUT 32 "din2"; + .port_info 4 /INPUT 1 "dval"; + .port_info 5 /OUTPUT 32 "result"; + .port_info 6 /OUTPUT 1 "rdy"; +P_0x5570afb2d180 .param/l "DIVIDE_0" 0 9 56, C4<0101>; +P_0x5570afb2d1c0 .param/l "DIVIDE_1" 0 9 57, C4<0110>; +P_0x5570afb2d200 .param/l "DIVIDE_2" 0 9 58, C4<0111>; +P_0x5570afb2d240 .param/l "DIVIDE_3" 0 9 59, C4<1000>; +P_0x5570afb2d280 .param/l "NORMALISE_1" 0 9 60, C4<1001>; +P_0x5570afb2d2c0 .param/l "NORMALISE_2" 0 9 61, C4<1010>; +P_0x5570afb2d300 .param/l "NORMALISE_A" 0 9 54, C4<0011>; +P_0x5570afb2d340 .param/l "NORMALISE_B" 0 9 55, C4<0100>; +P_0x5570afb2d380 .param/l "OUT_RDY" 0 9 64, C4<1101>; +P_0x5570afb2d3c0 .param/l "PACK" 0 9 63, C4<1100>; +P_0x5570afb2d400 .param/l "ROUND" 0 9 62, C4<1011>; +P_0x5570afb2d440 .param/l "SPECIAL_CASES" 0 9 53, C4<0010>; +P_0x5570afb2d480 .param/l "UNPACK" 0 9 52, C4<0001>; +P_0x5570afb2d4c0 .param/l "WAIT_REQ" 0 9 51, C4<0000>; +v0x5570afb2dbe0_0 .var "a", 31 0; +v0x5570afb2dcc0_0 .var "a_e", 9 0; +v0x5570afb2dda0_0 .var "a_m", 23 0; +v0x5570afb2de60_0 .var "a_s", 0 0; +v0x5570afb2df20_0 .var "b", 31 0; +v0x5570afb2e050_0 .var "b_e", 9 0; +v0x5570afb2e130_0 .var "b_m", 23 0; +v0x5570afb2e210_0 .var "b_s", 0 0; +v0x5570afb2e2d0_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb2e370_0 .var "count", 5 0; +v0x5570afb2e450_0 .net "din1", 31 0, L_0x5570afb67d50; alias, 1 drivers +v0x5570afb2e510_0 .net "din2", 31 0, L_0x5570afb67fd0; alias, 1 drivers +v0x5570afb2e5b0_0 .var "dividend", 50 0; +v0x5570afb2e670_0 .var "divisor", 50 0; +v0x5570afb2e750_0 .net "dval", 0 0, L_0x5570afb697e0; alias, 1 drivers +v0x5570afb2e810_0 .var "guard", 0 0; +v0x5570afb2e8d0_0 .var "quotient", 50 0; +v0x5570afb2eac0_0 .var "rdy", 0 0; +v0x5570afb2eb80_0 .var "remainder", 50 0; +v0x5570afb2ec60_0 .var "result", 31 0; +v0x5570afb2ed40_0 .var "round_bit", 0 0; +v0x5570afb2ee00_0 .net "rst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb2eea0_0 .var "state", 3 0; +v0x5570afb2ef80_0 .var "sticky", 0 0; +v0x5570afb2f040_0 .var "z", 31 0; +v0x5570afb2f120_0 .var "z_e", 9 0; +v0x5570afb2f200_0 .var "z_m", 23 0; +v0x5570afb2f2e0_0 .var "z_s", 0 0; +S_0x5570afab4ea0 .scope module, "u_sp_f2i" "fpu_sp_f2i" 6 160, 10 39 0, S_0x5570afab4420; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 32 "din"; + .port_info 3 /INPUT 1 "dval"; + .port_info 4 /OUTPUT 32 "result"; + .port_info 5 /OUTPUT 1 "rdy"; +P_0x5570afb2f540 .param/l "CONVERT" 0 10 53, C4<011>; +P_0x5570afb2f580 .param/l "OUT_RDY" 0 10 54, C4<100>; +P_0x5570afb2f5c0 .param/l "SPECIAL_CASES" 0 10 51, C4<001>; +P_0x5570afb2f600 .param/l "UNPACK" 0 10 52, C4<010>; +P_0x5570afb2f640 .param/l "WAIT_REQ" 0 10 50, C4<000>; +v0x5570afb2f960_0 .var "a", 31 0; +v0x5570afb2fa40_0 .var "a_e", 8 0; +v0x5570afb2fb20_0 .var "a_m", 31 0; +v0x5570afb2fc10_0 .var "a_s", 0 0; +v0x5570afb2fcd0_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb2fdc0_0 .net "din", 31 0, L_0x5570afb67d50; alias, 1 drivers +v0x5570afb2fed0_0 .net "dval", 0 0, L_0x5570afb69a10; alias, 1 drivers +v0x5570afb2ff90_0 .var "rdy", 0 0; +v0x5570afb30050_0 .var "result", 31 0; +v0x5570afb30130_0 .net "rst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb301d0_0 .var "state", 2 0; +v0x5570afb302b0_0 .var "z", 31 0; +S_0x5570afab5220 .scope module, "u_sp_i2f" "fpu_sp_i2f" 6 169, 11 39 0, S_0x5570afab4420; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 32 "din"; + .port_info 3 /INPUT 1 "dval"; + .port_info 4 /OUTPUT 32 "result"; + .port_info 5 /OUTPUT 1 "rdy"; +P_0x5570af9511e0 .param/l "CONVERT_0" 0 11 51, C4<001>; +P_0x5570af951220 .param/l "CONVERT_1" 0 11 52, C4<010>; +P_0x5570af951260 .param/l "CONVERT_2" 0 11 53, C4<011>; +P_0x5570af9512a0 .param/l "OUT_RDY" 0 11 56, C4<110>; +P_0x5570af9512e0 .param/l "PACK" 0 11 55, C4<101>; +P_0x5570af951320 .param/l "ROUND" 0 11 54, C4<100>; +P_0x5570af951360 .param/l "WAIT_REQ" 0 11 50, C4<000>; +v0x5570afb30860_0 .var "a", 31 0; +v0x5570afb30940_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb30a00_0 .net "din", 31 0, L_0x5570afb67d50; alias, 1 drivers +v0x5570afb30aa0_0 .net "dval", 0 0, L_0x5570afb69c40; alias, 1 drivers +v0x5570afb30b40_0 .var "guard", 0 0; +v0x5570afb30c00_0 .var "rdy", 0 0; +v0x5570afb30cc0_0 .var "result", 31 0; +v0x5570afb30da0_0 .var "round_bit", 0 0; +v0x5570afb30e60_0 .net "rst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb30f00_0 .var "state", 2 0; +v0x5570afb30fe0_0 .var "sticky", 0 0; +v0x5570afb310a0_0 .var "value", 31 0; +v0x5570afb31180_0 .var "z", 31 0; +v0x5570afb31260_0 .var "z_e", 7 0; +v0x5570afb31340_0 .var "z_m", 23 0; +v0x5570afb31420_0 .var "z_r", 7 0; +v0x5570afb31500_0 .var "z_s", 0 0; +S_0x5570afb317d0 .scope module, "u_sp_mul" "fpu_sp_mul" 6 138, 12 39 0, S_0x5570afab4420; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 32 "din1"; + .port_info 3 /INPUT 32 "din2"; + .port_info 4 /INPUT 1 "dval"; + .port_info 5 /OUTPUT 32 "result"; + .port_info 6 /OUTPUT 1 "rdy"; +P_0x5570afb31960 .param/l "MULTIPLY_0" 0 12 60, C4<0101>; +P_0x5570afb319a0 .param/l "MULTIPLY_1" 0 12 61, C4<0110>; +P_0x5570afb319e0 .param/l "NORMALISE_1" 0 12 62, C4<0111>; +P_0x5570afb31a20 .param/l "NORMALISE_2" 0 12 63, C4<1000>; +P_0x5570afb31a60 .param/l "NORMALISE_A" 0 12 58, C4<0011>; +P_0x5570afb31aa0 .param/l "NORMALISE_B" 0 12 59, C4<0100>; +P_0x5570afb31ae0 .param/l "OUT_RDY" 0 12 66, C4<1011>; +P_0x5570afb31b20 .param/l "PACK" 0 12 65, C4<1010>; +P_0x5570afb31b60 .param/l "ROUND" 0 12 64, C4<1001>; +P_0x5570afb31ba0 .param/l "SPECIAL_CASES" 0 12 57, C4<0010>; +P_0x5570afb31be0 .param/l "UNPACK" 0 12 56, C4<0001>; +P_0x5570afb31c20 .param/l "WAIT_REQ" 0 12 55, C4<0000>; +v0x5570afb32280_0 .var "a", 31 0; +v0x5570afb32360_0 .var "a_e", 9 0; +v0x5570afb32440_0 .var "a_m", 23 0; +v0x5570afb32500_0 .var "a_s", 0 0; +v0x5570afb325c0_0 .var "b", 31 0; +v0x5570afb326f0_0 .var "b_e", 9 0; +v0x5570afb327d0_0 .var "b_m", 23 0; +v0x5570afb328b0_0 .var "b_s", 0 0; +v0x5570afb32970_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb32a10_0 .net "din1", 31 0, L_0x5570afb67d50; alias, 1 drivers +v0x5570afb32b60_0 .net "din2", 31 0, L_0x5570afb67fd0; alias, 1 drivers +v0x5570afb32c20_0 .net "dval", 0 0, L_0x5570afb695e0; alias, 1 drivers +v0x5570afb32ce0_0 .var "guard", 0 0; +v0x5570afb32da0_0 .var "product", 47 0; +v0x5570afb32e80_0 .var "rdy", 0 0; +v0x5570afb32f40_0 .var "result", 31 0; +v0x5570afb33020_0 .var "round_bit", 0 0; +v0x5570afb331f0_0 .net "rst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb33290_0 .var "state", 3 0; +v0x5570afb33370_0 .var "sticky", 0 0; +v0x5570afb33430_0 .var "z", 31 0; +v0x5570afb33510_0 .var "z_e", 9 0; +v0x5570afb335f0_0 .var "z_m", 23 0; +v0x5570afb336d0_0 .var "z_s", 0 0; +S_0x5570afb36e60 .scope module, "u_reg" "fpu_reg" 4 103, 13 37 0, S_0x5570afab6020; + .timescale 0 0; + .port_info 0 /INPUT 1 "mclk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 1 "dmem_req"; + .port_info 3 /INPUT 1 "dmem_cmd"; + .port_info 4 /INPUT 2 "dmem_width"; + .port_info 5 /INPUT 5 "dmem_addr"; + .port_info 6 /INPUT 32 "dmem_wdata"; + .port_info 7 /OUTPUT 1 "dmem_req_ack"; + .port_info 8 /OUTPUT 32 "dmem_rdata"; + .port_info 9 /OUTPUT 2 "dmem_resp"; + .port_info 10 /OUTPUT 1 "cfg_fpu_val"; + .port_info 11 /INPUT 1 "fpu_done"; + .port_info 12 /INPUT 4 "cfg_fpu_cmd"; + .port_info 13 /OUTPUT 32 "cfg_fpu_din1"; + .port_info 14 /OUTPUT 32 "cfg_fpu_din2"; + .port_info 15 /INPUT 32 "fpu_result"; +L_0x5570afb56000 .functor AND 1, v0x5570afb40c30_0, v0x5570afb415d0_0, C4<1>, C4<1>; +L_0x5570afb56110 .functor AND 1, L_0x5570afb56000, L_0x5570afb56070, C4<1>, C4<1>; +L_0x5570afb56180 .functor AND 1, v0x5570afb40c30_0, v0x5570afb415d0_0, C4<1>, C4<1>; +L_0x5570afb56330 .functor AND 1, L_0x5570afb56180, L_0x5570afb561f0, C4<1>, C4<1>; +L_0x5570afb56490 .functor AND 1, v0x5570afb40c30_0, v0x5570afb415d0_0, C4<1>, C4<1>; +L_0x5570afb565f0 .functor AND 1, L_0x5570afb56490, L_0x5570afb56500, C4<1>, C4<1>; +L_0x5570afb56790 .functor AND 1, v0x5570afb40c30_0, v0x5570afb415d0_0, C4<1>, C4<1>; +L_0x5570afb56a50 .functor AND 1, L_0x5570afb56790, L_0x5570afb56920, C4<1>, C4<1>; +L_0x5570afb56b60 .functor AND 1, v0x5570afb40c30_0, v0x5570afb40cf0_0, C4<1>, C4<1>; +L_0x5570afb56cc0 .functor AND 1, L_0x5570afb56b60, L_0x5570afb56bd0, C4<1>, C4<1>; +L_0x5570afb56e30 .functor AND 1, v0x5570afb40c30_0, v0x5570afb40cf0_0, C4<1>, C4<1>; +L_0x5570afb56fd0 .functor AND 1, L_0x5570afb56e30, L_0x5570afb56ea0, C4<1>, C4<1>; +L_0x5570afb57150 .functor AND 1, v0x5570afb40c30_0, v0x5570afb40cf0_0, C4<1>, C4<1>; +L_0x5570afb572b0 .functor AND 1, L_0x5570afb57150, L_0x5570afb571c0, C4<1>, C4<1>; +L_0x5570afb570e0 .functor AND 1, v0x5570afb40c30_0, v0x5570afb40cf0_0, C4<1>, C4<1>; +L_0x5570afb576d0 .functor AND 1, L_0x5570afb570e0, L_0x5570afb574d0, C4<1>, C4<1>; +L_0x5570afb578c0 .functor AND 1, v0x5570afb38cf0_0, L_0x5570afb57820, C4<1>, C4<1>; +L_0x5570afb579d0 .functor BUFZ 1, v0x5570afb38cf0_0, C4<0>, C4<0>, C4<0>; +RS_0x7f116f7ce138 .resolv tri, L_0x5570afb687b0, L_0x5570afb69190; +L_0x5570afb67c90 .functor BUFZ 4, RS_0x7f116f7ce138, C4<0000>, C4<0000>, C4<0000>; +L_0x5570afb67d50 .functor BUFZ 32, v0x5570afb3ca00_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x5570afb67fd0 .functor BUFZ 32, v0x5570afb3d350_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x5570afb68090 .functor BUFZ 32, L_0x5570afb6be10, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x5570afb68a10 .functor AND 1, L_0x5570afb56110, L_0x5570afb68940, C4<1>, C4<1>; +L_0x5570afb68ba0 .functor AND 1, L_0x5570afb56110, L_0x5570afb68cb0, C4<1>, C4<1>; +v0x5570afb3d6a0_0 .net *"_ivl_0", 0 0, L_0x5570afb56000; 1 drivers +L_0x7f116f7820a8 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>; +v0x5570afb3d7a0_0 .net/2u *"_ivl_10", 2 0, L_0x7f116f7820a8; 1 drivers +v0x5570afb3d880_0 .net *"_ivl_12", 0 0, L_0x5570afb561f0; 1 drivers +v0x5570afb3d950_0 .net *"_ivl_16", 0 0, L_0x5570afb56490; 1 drivers +L_0x7f116f7820f0 .functor BUFT 1, C4<010>, C4<0>, C4<0>, C4<0>; +v0x5570afb3da30_0 .net/2u *"_ivl_18", 2 0, L_0x7f116f7820f0; 1 drivers +L_0x7f116f782060 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x5570afb3db60_0 .net/2u *"_ivl_2", 2 0, L_0x7f116f782060; 1 drivers +v0x5570afb3dc40_0 .net *"_ivl_20", 0 0, L_0x5570afb56500; 1 drivers +v0x5570afb3dd00_0 .net *"_ivl_24", 0 0, L_0x5570afb56790; 1 drivers +L_0x7f116f782138 .functor BUFT 1, C4<011>, C4<0>, C4<0>, C4<0>; +v0x5570afb3dde0_0 .net/2u *"_ivl_26", 2 0, L_0x7f116f782138; 1 drivers +v0x5570afb3dec0_0 .net *"_ivl_28", 0 0, L_0x5570afb56920; 1 drivers +v0x5570afb3df80_0 .net *"_ivl_32", 0 0, L_0x5570afb56b60; 1 drivers +L_0x7f116f782180 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x5570afb3e060_0 .net/2u *"_ivl_34", 2 0, L_0x7f116f782180; 1 drivers +v0x5570afb3e140_0 .net *"_ivl_36", 0 0, L_0x5570afb56bd0; 1 drivers +v0x5570afb3e200_0 .net *"_ivl_4", 0 0, L_0x5570afb56070; 1 drivers +v0x5570afb3e2c0_0 .net *"_ivl_40", 0 0, L_0x5570afb56e30; 1 drivers +L_0x7f116f7821c8 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>; +v0x5570afb3e3a0_0 .net/2u *"_ivl_42", 2 0, L_0x7f116f7821c8; 1 drivers +v0x5570afb3e480_0 .net *"_ivl_44", 0 0, L_0x5570afb56ea0; 1 drivers +v0x5570afb3e650_0 .net *"_ivl_48", 0 0, L_0x5570afb57150; 1 drivers +L_0x7f116f782210 .functor BUFT 1, C4<010>, C4<0>, C4<0>, C4<0>; +v0x5570afb3e730_0 .net/2u *"_ivl_50", 2 0, L_0x7f116f782210; 1 drivers +v0x5570afb3e810_0 .net *"_ivl_52", 0 0, L_0x5570afb571c0; 1 drivers +v0x5570afb3e8d0_0 .net *"_ivl_56", 0 0, L_0x5570afb570e0; 1 drivers +L_0x7f116f782258 .functor BUFT 1, C4<011>, C4<0>, C4<0>, C4<0>; +v0x5570afb3e9b0_0 .net/2u *"_ivl_58", 2 0, L_0x7f116f782258; 1 drivers +v0x5570afb3ea90_0 .net *"_ivl_60", 0 0, L_0x5570afb574d0; 1 drivers +v0x5570afb3eb50_0 .net *"_ivl_65", 0 0, L_0x5570afb57820; 1 drivers +v0x5570afb3ec10_0 .net *"_ivl_71", 0 0, L_0x5570afb579d0; 1 drivers +L_0x7f116f7822a0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5570afb3ecf0_0 .net/2u *"_ivl_74", 26 0, L_0x7f116f7822a0; 1 drivers +v0x5570afb3edd0_0 .net *"_ivl_8", 0 0, L_0x5570afb56180; 1 drivers +v0x5570afb3eeb0_0 .net *"_ivl_80", 3 0, L_0x5570afb67c90; 1 drivers +v0x5570afb3ef90_0 .net *"_ivl_88", 0 0, L_0x5570afb68940; 1 drivers +v0x5570afb3f070_0 .net *"_ivl_89", 0 0, L_0x5570afb68a10; 1 drivers +v0x5570afb3f150_0 .net *"_ivl_96", 0 0, L_0x5570afb68cb0; 1 drivers +v0x5570afb3f230_0 .net *"_ivl_97", 0 0, L_0x5570afb68ba0; 1 drivers +v0x5570afb3f310_0 .net8 "cfg_fpu_cmd", 3 0, RS_0x7f116f7ce138; 2 drivers +v0x5570afb3f5e0_0 .net "cfg_fpu_din1", 31 0, L_0x5570afb67d50; alias, 1 drivers +v0x5570afb3f680_0 .net "cfg_fpu_din2", 31 0, L_0x5570afb67fd0; alias, 1 drivers +v0x5570afb3f740_0 .net "cfg_fpu_req", 0 0, v0x5570afb38cf0_0; 1 drivers +v0x5570afb3f810_0 .var "cfg_fpu_req_l", 0 0; +v0x5570afb3f8b0_0 .net "cfg_fpu_val", 0 0, L_0x5570afb578c0; alias, 1 drivers +v0x5570afb3f980_0 .net "dmem_addr", 4 0, o0x7f116f7cec18; alias, 0 drivers +v0x5570afb3fa40_0 .var "dmem_addr_l", 1 0; +v0x5570afb3fb20_0 .net "dmem_cmd", 0 0, o0x7f116f7cec78; alias, 0 drivers +v0x5570afb3fbe0_0 .var "dmem_rdata", 31 0; +v0x5570afb3fcc0_0 .net "dmem_req", 0 0, o0x7f116f7cecd8; alias, 0 drivers +v0x5570afb3fd80_0 .var "dmem_req_ack", 0 0; +v0x5570afb3fe40_0 .var "dmem_resp", 1 0; +v0x5570afb3ff20_0 .net "dmem_wdata", 31 0, o0x7f116f7ced68; alias, 0 drivers +v0x5570afb40000_0 .net "dmem_width", 1 0, o0x7f116f7ced98; alias, 0 drivers +v0x5570afb400e0_0 .var "dmem_width_l", 1 0; +v0x5570afb401c0_0 .net "fpu_done", 0 0, L_0x5570afb6ad00; alias, 1 drivers +v0x5570afb40260_0 .net "fpu_result", 31 0, L_0x5570afb6be10; alias, 1 drivers +v0x5570afb40320_0 .net "mclk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb403c0_0 .net "reg_0", 31 0, L_0x5570afb67af0; 1 drivers +v0x5570afb40480_0 .net "reg_1", 31 0, v0x5570afb3ca00_0; 1 drivers +v0x5570afb40570_0 .net "reg_2", 31 0, v0x5570afb3d350_0; 1 drivers +v0x5570afb40640_0 .net "reg_3", 31 0, L_0x5570afb68090; 1 drivers +v0x5570afb40700_0 .var "reg_out", 31 0; +v0x5570afb407e0_0 .net "rst_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb40a90_0 .var "sw_addr", 2 0; +v0x5570afb40b70_0 .var "sw_be", 3 0; +v0x5570afb40c30_0 .var "sw_cs", 0 0; +v0x5570afb40cf0_0 .var "sw_rd_en", 0 0; +v0x5570afb40db0_0 .net "sw_rd_en_0", 0 0, L_0x5570afb56cc0; 1 drivers +v0x5570afb40e70_0 .net "sw_rd_en_1", 0 0, L_0x5570afb56fd0; 1 drivers +v0x5570afb40f30_0 .net "sw_rd_en_2", 0 0, L_0x5570afb572b0; 1 drivers +v0x5570afb40ff0_0 .net "sw_rd_en_3", 0 0, L_0x5570afb576d0; 1 drivers +v0x5570afb414c0_0 .var "sw_reg_wdata", 31 0; +v0x5570afb415d0_0 .var "sw_wr_en", 0 0; +v0x5570afb41690_0 .net "sw_wr_en_0", 0 0, L_0x5570afb56110; 1 drivers +v0x5570afb41750_0 .net "sw_wr_en_1", 0 0, L_0x5570afb56330; 1 drivers +v0x5570afb417f0_0 .net "sw_wr_en_2", 0 0, L_0x5570afb565f0; 1 drivers +v0x5570afb41890_0 .net "sw_wr_en_3", 0 0, L_0x5570afb56a50; 1 drivers +E_0x5570afb2b9e0/0 .event anyedge, v0x5570afb40a90_0, v0x5570afb403c0_0, v0x5570afb3ca00_0, v0x5570afb3d350_0; +E_0x5570afb2b9e0/1 .event anyedge, v0x5570afb40640_0; +E_0x5570afb2b9e0 .event/or E_0x5570afb2b9e0/0, E_0x5570afb2b9e0/1; +L_0x5570afb56070 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f782060; +L_0x5570afb561f0 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f7820a8; +L_0x5570afb56500 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f7820f0; +L_0x5570afb56920 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f782138; +L_0x5570afb56bd0 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f782180; +L_0x5570afb56ea0 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f7821c8; +L_0x5570afb571c0 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f782210; +L_0x5570afb574d0 .cmp/eq 3, v0x5570afb40a90_0, L_0x7f116f782258; +L_0x5570afb57820 .reduce/nor v0x5570afb3f810_0; +L_0x5570afb67af0 .concat8 [ 4 27 1 0], L_0x5570afb67c90, L_0x7f116f7822a0, L_0x5570afb579d0; +L_0x5570afb68940 .part v0x5570afb40b70_0, 0, 1; +L_0x5570afb68ab0 .concat [ 1 1 1 1], L_0x5570afb68a10, L_0x5570afb68a10, L_0x5570afb68a10, L_0x5570afb68a10; +L_0x5570afb68c10 .part v0x5570afb414c0_0, 0, 4; +L_0x5570afb68cb0 .part v0x5570afb40b70_0, 3, 1; +L_0x5570afb68f30 .concat [ 1 0 0 0], L_0x5570afb68ba0; +L_0x5570afb68fd0 .part v0x5570afb414c0_0, 31, 1; +S_0x5570afb371e0 .scope autofunction.vec4.s4, "conv_bsel" "conv_bsel" 13 85, 13 85 0, S_0x5570afb36e60; + .timescale 0 0; +v0x5570afb373c0_0 .var "bsel", 3 0; +; Variable conv_bsel is vec4 return value of scope S_0x5570afb371e0 +v0x5570afb37580_0 .var "haddr", 1 0; +v0x5570afb37670_0 .var "hwidth", 1 0; +TD_fpu_wrapper.u_reg.conv_bsel ; + %pushi/vec4 15, 15, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %load/vec4 v0x5570afb37670_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_0.2, 6; + %jmp T_0.4; +T_0.0 ; + %load/vec4 v0x5570afb37580_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_0.7, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_0.8, 6; + %jmp T_0.9; +T_0.5 ; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %jmp T_0.9; +T_0.6 ; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %jmp T_0.9; +T_0.7 ; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %jmp T_0.9; +T_0.8 ; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %jmp T_0.9; +T_0.9 ; + %pop/vec4 1; + %jmp T_0.4; +T_0.1 ; + %load/vec4 v0x5570afb37580_0; + %parti/s 1, 1, 2; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_0.10, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_0.11, 6; + %jmp T_0.12; +T_0.10 ; + %pushi/vec4 3, 0, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %jmp T_0.12; +T_0.11 ; + %pushi/vec4 12, 0, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %jmp T_0.12; +T_0.12 ; + %pop/vec4 1; + %jmp T_0.4; +T_0.2 ; + %pushi/vec4 15, 0, 4; + %store/vec4 v0x5570afb373c0_0, 0, 4; + %jmp T_0.4; +T_0.4 ; + %pop/vec4 1; + %load/vec4 v0x5570afb373c0_0; + %ret/vec4 0, 0, 4; Assign to conv_bsel (store_vec4_to_lval) + %end; +S_0x5570afb37750 .scope autofunction.vec4.s32, "conv_rdata" "conv_rdata" 13 169, 13 169 0, S_0x5570afb36e60; + .timescale 0 0; +; Variable conv_rdata is vec4 return value of scope S_0x5570afb37750 +v0x5570afb37a30_0 .var "haddr", 1 0; +v0x5570afb37b10_0 .var "hrdata", 31 0; +v0x5570afb37c00_0 .var "hwidth", 1 0; +v0x5570afb37ce0_0 .var "tmp", 31 0; +TD_fpu_wrapper.u_reg.conv_rdata ; + %pushi/vec4 4294967295, 4294967295, 32; + %store/vec4 v0x5570afb37ce0_0, 0, 32; + %load/vec4 v0x5570afb37c00_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_1.13, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_1.14, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_1.15, 6; + %jmp T_1.17; +T_1.13 ; + %load/vec4 v0x5570afb37a30_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_1.18, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_1.19, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_1.20, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_1.21, 6; + %jmp T_1.23; +T_1.18 ; + %load/vec4 v0x5570afb37b10_0; + %parti/s 8, 0, 2; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb37ce0_0, 4, 8; + %jmp T_1.23; +T_1.19 ; + %load/vec4 v0x5570afb37b10_0; + %parti/s 8, 8, 5; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb37ce0_0, 4, 8; + %jmp T_1.23; +T_1.20 ; + %load/vec4 v0x5570afb37b10_0; + %parti/s 8, 16, 6; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb37ce0_0, 4, 8; + %jmp T_1.23; +T_1.21 ; + %load/vec4 v0x5570afb37b10_0; + %parti/s 8, 24, 6; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb37ce0_0, 4, 8; + %jmp T_1.23; +T_1.23 ; + %pop/vec4 1; + %jmp T_1.17; +T_1.14 ; + %load/vec4 v0x5570afb37a30_0; + %parti/s 1, 1, 2; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_1.24, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_1.25, 6; + %jmp T_1.27; +T_1.24 ; + %load/vec4 v0x5570afb37b10_0; + %parti/s 16, 0, 2; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb37ce0_0, 4, 16; + %jmp T_1.27; +T_1.25 ; + %load/vec4 v0x5570afb37b10_0; + %parti/s 16, 16, 6; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb37ce0_0, 4, 16; + %jmp T_1.27; +T_1.27 ; + %pop/vec4 1; + %jmp T_1.17; +T_1.15 ; + %load/vec4 v0x5570afb37b10_0; + %store/vec4 v0x5570afb37ce0_0, 0, 32; + %jmp T_1.17; +T_1.17 ; + %pop/vec4 1; + %load/vec4 v0x5570afb37ce0_0; + %ret/vec4 0, 0, 32; Assign to conv_rdata (store_vec4_to_lval) + %end; +S_0x5570afb37e10 .scope autofunction.vec4.s32, "conv_wdata" "conv_wdata" 13 119, 13 119 0, S_0x5570afb36e60; + .timescale 0 0; +; Variable conv_wdata is vec4 return value of scope S_0x5570afb37e10 +v0x5570afb380d0_0 .var "dmem_addr", 1 0; +v0x5570afb381b0_0 .var "dmem_wdata", 31 0; +v0x5570afb382a0_0 .var "dmem_width", 1 0; +v0x5570afb38380_0 .var "tmp", 31 0; +TD_fpu_wrapper.u_reg.conv_wdata ; + %pushi/vec4 4294967295, 4294967295, 32; + %store/vec4 v0x5570afb38380_0, 0, 32; + %load/vec4 v0x5570afb382a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_2.28, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_2.29, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_2.30, 6; + %jmp T_2.32; +T_2.28 ; + %load/vec4 v0x5570afb380d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_2.33, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_2.34, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_2.35, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_2.36, 6; + %jmp T_2.38; +T_2.33 ; + %load/vec4 v0x5570afb381b0_0; + %parti/s 8, 0, 2; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb38380_0, 4, 8; + %jmp T_2.38; +T_2.34 ; + %load/vec4 v0x5570afb381b0_0; + %parti/s 8, 0, 2; + %ix/load 4, 8, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb38380_0, 4, 8; + %jmp T_2.38; +T_2.35 ; + %load/vec4 v0x5570afb381b0_0; + %parti/s 8, 0, 2; + %ix/load 4, 16, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb38380_0, 4, 8; + %jmp T_2.38; +T_2.36 ; + %load/vec4 v0x5570afb381b0_0; + %parti/s 8, 0, 2; + %ix/load 4, 24, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb38380_0, 4, 8; + %jmp T_2.38; +T_2.38 ; + %pop/vec4 1; + %jmp T_2.32; +T_2.29 ; + %load/vec4 v0x5570afb380d0_0; + %parti/s 1, 1, 2; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_2.39, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_2.40, 6; + %jmp T_2.42; +T_2.39 ; + %load/vec4 v0x5570afb381b0_0; + %parti/s 16, 0, 2; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb38380_0, 4, 16; + %jmp T_2.42; +T_2.40 ; + %load/vec4 v0x5570afb381b0_0; + %parti/s 16, 0, 2; + %ix/load 4, 16, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x5570afb38380_0, 4, 16; + %jmp T_2.42; +T_2.42 ; + %pop/vec4 1; + %jmp T_2.32; +T_2.30 ; + %load/vec4 v0x5570afb381b0_0; + %store/vec4 v0x5570afb38380_0, 0, 32; + %jmp T_2.32; +T_2.32 ; + %pop/vec4 1; + %load/vec4 v0x5570afb38380_0; + %ret/vec4 0, 0, 32; Assign to conv_wdata (store_vec4_to_lval) + %end; +S_0x5570afb384b0 .scope begin, "preg_out_Seq" "preg_out_Seq" 13 247, 13 247 0, S_0x5570afb36e60; + .timescale 0 0; +S_0x5570afb38690 .scope module, "u_reg0_31" "req_register" 13 310, 14 113 0, S_0x5570afb36e60; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /INPUT 1 "cpu_we"; + .port_info 3 /INPUT 1 "cpu_req"; + .port_info 4 /INPUT 1 "hware_ack"; + .port_info 5 /OUTPUT 1 "data_out"; +P_0x5570afb388c0 .param/l "RESET_DEFAULT" 0 14 128, +C4<00000000000000000000000000000000>; +v0x5570afb38ad0_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb38b90_0 .net "cpu_req", 0 0, L_0x5570afb68fd0; 1 drivers +v0x5570afb38c50_0 .net "cpu_we", 0 0, L_0x5570afb68f30; 1 drivers +v0x5570afb38cf0_0 .var "data_out", 0 0; +v0x5570afb38db0_0 .net "hware_ack", 0 0, L_0x5570afb6ad00; alias, 1 drivers +v0x5570afb38ea0_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +S_0x5570afb39020 .scope module, "u_reg0_3_0" "generic_register" 13 299, 14 207 0, S_0x5570afb36e60; + .timescale 0 0; + .port_info 0 /INPUT 4 "we"; + .port_info 1 /INPUT 4 "data_in"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "clk"; + .port_info 4 /OUTPUT 4 "data_out"; +P_0x5570afb26110 .param/l "RESET_DEFAULT" 0 14 219, +C4<00000000000000000000000000000000>; +P_0x5570afb26150 .param/l "WD" 0 14 218, +C4<00000000000000000000000000000100>; +v0x5570afb3bfa0_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb3c060_0 .net "data_in", 3 0, L_0x5570afb68c10; 1 drivers +v0x5570afb3c140_0 .net8 "data_out", 3 0, RS_0x7f116f7ce138; alias, 2 drivers +v0x5570afb3c200_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb3c2a0_0 .net "we", 3 0, L_0x5570afb68ab0; 1 drivers +L_0x5570afb57a40 .part L_0x5570afb68ab0, 0, 1; +L_0x5570afb681c0 .part L_0x5570afb68c10, 0, 1; +L_0x5570afb68260 .part L_0x5570afb68ab0, 1, 1; +L_0x5570afb68350 .part L_0x5570afb68c10, 1, 1; +L_0x5570afb68470 .part L_0x5570afb68ab0, 2, 1; +L_0x5570afb68510 .part L_0x5570afb68c10, 2, 1; +L_0x5570afb685f0 .part L_0x5570afb68ab0, 3, 1; +L_0x5570afb68690 .part L_0x5570afb68c10, 3, 1; +L_0x5570afb687b0 .concat8 [ 1 1 1 1], v0x5570afb39c90_0, v0x5570afb3a730_0, v0x5570afb3b1e0_0, v0x5570afb3bc80_0; +S_0x5570afb393b0 .scope generate, "gen_bit_reg[0]" "gen_bit_reg[0]" 14 229, 14 229 0, S_0x5570afb39020; + .timescale 0 0; +P_0x5570afb395d0 .param/l "i" 1 14 229, +C4<00>; +S_0x5570afb396b0 .scope module, "u_bit_reg" "bit_register" 14 230, 14 68 0, S_0x5570afb393b0; + .timescale 0 0; + .port_info 0 /INPUT 1 "we"; + .port_info 1 /INPUT 1 "clk"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "data_in"; + .port_info 4 /OUTPUT 1 "data_out"; +P_0x5570afb39890 .param/l "RESET_DEFAULT" 0 14 82, C4<0>; +v0x5570afb39a20_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb39bd0_0 .net "data_in", 0 0, L_0x5570afb681c0; 1 drivers +v0x5570afb39c90_0 .var "data_out", 0 0; +v0x5570afb39d60_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb39e00_0 .net "we", 0 0, L_0x5570afb57a40; 1 drivers +S_0x5570afb39fb0 .scope generate, "gen_bit_reg[1]" "gen_bit_reg[1]" 14 229, 14 229 0, S_0x5570afb39020; + .timescale 0 0; +P_0x5570afb3a1d0 .param/l "i" 1 14 229, +C4<01>; +S_0x5570afb3a290 .scope module, "u_bit_reg" "bit_register" 14 230, 14 68 0, S_0x5570afb39fb0; + .timescale 0 0; + .port_info 0 /INPUT 1 "we"; + .port_info 1 /INPUT 1 "clk"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "data_in"; + .port_info 4 /OUTPUT 1 "data_out"; +P_0x5570afb3a470 .param/l "RESET_DEFAULT" 0 14 82, C4<0>; +v0x5570afb3a5d0_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb3a670_0 .net "data_in", 0 0, L_0x5570afb68350; 1 drivers +v0x5570afb3a730_0 .var "data_out", 0 0; +v0x5570afb3a800_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb3a8a0_0 .net "we", 0 0, L_0x5570afb68260; 1 drivers +S_0x5570afb3aa50 .scope generate, "gen_bit_reg[2]" "gen_bit_reg[2]" 14 229, 14 229 0, S_0x5570afb39020; + .timescale 0 0; +P_0x5570afb3ac50 .param/l "i" 1 14 229, +C4<010>; +S_0x5570afb3ad10 .scope module, "u_bit_reg" "bit_register" 14 230, 14 68 0, S_0x5570afb3aa50; + .timescale 0 0; + .port_info 0 /INPUT 1 "we"; + .port_info 1 /INPUT 1 "clk"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "data_in"; + .port_info 4 /OUTPUT 1 "data_out"; +P_0x5570afb3aef0 .param/l "RESET_DEFAULT" 0 14 82, C4<0>; +v0x5570afb3b080_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb3b120_0 .net "data_in", 0 0, L_0x5570afb68510; 1 drivers +v0x5570afb3b1e0_0 .var "data_out", 0 0; +v0x5570afb3b2b0_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb3b350_0 .net "we", 0 0, L_0x5570afb68470; 1 drivers +S_0x5570afb3b500 .scope generate, "gen_bit_reg[3]" "gen_bit_reg[3]" 14 229, 14 229 0, S_0x5570afb39020; + .timescale 0 0; +P_0x5570afb3b700 .param/l "i" 1 14 229, +C4<011>; +S_0x5570afb3b7e0 .scope module, "u_bit_reg" "bit_register" 14 230, 14 68 0, S_0x5570afb3b500; + .timescale 0 0; + .port_info 0 /INPUT 1 "we"; + .port_info 1 /INPUT 1 "clk"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "data_in"; + .port_info 4 /OUTPUT 1 "data_out"; +P_0x5570afb3b9c0 .param/l "RESET_DEFAULT" 0 14 82, C4<0>; +v0x5570afb3bb20_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb3bbc0_0 .net "data_in", 0 0, L_0x5570afb68690; 1 drivers +v0x5570afb3bc80_0 .var "data_out", 0 0; +v0x5570afb3bd50_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb3bdf0_0 .net "we", 0 0, L_0x5570afb685f0; 1 drivers +S_0x5570afb3c470 .scope module, "u_reg_1" "gen_32b_reg" 13 324, 14 332 0, S_0x5570afb36e60; + .timescale 0 0; + .port_info 0 /INPUT 1 "cs"; + .port_info 1 /INPUT 4 "we"; + .port_info 2 /INPUT 32 "data_in"; + .port_info 3 /INPUT 1 "reset_n"; + .port_info 4 /INPUT 1 "clk"; + .port_info 5 /OUTPUT 32 "data_out"; +P_0x5570afb3c650 .param/l "RESET_DEFAULT" 0 14 344, C4<00000000000000000000000000000000>; +v0x5570afb3c790_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb3c850_0 .net "cs", 0 0, L_0x5570afb56330; alias, 1 drivers +v0x5570afb3c910_0 .net "data_in", 31 0, v0x5570afb414c0_0; 1 drivers +v0x5570afb3ca00_0 .var "data_out", 31 0; +v0x5570afb3cae0_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb3cbd0_0 .net "we", 3 0, v0x5570afb40b70_0; 1 drivers +S_0x5570afb3cdb0 .scope module, "u_reg_2" "gen_32b_reg" 13 337, 14 332 0, S_0x5570afb36e60; + .timescale 0 0; + .port_info 0 /INPUT 1 "cs"; + .port_info 1 /INPUT 4 "we"; + .port_info 2 /INPUT 32 "data_in"; + .port_info 3 /INPUT 1 "reset_n"; + .port_info 4 /INPUT 1 "clk"; + .port_info 5 /OUTPUT 32 "data_out"; +P_0x5570afb3cf90 .param/l "RESET_DEFAULT" 0 14 344, C4<00000000000000000000000000000000>; +v0x5570afb3d0d0_0 .net "clk", 0 0, o0x7f116f7cb4f8; alias, 0 drivers +v0x5570afb3d190_0 .net "cs", 0 0, L_0x5570afb565f0; alias, 1 drivers +v0x5570afb3d250_0 .net "data_in", 31 0, v0x5570afb414c0_0; alias, 1 drivers +v0x5570afb3d350_0 .var "data_out", 31 0; +v0x5570afb3d410_0 .net "reset_n", 0 0, L_0x5570afb6a800; alias, 1 drivers +v0x5570afb3d500_0 .net "we", 3 0, v0x5570afb40b70_0; alias, 1 drivers +S_0x5570afb41b10 .scope module, "u_skew" "clk_skew_adjust" 4 78, 15 78 0, S_0x5570afab6020; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk_in"; + .port_info 1 /INPUT 4 "sel"; + .port_info 2 /OUTPUT 1 "clk_out"; +L_0x5570afb53220 .functor BUFZ 1, o0x7f116f7cf368, C4<0>, C4<0>, C4<0>; +L_0x5570afb53360 .functor BUFZ 1, L_0x5570afb52150, C4<0>, C4<0>, C4<0>; +L_0x5570afb533f0 .functor BUFZ 1, L_0x5570afb521c0, C4<0>, C4<0>, C4<0>; +L_0x5570afb53480 .functor BUFZ 1, L_0x5570afb52270, C4<0>, C4<0>, C4<0>; +L_0x5570afb53540 .functor BUFZ 1, L_0x5570afb52320, C4<0>, C4<0>, C4<0>; +L_0x5570afb535b0 .functor BUFZ 1, L_0x5570afb52460, C4<0>, C4<0>, C4<0>; +L_0x5570afb53680 .functor BUFZ 1, L_0x5570afb525a0, C4<0>, C4<0>, C4<0>; +L_0x5570afb53710 .functor BUFZ 1, L_0x5570afb526e0, C4<0>, C4<0>, C4<0>; +L_0x5570afb537a0 .functor BUFZ 1, L_0x5570afb52820, C4<0>, C4<0>, C4<0>; +L_0x5570afb53830 .functor BUFZ 1, L_0x5570afb52960, C4<0>, C4<0>, C4<0>; +L_0x5570afb53920 .functor BUFZ 1, L_0x5570afb52aa0, C4<0>, C4<0>, C4<0>; +L_0x5570afb539b0 .functor BUFZ 1, L_0x5570afb52be0, C4<0>, C4<0>, C4<0>; +L_0x5570afb53ab0 .functor BUFZ 1, L_0x5570afb52d20, C4<0>, C4<0>, C4<0>; +L_0x5570afb53b40 .functor BUFZ 1, L_0x5570afb52e60, C4<0>, C4<0>, C4<0>; +L_0x5570afb53a40 .functor BUFZ 1, L_0x5570afb52fa0, C4<0>, C4<0>, C4<0>; +L_0x5570afb53cc0 .functor BUFZ 1, L_0x5570afb530e0, C4<0>, C4<0>, C4<0>; +L_0x5570afb55560 .functor BUFZ 1, L_0x5570afb55b50, C4<0>, C4<0>, C4<0>; +v0x5570afb4c6e0_0 .net "clk_d1", 0 0, L_0x5570afb52150; 1 drivers +v0x5570afb4c7f0_0 .net "clk_d10", 0 0, L_0x5570afb52aa0; 1 drivers +v0x5570afb4c900_0 .net "clk_d11", 0 0, L_0x5570afb52be0; 1 drivers +v0x5570afb4c9f0_0 .net "clk_d12", 0 0, L_0x5570afb52d20; 1 drivers +v0x5570afb4cae0_0 .net "clk_d13", 0 0, L_0x5570afb52e60; 1 drivers +v0x5570afb4cc20_0 .net "clk_d14", 0 0, L_0x5570afb52fa0; 1 drivers +v0x5570afb4cd10_0 .net "clk_d15", 0 0, L_0x5570afb530e0; 1 drivers +v0x5570afb4cdb0_0 .net "clk_d2", 0 0, L_0x5570afb521c0; 1 drivers +v0x5570afb4cea0_0 .net "clk_d3", 0 0, L_0x5570afb52270; 1 drivers +v0x5570afb4cf40_0 .net "clk_d4", 0 0, L_0x5570afb52320; 1 drivers +v0x5570afb4d030_0 .net "clk_d5", 0 0, L_0x5570afb52460; 1 drivers +v0x5570afb4d120_0 .net "clk_d6", 0 0, L_0x5570afb525a0; 1 drivers +v0x5570afb4d210_0 .net "clk_d7", 0 0, L_0x5570afb526e0; 1 drivers +v0x5570afb4d300_0 .net "clk_d8", 0 0, L_0x5570afb52820; 1 drivers +v0x5570afb4d3f0_0 .net "clk_d9", 0 0, L_0x5570afb52960; 1 drivers +v0x5570afb4d4e0_0 .net "clk_in", 0 0, o0x7f116f7cf368; alias, 0 drivers +v0x5570afb4d580_0 .net "clk_out", 0 0, L_0x5570afb55560; alias, 1 drivers +v0x5570afb4d620_0 .net "d00", 0 0, L_0x5570afb53e30; 1 drivers +v0x5570afb4d710_0 .net "d01", 0 0, L_0x5570afb54030; 1 drivers +v0x5570afb4d800_0 .net "d02", 0 0, L_0x5570afb541c0; 1 drivers +v0x5570afb4d8f0_0 .net "d03", 0 0, L_0x5570afb543e0; 1 drivers +v0x5570afb4d9e0_0 .net "d04", 0 0, L_0x5570afb54520; 1 drivers +v0x5570afb4dad0_0 .net "d05", 0 0, L_0x5570afb546b0; 1 drivers +v0x5570afb4dbc0_0 .net "d06", 0 0, L_0x5570afb54880; 1 drivers +v0x5570afb4dcb0_0 .net "d07", 0 0, L_0x5570afb54a10; 1 drivers +v0x5570afb4dda0_0 .net "d10", 0 0, L_0x5570afb54bf0; 1 drivers +v0x5570afb4de90_0 .net "d11", 0 0, L_0x5570afb54dc0; 1 drivers +v0x5570afb4df80_0 .net "d12", 0 0, L_0x5570afb55080; 1 drivers +v0x5570afb4e070_0 .net "d13", 0 0, L_0x5570afb552e0; 1 drivers +v0x5570afb4e160_0 .net "d20", 0 0, L_0x5570afb555d0; 1 drivers +v0x5570afb4e250_0 .net "d21", 0 0, L_0x5570afb55850; 1 drivers +v0x5570afb4e340_0 .net "d30", 0 0, L_0x5570afb55b50; 1 drivers +v0x5570afb4e3e0_0 .net "in0", 0 0, L_0x5570afb53220; 1 drivers +v0x5570afb4e480_0 .net "in1", 0 0, L_0x5570afb53360; 1 drivers +v0x5570afb4e520_0 .net "in10", 0 0, L_0x5570afb53920; 1 drivers +v0x5570afb4e5c0_0 .net "in11", 0 0, L_0x5570afb539b0; 1 drivers +v0x5570afb4e660_0 .net "in12", 0 0, L_0x5570afb53ab0; 1 drivers +v0x5570afb4e700_0 .net "in13", 0 0, L_0x5570afb53b40; 1 drivers +v0x5570afb4e7a0_0 .net "in14", 0 0, L_0x5570afb53a40; 1 drivers +v0x5570afb4e840_0 .net "in15", 0 0, L_0x5570afb53cc0; 1 drivers +v0x5570afb4e8e0_0 .net "in2", 0 0, L_0x5570afb533f0; 1 drivers +v0x5570afb4e980_0 .net "in3", 0 0, L_0x5570afb53480; 1 drivers +v0x5570afb4ea20_0 .net "in4", 0 0, L_0x5570afb53540; 1 drivers +v0x5570afb4eac0_0 .net "in5", 0 0, L_0x5570afb535b0; 1 drivers +v0x5570afb4eb60_0 .net "in6", 0 0, L_0x5570afb53680; 1 drivers +v0x5570afb4ec00_0 .net "in7", 0 0, L_0x5570afb53710; 1 drivers +v0x5570afb4eca0_0 .net "in8", 0 0, L_0x5570afb537a0; 1 drivers +v0x5570afb4ed40_0 .net "in9", 0 0, L_0x5570afb53830; 1 drivers +v0x5570afb4ede0_0 .net "sel", 3 0, o0x7f116f7d1018; alias, 0 drivers +L_0x5570afb53ef0 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb540d0 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb54260 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb54480 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb545c0 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb54750 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb54920 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb54ab0 .part o0x7f116f7d1018, 0, 1; +L_0x5570afb54d20 .part o0x7f116f7d1018, 1, 1; +L_0x5570afb54f80 .part o0x7f116f7d1018, 1, 1; +L_0x5570afb55240 .part o0x7f116f7d1018, 1, 1; +L_0x5570afb554c0 .part o0x7f116f7d1018, 1, 1; +L_0x5570afb557b0 .part o0x7f116f7d1018, 2, 1; +L_0x5570afb55a30 .part o0x7f116f7d1018, 2, 1; +L_0x5570afb55d30 .part o0x7f116f7d1018, 3, 1; +S_0x5570afb41d60 .scope module, "clkbuf_1" "ctech_delay_clkbuf" 15 143, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52150 .functor BUFZ 1, o0x7f116f7cf368, C4<0>, C4<0>, C4<0>; +v0x5570afb41f80_0 .net "A", 0 0, o0x7f116f7cf368; alias, 0 drivers +v0x5570afb42060_0 .net "X", 0 0, L_0x5570afb52150; alias, 1 drivers +S_0x5570afb42180 .scope module, "clkbuf_10" "ctech_delay_clkbuf" 15 152, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52aa0 .functor BUFZ 1, L_0x5570afb52960, C4<0>, C4<0>, C4<0>; +v0x5570afb423a0_0 .net "A", 0 0, L_0x5570afb52960; alias, 1 drivers +v0x5570afb42480_0 .net "X", 0 0, L_0x5570afb52aa0; alias, 1 drivers +S_0x5570afb425a0 .scope module, "clkbuf_11" "ctech_delay_clkbuf" 15 153, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52be0 .functor BUFZ 1, L_0x5570afb52aa0, C4<0>, C4<0>, C4<0>; +v0x5570afb427f0_0 .net "A", 0 0, L_0x5570afb52aa0; alias, 1 drivers +v0x5570afb428c0_0 .net "X", 0 0, L_0x5570afb52be0; alias, 1 drivers +S_0x5570afb429c0 .scope module, "clkbuf_12" "ctech_delay_clkbuf" 15 154, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52d20 .functor BUFZ 1, L_0x5570afb52be0, C4<0>, C4<0>, C4<0>; +v0x5570afb42be0_0 .net "A", 0 0, L_0x5570afb52be0; alias, 1 drivers +v0x5570afb42cd0_0 .net "X", 0 0, L_0x5570afb52d20; alias, 1 drivers +S_0x5570afb42dd0 .scope module, "clkbuf_13" "ctech_delay_clkbuf" 15 155, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52e60 .functor BUFZ 1, L_0x5570afb52d20, C4<0>, C4<0>, C4<0>; +v0x5570afb43040_0 .net "A", 0 0, L_0x5570afb52d20; alias, 1 drivers +v0x5570afb43100_0 .net "X", 0 0, L_0x5570afb52e60; alias, 1 drivers +S_0x5570afb43200 .scope module, "clkbuf_14" "ctech_delay_clkbuf" 15 156, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52fa0 .functor BUFZ 1, L_0x5570afb52e60, C4<0>, C4<0>, C4<0>; +v0x5570afb43420_0 .net "A", 0 0, L_0x5570afb52e60; alias, 1 drivers +v0x5570afb43510_0 .net "X", 0 0, L_0x5570afb52fa0; alias, 1 drivers +S_0x5570afb43610 .scope module, "clkbuf_15" "ctech_delay_clkbuf" 15 157, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb530e0 .functor BUFZ 1, L_0x5570afb52fa0, C4<0>, C4<0>, C4<0>; +v0x5570afb43830_0 .net "A", 0 0, L_0x5570afb52fa0; alias, 1 drivers +v0x5570afb43920_0 .net "X", 0 0, L_0x5570afb530e0; alias, 1 drivers +S_0x5570afb43a20 .scope module, "clkbuf_2" "ctech_delay_clkbuf" 15 144, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb521c0 .functor BUFZ 1, L_0x5570afb52150, C4<0>, C4<0>, C4<0>; +v0x5570afb43c40_0 .net "A", 0 0, L_0x5570afb52150; alias, 1 drivers +v0x5570afb43d30_0 .net "X", 0 0, L_0x5570afb521c0; alias, 1 drivers +S_0x5570afb43e30 .scope module, "clkbuf_3" "ctech_delay_clkbuf" 15 145, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52270 .functor BUFZ 1, L_0x5570afb521c0, C4<0>, C4<0>, C4<0>; +v0x5570afb44050_0 .net "A", 0 0, L_0x5570afb521c0; alias, 1 drivers +v0x5570afb44140_0 .net "X", 0 0, L_0x5570afb52270; alias, 1 drivers +S_0x5570afb44240 .scope module, "clkbuf_4" "ctech_delay_clkbuf" 15 146, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52320 .functor BUFZ 1, L_0x5570afb52270, C4<0>, C4<0>, C4<0>; +v0x5570afb44410_0 .net "A", 0 0, L_0x5570afb52270; alias, 1 drivers +v0x5570afb44500_0 .net "X", 0 0, L_0x5570afb52320; alias, 1 drivers +S_0x5570afb44600 .scope module, "clkbuf_5" "ctech_delay_clkbuf" 15 147, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52460 .functor BUFZ 1, L_0x5570afb52320, C4<0>, C4<0>, C4<0>; +v0x5570afb44820_0 .net "A", 0 0, L_0x5570afb52320; alias, 1 drivers +v0x5570afb44910_0 .net "X", 0 0, L_0x5570afb52460; alias, 1 drivers +S_0x5570afb44a10 .scope module, "clkbuf_6" "ctech_delay_clkbuf" 15 148, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb525a0 .functor BUFZ 1, L_0x5570afb52460, C4<0>, C4<0>, C4<0>; +v0x5570afb44c30_0 .net "A", 0 0, L_0x5570afb52460; alias, 1 drivers +v0x5570afb44d20_0 .net "X", 0 0, L_0x5570afb525a0; alias, 1 drivers +S_0x5570afb44e20 .scope module, "clkbuf_7" "ctech_delay_clkbuf" 15 149, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb526e0 .functor BUFZ 1, L_0x5570afb525a0, C4<0>, C4<0>, C4<0>; +v0x5570afb45040_0 .net "A", 0 0, L_0x5570afb525a0; alias, 1 drivers +v0x5570afb45130_0 .net "X", 0 0, L_0x5570afb526e0; alias, 1 drivers +S_0x5570afb45230 .scope module, "clkbuf_8" "ctech_delay_clkbuf" 15 150, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52820 .functor BUFZ 1, L_0x5570afb526e0, C4<0>, C4<0>, C4<0>; +v0x5570afb45450_0 .net "A", 0 0, L_0x5570afb526e0; alias, 1 drivers +v0x5570afb45540_0 .net "X", 0 0, L_0x5570afb52820; alias, 1 drivers +S_0x5570afb45640 .scope module, "clkbuf_9" "ctech_delay_clkbuf" 15 151, 3 110 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "X"; +L_0x5570afb52960 .functor BUFZ 1, L_0x5570afb52820, C4<0>, C4<0>, C4<0>; +v0x5570afb45860_0 .net "A", 0 0, L_0x5570afb52820; alias, 1 drivers +v0x5570afb45950_0 .net "X", 0 0, L_0x5570afb52960; alias, 1 drivers +S_0x5570afb45a40 .scope module, "u_mux_level_00" "ctech_mux2x1_2" 15 180, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb45c20 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb45db0_0 .net "A0", 0 0, L_0x5570afb53220; alias, 1 drivers +v0x5570afb45e90_0 .net "A1", 0 0, L_0x5570afb53360; alias, 1 drivers +v0x5570afb45f70_0 .net "S", 0 0, L_0x5570afb53ef0; 1 drivers +v0x5570afb46040_0 .net "X", 0 0, L_0x5570afb53e30; alias, 1 drivers +L_0x5570afb53e30 .functor MUXZ 1, L_0x5570afb53220, L_0x5570afb53360, L_0x5570afb53ef0, C4<>; +S_0x5570afb461d0 .scope module, "u_mux_level_01" "ctech_mux2x1_2" 15 181, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb463b0 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb46480_0 .net "A0", 0 0, L_0x5570afb533f0; alias, 1 drivers +v0x5570afb46580_0 .net "A1", 0 0, L_0x5570afb53480; alias, 1 drivers +v0x5570afb46660_0 .net "S", 0 0, L_0x5570afb540d0; 1 drivers +v0x5570afb46730_0 .net "X", 0 0, L_0x5570afb54030; alias, 1 drivers +L_0x5570afb54030 .functor MUXZ 1, L_0x5570afb533f0, L_0x5570afb53480, L_0x5570afb540d0, C4<>; +S_0x5570afb468c0 .scope module, "u_mux_level_02" "ctech_mux2x1_2" 15 182, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb46aa0 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb46b70_0 .net "A0", 0 0, L_0x5570afb53540; alias, 1 drivers +v0x5570afb46c70_0 .net "A1", 0 0, L_0x5570afb535b0; alias, 1 drivers +v0x5570afb46d50_0 .net "S", 0 0, L_0x5570afb54260; 1 drivers +v0x5570afb46e20_0 .net "X", 0 0, L_0x5570afb541c0; alias, 1 drivers +L_0x5570afb541c0 .functor MUXZ 1, L_0x5570afb53540, L_0x5570afb535b0, L_0x5570afb54260, C4<>; +S_0x5570afb46fb0 .scope module, "u_mux_level_03" "ctech_mux2x1_2" 15 183, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb47190 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb47260_0 .net "A0", 0 0, L_0x5570afb53680; alias, 1 drivers +v0x5570afb47360_0 .net "A1", 0 0, L_0x5570afb53710; alias, 1 drivers +v0x5570afb47440_0 .net "S", 0 0, L_0x5570afb54480; 1 drivers +v0x5570afb47510_0 .net "X", 0 0, L_0x5570afb543e0; alias, 1 drivers +L_0x5570afb543e0 .functor MUXZ 1, L_0x5570afb53680, L_0x5570afb53710, L_0x5570afb54480, C4<>; +S_0x5570afb476a0 .scope module, "u_mux_level_04" "ctech_mux2x1_2" 15 184, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb47880 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb479c0_0 .net "A0", 0 0, L_0x5570afb537a0; alias, 1 drivers +v0x5570afb47ac0_0 .net "A1", 0 0, L_0x5570afb53830; alias, 1 drivers +v0x5570afb47ba0_0 .net "S", 0 0, L_0x5570afb545c0; 1 drivers +v0x5570afb47c70_0 .net "X", 0 0, L_0x5570afb54520; alias, 1 drivers +L_0x5570afb54520 .functor MUXZ 1, L_0x5570afb537a0, L_0x5570afb53830, L_0x5570afb545c0, C4<>; +S_0x5570afb47e00 .scope module, "u_mux_level_05" "ctech_mux2x1_2" 15 185, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb47fe0 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb48120_0 .net "A0", 0 0, L_0x5570afb53920; alias, 1 drivers +v0x5570afb48220_0 .net "A1", 0 0, L_0x5570afb539b0; alias, 1 drivers +v0x5570afb48300_0 .net "S", 0 0, L_0x5570afb54750; 1 drivers +v0x5570afb483d0_0 .net "X", 0 0, L_0x5570afb546b0; alias, 1 drivers +L_0x5570afb546b0 .functor MUXZ 1, L_0x5570afb53920, L_0x5570afb539b0, L_0x5570afb54750, C4<>; +S_0x5570afb48560 .scope module, "u_mux_level_06" "ctech_mux2x1_2" 15 186, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb48740 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb48880_0 .net "A0", 0 0, L_0x5570afb53ab0; alias, 1 drivers +v0x5570afb48980_0 .net "A1", 0 0, L_0x5570afb53b40; alias, 1 drivers +v0x5570afb48a60_0 .net "S", 0 0, L_0x5570afb54920; 1 drivers +v0x5570afb48b30_0 .net "X", 0 0, L_0x5570afb54880; alias, 1 drivers +L_0x5570afb54880 .functor MUXZ 1, L_0x5570afb53ab0, L_0x5570afb53b40, L_0x5570afb54920, C4<>; +S_0x5570afb48cc0 .scope module, "u_mux_level_07" "ctech_mux2x1_2" 15 187, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb48ea0 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb48fe0_0 .net "A0", 0 0, L_0x5570afb53a40; alias, 1 drivers +v0x5570afb490e0_0 .net "A1", 0 0, L_0x5570afb53cc0; alias, 1 drivers +v0x5570afb491c0_0 .net "S", 0 0, L_0x5570afb54ab0; 1 drivers +v0x5570afb49290_0 .net "X", 0 0, L_0x5570afb54a10; alias, 1 drivers +L_0x5570afb54a10 .functor MUXZ 1, L_0x5570afb53a40, L_0x5570afb53cc0, L_0x5570afb54ab0, C4<>; +S_0x5570afb49420 .scope module, "u_mux_level_10" "ctech_mux2x1_2" 15 190, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb49600 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb49740_0 .net "A0", 0 0, L_0x5570afb53e30; alias, 1 drivers +v0x5570afb49850_0 .net "A1", 0 0, L_0x5570afb54030; alias, 1 drivers +v0x5570afb49920_0 .net "S", 0 0, L_0x5570afb54d20; 1 drivers +v0x5570afb499f0_0 .net "X", 0 0, L_0x5570afb54bf0; alias, 1 drivers +L_0x5570afb54bf0 .functor MUXZ 1, L_0x5570afb53e30, L_0x5570afb54030, L_0x5570afb54d20, C4<>; +S_0x5570afb49b60 .scope module, "u_mux_level_11" "ctech_mux2x1_2" 15 191, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb49d40 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb49e80_0 .net "A0", 0 0, L_0x5570afb541c0; alias, 1 drivers +v0x5570afb49f90_0 .net "A1", 0 0, L_0x5570afb543e0; alias, 1 drivers +v0x5570afb4a060_0 .net "S", 0 0, L_0x5570afb54f80; 1 drivers +v0x5570afb4a130_0 .net "X", 0 0, L_0x5570afb54dc0; alias, 1 drivers +L_0x5570afb54dc0 .functor MUXZ 1, L_0x5570afb541c0, L_0x5570afb543e0, L_0x5570afb54f80, C4<>; +S_0x5570afb4a2a0 .scope module, "u_mux_level_12" "ctech_mux2x1_2" 15 192, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb4a480 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb4a5c0_0 .net "A0", 0 0, L_0x5570afb54520; alias, 1 drivers +v0x5570afb4a6d0_0 .net "A1", 0 0, L_0x5570afb546b0; alias, 1 drivers +v0x5570afb4a7a0_0 .net "S", 0 0, L_0x5570afb55240; 1 drivers +v0x5570afb4a870_0 .net "X", 0 0, L_0x5570afb55080; alias, 1 drivers +L_0x5570afb55080 .functor MUXZ 1, L_0x5570afb54520, L_0x5570afb546b0, L_0x5570afb55240, C4<>; +S_0x5570afb4a9e0 .scope module, "u_mux_level_13" "ctech_mux2x1_2" 15 193, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb4abc0 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb4ad00_0 .net "A0", 0 0, L_0x5570afb54880; alias, 1 drivers +v0x5570afb4ae10_0 .net "A1", 0 0, L_0x5570afb54a10; alias, 1 drivers +v0x5570afb4aee0_0 .net "S", 0 0, L_0x5570afb554c0; 1 drivers +v0x5570afb4afb0_0 .net "X", 0 0, L_0x5570afb552e0; alias, 1 drivers +L_0x5570afb552e0 .functor MUXZ 1, L_0x5570afb54880, L_0x5570afb54a10, L_0x5570afb554c0, C4<>; +S_0x5570afb4b120 .scope module, "u_mux_level_20" "ctech_mux2x1_2" 15 196, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb4b300 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb4b440_0 .net "A0", 0 0, L_0x5570afb54bf0; alias, 1 drivers +v0x5570afb4b550_0 .net "A1", 0 0, L_0x5570afb54dc0; alias, 1 drivers +v0x5570afb4b620_0 .net "S", 0 0, L_0x5570afb557b0; 1 drivers +v0x5570afb4b6f0_0 .net "X", 0 0, L_0x5570afb555d0; alias, 1 drivers +L_0x5570afb555d0 .functor MUXZ 1, L_0x5570afb54bf0, L_0x5570afb54dc0, L_0x5570afb557b0, C4<>; +S_0x5570afb4b860 .scope module, "u_mux_level_21" "ctech_mux2x1_2" 15 197, 3 26 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb4ba40 .param/l "WB" 0 3 26, +C4<00000000000000000000000000000001>; +v0x5570afb4bb80_0 .net "A0", 0 0, L_0x5570afb55080; alias, 1 drivers +v0x5570afb4bc90_0 .net "A1", 0 0, L_0x5570afb552e0; alias, 1 drivers +v0x5570afb4bd60_0 .net "S", 0 0, L_0x5570afb55a30; 1 drivers +v0x5570afb4be30_0 .net "X", 0 0, L_0x5570afb55850; alias, 1 drivers +L_0x5570afb55850 .functor MUXZ 1, L_0x5570afb55080, L_0x5570afb552e0, L_0x5570afb55a30, C4<>; +S_0x5570afb4bfa0 .scope module, "u_mux_level_30" "ctech_mux2x1_4" 15 200, 3 50 0, S_0x5570afb41b10; + .timescale 0 0; + .port_info 0 /INPUT 1 "A0"; + .port_info 1 /INPUT 1 "A1"; + .port_info 2 /INPUT 1 "S"; + .port_info 3 /OUTPUT 1 "X"; +P_0x5570afb4c180 .param/l "WB" 0 3 50, +C4<00000000000000000000000000000001>; +v0x5570afb4c2c0_0 .net "A0", 0 0, L_0x5570afb555d0; alias, 1 drivers +v0x5570afb4c3d0_0 .net "A1", 0 0, L_0x5570afb55850; alias, 1 drivers +v0x5570afb4c4a0_0 .net "S", 0 0, L_0x5570afb55d30; 1 drivers +v0x5570afb4c570_0 .net "X", 0 0, L_0x5570afb55b50; alias, 1 drivers +L_0x5570afb55b50 .functor MUXZ 1, L_0x5570afb555d0, L_0x5570afb55850, L_0x5570afb55d30, C4<>; +S_0x5570afab3d20 .scope module, "gen_16b_reg" "gen_16b_reg" 14 293; + .timescale 0 0; + .port_info 0 /INPUT 1 "cs"; + .port_info 1 /INPUT 2 "we"; + .port_info 2 /INPUT 16 "data_in"; + .port_info 3 /INPUT 1 "reset_n"; + .port_info 4 /INPUT 1 "clk"; + .port_info 5 /OUTPUT 16 "data_out"; +P_0x5570afad2ae0 .param/l "RESET_DEFAULT" 0 14 305, C4<0000000000000000>; +o0x7f116f7d1348 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb4ff00_0 .net "clk", 0 0, o0x7f116f7d1348; 0 drivers +o0x7f116f7d1378 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb4ffc0_0 .net "cs", 0 0, o0x7f116f7d1378; 0 drivers +o0x7f116f7d13a8 .functor BUFZ 16, C4<zzzzzzzzzzzzzzzz>; HiZ drive +v0x5570afb50080_0 .net "data_in", 15 0, o0x7f116f7d13a8; 0 drivers +v0x5570afb50140_0 .var "data_out", 15 0; +o0x7f116f7d1408 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb50220_0 .net "reset_n", 0 0, o0x7f116f7d1408; 0 drivers +o0x7f116f7d1438 .functor BUFZ 2, C4<zz>; HiZ drive +v0x5570afb50330_0 .net "we", 1 0, o0x7f116f7d1438; 0 drivers +E_0x5570afb4fec0/0 .event negedge, v0x5570afb50220_0; +E_0x5570afb4fec0/1 .event posedge, v0x5570afb4ff00_0; +E_0x5570afb4fec0 .event/or E_0x5570afb4fec0/0, E_0x5570afb4fec0/1; +S_0x5570afadf340 .scope module, "gen_32b_reg2" "gen_32b_reg2" 14 373; + .timescale 0 0; + .port_info 0 /INPUT 32 "rst_in"; + .port_info 1 /INPUT 1 "cs"; + .port_info 2 /INPUT 4 "we"; + .port_info 3 /INPUT 32 "data_in"; + .port_info 4 /INPUT 1 "reset_n"; + .port_info 5 /INPUT 1 "clk"; + .port_info 6 /OUTPUT 32 "data_out"; +o0x7f116f7d1588 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb50550_0 .net "clk", 0 0, o0x7f116f7d1588; 0 drivers +o0x7f116f7d15b8 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb50630_0 .net "cs", 0 0, o0x7f116f7d15b8; 0 drivers +o0x7f116f7d15e8 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive +v0x5570afb506f0_0 .net "data_in", 31 0, o0x7f116f7d15e8; 0 drivers +v0x5570afb507b0_0 .var "data_out", 31 0; +o0x7f116f7d1648 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb50890_0 .net "reset_n", 0 0, o0x7f116f7d1648; 0 drivers +o0x7f116f7d1678 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive +v0x5570afb509a0_0 .net "rst_in", 31 0, o0x7f116f7d1678; 0 drivers +o0x7f116f7d16a8 .functor BUFZ 4, C4<zzzz>; HiZ drive +v0x5570afb50a80_0 .net "we", 3 0, o0x7f116f7d16a8; 0 drivers +E_0x5570afb28d30 .event posedge, v0x5570afb50550_0; +S_0x5570afab55a0 .scope module, "generic_intr_stat_reg" "generic_intr_stat_reg" 14 247; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /INPUT 1 "reg_we"; + .port_info 3 /INPUT 1 "reg_din"; + .port_info 4 /INPUT 1 "hware_req"; + .port_info 5 /OUTPUT 1 "data_out"; +P_0x5570afabfff0 .param/l "RESET_DEFAULT" 0 14 260, +C4<00000000000000000000000000000000>; +P_0x5570afac0030 .param/l "WD" 0 14 259, +C4<00000000000000000000000000000001>; +o0x7f116f7d1828 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb51910_0 .net "clk", 0 0, o0x7f116f7d1828; 0 drivers +v0x5570afb519d0_0 .net "data_out", 0 0, v0x5570afb51580_0; 1 drivers +o0x7f116f7d18e8 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb51a70_0 .net "hware_req", 0 0, o0x7f116f7d18e8; 0 drivers +o0x7f116f7d1858 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb51b40_0 .net "reg_din", 0 0, o0x7f116f7d1858; 0 drivers +o0x7f116f7d1888 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb51c10_0 .net "reg_we", 0 0, o0x7f116f7d1888; 0 drivers +o0x7f116f7d1918 .functor BUFZ 1, C4<z>; HiZ drive +v0x5570afb51d00_0 .net "reset_n", 0 0, o0x7f116f7d1918; 0 drivers +S_0x5570afb50c80 .scope generate, "gen_bit_reg[0]" "gen_bit_reg[0]" 14 271, 14 271 0, S_0x5570afab55a0; + .timescale 0 0; +P_0x5570afb50ea0 .param/l "i" 1 14 271, +C4<00>; +S_0x5570afb50f80 .scope module, "u_bit_reg" "stat_register" 14 272, 14 162 0, S_0x5570afb50c80; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /INPUT 1 "cpu_we"; + .port_info 3 /INPUT 1 "cpu_ack"; + .port_info 4 /INPUT 1 "hware_req"; + .port_info 5 /OUTPUT 1 "data_out"; +P_0x5570afb51160 .param/l "RESET_DEFAULT" 0 14 177, C4<0>; +v0x5570afb51340_0 .net "clk", 0 0, o0x7f116f7d1828; alias, 0 drivers +v0x5570afb51420_0 .net "cpu_ack", 0 0, o0x7f116f7d1858; alias, 0 drivers +v0x5570afb514e0_0 .net "cpu_we", 0 0, o0x7f116f7d1888; alias, 0 drivers +v0x5570afb51580_0 .var "data_out", 0 0; +v0x5570afb51640_0 .net "hware_req", 0 0, o0x7f116f7d18e8; alias, 0 drivers +v0x5570afb51750_0 .net "reset_n", 0 0, o0x7f116f7d1918; alias, 0 drivers +E_0x5570afb512e0/0 .event negedge, v0x5570afb51750_0; +E_0x5570afb512e0/1 .event posedge, v0x5570afb51340_0; +E_0x5570afb512e0 .event/or E_0x5570afb512e0/0, E_0x5570afb512e0/1; + .scope S_0x5570afaaf280; +T_3 ; + %wait E_0x5570afb29f70; + %load/vec4 v0x5570afb2a5a0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_3.0, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2a800_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2a700_0, 0; + %jmp T_3.1; +T_3.0 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb2a800_0, 0; + %load/vec4 v0x5570afb2a800_0; + %assign/vec4 v0x5570afb2a700_0, 0; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x5570afb396b0; +T_4 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb39d60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb39c90_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x5570afb39e00_0; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %load/vec4 v0x5570afb39bd0_0; + %assign/vec4 v0x5570afb39c90_0, 0; +T_4.2 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x5570afb3a290; +T_5 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb3a800_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb3a730_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x5570afb3a8a0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %load/vec4 v0x5570afb3a670_0; + %assign/vec4 v0x5570afb3a730_0, 0; +T_5.2 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x5570afb3ad10; +T_6 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb3b2b0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb3b1e0_0, 0; + %jmp T_6.1; +T_6.0 ; + %load/vec4 v0x5570afb3b350_0; + %flag_set/vec4 8; + %jmp/0xz T_6.2, 8; + %load/vec4 v0x5570afb3b120_0; + %assign/vec4 v0x5570afb3b1e0_0, 0; +T_6.2 ; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_0x5570afb3b7e0; +T_7 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb3bd50_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_7.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb3bc80_0, 0; + %jmp T_7.1; +T_7.0 ; + %load/vec4 v0x5570afb3bdf0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.2, 8; + %load/vec4 v0x5570afb3bbc0_0; + %assign/vec4 v0x5570afb3bc80_0, 0; +T_7.2 ; +T_7.1 ; + %jmp T_7; + .thread T_7; + .scope S_0x5570afb38690; +T_8 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb38ea0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb38cf0_0, 0; + %jmp T_8.1; +T_8.0 ; + %load/vec4 v0x5570afb38c50_0; + %load/vec4 v0x5570afb38b90_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb38cf0_0, 0; + %jmp T_8.3; +T_8.2 ; + %load/vec4 v0x5570afb38db0_0; + %flag_set/vec4 8; + %jmp/0xz T_8.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb38cf0_0, 0; +T_8.4 ; +T_8.3 ; +T_8.1 ; + %jmp T_8; + .thread T_8; + .scope S_0x5570afb3c470; +T_9 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb3cae0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_9.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x5570afb3ca00_0, 0; + %jmp T_9.1; +T_9.0 ; + %load/vec4 v0x5570afb3c850_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_9.4, 9; + %load/vec4 v0x5570afb3cbd0_0; + %parti/s 1, 0, 2; + %and; +T_9.4; + %flag_set/vec4 8; + %jmp/0xz T_9.2, 8; + %load/vec4 v0x5570afb3c910_0; + %parti/s 8, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3ca00_0, 4, 5; +T_9.2 ; + %load/vec4 v0x5570afb3c850_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_9.7, 9; + %load/vec4 v0x5570afb3cbd0_0; + %parti/s 1, 1, 2; + %and; +T_9.7; + %flag_set/vec4 8; + %jmp/0xz T_9.5, 8; + %load/vec4 v0x5570afb3c910_0; + %parti/s 8, 8, 5; + %ix/load 4, 8, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3ca00_0, 4, 5; +T_9.5 ; + %load/vec4 v0x5570afb3c850_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_9.10, 9; + %load/vec4 v0x5570afb3cbd0_0; + %parti/s 1, 2, 3; + %and; +T_9.10; + %flag_set/vec4 8; + %jmp/0xz T_9.8, 8; + %load/vec4 v0x5570afb3c910_0; + %parti/s 8, 16, 6; + %ix/load 4, 16, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3ca00_0, 4, 5; +T_9.8 ; + %load/vec4 v0x5570afb3c850_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_9.13, 9; + %load/vec4 v0x5570afb3cbd0_0; + %parti/s 1, 3, 3; + %and; +T_9.13; + %flag_set/vec4 8; + %jmp/0xz T_9.11, 8; + %load/vec4 v0x5570afb3c910_0; + %parti/s 8, 24, 6; + %ix/load 4, 24, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3ca00_0, 4, 5; +T_9.11 ; +T_9.1 ; + %jmp T_9; + .thread T_9; + .scope S_0x5570afb3cdb0; +T_10 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb3d410_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_10.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x5570afb3d350_0, 0; + %jmp T_10.1; +T_10.0 ; + %load/vec4 v0x5570afb3d190_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_10.4, 9; + %load/vec4 v0x5570afb3d500_0; + %parti/s 1, 0, 2; + %and; +T_10.4; + %flag_set/vec4 8; + %jmp/0xz T_10.2, 8; + %load/vec4 v0x5570afb3d250_0; + %parti/s 8, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3d350_0, 4, 5; +T_10.2 ; + %load/vec4 v0x5570afb3d190_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_10.7, 9; + %load/vec4 v0x5570afb3d500_0; + %parti/s 1, 1, 2; + %and; +T_10.7; + %flag_set/vec4 8; + %jmp/0xz T_10.5, 8; + %load/vec4 v0x5570afb3d250_0; + %parti/s 8, 8, 5; + %ix/load 4, 8, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3d350_0, 4, 5; +T_10.5 ; + %load/vec4 v0x5570afb3d190_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_10.10, 9; + %load/vec4 v0x5570afb3d500_0; + %parti/s 1, 2, 3; + %and; +T_10.10; + %flag_set/vec4 8; + %jmp/0xz T_10.8, 8; + %load/vec4 v0x5570afb3d250_0; + %parti/s 8, 16, 6; + %ix/load 4, 16, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3d350_0, 4, 5; +T_10.8 ; + %load/vec4 v0x5570afb3d190_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_10.13, 9; + %load/vec4 v0x5570afb3d500_0; + %parti/s 1, 3, 3; + %and; +T_10.13; + %flag_set/vec4 8; + %jmp/0xz T_10.11, 8; + %load/vec4 v0x5570afb3d250_0; + %parti/s 8, 24, 6; + %ix/load 4, 24, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb3d350_0, 4, 5; +T_10.11 ; +T_10.1 ; + %jmp T_10; + .thread T_10; + .scope S_0x5570afb36e60; +T_11 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb407e0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb40c30_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb3fd80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb40cf0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb415d0_0, 0; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x5570afb40a90_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x5570afb40b70_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x5570afb414c0_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x5570afb3fa40_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x5570afb400e0_0, 0; + %jmp T_11.1; +T_11.0 ; + %load/vec4 v0x5570afb3fcc0_0; + %flag_set/vec4 8; + %flag_get/vec4 8; + %jmp/0 T_11.2, 8; + %load/vec4 v0x5570afb3fd80_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_11.2; + %assign/vec4 v0x5570afb40c30_0, 0; + %load/vec4 v0x5570afb3fcc0_0; + %load/vec4 v0x5570afb3fd80_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; + %assign/vec4 v0x5570afb3fd80_0, 0; + %load/vec4 v0x5570afb3fb20_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %assign/vec4 v0x5570afb40cf0_0, 0; + %load/vec4 v0x5570afb3fb20_0; + %pad/u 32; + %pushi/vec4 1, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %assign/vec4 v0x5570afb415d0_0, 0; + %load/vec4 v0x5570afb3f980_0; + %parti/s 3, 2, 3; + %assign/vec4 v0x5570afb40a90_0, 0; + %load/vec4 v0x5570afb3f980_0; + %parti/s 2, 0, 2; + %assign/vec4 v0x5570afb3fa40_0, 0; + %load/vec4 v0x5570afb40000_0; + %assign/vec4 v0x5570afb400e0_0, 0; + %alloc S_0x5570afb371e0; + %load/vec4 v0x5570afb40000_0; + %load/vec4 v0x5570afb3f980_0; + %parti/s 2, 0, 2; + %store/vec4 v0x5570afb37580_0, 0, 2; + %store/vec4 v0x5570afb37670_0, 0, 2; + %callf/vec4 TD_fpu_wrapper.u_reg.conv_bsel, S_0x5570afb371e0; + %free S_0x5570afb371e0; + %assign/vec4 v0x5570afb40b70_0, 0; + %alloc S_0x5570afb37e10; + %load/vec4 v0x5570afb40000_0; + %load/vec4 v0x5570afb3f980_0; + %parti/s 2, 0, 2; + %load/vec4 v0x5570afb3ff20_0; + %store/vec4 v0x5570afb381b0_0, 0, 32; + %store/vec4 v0x5570afb380d0_0, 0, 2; + %store/vec4 v0x5570afb382a0_0, 0, 2; + %callf/vec4 TD_fpu_wrapper.u_reg.conv_wdata, S_0x5570afb37e10; + %free S_0x5570afb37e10; + %assign/vec4 v0x5570afb414c0_0, 0; +T_11.1 ; + %jmp T_11; + .thread T_11; + .scope S_0x5570afb36e60; +T_12 ; + %wait E_0x5570afb2bad0; + %fork t_1, S_0x5570afb384b0; + %jmp t_0; + .scope S_0x5570afb384b0; +t_1 ; + %load/vec4 v0x5570afb407e0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_12.0, 4; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x5570afb3fe40_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x5570afb3fbe0_0, 0; + %jmp T_12.1; +T_12.0 ; + %load/vec4 v0x5570afb40c30_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_12.4, 9; + %load/vec4 v0x5570afb40cf0_0; + %and; +T_12.4; + %flag_set/vec4 8; + %jmp/0xz T_12.2, 8; + %alloc S_0x5570afb37750; + %load/vec4 v0x5570afb400e0_0; + %load/vec4 v0x5570afb3fa40_0; + %load/vec4 v0x5570afb40700_0; + %store/vec4 v0x5570afb37b10_0, 0, 32; + %store/vec4 v0x5570afb37a30_0, 0, 2; + %store/vec4 v0x5570afb37c00_0, 0, 2; + %callf/vec4 TD_fpu_wrapper.u_reg.conv_rdata, S_0x5570afb37750; + %free S_0x5570afb37750; + %assign/vec4 v0x5570afb3fbe0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x5570afb3fe40_0, 0; + %jmp T_12.3; +T_12.2 ; + %load/vec4 v0x5570afb40c30_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_12.7, 9; + %load/vec4 v0x5570afb415d0_0; + %and; +T_12.7; + %flag_set/vec4 8; + %jmp/0xz T_12.5, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x5570afb3fe40_0, 0; + %jmp T_12.6; +T_12.5 ; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x5570afb3fe40_0, 0; +T_12.6 ; +T_12.3 ; +T_12.1 ; + %end; + .scope S_0x5570afb36e60; +t_0 %join; + %jmp T_12; + .thread T_12; + .scope S_0x5570afb36e60; +T_13 ; +Ewait_0 .event/or E_0x5570afb2b9e0, E_0x0; + %wait Ewait_0; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x5570afb40700_0, 0, 32; + %load/vec4 v0x5570afb40a90_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_13.3, 6; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x5570afb40700_0, 0, 32; + %jmp T_13.5; +T_13.0 ; + %load/vec4 v0x5570afb403c0_0; + %store/vec4 v0x5570afb40700_0, 0, 32; + %jmp T_13.5; +T_13.1 ; + %load/vec4 v0x5570afb40480_0; + %store/vec4 v0x5570afb40700_0, 0, 32; + %jmp T_13.5; +T_13.2 ; + %load/vec4 v0x5570afb40570_0; + %store/vec4 v0x5570afb40700_0, 0, 32; + %jmp T_13.5; +T_13.3 ; + %load/vec4 v0x5570afb40640_0; + %store/vec4 v0x5570afb40700_0, 0, 32; + %jmp T_13.5; +T_13.5 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13, $push; + .scope S_0x5570afb36e60; +T_14 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb407e0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_14.0, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb3f810_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v0x5570afb3f740_0; + %assign/vec4 v0x5570afb3f810_0, 0; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x5570afab47a0; +T_15 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb2ca50_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_15.0, 4; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2c6e0_0, 0; + %jmp T_15.1; +T_15.0 ; + %load/vec4 v0x5570afb2caf0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_15.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_15.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_15.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_15.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_15.6, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_15.7, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_15.8, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_15.9, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_15.10, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_15.11, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_15.12, 6; + %jmp T_15.13; +T_15.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2c6e0_0, 0; + %load/vec4 v0x5570afb2c480_0; + %flag_set/vec4 8; + %jmp/0xz T_15.14, 8; + %load/vec4 v0x5570afb2c2e0_0; + %assign/vec4 v0x5570afb2bb30_0, 0; + %load/vec4 v0x5570afb2c3a0_0; + %assign/vec4 v0x5570afb2be90_0, 0; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; +T_15.14 ; + %jmp T_15.13; +T_15.3 ; + %load/vec4 v0x5570afb2bb30_0; + %parti/s 23, 0, 2; + %concati/vec4 0, 0, 3; + %pad/u 27; + %assign/vec4 v0x5570afb2bd10_0, 0; + %load/vec4 v0x5570afb2be90_0; + %parti/s 23, 0, 2; + %concati/vec4 0, 0, 3; + %pad/u 27; + %assign/vec4 v0x5570afb2c0a0_0, 0; + %load/vec4 v0x5570afb2bb30_0; + %parti/s 8, 23, 6; + %pad/u 10; + %subi 127, 0, 10; + %assign/vec4 v0x5570afb2bc30_0, 0; + %load/vec4 v0x5570afb2be90_0; + %parti/s 8, 23, 6; + %pad/u 10; + %subi 127, 0, 10; + %assign/vec4 v0x5570afb2bfc0_0, 0; + %load/vec4 v0x5570afb2bb30_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb2bdd0_0, 0; + %load/vec4 v0x5570afb2be90_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb2c180_0, 0; + %pushi/vec4 2, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.13; +T_15.4 ; + %load/vec4 v0x5570afb2bc30_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.19, 4; + %load/vec4 v0x5570afb2bd10_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_15.19; + %flag_set/vec4 8; + %jmp/1 T_15.18, 8; + %load/vec4 v0x5570afb2bfc0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.20, 4; + %load/vec4 v0x5570afb2c0a0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_15.20; + %flag_set/vec4 9; + %flag_or 8, 9; +T_15.18; + %jmp/0xz T_15.16, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.17; +T_15.16 ; + %load/vec4 v0x5570afb2bc30_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %jmp/0xz T_15.21, 4; + %load/vec4 v0x5570afb2bdd0_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2bfc0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.25, 4; + %load/vec4 v0x5570afb2bdd0_0; + %load/vec4 v0x5570afb2c180_0; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_15.25; + %flag_set/vec4 8; + %jmp/0xz T_15.23, 8; + %load/vec4 v0x5570afb2c180_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; +T_15.23 ; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.22; +T_15.21 ; + %load/vec4 v0x5570afb2bfc0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %jmp/0xz T_15.26, 4; + %load/vec4 v0x5570afb2c180_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.27; +T_15.26 ; + %load/vec4 v0x5570afb2bc30_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.31, 4; + %load/vec4 v0x5570afb2bd10_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_15.31; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_15.30, 9; + %load/vec4 v0x5570afb2bfc0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.32, 4; + %load/vec4 v0x5570afb2c0a0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_15.32; + %and; +T_15.30; + %flag_set/vec4 8; + %jmp/0xz T_15.28, 8; + %load/vec4 v0x5570afb2bdd0_0; + %load/vec4 v0x5570afb2c180_0; + %and; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2bfc0_0; + %parti/s 8, 0, 2; + %addi 127, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2c0a0_0; + %parti/s 24, 3, 3; + %pad/u 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.29; +T_15.28 ; + %load/vec4 v0x5570afb2bc30_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.35, 4; + %load/vec4 v0x5570afb2bd10_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_15.35; + %flag_set/vec4 8; + %jmp/0xz T_15.33, 8; + %load/vec4 v0x5570afb2c180_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2bfc0_0; + %parti/s 8, 0, 2; + %addi 127, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2c0a0_0; + %parti/s 24, 3, 3; + %pad/u 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.34; +T_15.33 ; + %load/vec4 v0x5570afb2bfc0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.38, 4; + %load/vec4 v0x5570afb2c0a0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_15.38; + %flag_set/vec4 8; + %jmp/0xz T_15.36, 8; + %load/vec4 v0x5570afb2bdd0_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2bc30_0; + %parti/s 8, 0, 2; + %addi 127, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2bd10_0; + %parti/s 24, 3, 3; + %pad/u 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.37; +T_15.36 ; + %load/vec4 v0x5570afb2bc30_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %jmp/0xz T_15.39, 4; + %pushi/vec4 898, 0, 10; + %assign/vec4 v0x5570afb2bc30_0, 0; + %jmp T_15.40; +T_15.39 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 26, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2bd10_0, 4, 5; +T_15.40 ; + %load/vec4 v0x5570afb2bfc0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %jmp/0xz T_15.41, 4; + %pushi/vec4 898, 0, 10; + %assign/vec4 v0x5570afb2bfc0_0, 0; + %jmp T_15.42; +T_15.41 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 26, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2c0a0_0, 4, 5; +T_15.42 ; + %pushi/vec4 3, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; +T_15.37 ; +T_15.34 ; +T_15.29 ; +T_15.27 ; +T_15.22 ; +T_15.17 ; + %jmp T_15.13; +T_15.5 ; + %load/vec4 v0x5570afb2bfc0_0; + %load/vec4 v0x5570afb2bc30_0; + %cmp/s; + %jmp/0xz T_15.43, 5; + %load/vec4 v0x5570afb2bfc0_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb2bfc0_0, 0; + %load/vec4 v0x5570afb2c0a0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0x5570afb2c0a0_0, 0; + %load/vec4 v0x5570afb2c0a0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x5570afb2c0a0_0; + %parti/s 1, 1, 2; + %or; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2c0a0_0, 4, 5; + %jmp T_15.44; +T_15.43 ; + %load/vec4 v0x5570afb2bc30_0; + %load/vec4 v0x5570afb2bfc0_0; + %cmp/s; + %jmp/0xz T_15.45, 5; + %load/vec4 v0x5570afb2bc30_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb2bc30_0, 0; + %load/vec4 v0x5570afb2bd10_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0x5570afb2bd10_0, 0; + %load/vec4 v0x5570afb2bd10_0; + %parti/s 1, 0, 2; + %load/vec4 v0x5570afb2bd10_0; + %parti/s 1, 1, 2; + %or; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2bd10_0, 4, 5; + %jmp T_15.46; +T_15.45 ; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; +T_15.46 ; +T_15.44 ; + %jmp T_15.13; +T_15.6 ; + %load/vec4 v0x5570afb2bc30_0; + %assign/vec4 v0x5570afb2cd70_0, 0; + %load/vec4 v0x5570afb2bdd0_0; + %load/vec4 v0x5570afb2c180_0; + %cmp/e; + %jmp/0xz T_15.47, 4; + %load/vec4 v0x5570afb2bd10_0; + %pad/u 28; + %load/vec4 v0x5570afb2c0a0_0; + %pad/u 28; + %add; + %assign/vec4 v0x5570afb2c600_0, 0; + %load/vec4 v0x5570afb2bdd0_0; + %assign/vec4 v0x5570afb2cf30_0, 0; + %jmp T_15.48; +T_15.47 ; + %load/vec4 v0x5570afb2c0a0_0; + %load/vec4 v0x5570afb2bd10_0; + %cmp/u; + %flag_or 5, 4; + %jmp/0xz T_15.49, 5; + %load/vec4 v0x5570afb2bd10_0; + %pad/u 28; + %load/vec4 v0x5570afb2c0a0_0; + %pad/u 28; + %sub; + %assign/vec4 v0x5570afb2c600_0, 0; + %load/vec4 v0x5570afb2bdd0_0; + %assign/vec4 v0x5570afb2cf30_0, 0; + %jmp T_15.50; +T_15.49 ; + %load/vec4 v0x5570afb2c0a0_0; + %pad/u 28; + %load/vec4 v0x5570afb2bd10_0; + %pad/u 28; + %sub; + %assign/vec4 v0x5570afb2c600_0, 0; + %load/vec4 v0x5570afb2c180_0; + %assign/vec4 v0x5570afb2cf30_0, 0; +T_15.50 ; +T_15.48 ; + %pushi/vec4 5, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.13; +T_15.7 ; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 27, 6; + %flag_set/vec4 8; + %jmp/0xz T_15.51, 8; + %load/vec4 v0x5570afb2c600_0; + %parti/s 24, 4, 4; + %assign/vec4 v0x5570afb2ce50_0, 0; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 3, 3; + %assign/vec4 v0x5570afb2c540_0, 0; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 2, 3; + %assign/vec4 v0x5570afb2c880_0, 0; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 1, 2; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 0, 2; + %or; + %assign/vec4 v0x5570afb2cbd0_0, 0; + %load/vec4 v0x5570afb2cd70_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb2cd70_0, 0; + %jmp T_15.52; +T_15.51 ; + %load/vec4 v0x5570afb2c600_0; + %parti/s 24, 3, 3; + %assign/vec4 v0x5570afb2ce50_0, 0; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 2, 3; + %assign/vec4 v0x5570afb2c540_0, 0; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 1, 2; + %assign/vec4 v0x5570afb2c880_0, 0; + %load/vec4 v0x5570afb2c600_0; + %parti/s 1, 0, 2; + %assign/vec4 v0x5570afb2cbd0_0, 0; +T_15.52 ; + %pushi/vec4 6, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.13; +T_15.8 ; + %load/vec4 v0x5570afb2ce50_0; + %parti/s 1, 23, 6; + %pad/u 32; + %cmpi/e 0, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.55, 4; + %pushi/vec4 4294967170, 0, 32; + %load/vec4 v0x5570afb2cd70_0; + %pad/s 32; + %cmp/s; + %flag_get/vec4 5; + %and; +T_15.55; + %flag_set/vec4 8; + %jmp/0xz T_15.53, 8; + %load/vec4 v0x5570afb2cd70_0; + %subi 1, 0, 10; + %assign/vec4 v0x5570afb2cd70_0, 0; + %load/vec4 v0x5570afb2ce50_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2ce50_0, 0; + %load/vec4 v0x5570afb2c540_0; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2ce50_0, 4, 5; + %load/vec4 v0x5570afb2c880_0; + %assign/vec4 v0x5570afb2c540_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2c880_0, 0; + %jmp T_15.54; +T_15.53 ; + %pushi/vec4 7, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; +T_15.54 ; + %jmp T_15.13; +T_15.9 ; + %load/vec4 v0x5570afb2cd70_0; + %pad/s 32; + %cmpi/s 4294967170, 0, 32; + %jmp/0xz T_15.56, 5; + %load/vec4 v0x5570afb2cd70_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb2cd70_0, 0; + %load/vec4 v0x5570afb2ce50_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0x5570afb2ce50_0, 0; + %load/vec4 v0x5570afb2ce50_0; + %parti/s 1, 0, 2; + %assign/vec4 v0x5570afb2c540_0, 0; + %load/vec4 v0x5570afb2c540_0; + %assign/vec4 v0x5570afb2c880_0, 0; + %load/vec4 v0x5570afb2cbd0_0; + %load/vec4 v0x5570afb2c880_0; + %or; + %assign/vec4 v0x5570afb2cbd0_0, 0; + %jmp T_15.57; +T_15.56 ; + %pushi/vec4 8, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; +T_15.57 ; + %jmp T_15.13; +T_15.10 ; + %load/vec4 v0x5570afb2c540_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_15.60, 9; + %load/vec4 v0x5570afb2c880_0; + %load/vec4 v0x5570afb2cbd0_0; + %or; + %load/vec4 v0x5570afb2ce50_0; + %parti/s 1, 0, 2; + %or; + %and; +T_15.60; + %flag_set/vec4 8; + %jmp/0xz T_15.58, 8; + %load/vec4 v0x5570afb2ce50_0; + %addi 1, 0, 24; + %assign/vec4 v0x5570afb2ce50_0, 0; + %load/vec4 v0x5570afb2ce50_0; + %cmpi/e 16777215, 0, 24; + %jmp/0xz T_15.61, 4; + %load/vec4 v0x5570afb2cd70_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb2cd70_0, 0; +T_15.61 ; +T_15.58 ; + %pushi/vec4 9, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.13; +T_15.11 ; + %load/vec4 v0x5570afb2ce50_0; + %parti/s 23, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2cd70_0; + %parti/s 8, 0, 2; + %addi 127, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2cf30_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2cd70_0; + %pad/s 32; + %cmpi/e 4294967170, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.65, 4; + %load/vec4 v0x5570afb2ce50_0; + %parti/s 1, 23, 6; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_15.65; + %flag_set/vec4 8; + %jmp/0xz T_15.63, 8; + %pushi/vec4 0, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; +T_15.63 ; + %load/vec4 v0x5570afb2cd70_0; + %pad/s 32; + %cmpi/e 4294967170, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_15.68, 4; + %load/vec4 v0x5570afb2ce50_0; + %pushi/vec4 0, 0, 24; + %cmp/e; + %flag_get/vec4 4; + %and; +T_15.68; + %flag_set/vec4 8; + %jmp/0xz T_15.66, 8; + %pushi/vec4 0, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; +T_15.66 ; + %load/vec4 v0x5570afb2cd70_0; + %pad/s 32; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_15.69, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; + %load/vec4 v0x5570afb2cf30_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2cc90_0, 4, 5; +T_15.69 ; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.13; +T_15.12 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb2c6e0_0, 0; + %load/vec4 v0x5570afb2cc90_0; + %assign/vec4 v0x5570afb2c7a0_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x5570afb2caf0_0, 0; + %jmp T_15.13; +T_15.13 ; + %pop/vec4 1; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_0x5570afb317d0; +T_16 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb331f0_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_16.0, 4; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb32e80_0, 0; + %jmp T_16.1; +T_16.0 ; + %load/vec4 v0x5570afb33290_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_16.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_16.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_16.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_16.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_16.6, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_16.7, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_16.8, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_16.9, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_16.10, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_16.11, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_16.12, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_16.13, 6; + %jmp T_16.14; +T_16.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb32e80_0, 0; + %load/vec4 v0x5570afb32c20_0; + %flag_set/vec4 8; + %jmp/0xz T_16.15, 8; + %load/vec4 v0x5570afb32a10_0; + %assign/vec4 v0x5570afb32280_0, 0; + %load/vec4 v0x5570afb32b60_0; + %assign/vec4 v0x5570afb325c0_0, 0; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; +T_16.15 ; + %jmp T_16.14; +T_16.3 ; + %load/vec4 v0x5570afb32280_0; + %parti/s 23, 0, 2; + %pad/u 24; + %assign/vec4 v0x5570afb32440_0, 0; + %load/vec4 v0x5570afb325c0_0; + %parti/s 23, 0, 2; + %pad/u 24; + %assign/vec4 v0x5570afb327d0_0, 0; + %load/vec4 v0x5570afb32280_0; + %parti/s 8, 23, 6; + %pad/u 10; + %subi 127, 0, 10; + %assign/vec4 v0x5570afb32360_0, 0; + %load/vec4 v0x5570afb325c0_0; + %parti/s 8, 23, 6; + %pad/u 10; + %subi 127, 0, 10; + %assign/vec4 v0x5570afb326f0_0, 0; + %load/vec4 v0x5570afb32280_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb32500_0, 0; + %load/vec4 v0x5570afb325c0_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb328b0_0, 0; + %pushi/vec4 2, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.14; +T_16.4 ; + %load/vec4 v0x5570afb32360_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_16.20, 4; + %load/vec4 v0x5570afb32440_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_16.20; + %flag_set/vec4 8; + %jmp/1 T_16.19, 8; + %load/vec4 v0x5570afb326f0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_16.21, 4; + %load/vec4 v0x5570afb327d0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_16.21; + %flag_set/vec4 9; + %flag_or 8, 9; +T_16.19; + %jmp/0xz T_16.17, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 11, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.18; +T_16.17 ; + %load/vec4 v0x5570afb32360_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %jmp/0xz T_16.22, 4; + %load/vec4 v0x5570afb32500_0; + %load/vec4 v0x5570afb328b0_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %load/vec4 v0x5570afb326f0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_16.26, 4; + %load/vec4 v0x5570afb327d0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_16.26; + %flag_set/vec4 8; + %jmp/0xz T_16.24, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; +T_16.24 ; + %pushi/vec4 11, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.23; +T_16.22 ; + %load/vec4 v0x5570afb326f0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %jmp/0xz T_16.27, 4; + %load/vec4 v0x5570afb32500_0; + %load/vec4 v0x5570afb328b0_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %load/vec4 v0x5570afb32360_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_16.31, 4; + %load/vec4 v0x5570afb32440_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_16.31; + %flag_set/vec4 8; + %jmp/0xz T_16.29, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; +T_16.29 ; + %pushi/vec4 11, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.28; +T_16.27 ; + %load/vec4 v0x5570afb32360_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_16.34, 4; + %load/vec4 v0x5570afb32440_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_16.34; + %flag_set/vec4 8; + %jmp/0xz T_16.32, 8; + %load/vec4 v0x5570afb32500_0; + %load/vec4 v0x5570afb328b0_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 11, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.33; +T_16.32 ; + %load/vec4 v0x5570afb326f0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_16.37, 4; + %load/vec4 v0x5570afb327d0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_16.37; + %flag_set/vec4 8; + %jmp/0xz T_16.35, 8; + %load/vec4 v0x5570afb32500_0; + %load/vec4 v0x5570afb328b0_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 11, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.36; +T_16.35 ; + %load/vec4 v0x5570afb32360_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %jmp/0xz T_16.38, 4; + %pushi/vec4 898, 0, 10; + %assign/vec4 v0x5570afb32360_0, 0; + %jmp T_16.39; +T_16.38 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb32440_0, 4, 5; +T_16.39 ; + %load/vec4 v0x5570afb326f0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %jmp/0xz T_16.40, 4; + %pushi/vec4 898, 0, 10; + %assign/vec4 v0x5570afb326f0_0, 0; + %jmp T_16.41; +T_16.40 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb327d0_0, 4, 5; +T_16.41 ; + %pushi/vec4 3, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; +T_16.36 ; +T_16.33 ; +T_16.28 ; +T_16.23 ; +T_16.18 ; + %jmp T_16.14; +T_16.5 ; + %load/vec4 v0x5570afb32440_0; + %parti/s 1, 23, 6; + %flag_set/vec4 8; + %jmp/0xz T_16.42, 8; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.43; +T_16.42 ; + %load/vec4 v0x5570afb32440_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb32440_0, 0; + %load/vec4 v0x5570afb32360_0; + %subi 1, 0, 10; + %assign/vec4 v0x5570afb32360_0, 0; +T_16.43 ; + %jmp T_16.14; +T_16.6 ; + %load/vec4 v0x5570afb327d0_0; + %parti/s 1, 23, 6; + %flag_set/vec4 8; + %jmp/0xz T_16.44, 8; + %pushi/vec4 5, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.45; +T_16.44 ; + %load/vec4 v0x5570afb327d0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb327d0_0, 0; + %load/vec4 v0x5570afb326f0_0; + %subi 1, 0, 10; + %assign/vec4 v0x5570afb326f0_0, 0; +T_16.45 ; + %jmp T_16.14; +T_16.7 ; + %load/vec4 v0x5570afb32500_0; + %load/vec4 v0x5570afb328b0_0; + %xor; + %assign/vec4 v0x5570afb336d0_0, 0; + %load/vec4 v0x5570afb32360_0; + %load/vec4 v0x5570afb326f0_0; + %add; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb33510_0, 0; + %load/vec4 v0x5570afb32440_0; + %pad/u 48; + %load/vec4 v0x5570afb327d0_0; + %pad/u 48; + %mul; + %assign/vec4 v0x5570afb32da0_0, 0; + %pushi/vec4 6, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.14; +T_16.8 ; + %load/vec4 v0x5570afb32da0_0; + %parti/s 24, 24, 6; + %assign/vec4 v0x5570afb335f0_0, 0; + %load/vec4 v0x5570afb32da0_0; + %parti/s 1, 23, 6; + %assign/vec4 v0x5570afb32ce0_0, 0; + %load/vec4 v0x5570afb32da0_0; + %parti/s 1, 22, 6; + %assign/vec4 v0x5570afb33020_0, 0; + %load/vec4 v0x5570afb32da0_0; + %parti/s 22, 0, 2; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %assign/vec4 v0x5570afb33370_0, 0; + %pushi/vec4 7, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.14; +T_16.9 ; + %load/vec4 v0x5570afb335f0_0; + %parti/s 1, 23, 6; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_16.46, 4; + %load/vec4 v0x5570afb33510_0; + %subi 1, 0, 10; + %assign/vec4 v0x5570afb33510_0, 0; + %load/vec4 v0x5570afb335f0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb335f0_0, 0; + %load/vec4 v0x5570afb32ce0_0; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb335f0_0, 4, 5; + %load/vec4 v0x5570afb33020_0; + %assign/vec4 v0x5570afb32ce0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb33020_0, 0; + %jmp T_16.47; +T_16.46 ; + %pushi/vec4 8, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; +T_16.47 ; + %jmp T_16.14; +T_16.10 ; + %load/vec4 v0x5570afb33510_0; + %pad/s 32; + %cmpi/s 4294967170, 0, 32; + %jmp/0xz T_16.48, 5; + %load/vec4 v0x5570afb33510_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb33510_0, 0; + %load/vec4 v0x5570afb335f0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0x5570afb335f0_0, 0; + %load/vec4 v0x5570afb335f0_0; + %parti/s 1, 0, 2; + %assign/vec4 v0x5570afb32ce0_0, 0; + %load/vec4 v0x5570afb32ce0_0; + %assign/vec4 v0x5570afb33020_0, 0; + %load/vec4 v0x5570afb33370_0; + %load/vec4 v0x5570afb33020_0; + %or; + %assign/vec4 v0x5570afb33370_0, 0; + %jmp T_16.49; +T_16.48 ; + %pushi/vec4 9, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; +T_16.49 ; + %jmp T_16.14; +T_16.11 ; + %load/vec4 v0x5570afb32ce0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_16.52, 9; + %load/vec4 v0x5570afb33020_0; + %load/vec4 v0x5570afb33370_0; + %or; + %load/vec4 v0x5570afb335f0_0; + %parti/s 1, 0, 2; + %or; + %and; +T_16.52; + %flag_set/vec4 8; + %jmp/0xz T_16.50, 8; + %load/vec4 v0x5570afb335f0_0; + %addi 1, 0, 24; + %assign/vec4 v0x5570afb335f0_0, 0; + %load/vec4 v0x5570afb335f0_0; + %cmpi/e 16777215, 0, 24; + %jmp/0xz T_16.53, 4; + %load/vec4 v0x5570afb33510_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb33510_0, 0; +T_16.53 ; +T_16.50 ; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.14; +T_16.12 ; + %load/vec4 v0x5570afb335f0_0; + %parti/s 23, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %load/vec4 v0x5570afb33510_0; + %parti/s 8, 0, 2; + %addi 127, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %load/vec4 v0x5570afb336d0_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %load/vec4 v0x5570afb33510_0; + %pad/s 32; + %cmpi/e 4294967170, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_16.57, 4; + %load/vec4 v0x5570afb335f0_0; + %parti/s 1, 23, 6; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_16.57; + %flag_set/vec4 8; + %jmp/0xz T_16.55, 8; + %pushi/vec4 0, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; +T_16.55 ; + %load/vec4 v0x5570afb33510_0; + %pad/s 32; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_16.58, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; + %load/vec4 v0x5570afb336d0_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb33430_0, 4, 5; +T_16.58 ; + %pushi/vec4 11, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.14; +T_16.13 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb32e80_0, 0; + %load/vec4 v0x5570afb33430_0; + %assign/vec4 v0x5570afb32f40_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x5570afb33290_0, 0; + %jmp T_16.14; +T_16.14 ; + %pop/vec4 1; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_0x5570afab4b20; +T_17 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb2ee00_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_17.0, 4; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2eac0_0, 0; + %jmp T_17.1; +T_17.0 ; + %load/vec4 v0x5570afb2eea0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_17.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_17.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_17.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_17.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_17.6, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_17.7, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_17.8, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_17.9, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_17.10, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_17.11, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_17.12, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_17.13, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_17.14, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_17.15, 6; + %jmp T_17.16; +T_17.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2eac0_0, 0; + %load/vec4 v0x5570afb2e750_0; + %flag_set/vec4 8; + %jmp/0xz T_17.17, 8; + %load/vec4 v0x5570afb2e450_0; + %assign/vec4 v0x5570afb2dbe0_0, 0; + %load/vec4 v0x5570afb2e510_0; + %assign/vec4 v0x5570afb2df20_0, 0; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; +T_17.17 ; + %jmp T_17.16; +T_17.3 ; + %load/vec4 v0x5570afb2dbe0_0; + %parti/s 23, 0, 2; + %pad/u 24; + %assign/vec4 v0x5570afb2dda0_0, 0; + %load/vec4 v0x5570afb2df20_0; + %parti/s 23, 0, 2; + %pad/u 24; + %assign/vec4 v0x5570afb2e130_0, 0; + %load/vec4 v0x5570afb2dbe0_0; + %parti/s 8, 23, 6; + %pad/u 10; + %subi 127, 0, 10; + %assign/vec4 v0x5570afb2dcc0_0, 0; + %load/vec4 v0x5570afb2df20_0; + %parti/s 8, 23, 6; + %pad/u 10; + %subi 127, 0, 10; + %assign/vec4 v0x5570afb2e050_0, 0; + %load/vec4 v0x5570afb2dbe0_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb2de60_0, 0; + %load/vec4 v0x5570afb2df20_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb2e210_0, 0; + %pushi/vec4 2, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.16; +T_17.4 ; + %load/vec4 v0x5570afb2dcc0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.22, 4; + %load/vec4 v0x5570afb2dda0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_17.22; + %flag_set/vec4 8; + %jmp/1 T_17.21, 8; + %load/vec4 v0x5570afb2e050_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.23, 4; + %load/vec4 v0x5570afb2e130_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_17.23; + %flag_set/vec4 9; + %flag_or 8, 9; +T_17.21; + %jmp/0xz T_17.19, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.20; +T_17.19 ; + %load/vec4 v0x5570afb2dcc0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.26, 4; + %load/vec4 v0x5570afb2e050_0; + %pad/u 32; + %pushi/vec4 128, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_17.26; + %flag_set/vec4 8; + %jmp/0xz T_17.24, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.25; +T_17.24 ; + %load/vec4 v0x5570afb2dcc0_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %jmp/0xz T_17.27, 4; + %load/vec4 v0x5570afb2de60_0; + %load/vec4 v0x5570afb2e210_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %load/vec4 v0x5570afb2e050_0; + %pad/u 32; + %pushi/vec4 4294967169, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_17.31, 9; + %load/vec4 v0x5570afb2e130_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_17.31; + %flag_set/vec4 8; + %jmp/0xz T_17.29, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; +T_17.29 ; + %jmp T_17.28; +T_17.27 ; + %load/vec4 v0x5570afb2e050_0; + %pad/u 32; + %cmpi/e 128, 0, 32; + %jmp/0xz T_17.32, 4; + %load/vec4 v0x5570afb2de60_0; + %load/vec4 v0x5570afb2e210_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.33; +T_17.32 ; + %load/vec4 v0x5570afb2dcc0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.36, 4; + %load/vec4 v0x5570afb2dda0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_17.36; + %flag_set/vec4 8; + %jmp/0xz T_17.34, 8; + %load/vec4 v0x5570afb2de60_0; + %load/vec4 v0x5570afb2e210_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %load/vec4 v0x5570afb2e050_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.39, 4; + %load/vec4 v0x5570afb2e130_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_17.39; + %flag_set/vec4 8; + %jmp/0xz T_17.37, 8; + %pushi/vec4 1, 0, 1; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 22; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; +T_17.37 ; + %jmp T_17.35; +T_17.34 ; + %load/vec4 v0x5570afb2e050_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.42, 4; + %load/vec4 v0x5570afb2e130_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_17.42; + %flag_set/vec4 8; + %jmp/0xz T_17.40, 8; + %load/vec4 v0x5570afb2de60_0; + %load/vec4 v0x5570afb2e210_0; + %xor; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.41; +T_17.40 ; + %load/vec4 v0x5570afb2dcc0_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %jmp/0xz T_17.43, 4; + %pushi/vec4 898, 0, 10; + %assign/vec4 v0x5570afb2dcc0_0, 0; + %jmp T_17.44; +T_17.43 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2dda0_0, 4, 5; +T_17.44 ; + %load/vec4 v0x5570afb2e050_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %jmp/0xz T_17.45, 4; + %pushi/vec4 898, 0, 10; + %assign/vec4 v0x5570afb2e050_0, 0; + %jmp T_17.46; +T_17.45 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2e130_0, 4, 5; +T_17.46 ; + %pushi/vec4 3, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; +T_17.41 ; +T_17.35 ; +T_17.33 ; +T_17.28 ; +T_17.25 ; +T_17.20 ; + %jmp T_17.16; +T_17.5 ; + %load/vec4 v0x5570afb2dda0_0; + %parti/s 1, 23, 6; + %flag_set/vec4 8; + %jmp/0xz T_17.47, 8; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.48; +T_17.47 ; + %load/vec4 v0x5570afb2dda0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2dda0_0, 0; + %load/vec4 v0x5570afb2dcc0_0; + %subi 1, 0, 10; + %assign/vec4 v0x5570afb2dcc0_0, 0; +T_17.48 ; + %jmp T_17.16; +T_17.6 ; + %load/vec4 v0x5570afb2e130_0; + %parti/s 1, 23, 6; + %flag_set/vec4 8; + %jmp/0xz T_17.49, 8; + %pushi/vec4 5, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.50; +T_17.49 ; + %load/vec4 v0x5570afb2e130_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2e130_0, 0; + %load/vec4 v0x5570afb2e050_0; + %subi 1, 0, 10; + %assign/vec4 v0x5570afb2e050_0, 0; +T_17.50 ; + %jmp T_17.16; +T_17.7 ; + %load/vec4 v0x5570afb2de60_0; + %load/vec4 v0x5570afb2e210_0; + %xor; + %assign/vec4 v0x5570afb2f2e0_0, 0; + %load/vec4 v0x5570afb2dcc0_0; + %load/vec4 v0x5570afb2e050_0; + %sub; + %assign/vec4 v0x5570afb2f120_0, 0; + %pushi/vec4 0, 0, 51; + %assign/vec4 v0x5570afb2e8d0_0, 0; + %pushi/vec4 0, 0, 51; + %assign/vec4 v0x5570afb2eb80_0, 0; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x5570afb2e370_0, 0; + %load/vec4 v0x5570afb2dda0_0; + %pad/u 51; + %ix/load 4, 27, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2e5b0_0, 0; + %load/vec4 v0x5570afb2e130_0; + %pad/u 51; + %assign/vec4 v0x5570afb2e670_0, 0; + %pushi/vec4 6, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.16; +T_17.8 ; + %load/vec4 v0x5570afb2e8d0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2e8d0_0, 0; + %load/vec4 v0x5570afb2eb80_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2eb80_0, 0; + %load/vec4 v0x5570afb2e5b0_0; + %parti/s 1, 50, 7; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2eb80_0, 4, 5; + %load/vec4 v0x5570afb2e5b0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2e5b0_0, 0; + %pushi/vec4 7, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.16; +T_17.9 ; + %load/vec4 v0x5570afb2e670_0; + %load/vec4 v0x5570afb2eb80_0; + %cmp/u; + %flag_or 5, 4; + %jmp/0xz T_17.51, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2e8d0_0, 4, 5; + %load/vec4 v0x5570afb2eb80_0; + %load/vec4 v0x5570afb2e670_0; + %sub; + %assign/vec4 v0x5570afb2eb80_0, 0; +T_17.51 ; + %load/vec4 v0x5570afb2e370_0; + %pad/u 32; + %cmpi/e 49, 0, 32; + %jmp/0xz T_17.53, 4; + %pushi/vec4 8, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.54; +T_17.53 ; + %load/vec4 v0x5570afb2e370_0; + %addi 1, 0, 6; + %assign/vec4 v0x5570afb2e370_0, 0; + %pushi/vec4 6, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; +T_17.54 ; + %jmp T_17.16; +T_17.10 ; + %load/vec4 v0x5570afb2e8d0_0; + %parti/s 24, 3, 3; + %assign/vec4 v0x5570afb2f200_0, 0; + %load/vec4 v0x5570afb2e8d0_0; + %parti/s 1, 2, 3; + %assign/vec4 v0x5570afb2e810_0, 0; + %load/vec4 v0x5570afb2e8d0_0; + %parti/s 1, 1, 2; + %assign/vec4 v0x5570afb2ed40_0, 0; + %load/vec4 v0x5570afb2e8d0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x5570afb2eb80_0; + %pushi/vec4 0, 0, 51; + %cmp/ne; + %flag_get/vec4 4; + %or; + %assign/vec4 v0x5570afb2ef80_0, 0; + %pushi/vec4 9, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.16; +T_17.11 ; + %load/vec4 v0x5570afb2f200_0; + %parti/s 1, 23, 6; + %pad/u 32; + %cmpi/e 0, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.57, 4; + %pushi/vec4 4294967170, 0, 32; + %load/vec4 v0x5570afb2f120_0; + %pad/s 32; + %cmp/s; + %flag_get/vec4 5; + %and; +T_17.57; + %flag_set/vec4 8; + %jmp/0xz T_17.55, 8; + %load/vec4 v0x5570afb2f120_0; + %subi 1, 0, 10; + %assign/vec4 v0x5570afb2f120_0, 0; + %load/vec4 v0x5570afb2f200_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb2f200_0, 0; + %load/vec4 v0x5570afb2e810_0; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f200_0, 4, 5; + %load/vec4 v0x5570afb2ed40_0; + %assign/vec4 v0x5570afb2e810_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2ed40_0, 0; + %jmp T_17.56; +T_17.55 ; + %pushi/vec4 10, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; +T_17.56 ; + %jmp T_17.16; +T_17.12 ; + %load/vec4 v0x5570afb2f120_0; + %pad/s 32; + %cmpi/s 4294967170, 0, 32; + %jmp/0xz T_17.58, 5; + %load/vec4 v0x5570afb2f120_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb2f120_0, 0; + %load/vec4 v0x5570afb2f200_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0x5570afb2f200_0, 0; + %load/vec4 v0x5570afb2f200_0; + %parti/s 1, 0, 2; + %assign/vec4 v0x5570afb2e810_0, 0; + %load/vec4 v0x5570afb2e810_0; + %assign/vec4 v0x5570afb2ed40_0, 0; + %load/vec4 v0x5570afb2ef80_0; + %load/vec4 v0x5570afb2ed40_0; + %or; + %assign/vec4 v0x5570afb2ef80_0, 0; + %jmp T_17.59; +T_17.58 ; + %pushi/vec4 11, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; +T_17.59 ; + %jmp T_17.16; +T_17.13 ; + %load/vec4 v0x5570afb2e810_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_17.62, 9; + %load/vec4 v0x5570afb2ed40_0; + %load/vec4 v0x5570afb2ef80_0; + %or; + %load/vec4 v0x5570afb2f200_0; + %parti/s 1, 0, 2; + %or; + %and; +T_17.62; + %flag_set/vec4 8; + %jmp/0xz T_17.60, 8; + %load/vec4 v0x5570afb2f200_0; + %addi 1, 0, 24; + %assign/vec4 v0x5570afb2f200_0, 0; + %load/vec4 v0x5570afb2f200_0; + %cmpi/e 16777215, 0, 24; + %jmp/0xz T_17.63, 4; + %load/vec4 v0x5570afb2f120_0; + %addi 1, 0, 10; + %assign/vec4 v0x5570afb2f120_0, 0; +T_17.63 ; +T_17.60 ; + %pushi/vec4 12, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.16; +T_17.14 ; + %load/vec4 v0x5570afb2f200_0; + %parti/s 23, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %load/vec4 v0x5570afb2f120_0; + %parti/s 8, 0, 2; + %addi 127, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %load/vec4 v0x5570afb2f2e0_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %load/vec4 v0x5570afb2f120_0; + %pad/s 32; + %cmpi/e 4294967170, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_17.67, 4; + %load/vec4 v0x5570afb2f200_0; + %parti/s 1, 23, 6; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_17.67; + %flag_set/vec4 8; + %jmp/0xz T_17.65, 8; + %pushi/vec4 0, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; +T_17.65 ; + %load/vec4 v0x5570afb2f120_0; + %pad/s 32; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_17.68, 5; + %pushi/vec4 0, 0, 23; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %pushi/vec4 255, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; + %load/vec4 v0x5570afb2f2e0_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2f040_0, 4, 5; +T_17.68 ; + %pushi/vec4 13, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.16; +T_17.15 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb2eac0_0, 0; + %load/vec4 v0x5570afb2f040_0; + %assign/vec4 v0x5570afb2ec60_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x5570afb2eea0_0, 0; + %jmp T_17.16; +T_17.16 ; + %pop/vec4 1; +T_17.1 ; + %jmp T_17; + .thread T_17; + .scope S_0x5570afab4ea0; +T_18 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb30130_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_18.0, 4; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2ff90_0, 0; + %jmp T_18.1; +T_18.0 ; + %load/vec4 v0x5570afb301d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_18.2, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_18.3, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_18.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_18.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_18.6, 6; + %jmp T_18.7; +T_18.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb2ff90_0, 0; + %load/vec4 v0x5570afb2fed0_0; + %flag_set/vec4 8; + %jmp/0xz T_18.8, 8; + %load/vec4 v0x5570afb2fdc0_0; + %assign/vec4 v0x5570afb2f960_0, 0; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; +T_18.8 ; + %jmp T_18.7; +T_18.3 ; + %pushi/vec4 1, 0, 1; + %load/vec4 v0x5570afb2f960_0; + %parti/s 23, 0, 2; + %concat/vec4; draw_concat_vec4 + %ix/load 4, 8, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2fb20_0, 4, 5; + %pushi/vec4 0, 0, 8; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb2fb20_0, 4, 5; + %load/vec4 v0x5570afb2f960_0; + %parti/s 8, 23, 6; + %pad/u 9; + %subi 127, 0, 9; + %assign/vec4 v0x5570afb2fa40_0, 0; + %load/vec4 v0x5570afb2f960_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb2fc10_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; + %jmp T_18.7; +T_18.4 ; + %load/vec4 v0x5570afb2fa40_0; + %pad/s 32; + %cmpi/e 4294967169, 0, 32; + %jmp/0xz T_18.10, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x5570afb302b0_0, 0; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; + %jmp T_18.11; +T_18.10 ; + %load/vec4 v0x5570afb2fa40_0; + %pad/s 32; + %cmpi/s 31, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_18.12, 5; + %pushi/vec4 2147483648, 0, 32; + %assign/vec4 v0x5570afb302b0_0, 0; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; + %jmp T_18.13; +T_18.12 ; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; +T_18.13 ; +T_18.11 ; + %jmp T_18.7; +T_18.5 ; + %load/vec4 v0x5570afb2fa40_0; + %pad/s 32; + %cmpi/s 31, 0, 32; + %flag_get/vec4 5; + %jmp/0 T_18.16, 5; + %load/vec4 v0x5570afb2fb20_0; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_18.16; + %flag_set/vec4 8; + %jmp/0xz T_18.14, 8; + %load/vec4 v0x5570afb2fa40_0; + %addi 1, 0, 9; + %assign/vec4 v0x5570afb2fa40_0, 0; + %load/vec4 v0x5570afb2fb20_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0x5570afb2fb20_0, 0; + %jmp T_18.15; +T_18.14 ; + %load/vec4 v0x5570afb2fb20_0; + %parti/s 1, 31, 6; + %flag_set/vec4 8; + %jmp/0xz T_18.17, 8; + %pushi/vec4 2147483648, 0, 32; + %assign/vec4 v0x5570afb302b0_0, 0; + %jmp T_18.18; +T_18.17 ; + %load/vec4 v0x5570afb2fc10_0; + %flag_set/vec4 8; + %jmp/0 T_18.19, 8; + %load/vec4 v0x5570afb2fb20_0; + %inv; + %pushi/vec4 1, 0, 32; + %add; + %jmp/1 T_18.20, 8; +T_18.19 ; End of true expr. + %load/vec4 v0x5570afb2fb20_0; + %jmp/0 T_18.20, 8; + ; End of false expr. + %blend; +T_18.20; + %assign/vec4 v0x5570afb302b0_0, 0; +T_18.18 ; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; +T_18.15 ; + %jmp T_18.7; +T_18.6 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb2ff90_0, 0; + %load/vec4 v0x5570afb302b0_0; + %assign/vec4 v0x5570afb30050_0, 0; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x5570afb301d0_0, 0; + %jmp T_18.7; +T_18.7 ; + %pop/vec4 1; +T_18.1 ; + %jmp T_18; + .thread T_18; + .scope S_0x5570afab5220; +T_19 ; + %wait E_0x5570afb2bad0; + %load/vec4 v0x5570afb30e60_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_19.0, 4; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb30c00_0, 0; + %jmp T_19.1; +T_19.0 ; + %load/vec4 v0x5570afb30f00_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_19.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_19.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_19.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_19.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_19.6, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_19.7, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_19.8, 6; + %jmp T_19.9; +T_19.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb30c00_0, 0; + %load/vec4 v0x5570afb30aa0_0; + %flag_set/vec4 8; + %jmp/0xz T_19.10, 8; + %load/vec4 v0x5570afb30a00_0; + %assign/vec4 v0x5570afb30860_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; +T_19.10 ; + %jmp T_19.9; +T_19.3 ; + %load/vec4 v0x5570afb30860_0; + %cmpi/e 0, 0, 32; + %jmp/0xz T_19.12, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb31500_0, 0; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x5570afb31340_0, 0; + %pushi/vec4 129, 0, 8; + %assign/vec4 v0x5570afb31260_0, 0; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; + %jmp T_19.13; +T_19.12 ; + %load/vec4 v0x5570afb30860_0; + %parti/s 1, 31, 6; + %flag_set/vec4 8; + %jmp/0 T_19.14, 8; + %load/vec4 v0x5570afb30860_0; + %inv; + %pushi/vec4 1, 0, 32; + %add; + %jmp/1 T_19.15, 8; +T_19.14 ; End of true expr. + %load/vec4 v0x5570afb30860_0; + %jmp/0 T_19.15, 8; + ; End of false expr. + %blend; +T_19.15; + %assign/vec4 v0x5570afb310a0_0, 0; + %load/vec4 v0x5570afb30860_0; + %parti/s 1, 31, 6; + %assign/vec4 v0x5570afb31500_0, 0; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; +T_19.13 ; + %jmp T_19.9; +T_19.4 ; + %pushi/vec4 31, 0, 8; + %assign/vec4 v0x5570afb31260_0, 0; + %load/vec4 v0x5570afb310a0_0; + %parti/s 24, 8, 5; + %assign/vec4 v0x5570afb31340_0, 0; + %load/vec4 v0x5570afb310a0_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x5570afb31420_0, 0; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; + %jmp T_19.9; +T_19.5 ; + %load/vec4 v0x5570afb31340_0; + %parti/s 1, 23, 6; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_19.16, 8; + %load/vec4 v0x5570afb31260_0; + %subi 1, 0, 8; + %assign/vec4 v0x5570afb31260_0, 0; + %load/vec4 v0x5570afb31340_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb31340_0, 0; + %load/vec4 v0x5570afb31420_0; + %parti/s 1, 7, 4; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb31340_0, 4, 5; + %load/vec4 v0x5570afb31420_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %assign/vec4 v0x5570afb31420_0, 0; + %jmp T_19.17; +T_19.16 ; + %load/vec4 v0x5570afb31420_0; + %parti/s 1, 7, 4; + %assign/vec4 v0x5570afb30b40_0, 0; + %load/vec4 v0x5570afb31420_0; + %parti/s 1, 6, 4; + %assign/vec4 v0x5570afb30da0_0, 0; + %load/vec4 v0x5570afb31420_0; + %parti/s 6, 0, 2; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %assign/vec4 v0x5570afb30fe0_0, 0; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; +T_19.17 ; + %jmp T_19.9; +T_19.6 ; + %load/vec4 v0x5570afb30b40_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_19.20, 9; + %load/vec4 v0x5570afb30da0_0; + %flag_set/vec4 9; + %jmp/1 T_19.22, 9; + %load/vec4 v0x5570afb30fe0_0; + %flag_set/vec4 10; + %flag_or 9, 10; +T_19.22; + %flag_get/vec4 9; + %jmp/1 T_19.21, 9; + %load/vec4 v0x5570afb31340_0; + %parti/s 1, 0, 2; + %or; +T_19.21; + %and; +T_19.20; + %flag_set/vec4 8; + %jmp/0xz T_19.18, 8; + %load/vec4 v0x5570afb31340_0; + %addi 1, 0, 24; + %assign/vec4 v0x5570afb31340_0, 0; + %load/vec4 v0x5570afb31340_0; + %cmpi/e 16777215, 0, 24; + %jmp/0xz T_19.23, 4; + %load/vec4 v0x5570afb31260_0; + %addi 1, 0, 8; + %assign/vec4 v0x5570afb31260_0, 0; +T_19.23 ; +T_19.18 ; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; + %jmp T_19.9; +T_19.7 ; + %load/vec4 v0x5570afb31340_0; + %parti/s 23, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb31180_0, 4, 5; + %load/vec4 v0x5570afb31260_0; + %addi 127, 0, 8; + %ix/load 4, 23, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb31180_0, 4, 5; + %load/vec4 v0x5570afb31500_0; + %ix/load 4, 31, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb31180_0, 4, 5; + %pushi/vec4 6, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; + %jmp T_19.9; +T_19.8 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb30c00_0, 0; + %load/vec4 v0x5570afb31180_0; + %assign/vec4 v0x5570afb30cc0_0, 0; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x5570afb30f00_0, 0; + %jmp T_19.9; +T_19.9 ; + %pop/vec4 1; +T_19.1 ; + %jmp T_19; + .thread T_19; + .scope S_0x5570afab3d20; +T_20 ; + %wait E_0x5570afb4fec0; + %load/vec4 v0x5570afb50220_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_20.0, 4; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x5570afb50140_0, 0; + %jmp T_20.1; +T_20.0 ; + %load/vec4 v0x5570afb4ffc0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_20.4, 9; + %load/vec4 v0x5570afb50330_0; + %parti/s 1, 0, 2; + %and; +T_20.4; + %flag_set/vec4 8; + %jmp/0xz T_20.2, 8; + %load/vec4 v0x5570afb50080_0; + %parti/s 8, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb50140_0, 4, 5; +T_20.2 ; + %load/vec4 v0x5570afb4ffc0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_20.7, 9; + %load/vec4 v0x5570afb50330_0; + %parti/s 1, 1, 2; + %and; +T_20.7; + %flag_set/vec4 8; + %jmp/0xz T_20.5, 8; + %load/vec4 v0x5570afb50080_0; + %parti/s 8, 8, 5; + %ix/load 4, 8, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb50140_0, 4, 5; +T_20.5 ; +T_20.1 ; + %jmp T_20; + .thread T_20; + .scope S_0x5570afadf340; +T_21 ; + %wait E_0x5570afb28d30; + %load/vec4 v0x5570afb50890_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_21.0, 4; + %load/vec4 v0x5570afb509a0_0; + %assign/vec4 v0x5570afb507b0_0, 0; + %jmp T_21.1; +T_21.0 ; + %load/vec4 v0x5570afb50630_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_21.4, 9; + %load/vec4 v0x5570afb50a80_0; + %parti/s 1, 0, 2; + %and; +T_21.4; + %flag_set/vec4 8; + %jmp/0xz T_21.2, 8; + %load/vec4 v0x5570afb506f0_0; + %parti/s 8, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb507b0_0, 4, 5; +T_21.2 ; + %load/vec4 v0x5570afb50630_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_21.7, 9; + %load/vec4 v0x5570afb50a80_0; + %parti/s 1, 1, 2; + %and; +T_21.7; + %flag_set/vec4 8; + %jmp/0xz T_21.5, 8; + %load/vec4 v0x5570afb506f0_0; + %parti/s 8, 8, 5; + %ix/load 4, 8, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb507b0_0, 4, 5; +T_21.5 ; + %load/vec4 v0x5570afb50630_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_21.10, 9; + %load/vec4 v0x5570afb50a80_0; + %parti/s 1, 2, 3; + %and; +T_21.10; + %flag_set/vec4 8; + %jmp/0xz T_21.8, 8; + %load/vec4 v0x5570afb506f0_0; + %parti/s 8, 16, 6; + %ix/load 4, 16, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb507b0_0, 4, 5; +T_21.8 ; + %load/vec4 v0x5570afb50630_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_21.13, 9; + %load/vec4 v0x5570afb50a80_0; + %parti/s 1, 3, 3; + %and; +T_21.13; + %flag_set/vec4 8; + %jmp/0xz T_21.11, 8; + %load/vec4 v0x5570afb506f0_0; + %parti/s 8, 24, 6; + %ix/load 4, 24, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x5570afb507b0_0, 4, 5; +T_21.11 ; +T_21.1 ; + %jmp T_21; + .thread T_21; + .scope S_0x5570afb50f80; +T_22 ; + %wait E_0x5570afb512e0; + %load/vec4 v0x5570afb51750_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_22.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb51580_0, 0; + %jmp T_22.1; +T_22.0 ; + %load/vec4 v0x5570afb51640_0; + %flag_set/vec4 8; + %jmp/0xz T_22.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x5570afb51580_0, 0; + %jmp T_22.3; +T_22.2 ; + %load/vec4 v0x5570afb514e0_0; + %load/vec4 v0x5570afb51420_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_22.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x5570afb51580_0, 0; +T_22.4 ; +T_22.3 ; +T_22.1 ; + %jmp T_22; + .thread T_22; +# The file index is used to find the file name in the following table. +:file_names 16; + "N/A"; + "<interactive>"; + "-"; + "../../lib/ctech_cells.sv"; + "fpu_wrapper.sv"; + "../../lib/reset_sync.sv"; + "../../fpu/verilog/rtl/fpu_sp_top.sv"; + "../../fpu/verilog/rtl//fpu_parms.v"; + "../../fpu/verilog/rtl/fpu_sp_add.sv"; + "../../fpu/verilog/rtl/fpu_sp_div.sv"; + "../../fpu/verilog/rtl/fpu_sp_f2i.sv"; + "../../fpu/verilog/rtl/fpu_sp_i2f.sv"; + "../../fpu/verilog/rtl/fpu_sp_mul.sv"; + "fpu_reg.sv"; + "../../lib/registers.v"; + "../../lib/clk_skew_adjust.gv";
diff --git a/verilog/rtl/fpu_wrapper/src/fpu_reg.sv b/verilog/rtl/fpu_wrapper/src/fpu_reg.sv new file mode 100644 index 0000000..8cb2bdd --- /dev/null +++ b/verilog/rtl/fpu_wrapper/src/fpu_reg.sv
@@ -0,0 +1,350 @@ +/********************************************************************************* + SPDX-FileCopyrightText: 2021 , Dinesh Annayya + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + SPDX-License-Identifier: Apache-2.0 + SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com> + +***********************************************************************************/ +/********************************************************************************** + + FPU Register Interface matching to RISCV DMEM i/f + + Description: + + To Do: + + Author(s): + - Dinesh Annayya, dinesh.annayya@gmail.com + + Revision : + 0.0 - Nov 9, 2022 + Initial Version + + +************************************************************************************/ + +module fpu_reg ( + input logic mclk , + input logic rst_n , + + + input logic dmem_req, + input logic dmem_cmd, + input logic [1:0] dmem_width, + input logic [4:0] dmem_addr, + input logic [31:0] dmem_wdata, + output logic dmem_req_ack, + output logic [31:0] dmem_rdata, + output logic [1:0] dmem_resp, + + + // Encription Reg Interface + output logic cfg_fpu_val , + input logic fpu_done , + output logic [3:0] cfg_fpu_cmd , + output logic [31:0] cfg_fpu_din1 , + output logic [31:0] cfg_fpu_din2 , + input logic [31:0] fpu_result + + + ); + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_cs ; +logic sw_rd_en ; +logic sw_wr_en ; +logic [2:0] sw_addr ; +logic [31:0] sw_reg_wdata ; +logic [3:0] sw_be ; + +logic [31:0] reg_out ; +logic [31:0] reg_0 ; +logic [31:0] reg_1 ; +logic [31:0] reg_2 ; +logic [31:0] reg_3 ; +logic cfg_fpu_req ; +logic cfg_fpu_req_l ; +logic [1:0] dmem_addr_l ; +logic [1:0] dmem_width_l ; + +//Generate Byte Select +function automatic logic[3:0] conv_bsel ( + input logic [1:0] hwidth, + input logic [1:0] haddr +); + logic [3:0] bsel; +begin + bsel = 'x; + case (hwidth) + 2'b00 : begin + case (haddr) + 2'b00 : bsel = 4'b0001; + 2'b01 : bsel = 4'b0010; + 2'b10 : bsel = 4'b0100; + 2'b11 : bsel = 4'b1000; + endcase + end + 2'b01 : begin + case (haddr[1]) + 1'b0 : bsel = 4'b0011; + 1'b1 : bsel = 4'b1100; + endcase + end + 2'b10 : begin + bsel = 4'b1111; + end + default : begin + end + endcase + conv_bsel = bsel; +end +endfunction + + +//Generate wdata based on width and address[1:0] +function automatic logic[31:0] conv_wdata ( + input logic [1:0] dmem_width, + input logic [1:0] dmem_addr, + input logic [31:0] dmem_wdata +); + logic [31:0] tmp; +begin + tmp = 'x; + case (dmem_width) + 2'b00 : begin + case (dmem_addr) + 2'b00 : begin + tmp[7:0] = dmem_wdata[7:0]; + end + 2'b01 : begin + tmp[15:8] = dmem_wdata[7:0]; + end + 2'b10 : begin + tmp[23:16] = dmem_wdata[7:0]; + end + 2'b11 : begin + tmp[31:24] = dmem_wdata[7:0]; + end + default : begin + end + endcase + end + 2'b01 : begin + case (dmem_addr[1]) + 1'b0 : begin + tmp[15:0] = dmem_wdata[15:0]; + end + 1'b1 : begin + tmp[31:16] = dmem_wdata[15:0]; + end + default : begin + end + endcase + end + 2'b10 : begin + tmp = dmem_wdata; + end + default : begin + end + endcase + conv_wdata = tmp; +end +endfunction + +//Generate rdata based on width and address[1:0] +function automatic logic[31:0] conv_rdata ( + input logic [1:0] hwidth, + input logic [1:0] haddr, + input logic [31:0] hrdata +); + logic [31:0] tmp; +begin + tmp = 'x; + case (hwidth) + 2'b00 : begin + case (haddr) + 2'b00 : tmp[7:0] = hrdata[7:0]; + 2'b01 : tmp[7:0] = hrdata[15:8]; + 2'b10 : tmp[7:0] = hrdata[23:16]; + 2'b11 : tmp[7:0] = hrdata[31:24]; + default : begin + end + endcase + end + 2'b01 : begin + case (haddr[1]) + 1'b0 : tmp[15:0] = hrdata[15:0]; + 1'b1 : tmp[15:0] = hrdata[31:16]; + default : begin + end + endcase + end + 2'b10 : begin + tmp = hrdata; + end + default : begin + end + endcase + conv_rdata = tmp; +end +endfunction + + +always_ff @(negedge rst_n, posedge mclk) begin + if (~rst_n) begin + sw_cs <= '0; + dmem_req_ack <= '0; + sw_rd_en <= '0; + sw_wr_en <= '0; + sw_addr <= '0; + sw_be <= '0; + sw_reg_wdata <= '0; + dmem_addr_l <= '0; + dmem_width_l <= '0; + end else begin + sw_cs <= (dmem_req) && (dmem_req_ack == 0) ; + dmem_req_ack <= dmem_req & (dmem_req_ack ==0) ; + sw_rd_en <= (dmem_cmd == 0); + sw_wr_en <= (dmem_cmd == 1); + sw_addr <= dmem_addr[4:2]; + dmem_addr_l <= dmem_addr[1:0]; + dmem_width_l <= dmem_width[1:0]; + sw_be <= conv_bsel(dmem_width,dmem_addr[1:0]); + sw_reg_wdata <= conv_wdata(dmem_width,dmem_addr[1:0],dmem_wdata); + end +end + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_cs & sw_wr_en & (sw_addr == 3'h0); +wire sw_wr_en_1 = sw_cs & sw_wr_en & (sw_addr == 3'h1); +wire sw_wr_en_2 = sw_cs & sw_wr_en & (sw_addr == 3'h2); +wire sw_wr_en_3 = sw_cs & sw_wr_en & (sw_addr == 3'h3); + +wire sw_rd_en_0 = sw_cs & sw_rd_en & (sw_addr == 3'h0); +wire sw_rd_en_1 = sw_cs & sw_rd_en & (sw_addr == 3'h1); +wire sw_rd_en_2 = sw_cs & sw_rd_en & (sw_addr == 3'h2); +wire sw_rd_en_3 = sw_cs & sw_rd_en & (sw_addr == 3'h3); + + + +always @ (posedge mclk or negedge rst_n) +begin : preg_out_Seq + if (rst_n == 1'b0) begin + dmem_resp <= 2'b00; + dmem_rdata <= 'h0; + end else if (sw_cs && sw_rd_en) begin + dmem_rdata <= conv_rdata(dmem_width_l,dmem_addr_l[1:0],reg_out); + dmem_resp <= 2'b01; + end else if (sw_cs && sw_wr_en) begin + dmem_resp <= 2'b01; + end else begin + dmem_resp <= 2'b00; + end +end + +//----------------------------------------------------------------------- +// Register Read Path Multiplexer instantiation +//----------------------------------------------------------------------- + +always_comb +begin + reg_out [31:0] = 32'h0; + + case (sw_addr [2:0]) + 3'b000 : reg_out [31:0] = reg_0 [31:0]; + 3'b001 : reg_out [31:0] = reg_1 [31:0]; + 3'b010 : reg_out [31:0] = reg_2 [31:0]; + 3'b011 : reg_out [31:0] = reg_3 [31:0]; + default : reg_out [31:0] = 32'h0; + endcase +end + + +assign cfg_fpu_val = (cfg_fpu_req && !cfg_fpu_req_l); + +always @ (posedge mclk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + cfg_fpu_req_l <= 1'b0; + end else begin + cfg_fpu_req_l <= cfg_fpu_req; + end +end +assign reg_0[31] = cfg_fpu_req; +assign reg_0[30:4] = 'h0; +assign reg_0[3:0] = cfg_fpu_cmd; + + +assign cfg_fpu_din1 = reg_1; +assign cfg_fpu_din2 = reg_2; +assign reg_3 = fpu_result; + +// Register-0 +generic_register #(4,0 ) u_reg0_3_0 ( + .we ({4{sw_wr_en_0 & + sw_be[0] }} ), + .data_in (sw_reg_wdata[3:0] ), + .reset_n (rst_n ), + .clk (mclk ), + + //List of Outs + .data_out (cfg_fpu_cmd ) + ); + +req_register #(0 ) u_reg0_31 ( + .cpu_we ({sw_wr_en_0 & + sw_be[3] }), + .cpu_req (sw_reg_wdata[31] ), + .hware_ack (fpu_done ), + .reset_n (rst_n ), + .clk (mclk ), + + //List of Outs + .data_out (cfg_fpu_req ) + ); + + +// Register-1 +gen_32b_reg #(32'h0) u_reg_1 ( + //List of Inputs + .reset_n (rst_n ), + .clk (mclk ), + .cs (sw_wr_en_1 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_1 ) + ); + +// Register-2 +gen_32b_reg #(32'h0) u_reg_2 ( + //List of Inputs + .reset_n (rst_n ), + .clk (mclk ), + .cs (sw_wr_en_2 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_2 ) + ); + + +endmodule
diff --git a/verilog/rtl/fpu_wrapper/src/fpu_wrapper.sv b/verilog/rtl/fpu_wrapper/src/fpu_wrapper.sv new file mode 100644 index 0000000..8fbc3ef --- /dev/null +++ b/verilog/rtl/fpu_wrapper/src/fpu_wrapper.sv
@@ -0,0 +1,143 @@ +/********************************************************************************* + SPDX-FileCopyrightText: 2021 , Dinesh Annayya + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + SPDX-License-Identifier: Apache-2.0 + SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com> + +***********************************************************************************/ +/********************************************************************************** + + FPU Wrapper + + Description + This module includes fpu register and FPU Single Point Computing logic + + To Do: + + Author(s): + - Dinesh Annayya, dinesh.annayya@gmail.com + + Revision : + 0.0 - Nov 9, 2022 + Initial Version + + +************************************************************************************/ + + +module fpu_wrapper #( parameter WB_WIDTH = 32) ( +`ifdef USE_POWER_PINS + input logic vccd1, // User area 1 1.8V supply + input logic vssd1, // User area 1 digital ground +`endif + + input logic mclk, + input logic rst_n, + + input logic [3:0] cfg_cska, + input logic wbd_clk_int, + output logic wbd_clk_out, + + input logic dmem_req, + input logic dmem_cmd, + input logic [1:0] dmem_width, + input logic [4:0] dmem_addr, + input logic [31:0] dmem_wdata, + output logic dmem_req_ack, + output logic [31:0] dmem_rdata, + output logic [1:0] dmem_resp +); + + +logic rst_ss_n; + +// FPU local variable +logic cfg_fpu_val ; +logic fpu_done ; +logic [3:0] cfg_fpu_cmd ; +logic [31:0] cfg_fpu_din1 ; +logic [31:0] cfg_fpu_din2 ; +logic [31:0] fpu_result ; + + + +//################################### +// Clock Skey for WB clock +//################################### +clk_skew_adjust u_skew + ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif + .clk_in (wbd_clk_int ), + .sel (cfg_cska ), + .clk_out (wbd_clk_out ) + ); + +//################################### +// Application Reset Synchronization +//################################### +reset_sync u_app_rst ( + .scan_mode (1'b0 ), + .dclk (mclk ), // Destination clock domain + .arst_n (rst_n ), // active low async reset + .srst_n (rst_ss_n ) + ); + + +//################################### +// FPU Register +//################################### +fpu_reg u_reg( + .mclk (mclk ), + .rst_n (rst_ss_n ), + + .dmem_req (dmem_req ), + .dmem_cmd (dmem_cmd ), + .dmem_width (dmem_width ), + .dmem_addr (dmem_addr ), + .dmem_wdata (dmem_wdata ), + .dmem_req_ack (dmem_req_ack ), + .dmem_rdata (dmem_rdata ), + .dmem_resp (dmem_resp ), + + // FPU Reg Interface + .cfg_fpu_val (cfg_fpu_val ), + .fpu_done (fpu_done ), + .cfg_fpu_cmd (cfg_fpu_cmd ), + .cfg_fpu_din1 (cfg_fpu_din1 ), + .cfg_fpu_din2 (cfg_fpu_din2 ), + .fpu_result (fpu_result ) + + ); + +//################################### +// FPU Single Point Precsion +//################################### +fpu_sp_top u_fpu_core( + .clk (mclk ), + .rst_n (rst_ss_n ), + .cmd (cfg_fpu_cmd ), + .din1 (cfg_fpu_din1 ), + .din2 (cfg_fpu_din2 ), + .dval (cfg_fpu_val ), + .result (fpu_result ), + .rdy (fpu_done ) +); + + +endmodule + +
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv index 25514f1..b3abb95 100644 --- a/verilog/rtl/pinmux/src/glbl_reg.sv +++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -66,7 +66,7 @@ // Global Reset control - output logic [1:0] cpu_core_rst_n , + output logic [3:0] cpu_core_rst_n , output logic cpu_intf_rst_n , output logic qspim_rst_n , output logic sspim_rst_n , @@ -282,6 +282,10 @@ ctech_buf u_buf_cpu0_rst (.A(cfg_rst_ctrl[8]),.X(cpu_core_rst_n[0])); ctech_buf u_buf_cpu1_rst (.A(cfg_rst_ctrl[9]),.X(cpu_core_rst_n[1])); +ctech_buf u_buf_cpu2_rst (.A(cfg_rst_ctrl[10]),.X(cpu_core_rst_n[2])); +ctech_buf u_buf_cpu3_rst (.A(cfg_rst_ctrl[11]),.X(cpu_core_rst_n[3])); + + //--------------------------------------------------------- // Default reset value decided based on riscv boot mode @@ -756,6 +760,9 @@ (cfg_mon_sel == 4'b110) ? usb_clk : (cfg_mon_sel == 4'b111) ? rtc_clk : 1'b0; +wire dbg_clk_ref_buf; +ctech_clk_buf u_clkbuf_dbg_ref (.A (dbg_clk_ref), . X(dbg_clk_ref_buf)); + // DIv16 to debug monitor purpose logic dbg_clk_div16; @@ -763,7 +770,7 @@ // Outputs .clk_o (dbg_clk_div16 ), // Inputs - .mclk (dbg_clk_ref ), + .mclk (dbg_clk_ref_buf ), .reset_n (e_reset_n ), .clk_div_ratio (4'hE ) );
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv index 491a4a0..58419e2 100755 --- a/verilog/rtl/pinmux/src/pinmux_top.sv +++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -106,7 +106,7 @@ output logic rtc_clk , // Global Reset control - output logic [1:0] cpu_core_rst_n , + output logic [3:0] cpu_core_rst_n , output logic cpu_intf_rst_n , output logic qspim_rst_n , output logic sspim_rst_n , @@ -196,8 +196,14 @@ output logic[4:0] cfg_pll_fed_div , // PLL feedback division ratio output logic cfg_dco_mode , // Run PLL in DCO mode output logic[25:0] cfg_dc_trim , // External trim for DCO mode - output logic pll_ref_clk // Input oscillator to match + output logic pll_ref_clk , // Input oscillator to match + + // DAC Config + output logic [7:0] cfg_dac0_mux_sel , + output logic [7:0] cfg_dac1_mux_sel , + output logic [7:0] cfg_dac2_mux_sel , + output logic [7:0] cfg_dac3_mux_sel ); @@ -261,6 +267,7 @@ `define SEL_TIMER 3'b011 // TIMER REGISTER `define SEL_SEMA 3'b100 // SEMAPHORE REGISTER `define SEL_WS 3'b101 // WS281x REGISTER +`define SEL_D2A 3'b110 // Digital2Analog REGISTER //---------------------------------------- @@ -284,28 +291,11 @@ logic [31:0] reg_ws_rdata; logic reg_ws_ack; +logic [31:0] reg_d2a_rdata; +logic reg_d2a_ack; + logic [7:0] pwm_gpio_in; -assign reg_rdata = (reg_addr[9:7] == `SEL_GLBL) ? {reg_glbl_rdata} : - (reg_addr[9:7] == `SEL_GPIO) ? {reg_gpio_rdata} : - (reg_addr[9:7] == `SEL_PWM) ? {reg_pwm_rdata} : - (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_rdata : - (reg_addr[9:7] == `SEL_SEMA) ? {16'h0,reg_sema_rdata} : - (reg_addr[9:7] == `SEL_WS) ? reg_ws_rdata : 'h0; - -assign reg_ack = (reg_addr[9:7] == `SEL_GLBL) ? reg_glbl_ack : - (reg_addr[9:7] == `SEL_GPIO) ? reg_gpio_ack : - (reg_addr[9:7] == `SEL_PWM) ? reg_pwm_ack : - (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_ack : - (reg_addr[9:7] == `SEL_SEMA) ? reg_sema_ack : - (reg_addr[9:7] == `SEL_WS) ? reg_ws_ack : 1'b0; - -wire reg_glbl_cs = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0; -wire reg_gpio_cs = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0; -wire reg_pwm_cs = (reg_addr[9:7] == `SEL_PWM) ? reg_cs : 1'b0; -wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0; -wire reg_sema_cs = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0; -wire reg_ws_cs = (reg_addr[9:7] == `SEL_WS) ? reg_cs : 1'b0; //--------------------------------------------------------------------- @@ -621,6 +611,72 @@ ); +//----------------------------------------------------------------------- +// Digital To Analog Register +//----------------------------------------------------------------------- +dig2ana_reg u_d2a( + // System Signals + // Inputs + .mclk ( mclk ), + .h_reset_n (s_reset_ssn ), + + // Reg Bus Interface Signal + .reg_cs (reg_d2a_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[5:2] ), + .reg_wdata (reg_wdata[31:0] ), + .reg_be (reg_be[3:0] ), + + // Outputs + .reg_rdata (reg_d2a_rdata ), + .reg_ack (reg_d2a_ack ), + + .cfg_dac0_mux_sel (cfg_dac0_mux_sel ), + .cfg_dac1_mux_sel (cfg_dac1_mux_sel ), + .cfg_dac2_mux_sel (cfg_dac2_mux_sel ), + .cfg_dac3_mux_sel (cfg_dac3_mux_sel ) + + + ); + +//------------------------------------------------- +// Register Block Selection Logic +//------------------------------------------------- +reg [2:0] reg_blk_sel; + +always @(posedge mclk or negedge s_reset_ssn) +begin + if(s_reset_ssn == 1'b0) begin + reg_blk_sel <= 'h0; + end + else begin + if(reg_cs) reg_blk_sel <= reg_addr[9:7]; + end +end + +assign reg_rdata = (reg_blk_sel == `SEL_GLBL) ? {reg_glbl_rdata} : + (reg_blk_sel == `SEL_GPIO) ? {reg_gpio_rdata} : + (reg_blk_sel == `SEL_PWM) ? {reg_pwm_rdata} : + (reg_blk_sel == `SEL_TIMER) ? reg_timer_rdata : + (reg_blk_sel == `SEL_SEMA) ? {16'h0,reg_sema_rdata} : + (reg_blk_sel == `SEL_WS) ? reg_ws_rdata : + (reg_blk_sel == `SEL_D2A) ? reg_d2a_rdata : 'h0; + +assign reg_ack = (reg_blk_sel == `SEL_GLBL) ? reg_glbl_ack : + (reg_blk_sel == `SEL_GPIO) ? reg_gpio_ack : + (reg_blk_sel == `SEL_PWM) ? reg_pwm_ack : + (reg_blk_sel == `SEL_TIMER) ? reg_timer_ack : + (reg_blk_sel == `SEL_SEMA) ? reg_sema_ack : + (reg_blk_sel == `SEL_WS) ? reg_ws_ack : + (reg_blk_sel == `SEL_D2A) ? reg_d2a_ack : 1'b0; + +wire reg_glbl_cs = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0; +wire reg_gpio_cs = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0; +wire reg_pwm_cs = (reg_addr[9:7] == `SEL_PWM) ? reg_cs : 1'b0; +wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0; +wire reg_sema_cs = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0; +wire reg_ws_cs = (reg_addr[9:7] == `SEL_WS) ? reg_cs : 1'b0; +wire reg_d2a_cs = (reg_addr[9:7] == `SEL_D2A) ? reg_cs : 1'b0; endmodule
diff --git a/verilog/rtl/pwm/src/pwm.sv b/verilog/rtl/pwm/src/pwm.sv index 922c369..2ed7a03 100644 --- a/verilog/rtl/pwm/src/pwm.sv +++ b/verilog/rtl/pwm/src/pwm.sv
@@ -45,7 +45,7 @@ logic [15:0] pwm_cnt ; // PWM counter logic cnt_trg ; logic pwm_wfm_i ; -logic pwm_wfm_hold; +logic pwm_wfm_r ; // Register pwm logic comp0_match ; logic comp1_match ; logic comp2_match ; @@ -214,25 +214,27 @@ always @(posedge mclk or negedge h_reset_n) begin if ( ~h_reset_n ) begin - pwm_wfm_hold <= 1'b0; - end else if(cfg_pwm_enb) begin - pwm_wfm_hold <= pwm_wfm_i; + pwm_wfm_r <= 1'b0; + end else begin + if(cfg_pwm_hold) begin + if(cfg_pwm_enb ) begin + pwm_wfm_r <= pwm_wfm_i; + end + end else begin + pwm_wfm_r <= pwm_wfm_i; + end end end + //-------------------------------------------- // Final Waveform output generation based // on pwm_hold and pwm_inv combination //-------------------------------------------- always_comb begin pwm_wfm_o = 0; - if(!cfg_pwm_enb && cfg_pwm_hold) begin - if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_hold; - else pwm_wfm_o = pwm_wfm_hold; - end else begin - if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_i; - else pwm_wfm_o = pwm_wfm_i; - end + if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_r; + else pwm_wfm_o = pwm_wfm_r; end //----------------------------------------
diff --git a/verilog/rtl/security_core b/verilog/rtl/security_core new file mode 160000 index 0000000..472d98e --- /dev/null +++ b/verilog/rtl/security_core
@@ -0,0 +1 @@ +Subproject commit 472d98ee3bfb82a4adaf40b7d5d329ba61f51588
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh index 325c436..faf789f 100644 --- a/verilog/rtl/user_params.svh +++ b/verilog/rtl/user_params.svh
@@ -4,13 +4,14 @@ // ASCI Representation of RISC = 32'h8273_8343 parameter CHIP_SIGNATURE = 32'h8273_8343; // Software Reg-1, Release date: <DAY><MONTH><YEAR> -parameter CHIP_RELEASE_DATE = 32'h1409_2022; +parameter CHIP_RELEASE_DATE = 32'h0711_2022; // Software Reg-2: Poject Revison 5.1 = 0005200 -parameter CHIP_REVISION = 32'h0005_5000; +parameter CHIP_REVISION = 32'h0005_7000; -parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_0111; +parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_0111_1010_1000_1001_1100; +parameter CLK_SKEW2_RESET_VAL = 32'b0000; -parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1010_0000; +parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000; /***************************************************** pad_strap_in decoding @@ -40,8 +41,8 @@ 0 - Cache Enable 1 - Bypass cache (Default) bit [10] - Riscv SRAM clock edge selection - 0 - Normal - 1 - Invert (Default) + 0 - Normal (Default) + 1 - Invert bit [12:11] - Skew selection 2'b00 - Default value (Default) 2'b01 - Default value + 2 @@ -138,13 +139,13 @@ `define STRAP_RISCV_CACHE_BYPASS 13 `define STRAP_RISCV_SRAM_CLK_EDGE 14 `define STRAP_QSPI_PRE_SRAM 15 // Previous SRAM Strap Status -`define STRAP_CLK_SKEW_WI 17:16 -`define STRAP_CLK_SKEW_WH 19:18 -`define STRAP_CLK_SKEW_RISCV 21:20 -`define STRAP_CLK_SKEW_QSPI 23:22 -`define STRAP_CLK_SKEW_UART 25:24 -`define STRAP_CLK_SKEW_PINMUX 27:26 -`define STRAP_CLK_SKEW_QSPI_CO 29:28 +`define STRAP_SCLK_SKEW_WI 17:16 +`define STRAP_SCLK_SKEW_WH 19:18 +`define STRAP_SCLK_SKEW_RISCV 21:20 +`define STRAP_SCLK_SKEW_QSPI 23:22 +`define STRAP_SCLK_SKEW_UART 25:24 +`define STRAP_SCLK_SKEW_PINMUX 27:26 +`define STRAP_SCLK_SKEW_QSPI_CO 29:28 `define STRAP_QSPI_INIT_BYPASS 30 `define STRAP_SOFT_REBOOT_REQ 31
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index cd0b302..7337ceb 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -40,6 +40,8 @@ //// 13. 3 x Hardware Timer //// //// 14. UART Master //// //// 15. SPI Slave (As Arduino ISP) //// +//// 16. AES 126 Encription/Decryption //// +//// 17. FPU (Single Precision) //// //// //// //// To Do: //// //// nothing //// @@ -275,7 +277,12 @@ //// 2'b00 - Auto, 2'b01 - 50Mhz, 2'b10 - 4Mhz, //// //// 2'b11 - LA control //// //// B. digital_pll is re-synth with maual placement //// -//// //// +//// 5.6 Sept 29 2022, Dinesh A //// +//// A. 4x 8bit DAC Integration //// +//// B. clock skew control added for core clock //// +//// 5.7 Nov 7, 2022, Dinesh A //// +//// A. AES 128 Bit Encription and Decryption integration //// +//// B. FPU Integration //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -577,7 +584,7 @@ // CPU Configuration //---------------------------------------------------- wire cpu_intf_rst_n ; -wire [1:0] cpu_core_rst_n ; +wire [3:0] cpu_core_rst_n ; wire qspim_rst_n ; wire sspim_rst_n ; wire [1:0] uart_rst_n ; // uart reset @@ -600,22 +607,23 @@ wire [7:0] cfg_glb_ctrl ; -wire [31:0] cfg_clk_ctrl1 ; -wire [3:0] cfg_cska_wi ; // clock skew adjust for wishbone interconnect -wire [3:0] cfg_cska_wh ; // clock skew adjust for web host +wire [31:0] cfg_clk_skew_ctrl1 ; +wire [31:0] cfg_clk_skew_ctrl2 ; +wire [3:0] cfg_wcska_wi ; // clock skew adjust for wishbone interconnect +wire [3:0] cfg_wcska_wh ; // clock skew adjust for web host -wire [3:0] cfg_cska_riscv ; // clock skew adjust for riscv -wire [3:0] cfg_cska_uart ; // clock skew adjust for uart -wire [3:0] cfg_cska_qspi ; // clock skew adjust for spi -wire [3:0] cfg_cska_pinmux ; // clock skew adjust for pinmux -wire [3:0] cfg_cska_qspi_co ; // clock skew adjust for global reg +wire [3:0] cfg_wcska_riscv ; // clock skew adjust for riscv +wire [3:0] cfg_wcska_uart ; // clock skew adjust for uart +wire [3:0] cfg_wcska_qspi ; // clock skew adjust for spi +wire [3:0] cfg_wcska_pinmux ; // clock skew adjust for pinmux +wire [3:0] cfg_wcska_qspi_co ; // clock skew adjust for global reg // Bus Repeater Signals output from Wishbone Interface -wire [3:0] cfg_cska_riscv_rp ; // clock skew adjust for riscv -wire [3:0] cfg_cska_uart_rp ; // clock skew adjust for uart -wire [3:0] cfg_cska_qspi_rp ; // clock skew adjust for spi -wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux -wire [3:0] cfg_cska_qspi_co_rp ; // clock skew adjust for global reg +wire [3:0] cfg_wcska_riscv_rp ; // clock skew adjust for riscv +wire [3:0] cfg_wcska_uart_rp ; // clock skew adjust for uart +wire [3:0] cfg_wcska_qspi_rp ; // clock skew adjust for spi +wire [3:0] cfg_wcska_pinmux_rp ; // clock skew adjust for pinmux +wire [3:0] cfg_wcska_qspi_co_rp ; // clock skew adjust for global reg wire [31:0] irq_lines_rp ; // Repeater wire soft_irq_rp ; // Repeater @@ -734,6 +742,36 @@ wire usb_intr_o ; wire i2cm_intr_o ; +//------------------------------------------------------------ +// AES Integration local decleration +//------------------------------------------------------------ +wire cpu_clk_aes ; +wire [3:0] cfg_ccska_aes ; +wire [3:0] cfg_ccska_aes_rp ; +wire aes_dmem_req ; +wire aes_dmem_cmd ; +wire [1:0] aes_dmem_width ; +wire [6:0] aes_dmem_addr ; +wire [31:0] aes_dmem_wdata ; +wire aes_dmem_req_ack ; +wire [31:0] aes_dmem_rdata ; +wire [1:0] aes_dmem_resp ; + +//------------------------------------------------------------ +// FPU Integration local decleration +//------------------------------------------------------------ +wire cpu_clk_fpu ; +wire [3:0] cfg_ccska_fpu ; +wire [3:0] cfg_ccska_fpu_rp ; +wire fpu_dmem_req ; +wire fpu_dmem_cmd ; +wire [1:0] fpu_dmem_width ; +wire [4:0] fpu_dmem_addr ; +wire [31:0] fpu_dmem_wdata ; +wire fpu_dmem_req_ack ; +wire [31:0] fpu_dmem_rdata ; +wire [1:0] fpu_dmem_resp ; + //---------------------------------------------------------------- // UART Master I/F // ------------------------------------------------------------- @@ -757,12 +795,29 @@ wire s_reset_n ; wire cfg_strap_pad_ctrl ; +wire e_reset_n_rp ; +wire p_reset_n_rp ; +wire s_reset_n_rp ; +wire cfg_strap_pad_ctrl_rp ; +//---------------------------------------------------------------------- +// DAC Config +//---------------------------------------------------------------------- +wire [7:0] cfg_dac0_mux_sel ; +wire [7:0] cfg_dac1_mux_sel ; +wire [7:0] cfg_dac2_mux_sel ; +wire [7:0] cfg_dac3_mux_sel ; + //--------------------------------------------------------------------- // Strap //--------------------------------------------------------------------- wire [31:0] system_strap ; wire [31:0] strap_sticky ; wire [1:0] strap_uartm ; + +wire [31:0] system_strap_rp ; +wire [31:0] strap_sticky_rp ; +wire [1:0] strap_uartm_rp ; + wire [1:0] strap_qspi_flash = system_strap[`STRAP_QSPI_FLASH]; wire strap_qspi_sram = system_strap[`STRAP_QSPI_SRAM]; wire strap_qspi_pre_sram = system_strap[`STRAP_QSPI_PRE_SRAM]; @@ -780,22 +835,43 @@ wire cfg_bypass_dcache = cfg_riscv_ctrl[11]; ///////////////////////////////////////////////////////// -// Clock Skew Ctrl +// System/WB Clock Skew Ctrl //////////////////////////////////////////////////////// -assign cfg_cska_wi = cfg_clk_ctrl1[3:0]; -assign cfg_cska_wh = cfg_clk_ctrl1[7:4]; -assign cfg_cska_riscv = cfg_clk_ctrl1[11:8]; -assign cfg_cska_qspi = cfg_clk_ctrl1[15:12]; -assign cfg_cska_uart = cfg_clk_ctrl1[19:16]; -assign cfg_cska_pinmux = cfg_clk_ctrl1[23:20]; -assign cfg_cska_qspi_co = cfg_clk_ctrl1[27:24]; +assign cfg_wcska_wi = cfg_clk_skew_ctrl1[3:0]; +assign cfg_wcska_wh = cfg_clk_skew_ctrl1[7:4]; +assign cfg_wcska_riscv = cfg_clk_skew_ctrl1[11:8]; +assign cfg_wcska_qspi = cfg_clk_skew_ctrl1[15:12]; +assign cfg_wcska_uart = cfg_clk_skew_ctrl1[19:16]; +assign cfg_wcska_pinmux = cfg_clk_skew_ctrl1[23:20]; +assign cfg_wcska_qspi_co = cfg_clk_skew_ctrl1[27:24]; +///////////////////////////////////////////////////////// +// RISCV Clock skew control +///////////////////////////////////////////////////////// +wire [3:0] cfg_ccska_riscv_intf_rp ; +wire [3:0] cfg_ccska_riscv_icon_rp ; +wire [3:0] cfg_ccska_riscv_core0_rp ; +wire [3:0] cfg_ccska_riscv_core1_rp ; +wire [3:0] cfg_ccska_riscv_core2_rp ; +wire [3:0] cfg_ccska_riscv_core3_rp ; + +wire [3:0] cfg_ccska_riscv_intf = cfg_clk_skew_ctrl2[3:0]; +wire [3:0] cfg_ccska_riscv_icon = cfg_clk_skew_ctrl2[7:4]; +wire [3:0] cfg_ccska_riscv_core0 = cfg_clk_skew_ctrl2[11:8]; +wire [3:0] cfg_ccska_riscv_core1 = cfg_clk_skew_ctrl2[15:12]; +wire [3:0] cfg_ccska_riscv_core2 = cfg_clk_skew_ctrl2[19:16]; +wire [3:0] cfg_ccska_riscv_core3 = cfg_clk_skew_ctrl2[23:20]; +assign cfg_ccska_aes = cfg_clk_skew_ctrl2[27:24]; +assign cfg_ccska_fpu = cfg_clk_skew_ctrl2[31:28]; assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug}; wire int_pll_clock = pll_clk_out[0]; +/*********************************************** + Wishbone HOST +*************************************************/ wb_host u_wb_host( `ifdef USE_POWER_PINS @@ -815,8 +891,8 @@ .s_reset_n (s_reset_n ), // soft reset .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ), .system_strap (system_strap ), - .strap_sticky (strap_sticky ), - .strap_uartm (strap_uartm ), + .strap_sticky (strap_sticky_rp ), + .strap_uartm (strap_uartm_rp ), .wbd_int_rst_n (wbd_int_rst_n ), .wbd_pll_rst_n (wbd_pll_rst_n ), @@ -837,7 +913,7 @@ // Clock Skeq Adjust .wbd_clk_int (wbd_clk_int ), .wbd_clk_wh (wbd_clk_wh ), - .cfg_cska_wh (cfg_cska_wh ), + .cfg_cska_wh (cfg_wcska_wh ), // Slave Port .wbs_clk_out (wbd_clk_int ), @@ -852,7 +928,8 @@ .wbs_ack_i (wbd_int_ack_o ), .wbs_err_i (wbd_int_err_o ), - .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), + .cfg_clk_skew_ctrl1 (cfg_clk_skew_ctrl1 ), + .cfg_clk_skew_ctrl2 (cfg_clk_skew_ctrl2 ), .la_data_in (la_data_in[17:0] ), @@ -869,9 +946,12 @@ ); +/**************************************************************** + Digital PLL +*****************************************************************/ // This rtl/gds picked from efabless caravel project -digital_pll u_pll( +dg_pll u_pll( `ifdef USE_POWER_PINS .VPWR (vccd1 ), .VGND (vssd1 ), @@ -892,18 +972,18 @@ //------------------------------------------------------------------------------ ycr2_top_wb u_riscv_top ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .wbd_clk_int (wbd_clk_risc_rp ), - .cfg_cska_riscv (cfg_cska_riscv_rp ), - .wbd_clk_riscv (wbd_clk_riscv_skew ), + .wbd_clk_int (wbd_clk_risc_rp ), + .cfg_wcska_riscv_intf (cfg_wcska_riscv_rp ), + .wbd_clk_skew (wbd_clk_riscv_skew ), // Reset .pwrup_rst_n (wbd_int_rst_n ), .rst_n (wbd_int_rst_n ), .cpu_intf_rst_n (cpu_intf_rst_n ), - .cpu_core_rst_n (cpu_core_rst_n ), + .cpu_core_rst_n (cpu_core_rst_n[1:0] ), .riscv_debug (riscv_debug ), .core_debug_sel (cfg_riscv_debug_sel ), .cfg_sram_lphase (cfg_riscv_sram_lphase ), @@ -912,48 +992,53 @@ .cfg_bypass_dcache (cfg_bypass_dcache ), // Clock - .core_clk (cpu_clk ), - .rtc_clk (rtc_clk ), + .core_clk_int (cpu_clk ), + .cfg_ccska_riscv_intf (cfg_ccska_riscv_intf_rp ), + .cfg_ccska_riscv_icon (cfg_ccska_riscv_icon_rp ), + .cfg_ccska_riscv_core0 (cfg_ccska_riscv_core0_rp ), + .cfg_ccska_riscv_core1 (cfg_ccska_riscv_core1_rp ), + + .rtc_clk (rtc_clk ), // IRQ - .irq_lines (irq_lines_rp ), - .soft_irq (soft_irq_rp ), // TODO - Interrupts + .irq_lines (irq_lines_rp ), + .soft_irq (soft_irq_rp ), // TODO - Interrupts // DFT - // .test_mode (1'b0 ), // Moved inside IP - // .test_rst_n (1'b1 ), // Moved inside IP + // .test_mode (1'b0 ), // Moved inside IP + // .test_rst_n (1'b1 ), // Moved inside IP `ifndef SCR1_TCM_MEM // SRAM-0 PORT-0 - .sram0_clk0 (sram0_clk0 ), - .sram0_csb0 (sram0_csb0 ), - .sram0_web0 (sram0_web0 ), - .sram0_addr0 (sram0_addr0 ), - .sram0_wmask0 (sram0_wmask0 ), - .sram0_din0 (sram0_din0 ), - .sram0_dout0 (sram0_dout0 ), + .sram0_clk0 (sram0_clk0 ), + .sram0_csb0 (sram0_csb0 ), + .sram0_web0 (sram0_web0 ), + .sram0_addr0 (sram0_addr0 ), + .sram0_wmask0 (sram0_wmask0 ), + .sram0_din0 (sram0_din0 ), + .sram0_dout0 (sram0_dout0 ), // SRAM-0 PORT-0 - .sram0_clk1 (sram0_clk1 ), - .sram0_csb1 (sram0_csb1 ), - .sram0_addr1 (sram0_addr1 ), - .sram0_dout1 (sram0_dout1 ), + .sram0_clk1 (sram0_clk1 ), + .sram0_csb1 (sram0_csb1 ), + .sram0_addr1 (sram0_addr1 ), + .sram0_dout1 (sram0_dout1 ), // // SRAM-1 PORT-0 - // .sram1_clk0 (sram1_clk0 ), - // .sram1_csb0 (sram1_csb0 ), - // .sram1_web0 (sram1_web0 ), - // .sram1_addr0 (sram1_addr0 ), - // .sram1_wmask0 (sram1_wmask0 ), - // .sram1_din0 (sram1_din0 ), - // .sram1_dout0 (sram1_dout0 ), + // .sram1_clk0 (sram1_clk0 ), + // .sram1_csb0 (sram1_csb0 ), + // .sram1_web0 (sram1_web0 ), + // .sram1_addr0 (sram1_addr0 ), + // .sram1_wmask0 (sram1_wmask0 ), + // .sram1_din0 (sram1_din0 ), + // .sram1_dout0 (sram1_dout0 ), // // // SRAM PORT-0 - // .sram1_clk1 (sram1_clk1 ), - // .sram1_csb1 (sram1_csb1 ), - // .sram1_addr1 (sram1_addr1 ), - // .sram1_dout1 (sram1_dout1 ), + // .sram1_clk1 (sram1_clk1 ), + // .sram1_csb1 (sram1_csb1 ), + // .sram1_addr1 (sram1_addr1 ), + // .sram1_dout1 (sram1_dout1 ), `endif .wb_rst_n (wbd_int_rst_n ), @@ -1024,7 +1109,25 @@ .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), .wbd_dmem_lack_i (wbd_riscv_dmem_lack_o ), - .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) + .wbd_dmem_err_i (wbd_riscv_dmem_err_o ), + + .aes_dmem_req (aes_dmem_req ), + .aes_dmem_cmd (aes_dmem_cmd ), + .aes_dmem_width (aes_dmem_width ), + .aes_dmem_addr (aes_dmem_addr ), + .aes_dmem_wdata (aes_dmem_wdata ), + .aes_dmem_req_ack (aes_dmem_req_ack ), + .aes_dmem_rdata (aes_dmem_rdata ), + .aes_dmem_resp (aes_dmem_resp ), + + .fpu_dmem_req (fpu_dmem_req ), + .fpu_dmem_cmd (fpu_dmem_cmd ), + .fpu_dmem_width (fpu_dmem_width ), + .fpu_dmem_addr (fpu_dmem_addr ), + .fpu_dmem_wdata (fpu_dmem_wdata ), + .fpu_dmem_req_ack (fpu_dmem_req_ack ), + .fpu_dmem_rdata (fpu_dmem_rdata ), + .fpu_dmem_resp (fpu_dmem_resp ) ); `ifndef SCR1_TCM_MEM @@ -1112,6 +1215,57 @@ .dout1 (dcache_mem_dout1 ) ); +/*********************************************** + AES 128 Bit +*************************************************/ +aes_top u_aes ( +`ifdef USE_POWER_PINS + .vccd1 (vdda1 ), + .vssd1 (vssa1 ), +`endif + + .mclk (cpu_clk_aes ), + .rst_n (cpu_intf_rst_n ), + + .cfg_cska (cfg_ccska_aes_rp ), + .wbd_clk_int (cpu_clk ), + .wbd_clk_out (cpu_clk_aes ), + + .dmem_req (aes_dmem_req ), + .dmem_cmd (aes_dmem_cmd ), + .dmem_width (aes_dmem_width ), + .dmem_addr (aes_dmem_addr ), + .dmem_wdata (aes_dmem_wdata ), + .dmem_req_ack (aes_dmem_req_ack ), + .dmem_rdata (aes_dmem_rdata ), + .dmem_resp (aes_dmem_resp ) +); + +/*********************************************** + FPU +*************************************************/ +fpu_wrapper u_fpu ( +`ifdef USE_POWER_PINS + .vccd1 (vdda1 ), + .vssd1 (vssa1 ), +`endif + + .mclk (cpu_clk_fpu ), + .rst_n (cpu_intf_rst_n ), + + .cfg_cska (cfg_ccska_fpu_rp ), + .wbd_clk_int (cpu_clk ), + .wbd_clk_out (cpu_clk_fpu ), + + .dmem_req (fpu_dmem_req ), + .dmem_cmd (fpu_dmem_cmd ), + .dmem_width (fpu_dmem_width ), + .dmem_addr (fpu_dmem_addr ), + .dmem_wdata (fpu_dmem_wdata ), + .dmem_req_ack (fpu_dmem_req_ack ), + .dmem_rdata (fpu_dmem_rdata ), + .dmem_resp (fpu_dmem_resp ) +); /********************************************************* * SPI Master @@ -1140,8 +1294,8 @@ .cfg_init_bypass (strap_qspi_init_bypass ), // Clock Skew Adjust - .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), - .cfg_cska_spi (cfg_cska_qspi_rp ), + .cfg_cska_sp_co (cfg_wcska_qspi_co_rp ), + .cfg_cska_spi (cfg_wcska_qspi_rp ), .wbd_clk_int (wbd_clk_qspi_rp ), .wbd_clk_spi (wbd_clk_spi ), @@ -1173,7 +1327,7 @@ wb_interconnect #( `ifndef SYNTHESIS .CH_CLK_WD (4 ), - .CH_DATA_WD (53 ) + .CH_DATA_WD (154 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS @@ -1191,31 +1345,61 @@ wbd_clk_qspi_rp, wbd_clk_risc_rp} ), .ch_data_in ({ + cfg_ccska_fpu[3:0], + cfg_ccska_aes[3:0], + strap_sticky[31:0], + strap_uartm[1:0], + system_strap[31:0], + p_reset_n, + e_reset_n, + cfg_strap_pad_ctrl, soft_irq, irq_lines[31:0], - cfg_cska_qspi_co[3:0], - cfg_cska_pinmux[3:0], - cfg_cska_uart[3:0], - cfg_cska_qspi[3:0], - cfg_cska_riscv[3:0] + cfg_ccska_riscv_core3[3:0], + cfg_ccska_riscv_core2[3:0], + cfg_ccska_riscv_core1[3:0], + cfg_ccska_riscv_core0[3:0], + cfg_ccska_riscv_icon[3:0], + cfg_ccska_riscv_intf[3:0], + + cfg_wcska_qspi_co[3:0], + cfg_wcska_pinmux[3:0], + cfg_wcska_uart[3:0], + cfg_wcska_qspi[3:0], + cfg_wcska_riscv[3:0] } ), .ch_data_out ({ + cfg_ccska_fpu_rp[3:0], + cfg_ccska_aes_rp[3:0], + strap_sticky_rp[31:0], + strap_uartm_rp[1:0], + system_strap_rp[31:0], + p_reset_n_rp, + e_reset_n_rp, + cfg_strap_pad_ctrl_rp, soft_irq_rp, irq_lines_rp[31:0], - cfg_cska_qspi_co_rp[3:0], - cfg_cska_pinmux_rp[3:0], - cfg_cska_uart_rp[3:0], - cfg_cska_qspi_rp[3:0], - cfg_cska_riscv_rp[3:0] - } ), + cfg_ccska_riscv_core3_rp[3:0], + cfg_ccska_riscv_core2_rp[3:0], + cfg_ccska_riscv_core1_rp[3:0], + cfg_ccska_riscv_core0_rp[3:0], + cfg_ccska_riscv_icon_rp[3:0], + cfg_ccska_riscv_intf_rp[3:0], + + cfg_wcska_qspi_co_rp[3:0], + cfg_wcska_pinmux_rp[3:0], + cfg_wcska_uart_rp[3:0], + cfg_wcska_qspi_rp[3:0], + cfg_wcska_riscv_rp[3:0] + } ), // Clock Skew adjust - .wbd_clk_int (wbd_clk_int ), - .cfg_cska_wi (cfg_cska_wi ), - .wbd_clk_wi (wbd_clk_wi_skew ), + .wbd_clk_int (wbd_clk_int ), + .cfg_cska_wi (cfg_wcska_wi ), + .wbd_clk_wi (wbd_clk_wi_skew ), .clk_i (wbd_clk_wi_skew ), .rst_n (wbd_int_rst_n ), @@ -1319,7 +1503,7 @@ .vssd1 (vssd1 ),// User area 1 digital ground `endif .wbd_clk_int (wbd_clk_uart_rp ), - .cfg_cska_uart (cfg_cska_uart_rp ), + .cfg_cska_uart (cfg_wcska_uart_rp ), .wbd_clk_uart (wbd_clk_uart_skew ), .uart_rstn (uart_rst_n ), // uart reset @@ -1377,19 +1561,19 @@ .vssd1 (vssd1 ),// User area 1 digital ground `endif //clk skew adjust - .cfg_cska_pinmux (cfg_cska_pinmux_rp ), + .cfg_cska_pinmux (cfg_wcska_pinmux_rp ), .wbd_clk_int (wbd_clk_pinmux_rp ), .wbd_clk_pinmux (wbd_clk_pinmux_skew ), // System Signals // Inputs .mclk (wbd_clk_pinmux_skew ), - .e_reset_n (e_reset_n ), - .p_reset_n (p_reset_n ), + .e_reset_n (e_reset_n_rp ), + .p_reset_n (p_reset_n_rp ), .s_reset_n (wbd_int_rst_n ), - .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ), - .system_strap (system_strap ), + .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl_rp ), + .system_strap (system_strap_rp ), .strap_sticky (strap_sticky ), .strap_uartm (strap_uartm ), @@ -1490,68 +1674,34 @@ .cfg_pll_fed_div (cfg_pll_fed_div ), .cfg_dco_mode (cfg_dco_mode ), .cfg_dc_trim (cfg_dc_trim ), - .pll_ref_clk (pll_ref_clk ) + .pll_ref_clk (pll_ref_clk ), + .cfg_dac0_mux_sel (cfg_dac0_mux_sel ), + .cfg_dac1_mux_sel (cfg_dac1_mux_sel ), + .cfg_dac2_mux_sel (cfg_dac2_mux_sel ), + .cfg_dac3_mux_sel (cfg_dac3_mux_sel ) ); -/*** -sar_adc u_adc ( + + + +dac_top u_4x8bit_dac( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground - .vccd2 (vccd1), // (vccd2),// User area 2 1.8V supply (analog) - DOTO: Need Fix - .vssd2 (vssd1), // (vssd2),// User area 2 ground (analog) - DOTO: Need Fix + .vccd1 (vdda1 ), + .vssd1 (vssa1 ), `endif - - - .clk (wbd_clk_adc_rp ),// The clock (digital) - .reset_n (wbd_int_rst_n ),// Active low reset (digital) - - // Reg Bus Interface Signal - .reg_cs (wbd_adc_stb_o ), - .reg_wr (wbd_adc_we_o ), - .reg_addr (wbd_adc_adr_o[7:0] ), - .reg_wdata (wbd_adc_dat_o ), - .reg_be (wbd_adc_sel_o ), - - // Outputs - .reg_rdata (wbd_adc_dat_i ), - .reg_ack (wbd_adc_ack_i ), - - .pulse1m_mclk (pulse1m_mclk), + .Vref (analog_io[23]), + .DIn0 (cfg_dac0_mux_sel), + .DIn1 (cfg_dac1_mux_sel), + .DIn2 (cfg_dac2_mux_sel), + .DIn3 (cfg_dac3_mux_sel), + .Vout0(analog_io[15] ), + .Vout1(analog_io[16] ), + .Vout2(analog_io[17] ), + .Vout3(analog_io[18] ) + ); - // DAC I/F - .sar2dac (sar2dac ), - //.analog_dac_out (analog_dac_out) , // TODO: Need to connect to DAC O/P - .analog_dac_out (analog_io[6]) , - - // ADC Input - .analog_din(analog_io[5:0]) // (Analog) - -); -***/ - -/**** -* TODO: Need to uncomment the DAC -DAC_8BIT u_dac ( - `ifdef USE_POWER_PINS - .vdd(vccd2), - .gnd(vssd2), - `endif - .d0(sar2dac[0]), - .d1(sar2dac[1]), - .d2(sar2dac[2]), - .d3(sar2dac[3]), - .d4(sar2dac[4]), - .d5(sar2dac[5]), - .d6(sar2dac[6]), - .d7(sar2dac[7]), - .inp1(analog_io[6]), - .out_v(analog_dac_out) - ); - -**/ endmodule : user_project_wrapper
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v index 28b4293..3c904f9 100644 --- a/verilog/rtl/user_reg_map.v +++ b/verilog/rtl/user_reg_map.v
@@ -15,6 +15,7 @@ `define ADDR_SPACE_TIMER 32'h3002_0180 `define ADDR_SPACE_SEMA 32'h3002_0200 `define ADDR_SPACE_WS281X 32'h3002_0280 +`define ADDR_SPACE_ANALOG 32'h3002_0300 `define ADDR_SPACE_WBHOST 32'h3008_0000 //-------------------------------------------------- @@ -125,6 +126,15 @@ `define SEMA_CFG_LOCK_14 8'h38 // reg_14 - Semaphore Lock Bit-14 `define SEMA_CFG_STATUS 8'h3C // reg_15 - Semaphore Lock Status + +//---------------------------------------------------- +// Analog Configuration +//---------------------------------------------------- +`define ANALOG_CFG_DAC0 8'h00 +`define ANALOG_CFG_DAC1 8'h04 +`define ANALOG_CFG_DAC2 8'h08 +`define ANALOG_CFG_DAC3 8'h0C + //---------------------------------------------------------- // QSPI Register Map //----------------------------------------------------------
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index d56b92a..cc966e2 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -142,7 +142,8 @@ input logic wbs_ack_i , // acknowlegement input logic wbs_err_i , // error - output logic [31:0] cfg_clk_ctrl1 , + output logic [31:0] cfg_clk_skew_ctrl1 , + output logic [31:0] cfg_clk_skew_ctrl2 , input logic [17:0] la_data_in , @@ -487,7 +488,8 @@ .wbs_clk_out (wbs_clk_out ), // System clock .cfg_bank_sel (cfg_bank_sel ), - .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), + .cfg_clk_skew_ctrl1 (cfg_clk_skew_ctrl1 ), + .cfg_clk_skew_ctrl2 (cfg_clk_skew_ctrl2 ), .cfg_fast_sim (cfg_fast_sim ) );
diff --git a/verilog/rtl/wb_host/src/wbh_reg.sv b/verilog/rtl/wb_host/src/wbh_reg.sv index 5985135..ab3ad2b 100644 --- a/verilog/rtl/wb_host/src/wbh_reg.sv +++ b/verilog/rtl/wb_host/src/wbh_reg.sv
@@ -61,12 +61,14 @@ output logic [15:0] cfg_bank_sel , - output logic [31:0] cfg_clk_ctrl1 , + output logic [31:0] cfg_clk_skew_ctrl1 , + output logic [31:0] cfg_clk_skew_ctrl2 , output logic cfg_fast_sim ); logic [2:0] sw_addr ; +logic [3:0] sw_be ; logic sw_rd_en ; logic sw_wr_en ; logic sw_wr_en_0 ; @@ -78,10 +80,10 @@ logic [31:0] reg_out ; logic [31:0] reg_0 ; // Software_Reg_0 -logic [7:0] cfg_clk_ctrl2 ; +logic [7:0] cfg_clk_ctrl ; logic [3:0] cfg_wb_clk_ctrl ; logic [3:0] cfg_cpu_clk_ctrl ; -logic [31:0] cfg_glb_ctrl ; +logic [15:0] cfg_glb_ctrl ; logic wbs_clk_div ; logic wbs_ref_clk_div_2 ; logic wbs_ref_clk_div_4 ; @@ -89,6 +91,7 @@ assign sw_addr = reg_addr ; +assign sw_be = reg_be ; assign sw_rd_en = reg_cs & !reg_wr; assign sw_wr_en = reg_cs & reg_wr; @@ -120,10 +123,29 @@ end +//----------------------------------- +// reg-out mux +//----------------------------------- + +always @( *) +begin + reg_out [31:0] = 'h0; + + case (sw_addr [2:0]) + 3'b000 : reg_out [31:0] = {8'h0,cfg_clk_ctrl[7:0],cfg_glb_ctrl[15:0]}; + 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]}; + 3'b010 : reg_out [31:0] = cfg_clk_skew_ctrl1 [31:0]; + 3'b011 : reg_out [31:0] = cfg_clk_skew_ctrl2[31:0]; + 3'b101 : reg_out [31:0] = system_strap [31:0]; + default : reg_out [31:0] = 'h0; + endcase +end + + +//----------------------------------- +// reg-0 //------------------------------------- -// Global + Clock Control -// ------------------------------------- -assign cfg_glb_ctrl = reg_0[31:0]; + // Reset control // On Power-up wb & pll power default enabled ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0] & s_reset_n),.X(wbd_int_rst_n)); @@ -132,38 +154,36 @@ //assign cfg_fast_sim = cfg_glb_ctrl[8]; ctech_clk_buf u_fastsim_buf (.A (cfg_glb_ctrl[8]), . X(cfg_fast_sim)); // To Bypass Reset FSM initial wait time - - -assign cfg_wb_clk_ctrl = cfg_clk_ctrl2[3:0]; -assign cfg_cpu_clk_ctrl = cfg_clk_ctrl2[7:4]; - - -always @( *) -begin - reg_out [31:0] = 'h0; - - case (sw_addr [2:0]) - 3'b000 : reg_out [31:0] = reg_0; - 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]}; - 3'b010 : reg_out [31:0] = cfg_clk_ctrl1 [31:0]; - 3'b011 : reg_out [31:0] = {24'h0,cfg_clk_ctrl2 [7:0]}; - 3'b101 : reg_out [31:0] = system_strap [31:0]; - default : reg_out [31:0] = 'h0; - endcase -end - - - -generic_register #(32,32'h3 ) u_glb_ctrl ( - .we ({32{sw_wr_en_0}} ), - .data_in (reg_wdata[31:0] ), - .reset_n (e_reset_n ), - .clk (mclk ), +gen_16b_reg #(16'h3 ) u_glb_ctrl ( + .cs (sw_wr_en_0 ), + .we (sw_be[1:0] ), + .data_in (reg_wdata[15:0] ), + .reset_n (e_reset_n ), + .clk (mclk ), //List of Outs - .data_out (reg_0[31:0]) + .data_out (cfg_glb_ctrl[15:0]) ); + +//-------------------------------- +// clock control +//-------------------------------- +assign cfg_wb_clk_ctrl = cfg_clk_ctrl[3:0]; +assign cfg_cpu_clk_ctrl = cfg_clk_ctrl[7:4]; +always @ (posedge mclk) begin + if (p_reset_n == 1'b0) begin + cfg_clk_ctrl <= strap_sticky[7:0] ; + end + else begin + if(sw_wr_en_0 & sw_be[2] ) + cfg_clk_ctrl <= reg_wdata[23:16]; + end +end +//------------------------------------------------- +// reg-1 +//------------------------------------------------- + generic_register #(16,16'h1000 ) u_bank_sel ( .we ({16{sw_wr_en_1}} ), .data_in (reg_wdata[15:0] ), @@ -175,75 +195,68 @@ ); //----------------------------------------------- -// clock control-1 +// reg-2: clock skew control-1 //---------------------------------------------- wire [31:0] rst_clk_ctrl1; -assign rst_clk_ctrl1[3:0] = (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b00) ? SKEW_RESET_VAL[3:0] : - (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 : - (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4; +assign rst_clk_ctrl1[3:0] = (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b00) ? CLK_SKEW1_RESET_VAL[3:0] : + (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b01) ? CLK_SKEW1_RESET_VAL[3:0] + 2 : + (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b10) ? CLK_SKEW1_RESET_VAL[3:0] + 4 : CLK_SKEW1_RESET_VAL[3:0]-4; -assign rst_clk_ctrl1[7:4] = (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b00) ? SKEW_RESET_VAL[7:4] : - (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 : - (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4; +assign rst_clk_ctrl1[7:4] = (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b00) ? CLK_SKEW1_RESET_VAL[7:4] : + (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b01) ? CLK_SKEW1_RESET_VAL[7:4] + 2 : + (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b10) ? CLK_SKEW1_RESET_VAL[7:4] + 4 : CLK_SKEW1_RESET_VAL[7:4]-4; -assign rst_clk_ctrl1[11:8] = (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b00) ? SKEW_RESET_VAL[11:8] : - (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 : - (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4; +assign rst_clk_ctrl1[11:8] = (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b00) ? CLK_SKEW1_RESET_VAL[11:8] : + (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b01) ? CLK_SKEW1_RESET_VAL[11:8] + 2 : + (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b10) ? CLK_SKEW1_RESET_VAL[11:8] + 4 : CLK_SKEW1_RESET_VAL[11:8]-4; -assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b00) ? SKEW_RESET_VAL[15:12] : - (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 : - (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4; +assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b00) ? CLK_SKEW1_RESET_VAL[15:12] : + (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b01) ? CLK_SKEW1_RESET_VAL[15:12] + 2 : + (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b10) ? CLK_SKEW1_RESET_VAL[15:12] + 4 : CLK_SKEW1_RESET_VAL[15:12]-4; -assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b00) ? SKEW_RESET_VAL[19:16] : - (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 : - (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4; +assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b00) ? CLK_SKEW1_RESET_VAL[19:16] : + (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b01) ? CLK_SKEW1_RESET_VAL[19:16] + 2 : + (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b10) ? CLK_SKEW1_RESET_VAL[19:16] + 4 : CLK_SKEW1_RESET_VAL[19:16]-4; -assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b00) ? SKEW_RESET_VAL[23:20] : - (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 : - (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4; +assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b00) ? CLK_SKEW1_RESET_VAL[23:20] : + (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b01) ? CLK_SKEW1_RESET_VAL[23:20] + 2 : + (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b10) ? CLK_SKEW1_RESET_VAL[23:20] + 4 : CLK_SKEW1_RESET_VAL[23:20]-4; -assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b00) ? SKEW_RESET_VAL[27:24] : - (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 : - (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4; +assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b00) ? CLK_SKEW1_RESET_VAL[27:24] : + (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 : + (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4; assign rst_clk_ctrl1[31:28] = 4'b0; always @ (posedge mclk ) begin if (p_reset_n == 1'b0) begin - cfg_clk_ctrl1 <= rst_clk_ctrl1 ; + cfg_clk_skew_ctrl1 <= rst_clk_ctrl1 ; end else begin if(sw_wr_en_2 ) - cfg_clk_ctrl1 <= reg_wdata[31:0]; + cfg_clk_skew_ctrl1 <= reg_wdata[31:0]; end end -//-------------------------------- -// clock control-2 -//-------------------------------- -always @ (posedge mclk) begin - if (p_reset_n == 1'b0) begin - cfg_clk_ctrl2 <= strap_sticky[7:0] ; - end - else begin - if(sw_wr_en_3 ) - cfg_clk_ctrl2 <= reg_wdata[7:0]; - end -end - +//----------------------------------------------- +// reg-3: clock skew control-2 +// This skew control the RISCV clock, Since riscv clock need to stable on power-up +// we have not given any strap control for it. +//---------------------------------------------- always @ (posedge mclk ) begin if (p_reset_n == 1'b0) begin - cfg_clk_ctrl2 <= strap_sticky[7:0] ; + cfg_clk_skew_ctrl2 <= CLK_SKEW2_RESET_VAL ; end else begin if(sw_wr_en_3 ) - cfg_clk_ctrl2 <= reg_wdata[7:0]; + cfg_clk_skew_ctrl2 <= reg_wdata[31:0]; end end + //------------------------------------------------------------- // Note: system_strap reset (p_reset_n) will be released // eariler than s_reset_n to take care of strap loading
diff --git a/verilog/rtl/yifive/ycr2c b/verilog/rtl/yifive/ycr2c index c9d988c..10f852e 160000 --- a/verilog/rtl/yifive/ycr2c +++ b/verilog/rtl/yifive/ycr2c
@@ -1 +1 @@ -Subproject commit c9d988cbb4df50e5528ff6cb990010a33d0f597c +Subproject commit 10f852e4cca80b8243ec9a74e5536bd827da5246